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-rw-r--r--include/asm-m32r/m32102.h314
1 files changed, 0 insertions, 314 deletions
diff --git a/include/asm-m32r/m32102.h b/include/asm-m32r/m32102.h
deleted file mode 100644
index 52807f8db166..000000000000
--- a/include/asm-m32r/m32102.h
+++ /dev/null
@@ -1,314 +0,0 @@
1#ifndef _M32102_H_
2#define _M32102_H_
3
4/*
5 * Renesas M32R 32102 group
6 *
7 * Copyright (c) 2001 Hitoshi Yamamoto
8 * Copyright (c) 2003, 2004 Renesas Technology Corp.
9 */
10
11/*======================================================================*
12 * Special Function Register
13 *======================================================================*/
14#if !defined(CONFIG_CHIP_M32104)
15#define M32R_SFR_OFFSET (0x00E00000) /* 0x00E00000-0x00EFFFFF 1[MB] */
16#else
17#define M32R_SFR_OFFSET (0x00700000) /* 0x00700000-0x007FFFFF 1[MB] */
18#endif
19
20/*
21 * Clock and Power Management registers.
22 */
23#define M32R_CPM_OFFSET (0x000F4000+M32R_SFR_OFFSET)
24
25#define M32R_CPM_CPUCLKCR_PORTL (0x00+M32R_CPM_OFFSET)
26#define M32R_CPM_CLKMOD_PORTL (0x04+M32R_CPM_OFFSET)
27#define M32R_CPM_PLLCR_PORTL (0x08+M32R_CPM_OFFSET)
28
29/*
30 * DMA Controller registers.
31 */
32#define M32R_DMA_OFFSET (0x000F8000+M32R_SFR_OFFSET)
33
34#define M32R_DMAEN_PORTL (0x000+M32R_DMA_OFFSET)
35#define M32R_DMAISTS_PORTL (0x004+M32R_DMA_OFFSET)
36#define M32R_DMAEDET_PORTL (0x008+M32R_DMA_OFFSET)
37#define M32R_DMAASTS_PORTL (0x00c+M32R_DMA_OFFSET)
38
39#define M32R_DMA0CR0_PORTL (0x100+M32R_DMA_OFFSET)
40#define M32R_DMA0CR1_PORTL (0x104+M32R_DMA_OFFSET)
41#define M32R_DMA0CSA_PORTL (0x108+M32R_DMA_OFFSET)
42#define M32R_DMA0RSA_PORTL (0x10c+M32R_DMA_OFFSET)
43#define M32R_DMA0CDA_PORTL (0x110+M32R_DMA_OFFSET)
44#define M32R_DMA0RDA_PORTL (0x114+M32R_DMA_OFFSET)
45#define M32R_DMA0CBCUT_PORTL (0x118+M32R_DMA_OFFSET)
46#define M32R_DMA0RBCUT_PORTL (0x11c+M32R_DMA_OFFSET)
47
48#define M32R_DMA1CR0_PORTL (0x200+M32R_DMA_OFFSET)
49#define M32R_DMA1CR1_PORTL (0x204+M32R_DMA_OFFSET)
50#define M32R_DMA1CSA_PORTL (0x208+M32R_DMA_OFFSET)
51#define M32R_DMA1RSA_PORTL (0x20c+M32R_DMA_OFFSET)
52#define M32R_DMA1CDA_PORTL (0x210+M32R_DMA_OFFSET)
53#define M32R_DMA1RDA_PORTL (0x214+M32R_DMA_OFFSET)
54#define M32R_DMA1CBCUT_PORTL (0x218+M32R_DMA_OFFSET)
55#define M32R_DMA1RBCUT_PORTL (0x21c+M32R_DMA_OFFSET)
56
57/*
58 * Multi Function Timer registers.
59 */
60#define M32R_MFT_OFFSET (0x000FC000+M32R_SFR_OFFSET)
61
62#define M32R_MFTCR_PORTL (0x000+M32R_MFT_OFFSET) /* MFT control */
63#define M32R_MFTRPR_PORTL (0x004+M32R_MFT_OFFSET) /* MFT real port */
64
65#define M32R_MFT0_OFFSET (0x100+M32R_MFT_OFFSET)
66#define M32R_MFT0MOD_PORTL (0x00+M32R_MFT0_OFFSET) /* MFT0 mode */
67#define M32R_MFT0BOS_PORTL (0x04+M32R_MFT0_OFFSET) /* MFT0 b-port output status */
68#define M32R_MFT0CUT_PORTL (0x08+M32R_MFT0_OFFSET) /* MFT0 count */
69#define M32R_MFT0RLD_PORTL (0x0C+M32R_MFT0_OFFSET) /* MFT0 reload */
70#define M32R_MFT0CMPRLD_PORTL (0x10+M32R_MFT0_OFFSET) /* MFT0 compare reload */
71
72#define M32R_MFT1_OFFSET (0x200+M32R_MFT_OFFSET)
73#define M32R_MFT1MOD_PORTL (0x00+M32R_MFT1_OFFSET) /* MFT1 mode */
74#define M32R_MFT1BOS_PORTL (0x04+M32R_MFT1_OFFSET) /* MFT1 b-port output status */
75#define M32R_MFT1CUT_PORTL (0x08+M32R_MFT1_OFFSET) /* MFT1 count */
76#define M32R_MFT1RLD_PORTL (0x0C+M32R_MFT1_OFFSET) /* MFT1 reload */
77#define M32R_MFT1CMPRLD_PORTL (0x10+M32R_MFT1_OFFSET) /* MFT1 compare reload */
78
79#define M32R_MFT2_OFFSET (0x300+M32R_MFT_OFFSET)
80#define M32R_MFT2MOD_PORTL (0x00+M32R_MFT2_OFFSET) /* MFT2 mode */
81#define M32R_MFT2BOS_PORTL (0x04+M32R_MFT2_OFFSET) /* MFT2 b-port output status */
82#define M32R_MFT2CUT_PORTL (0x08+M32R_MFT2_OFFSET) /* MFT2 count */
83#define M32R_MFT2RLD_PORTL (0x0C+M32R_MFT2_OFFSET) /* MFT2 reload */
84#define M32R_MFT2CMPRLD_PORTL (0x10+M32R_MFT2_OFFSET) /* MFT2 compare reload */
85
86#define M32R_MFT3_OFFSET (0x400+M32R_MFT_OFFSET)
87#define M32R_MFT3MOD_PORTL (0x00+M32R_MFT3_OFFSET) /* MFT3 mode */
88#define M32R_MFT3BOS_PORTL (0x04+M32R_MFT3_OFFSET) /* MFT3 b-port output status */
89#define M32R_MFT3CUT_PORTL (0x08+M32R_MFT3_OFFSET) /* MFT3 count */
90#define M32R_MFT3RLD_PORTL (0x0C+M32R_MFT3_OFFSET) /* MFT3 reload */
91#define M32R_MFT3CMPRLD_PORTL (0x10+M32R_MFT3_OFFSET) /* MFT3 compare reload */
92
93#define M32R_MFT4_OFFSET (0x500+M32R_MFT_OFFSET)
94#define M32R_MFT4MOD_PORTL (0x00+M32R_MFT4_OFFSET) /* MFT4 mode */
95#define M32R_MFT4BOS_PORTL (0x04+M32R_MFT4_OFFSET) /* MFT4 b-port output status */
96#define M32R_MFT4CUT_PORTL (0x08+M32R_MFT4_OFFSET) /* MFT4 count */
97#define M32R_MFT4RLD_PORTL (0x0C+M32R_MFT4_OFFSET) /* MFT4 reload */
98#define M32R_MFT4CMPRLD_PORTL (0x10+M32R_MFT4_OFFSET) /* MFT4 compare reload */
99
100#define M32R_MFT5_OFFSET (0x600+M32R_MFT_OFFSET)
101#define M32R_MFT5MOD_PORTL (0x00+M32R_MFT5_OFFSET) /* MFT4 mode */
102#define M32R_MFT5BOS_PORTL (0x04+M32R_MFT5_OFFSET) /* MFT4 b-port output status */
103#define M32R_MFT5CUT_PORTL (0x08+M32R_MFT5_OFFSET) /* MFT4 count */
104#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */
105#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */
106
107#if (defined(CONFIG_CHIP_M32700) && !defined(CONFIG_PLAT_MAPPI2)) \
108 || defined(CONFIG_CHIP_M32104)
109#define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */
110#define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */
111#define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */
112#define M32R_MFTCR_MFT3MSK (1UL<<28) /* b3 */
113#define M32R_MFTCR_MFT4MSK (1UL<<27) /* b4 */
114#define M32R_MFTCR_MFT5MSK (1UL<<26) /* b5 */
115#define M32R_MFTCR_MFT0EN (1UL<<23) /* b8 */
116#define M32R_MFTCR_MFT1EN (1UL<<22) /* b9 */
117#define M32R_MFTCR_MFT2EN (1UL<<21) /* b10 */
118#define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */
119#define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */
120#define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */
121#else
122#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */
123#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */
124#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */
125#define M32R_MFTCR_MFT3MSK (1UL<<12) /* b19 */
126#define M32R_MFTCR_MFT4MSK (1UL<<11) /* b20 */
127#define M32R_MFTCR_MFT5MSK (1UL<<10) /* b21 */
128#define M32R_MFTCR_MFT0EN (1UL<<7) /* b24 */
129#define M32R_MFTCR_MFT1EN (1UL<<6) /* b25 */
130#define M32R_MFTCR_MFT2EN (1UL<<5) /* b26 */
131#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */
132#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */
133#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */
134#endif
135
136#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */
137#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */
138#define M32R_MFTMOD_GTSEL000 (0UL<<8) /* b21-23 : 000 */
139#define M32R_MFTMOD_GTSEL001 (1UL<<8) /* b21-23 : 001 */
140#define M32R_MFTMOD_GTSEL010 (2UL<<8) /* b21-23 : 010 */
141#define M32R_MFTMOD_GTSEL011 (3UL<<8) /* b21-23 : 011 */
142#define M32R_MFTMOD_GTSEL110 (6UL<<8) /* b21-23 : 110 */
143#define M32R_MFTMOD_GTSEL111 (7UL<<8) /* b21-23 : 111 */
144#define M32R_MFTMOD_CMSEL (1UL<<3) /* b28 */
145#define M32R_MFTMOD_CSSEL000 (0UL<<0) /* b29-b31 : 000 */
146#define M32R_MFTMOD_CSSEL001 (1UL<<0) /* b29-b31 : 001 */
147#define M32R_MFTMOD_CSSEL010 (2UL<<0) /* b29-b31 : 010 */
148#define M32R_MFTMOD_CSSEL011 (3UL<<0) /* b29-b31 : 011 */
149#define M32R_MFTMOD_CSSEL100 (4UL<<0) /* b29-b31 : 100 */
150#define M32R_MFTMOD_CSSEL110 (6UL<<0) /* b29-b31 : 110 */
151
152/*
153 * Serial I/O registers.
154 */
155#define M32R_SIO_OFFSET (0x000FD000+M32R_SFR_OFFSET)
156
157#define M32R_SIO0_CR_PORTL (0x000+M32R_SIO_OFFSET)
158#define M32R_SIO0_MOD0_PORTL (0x004+M32R_SIO_OFFSET)
159#define M32R_SIO0_MOD1_PORTL (0x008+M32R_SIO_OFFSET)
160#define M32R_SIO0_STS_PORTL (0x00C+M32R_SIO_OFFSET)
161#define M32R_SIO0_TRCR_PORTL (0x010+M32R_SIO_OFFSET)
162#define M32R_SIO0_BAUR_PORTL (0x014+M32R_SIO_OFFSET)
163#define M32R_SIO0_RBAUR_PORTL (0x018+M32R_SIO_OFFSET)
164#define M32R_SIO0_TXB_PORTL (0x01C+M32R_SIO_OFFSET)
165#define M32R_SIO0_RXB_PORTL (0x020+M32R_SIO_OFFSET)
166
167/*
168 * Interrupt Control Unit registers.
169 */
170#define M32R_ICU_OFFSET (0x000FF000+M32R_SFR_OFFSET)
171#define M32R_ICU_ISTS_PORTL (0x004+M32R_ICU_OFFSET)
172#define M32R_ICU_IREQ0_PORTL (0x008+M32R_ICU_OFFSET)
173#define M32R_ICU_IREQ1_PORTL (0x00C+M32R_ICU_OFFSET)
174#define M32R_ICU_SBICR_PORTL (0x018+M32R_ICU_OFFSET)
175#define M32R_ICU_IMASK_PORTL (0x01C+M32R_ICU_OFFSET)
176#define M32R_ICU_CR1_PORTL (0x200+M32R_ICU_OFFSET) /* INT0 */
177#define M32R_ICU_CR2_PORTL (0x204+M32R_ICU_OFFSET) /* INT1 */
178#define M32R_ICU_CR3_PORTL (0x208+M32R_ICU_OFFSET) /* INT2 */
179#define M32R_ICU_CR4_PORTL (0x20C+M32R_ICU_OFFSET) /* INT3 */
180#define M32R_ICU_CR5_PORTL (0x210+M32R_ICU_OFFSET) /* INT4 */
181#define M32R_ICU_CR6_PORTL (0x214+M32R_ICU_OFFSET) /* INT5 */
182#define M32R_ICU_CR7_PORTL (0x218+M32R_ICU_OFFSET) /* INT6 */
183#define M32R_ICU_CR8_PORTL (0x219+M32R_ICU_OFFSET) /* INT7 */
184#define M32R_ICU_CR16_PORTL (0x23C+M32R_ICU_OFFSET) /* MFT0 */
185#define M32R_ICU_CR17_PORTL (0x240+M32R_ICU_OFFSET) /* MFT1 */
186#define M32R_ICU_CR18_PORTL (0x244+M32R_ICU_OFFSET) /* MFT2 */
187#define M32R_ICU_CR19_PORTL (0x248+M32R_ICU_OFFSET) /* MFT3 */
188#define M32R_ICU_CR20_PORTL (0x24C+M32R_ICU_OFFSET) /* MFT4 */
189#define M32R_ICU_CR21_PORTL (0x250+M32R_ICU_OFFSET) /* MFT5 */
190#define M32R_ICU_CR32_PORTL (0x27C+M32R_ICU_OFFSET) /* DMA0 */
191#define M32R_ICU_CR33_PORTL (0x280+M32R_ICU_OFFSET) /* DMA1 */
192#define M32R_ICU_CR48_PORTL (0x2BC+M32R_ICU_OFFSET) /* SIO0 */
193#define M32R_ICU_CR49_PORTL (0x2C0+M32R_ICU_OFFSET) /* SIO0 */
194#define M32R_ICU_CR50_PORTL (0x2C4+M32R_ICU_OFFSET) /* SIO1 */
195#define M32R_ICU_CR51_PORTL (0x2C8+M32R_ICU_OFFSET) /* SIO1 */
196#define M32R_ICU_CR52_PORTL (0x2CC+M32R_ICU_OFFSET) /* SIO2 */
197#define M32R_ICU_CR53_PORTL (0x2D0+M32R_ICU_OFFSET) /* SIO2 */
198#define M32R_ICU_CR54_PORTL (0x2D4+M32R_ICU_OFFSET) /* SIO3 */
199#define M32R_ICU_CR55_PORTL (0x2D8+M32R_ICU_OFFSET) /* SIO3 */
200#define M32R_ICU_CR56_PORTL (0x2DC+M32R_ICU_OFFSET) /* SIO4 */
201#define M32R_ICU_CR57_PORTL (0x2E0+M32R_ICU_OFFSET) /* SIO4 */
202
203#ifdef CONFIG_SMP
204#define M32R_ICU_IPICR0_PORTL (0x2dc+M32R_ICU_OFFSET) /* IPI0 */
205#define M32R_ICU_IPICR1_PORTL (0x2e0+M32R_ICU_OFFSET) /* IPI1 */
206#define M32R_ICU_IPICR2_PORTL (0x2e4+M32R_ICU_OFFSET) /* IPI2 */
207#define M32R_ICU_IPICR3_PORTL (0x2e8+M32R_ICU_OFFSET) /* IPI3 */
208#define M32R_ICU_IPICR4_PORTL (0x2ec+M32R_ICU_OFFSET) /* IPI4 */
209#define M32R_ICU_IPICR5_PORTL (0x2f0+M32R_ICU_OFFSET) /* IPI5 */
210#define M32R_ICU_IPICR6_PORTL (0x2f4+M32R_ICU_OFFSET) /* IPI6 */
211#define M32R_ICU_IPICR7_PORTL (0x2f8+M32R_ICU_OFFSET) /* IPI7 */
212#endif /* CONFIG_SMP */
213
214#define M32R_ICUIMASK_IMSK0 (0UL<<16) /* b13-b15: Disable interrupt */
215#define M32R_ICUIMASK_IMSK1 (1UL<<16) /* b13-b15: Enable level 0 interrupt */
216#define M32R_ICUIMASK_IMSK2 (2UL<<16) /* b13-b15: Enable level 0,1 interrupt */
217#define M32R_ICUIMASK_IMSK3 (3UL<<16) /* b13-b15: Enable level 0-2 interrupt */
218#define M32R_ICUIMASK_IMSK4 (4UL<<16) /* b13-b15: Enable level 0-3 interrupt */
219#define M32R_ICUIMASK_IMSK5 (5UL<<16) /* b13-b15: Enable level 0-4 interrupt */
220#define M32R_ICUIMASK_IMSK6 (6UL<<16) /* b13-b15: Enable level 0-5 interrupt */
221#define M32R_ICUIMASK_IMSK7 (7UL<<16) /* b13-b15: Enable level 0-6 interrupt */
222
223#define M32R_ICUCR_IEN (1UL<<12) /* b19: Interrupt enable */
224#define M32R_ICUCR_IRQ (1UL<<8) /* b23: Interrupt request */
225#define M32R_ICUCR_ISMOD00 (0UL<<4) /* b26-b27: Interrupt sense mode Edge HtoL */
226#define M32R_ICUCR_ISMOD01 (1UL<<4) /* b26-b27: Interrupt sense mode Level L */
227#define M32R_ICUCR_ISMOD10 (2UL<<4) /* b26-b27: Interrupt sense mode Edge LtoH*/
228#define M32R_ICUCR_ISMOD11 (3UL<<4) /* b26-b27: Interrupt sense mode Level H */
229#define M32R_ICUCR_ILEVEL0 (0UL<<0) /* b29-b31: Interrupt priority level 0 */
230#define M32R_ICUCR_ILEVEL1 (1UL<<0) /* b29-b31: Interrupt priority level 1 */
231#define M32R_ICUCR_ILEVEL2 (2UL<<0) /* b29-b31: Interrupt priority level 2 */
232#define M32R_ICUCR_ILEVEL3 (3UL<<0) /* b29-b31: Interrupt priority level 3 */
233#define M32R_ICUCR_ILEVEL4 (4UL<<0) /* b29-b31: Interrupt priority level 4 */
234#define M32R_ICUCR_ILEVEL5 (5UL<<0) /* b29-b31: Interrupt priority level 5 */
235#define M32R_ICUCR_ILEVEL6 (6UL<<0) /* b29-b31: Interrupt priority level 6 */
236#define M32R_ICUCR_ILEVEL7 (7UL<<0) /* b29-b31: Disable interrupt */
237
238#define M32R_IRQ_INT0 (1) /* INT0 */
239#define M32R_IRQ_INT1 (2) /* INT1 */
240#define M32R_IRQ_INT2 (3) /* INT2 */
241#define M32R_IRQ_INT3 (4) /* INT3 */
242#define M32R_IRQ_INT4 (5) /* INT4 */
243#define M32R_IRQ_INT5 (6) /* INT5 */
244#define M32R_IRQ_INT6 (7) /* INT6 */
245#define M32R_IRQ_MFT0 (16) /* MFT0 */
246#define M32R_IRQ_MFT1 (17) /* MFT1 */
247#define M32R_IRQ_MFT2 (18) /* MFT2 */
248#define M32R_IRQ_MFT3 (19) /* MFT3 */
249#ifdef CONFIG_CHIP_M32104
250#define M32R_IRQ_MFTX0 (24) /* MFTX0 */
251#define M32R_IRQ_MFTX1 (25) /* MFTX1 */
252#define M32R_IRQ_DMA0 (32) /* DMA0 */
253#define M32R_IRQ_DMA1 (33) /* DMA1 */
254#define M32R_IRQ_DMA2 (34) /* DMA2 */
255#define M32R_IRQ_DMA3 (35) /* DMA3 */
256#define M32R_IRQ_SIO0_R (40) /* SIO0 send */
257#define M32R_IRQ_SIO0_S (41) /* SIO0 receive */
258#define M32R_IRQ_SIO1_R (42) /* SIO1 send */
259#define M32R_IRQ_SIO1_S (43) /* SIO1 receive */
260#define M32R_IRQ_SIO2_R (44) /* SIO2 send */
261#define M32R_IRQ_SIO2_S (45) /* SIO2 receive */
262#define M32R_IRQ_SIO3_R (46) /* SIO3 send */
263#define M32R_IRQ_SIO3_S (47) /* SIO3 receive */
264#define M32R_IRQ_ADC (56) /* ADC */
265#define M32R_IRQ_PC (57) /* PC */
266#else /* ! M32104 */
267#define M32R_IRQ_DMA0 (32) /* DMA0 */
268#define M32R_IRQ_DMA1 (33) /* DMA1 */
269#define M32R_IRQ_SIO0_R (48) /* SIO0 send */
270#define M32R_IRQ_SIO0_S (49) /* SIO0 receive */
271#define M32R_IRQ_SIO1_R (50) /* SIO1 send */
272#define M32R_IRQ_SIO1_S (51) /* SIO1 receive */
273#define M32R_IRQ_SIO2_R (52) /* SIO2 send */
274#define M32R_IRQ_SIO2_S (53) /* SIO2 receive */
275#define M32R_IRQ_SIO3_R (54) /* SIO3 send */
276#define M32R_IRQ_SIO3_S (55) /* SIO3 receive */
277#define M32R_IRQ_SIO4_R (56) /* SIO4 send */
278#define M32R_IRQ_SIO4_S (57) /* SIO4 receive */
279#endif /* ! M32104 */
280
281#ifdef CONFIG_SMP
282#define M32R_IRQ_IPI0 (56)
283#define M32R_IRQ_IPI1 (57)
284#define M32R_IRQ_IPI2 (58)
285#define M32R_IRQ_IPI3 (59)
286#define M32R_IRQ_IPI4 (60)
287#define M32R_IRQ_IPI5 (61)
288#define M32R_IRQ_IPI6 (62)
289#define M32R_IRQ_IPI7 (63)
290#define M32R_CPUID_PORTL (0xffffffe0)
291
292#define M32R_FPGA_TOP (0x000F0000+M32R_SFR_OFFSET)
293
294#define M32R_FPGA_NUM_OF_CPUS_PORTL (0x00+M32R_FPGA_TOP)
295#define M32R_FPGA_CPU_NAME0_PORTL (0x10+M32R_FPGA_TOP)
296#define M32R_FPGA_CPU_NAME1_PORTL (0x14+M32R_FPGA_TOP)
297#define M32R_FPGA_CPU_NAME2_PORTL (0x18+M32R_FPGA_TOP)
298#define M32R_FPGA_CPU_NAME3_PORTL (0x1c+M32R_FPGA_TOP)
299#define M32R_FPGA_MODEL_ID0_PORTL (0x20+M32R_FPGA_TOP)
300#define M32R_FPGA_MODEL_ID1_PORTL (0x24+M32R_FPGA_TOP)
301#define M32R_FPGA_MODEL_ID2_PORTL (0x28+M32R_FPGA_TOP)
302#define M32R_FPGA_MODEL_ID3_PORTL (0x2c+M32R_FPGA_TOP)
303#define M32R_FPGA_VERSION0_PORTL (0x30+M32R_FPGA_TOP)
304#define M32R_FPGA_VERSION1_PORTL (0x34+M32R_FPGA_TOP)
305
306#endif /* CONFIG_SMP */
307
308#ifndef __ASSEMBLY__
309typedef struct {
310 unsigned long icucr; /* ICU Control Register */
311} icu_data_t;
312#endif
313
314#endif /* _M32102_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 04:40:23 -0500