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Diffstat (limited to 'include/asm-m32r/m32102.h')
-rw-r--r--include/asm-m32r/m32102.h38
1 files changed, 28 insertions, 10 deletions
diff --git a/include/asm-m32r/m32102.h b/include/asm-m32r/m32102.h
index cb98101f4f6e..a1f0d1fe9eb8 100644
--- a/include/asm-m32r/m32102.h
+++ b/include/asm-m32r/m32102.h
@@ -11,7 +11,11 @@
11/*======================================================================* 11/*======================================================================*
12 * Special Function Register 12 * Special Function Register
13 *======================================================================*/ 13 *======================================================================*/
14#if !defined(CONFIG_CHIP_M32104)
14#define M32R_SFR_OFFSET (0x00E00000) /* 0x00E00000-0x00EFFFFF 1[MB] */ 15#define M32R_SFR_OFFSET (0x00E00000) /* 0x00E00000-0x00EFFFFF 1[MB] */
16#else
17#define M32R_SFR_OFFSET (0x00700000) /* 0x00700000-0x007FFFFF 1[MB] */
18#endif
15 19
16/* 20/*
17 * Clock and Power Management registers. 21 * Clock and Power Management registers.
@@ -100,7 +104,7 @@
100#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */ 104#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */
101#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */ 105#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */
102 106
103#ifdef CONFIG_CHIP_M32700 107#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32104)
104#define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */ 108#define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */
105#define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */ 109#define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */
106#define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */ 110#define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */
@@ -113,7 +117,7 @@
113#define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */ 117#define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */
114#define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */ 118#define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */
115#define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */ 119#define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */
116#else /* not CONFIG_CHIP_M32700 */ 120#else /* not CONFIG_CHIP_M32700 && not CONFIG_CHIP_M32104 */
117#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */ 121#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */
118#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */ 122#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */
119#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */ 123#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */
@@ -126,7 +130,7 @@
126#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */ 130#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */
127#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */ 131#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */
128#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */ 132#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */
129#endif /* not CONFIG_CHIP_M32700 */ 133#endif /* not CONFIG_CHIP_M32700 && not CONFIG_CHIP_M32104 */
130 134
131#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */ 135#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */
132#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */ 136#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */
@@ -241,8 +245,24 @@
241#define M32R_IRQ_MFT1 (17) /* MFT1 */ 245#define M32R_IRQ_MFT1 (17) /* MFT1 */
242#define M32R_IRQ_MFT2 (18) /* MFT2 */ 246#define M32R_IRQ_MFT2 (18) /* MFT2 */
243#define M32R_IRQ_MFT3 (19) /* MFT3 */ 247#define M32R_IRQ_MFT3 (19) /* MFT3 */
244#define M32R_IRQ_MFT4 (20) /* MFT4 */ 248#ifdef CONFIG_CHIP_M32104
245#define M32R_IRQ_MFT5 (21) /* MFT5 */ 249#define M32R_IRQ_MFTX0 (24) /* MFTX0 */
250#define M32R_IRQ_MFTX1 (25) /* MFTX1 */
251#define M32R_IRQ_DMA0 (32) /* DMA0 */
252#define M32R_IRQ_DMA1 (33) /* DMA1 */
253#define M32R_IRQ_DMA2 (34) /* DMA2 */
254#define M32R_IRQ_DMA3 (35) /* DMA3 */
255#define M32R_IRQ_SIO0_R (40) /* SIO0 send */
256#define M32R_IRQ_SIO0_S (41) /* SIO0 receive */
257#define M32R_IRQ_SIO1_R (42) /* SIO1 send */
258#define M32R_IRQ_SIO1_S (43) /* SIO1 receive */
259#define M32R_IRQ_SIO2_R (44) /* SIO2 send */
260#define M32R_IRQ_SIO2_S (45) /* SIO2 receive */
261#define M32R_IRQ_SIO3_R (46) /* SIO3 send */
262#define M32R_IRQ_SIO3_S (47) /* SIO3 receive */
263#define M32R_IRQ_ADC (56) /* ADC */
264#define M32R_IRQ_PC (57) /* PC */
265#else /* ! M32104 */
246#define M32R_IRQ_DMA0 (32) /* DMA0 */ 266#define M32R_IRQ_DMA0 (32) /* DMA0 */
247#define M32R_IRQ_DMA1 (33) /* DMA1 */ 267#define M32R_IRQ_DMA1 (33) /* DMA1 */
248#define M32R_IRQ_SIO0_R (48) /* SIO0 send */ 268#define M32R_IRQ_SIO0_R (48) /* SIO0 send */
@@ -255,6 +275,7 @@
255#define M32R_IRQ_SIO3_S (55) /* SIO3 receive */ 275#define M32R_IRQ_SIO3_S (55) /* SIO3 receive */
256#define M32R_IRQ_SIO4_R (56) /* SIO4 send */ 276#define M32R_IRQ_SIO4_R (56) /* SIO4 send */
257#define M32R_IRQ_SIO4_S (57) /* SIO4 receive */ 277#define M32R_IRQ_SIO4_S (57) /* SIO4 receive */
278#endif /* ! M32104 */
258 279
259#ifdef CONFIG_SMP 280#ifdef CONFIG_SMP
260#define M32R_IRQ_IPI0 (56) 281#define M32R_IRQ_IPI0 (56)
@@ -281,15 +302,12 @@
281#define M32R_FPGA_VERSION0_PORTL (0x30+M32R_FPGA_TOP) 302#define M32R_FPGA_VERSION0_PORTL (0x30+M32R_FPGA_TOP)
282#define M32R_FPGA_VERSION1_PORTL (0x34+M32R_FPGA_TOP) 303#define M32R_FPGA_VERSION1_PORTL (0x34+M32R_FPGA_TOP)
283 304
305#endif /* CONFIG_SMP */
306
284#ifndef __ASSEMBLY__ 307#ifndef __ASSEMBLY__
285/* For NETDEV WATCHDOG */
286typedef struct { 308typedef struct {
287 unsigned long icucr; /* ICU Control Register */ 309 unsigned long icucr; /* ICU Control Register */
288} icu_data_t; 310} icu_data_t;
289
290extern icu_data_t icu_data[];
291#endif 311#endif
292 312
293#endif /* CONFIG_SMP */
294
295#endif /* _M32102_H_ */ 313#endif /* _M32102_H_ */