diff options
Diffstat (limited to 'include/asm-ia64')
-rw-r--r-- | include/asm-ia64/io.h | 2 | ||||
-rw-r--r-- | include/asm-ia64/mmu_context.h | 7 | ||||
-rw-r--r-- | include/asm-ia64/page.h | 27 | ||||
-rw-r--r-- | include/asm-ia64/pgtable.h | 13 | ||||
-rw-r--r-- | include/asm-ia64/sn/addrs.h | 33 | ||||
-rw-r--r-- | include/asm-ia64/system.h | 5 |
6 files changed, 45 insertions, 42 deletions
diff --git a/include/asm-ia64/io.h b/include/asm-ia64/io.h index a2f92edd717d..cf772a67f858 100644 --- a/include/asm-ia64/io.h +++ b/include/asm-ia64/io.h | |||
@@ -23,7 +23,7 @@ | |||
23 | #define __SLOW_DOWN_IO do { } while (0) | 23 | #define __SLOW_DOWN_IO do { } while (0) |
24 | #define SLOW_DOWN_IO do { } while (0) | 24 | #define SLOW_DOWN_IO do { } while (0) |
25 | 25 | ||
26 | #define __IA64_UNCACHED_OFFSET 0xc000000000000000UL /* region 6 */ | 26 | #define __IA64_UNCACHED_OFFSET RGN_BASE(RGN_UNCACHED) |
27 | 27 | ||
28 | /* | 28 | /* |
29 | * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but | 29 | * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but |
diff --git a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h index 0680d163be97..8d6e72f7b08e 100644 --- a/include/asm-ia64/mmu_context.h +++ b/include/asm-ia64/mmu_context.h | |||
@@ -19,6 +19,7 @@ | |||
19 | 19 | ||
20 | #define ia64_rid(ctx,addr) (((ctx) << 3) | (addr >> 61)) | 20 | #define ia64_rid(ctx,addr) (((ctx) << 3) | (addr >> 61)) |
21 | 21 | ||
22 | # include <asm/page.h> | ||
22 | # ifndef __ASSEMBLY__ | 23 | # ifndef __ASSEMBLY__ |
23 | 24 | ||
24 | #include <linux/compiler.h> | 25 | #include <linux/compiler.h> |
@@ -122,7 +123,7 @@ reload_context (nv_mm_context_t context) | |||
122 | unsigned long rid_incr = 0; | 123 | unsigned long rid_incr = 0; |
123 | unsigned long rr0, rr1, rr2, rr3, rr4, old_rr4; | 124 | unsigned long rr0, rr1, rr2, rr3, rr4, old_rr4; |
124 | 125 | ||
125 | old_rr4 = ia64_get_rr(0x8000000000000000UL); | 126 | old_rr4 = ia64_get_rr(RGN_BASE(RGN_HPAGE)); |
126 | rid = context << 3; /* make space for encoding the region number */ | 127 | rid = context << 3; /* make space for encoding the region number */ |
127 | rid_incr = 1 << 8; | 128 | rid_incr = 1 << 8; |
128 | 129 | ||
@@ -134,6 +135,10 @@ reload_context (nv_mm_context_t context) | |||
134 | rr4 = rr0 + 4*rid_incr; | 135 | rr4 = rr0 + 4*rid_incr; |
135 | #ifdef CONFIG_HUGETLB_PAGE | 136 | #ifdef CONFIG_HUGETLB_PAGE |
136 | rr4 = (rr4 & (~(0xfcUL))) | (old_rr4 & 0xfc); | 137 | rr4 = (rr4 & (~(0xfcUL))) | (old_rr4 & 0xfc); |
138 | |||
139 | # if RGN_HPAGE != 4 | ||
140 | # error "reload_context assumes RGN_HPAGE is 4" | ||
141 | # endif | ||
137 | #endif | 142 | #endif |
138 | 143 | ||
139 | ia64_set_rr(0x0000000000000000UL, rr0); | 144 | ia64_set_rr(0x0000000000000000UL, rr0); |
diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h index 08894f73abf0..9edffad8c28b 100644 --- a/include/asm-ia64/page.h +++ b/include/asm-ia64/page.h | |||
@@ -13,6 +13,19 @@ | |||
13 | #include <asm/types.h> | 13 | #include <asm/types.h> |
14 | 14 | ||
15 | /* | 15 | /* |
16 | * The top three bits of an IA64 address are its Region Number. | ||
17 | * Different regions are assigned to different purposes. | ||
18 | */ | ||
19 | #define RGN_SHIFT (61) | ||
20 | #define RGN_BASE(r) (__IA64_UL_CONST(r)<<RGN_SHIFT) | ||
21 | #define RGN_BITS (RGN_BASE(-1)) | ||
22 | |||
23 | #define RGN_KERNEL 7 /* Identity mapped region */ | ||
24 | #define RGN_UNCACHED 6 /* Identity mapped I/O region */ | ||
25 | #define RGN_GATE 5 /* Gate page, Kernel text, etc */ | ||
26 | #define RGN_HPAGE 4 /* For Huge TLB pages */ | ||
27 | |||
28 | /* | ||
16 | * PAGE_SHIFT determines the actual kernel page size. | 29 | * PAGE_SHIFT determines the actual kernel page size. |
17 | */ | 30 | */ |
18 | #if defined(CONFIG_IA64_PAGE_SIZE_4KB) | 31 | #if defined(CONFIG_IA64_PAGE_SIZE_4KB) |
@@ -36,10 +49,9 @@ | |||
36 | 49 | ||
37 | #define RGN_MAP_LIMIT ((1UL << (4*PAGE_SHIFT - 12)) - PAGE_SIZE) /* per region addr limit */ | 50 | #define RGN_MAP_LIMIT ((1UL << (4*PAGE_SHIFT - 12)) - PAGE_SIZE) /* per region addr limit */ |
38 | 51 | ||
52 | |||
39 | #ifdef CONFIG_HUGETLB_PAGE | 53 | #ifdef CONFIG_HUGETLB_PAGE |
40 | # define REGION_HPAGE (4UL) /* note: this is hardcoded in reload_context()!*/ | 54 | # define HPAGE_REGION_BASE RGN_BASE(RGN_HPAGE) |
41 | # define REGION_SHIFT 61 | ||
42 | # define HPAGE_REGION_BASE (REGION_HPAGE << REGION_SHIFT) | ||
43 | # define HPAGE_SHIFT hpage_shift | 55 | # define HPAGE_SHIFT hpage_shift |
44 | # define HPAGE_SHIFT_DEFAULT 28 /* check ia64 SDM for architecture supported size */ | 56 | # define HPAGE_SHIFT_DEFAULT 28 /* check ia64 SDM for architecture supported size */ |
45 | # define HPAGE_SIZE (__IA64_UL_CONST(1) << HPAGE_SHIFT) | 57 | # define HPAGE_SIZE (__IA64_UL_CONST(1) << HPAGE_SHIFT) |
@@ -130,16 +142,13 @@ typedef union ia64_va { | |||
130 | #define REGION_NUMBER(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg;}) | 142 | #define REGION_NUMBER(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg;}) |
131 | #define REGION_OFFSET(x) ({ia64_va _v; _v.l = (long) (x); _v.f.off;}) | 143 | #define REGION_OFFSET(x) ({ia64_va _v; _v.l = (long) (x); _v.f.off;}) |
132 | 144 | ||
133 | #define REGION_SIZE REGION_NUMBER(1) | ||
134 | #define REGION_KERNEL 7 | ||
135 | |||
136 | #ifdef CONFIG_HUGETLB_PAGE | 145 | #ifdef CONFIG_HUGETLB_PAGE |
137 | # define htlbpage_to_page(x) (((unsigned long) REGION_NUMBER(x) << 61) \ | 146 | # define htlbpage_to_page(x) (((unsigned long) REGION_NUMBER(x) << 61) \ |
138 | | (REGION_OFFSET(x) >> (HPAGE_SHIFT-PAGE_SHIFT))) | 147 | | (REGION_OFFSET(x) >> (HPAGE_SHIFT-PAGE_SHIFT))) |
139 | # define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) | 148 | # define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) |
140 | # define is_hugepage_only_range(mm, addr, len) \ | 149 | # define is_hugepage_only_range(mm, addr, len) \ |
141 | (REGION_NUMBER(addr) == REGION_HPAGE && \ | 150 | (REGION_NUMBER(addr) == RGN_HPAGE && \ |
142 | REGION_NUMBER((addr)+(len)-1) == REGION_HPAGE) | 151 | REGION_NUMBER((addr)+(len)-1) == RGN_HPAGE) |
143 | extern unsigned int hpage_shift; | 152 | extern unsigned int hpage_shift; |
144 | #endif | 153 | #endif |
145 | 154 | ||
@@ -197,7 +206,7 @@ get_order (unsigned long size) | |||
197 | # define __pgprot(x) (x) | 206 | # define __pgprot(x) (x) |
198 | #endif /* !STRICT_MM_TYPECHECKS */ | 207 | #endif /* !STRICT_MM_TYPECHECKS */ |
199 | 208 | ||
200 | #define PAGE_OFFSET __IA64_UL_CONST(0xe000000000000000) | 209 | #define PAGE_OFFSET RGN_BASE(RGN_KERNEL) |
201 | 210 | ||
202 | #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | \ | 211 | #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | \ |
203 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC | \ | 212 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC | \ |
diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h index 48586e08f432..2e34c06e6777 100644 --- a/include/asm-ia64/pgtable.h +++ b/include/asm-ia64/pgtable.h | |||
@@ -204,21 +204,18 @@ ia64_phys_addr_valid (unsigned long addr) | |||
204 | #define set_pte(ptep, pteval) (*(ptep) = (pteval)) | 204 | #define set_pte(ptep, pteval) (*(ptep) = (pteval)) |
205 | #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) | 205 | #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) |
206 | 206 | ||
207 | #define RGN_SIZE (1UL << 61) | 207 | #define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL) |
208 | #define RGN_KERNEL 7 | ||
209 | |||
210 | #define VMALLOC_START 0xa000000200000000UL | ||
211 | #ifdef CONFIG_VIRTUAL_MEM_MAP | 208 | #ifdef CONFIG_VIRTUAL_MEM_MAP |
212 | # define VMALLOC_END_INIT (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9))) | 209 | # define VMALLOC_END_INIT (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9))) |
213 | # define VMALLOC_END vmalloc_end | 210 | # define VMALLOC_END vmalloc_end |
214 | extern unsigned long vmalloc_end; | 211 | extern unsigned long vmalloc_end; |
215 | #else | 212 | #else |
216 | # define VMALLOC_END (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9))) | 213 | # define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9))) |
217 | #endif | 214 | #endif |
218 | 215 | ||
219 | /* fs/proc/kcore.c */ | 216 | /* fs/proc/kcore.c */ |
220 | #define kc_vaddr_to_offset(v) ((v) - 0xa000000000000000UL) | 217 | #define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE)) |
221 | #define kc_offset_to_vaddr(o) ((o) + 0xa000000000000000UL) | 218 | #define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE)) |
222 | 219 | ||
223 | /* | 220 | /* |
224 | * Conversion functions: convert page frame number (pfn) and a protection value to a page | 221 | * Conversion functions: convert page frame number (pfn) and a protection value to a page |
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h index 8881882ccafb..5b7823d57d4a 100644 --- a/include/asm-ia64/sn/addrs.h +++ b/include/asm-ia64/sn/addrs.h | |||
@@ -65,7 +65,6 @@ | |||
65 | 65 | ||
66 | #define NASID_MASK ((u64)NASID_BITMASK << NASID_SHIFT) | 66 | #define NASID_MASK ((u64)NASID_BITMASK << NASID_SHIFT) |
67 | #define AS_MASK ((u64)AS_BITMASK << AS_SHIFT) | 67 | #define AS_MASK ((u64)AS_BITMASK << AS_SHIFT) |
68 | #define REGION_BITS 0xe000000000000000UL | ||
69 | 68 | ||
70 | 69 | ||
71 | /* | 70 | /* |
@@ -79,38 +78,30 @@ | |||
79 | #define AS_CAC_SPACE (AS_CAC_VAL << AS_SHIFT) | 78 | #define AS_CAC_SPACE (AS_CAC_VAL << AS_SHIFT) |
80 | 79 | ||
81 | 80 | ||
82 | /* | ||
83 | * Base addresses for various address ranges. | ||
84 | */ | ||
85 | #define CACHED 0xe000000000000000UL | ||
86 | #define UNCACHED 0xc000000000000000UL | ||
87 | #define UNCACHED_PHYS 0x8000000000000000UL | ||
88 | |||
89 | |||
90 | /* | 81 | /* |
91 | * Virtual Mode Local & Global MMR space. | 82 | * Virtual Mode Local & Global MMR space. |
92 | */ | 83 | */ |
93 | #define SH1_LOCAL_MMR_OFFSET 0x8000000000UL | 84 | #define SH1_LOCAL_MMR_OFFSET 0x8000000000UL |
94 | #define SH2_LOCAL_MMR_OFFSET 0x0200000000UL | 85 | #define SH2_LOCAL_MMR_OFFSET 0x0200000000UL |
95 | #define LOCAL_MMR_OFFSET (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET) | 86 | #define LOCAL_MMR_OFFSET (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET) |
96 | #define LOCAL_MMR_SPACE (UNCACHED | LOCAL_MMR_OFFSET) | 87 | #define LOCAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET) |
97 | #define LOCAL_PHYS_MMR_SPACE (UNCACHED_PHYS | LOCAL_MMR_OFFSET) | 88 | #define LOCAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET) |
98 | 89 | ||
99 | #define SH1_GLOBAL_MMR_OFFSET 0x0800000000UL | 90 | #define SH1_GLOBAL_MMR_OFFSET 0x0800000000UL |
100 | #define SH2_GLOBAL_MMR_OFFSET 0x0300000000UL | 91 | #define SH2_GLOBAL_MMR_OFFSET 0x0300000000UL |
101 | #define GLOBAL_MMR_OFFSET (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET) | 92 | #define GLOBAL_MMR_OFFSET (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET) |
102 | #define GLOBAL_MMR_SPACE (UNCACHED | GLOBAL_MMR_OFFSET) | 93 | #define GLOBAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET) |
103 | 94 | ||
104 | /* | 95 | /* |
105 | * Physical mode addresses | 96 | * Physical mode addresses |
106 | */ | 97 | */ |
107 | #define GLOBAL_PHYS_MMR_SPACE (UNCACHED_PHYS | GLOBAL_MMR_OFFSET) | 98 | #define GLOBAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET) |
108 | 99 | ||
109 | 100 | ||
110 | /* | 101 | /* |
111 | * Clear region & AS bits. | 102 | * Clear region & AS bits. |
112 | */ | 103 | */ |
113 | #define TO_PHYS_MASK (~(REGION_BITS | AS_MASK)) | 104 | #define TO_PHYS_MASK (~(RGN_BITS | AS_MASK)) |
114 | 105 | ||
115 | 106 | ||
116 | /* | 107 | /* |
@@ -135,10 +126,10 @@ | |||
135 | /* | 126 | /* |
136 | * general address defines | 127 | * general address defines |
137 | */ | 128 | */ |
138 | #define CAC_BASE (CACHED | AS_CAC_SPACE) | 129 | #define CAC_BASE (PAGE_OFFSET | AS_CAC_SPACE) |
139 | #define AMO_BASE (UNCACHED | AS_AMO_SPACE) | 130 | #define AMO_BASE (__IA64_UNCACHED_OFFSET | AS_AMO_SPACE) |
140 | #define AMO_PHYS_BASE (UNCACHED_PHYS | AS_AMO_SPACE) | 131 | #define AMO_PHYS_BASE (RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE) |
141 | #define GET_BASE (CACHED | AS_GET_SPACE) | 132 | #define GET_BASE (PAGE_OFFSET | AS_GET_SPACE) |
142 | 133 | ||
143 | /* | 134 | /* |
144 | * Convert Memory addresses between various addressing modes. | 135 | * Convert Memory addresses between various addressing modes. |
@@ -183,8 +174,8 @@ | |||
183 | /* | 174 | /* |
184 | * Macros to test for address type. | 175 | * Macros to test for address type. |
185 | */ | 176 | */ |
186 | #define IS_AMO_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_BASE) | 177 | #define IS_AMO_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE) |
187 | #define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_PHYS_BASE) | 178 | #define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE) |
188 | 179 | ||
189 | 180 | ||
190 | /* | 181 | /* |
@@ -199,7 +190,7 @@ | |||
199 | #define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \ | 190 | #define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \ |
200 | ((u64) (w) << TIO_SWIN_SIZE_BITS)) | 191 | ((u64) (w) << TIO_SWIN_SIZE_BITS)) |
201 | #define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n)) | 192 | #define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n)) |
202 | #define TIO_IO_BASE(n) (UNCACHED | NASID_SPACE(n)) | 193 | #define TIO_IO_BASE(n) (__IA64_UNCACHED_OFFSET | NASID_SPACE(n)) |
203 | #define BWIN_SIZE (1UL << BWIN_SIZE_BITS) | 194 | #define BWIN_SIZE (1UL << BWIN_SIZE_BITS) |
204 | #define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE) | 195 | #define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE) |
205 | #define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS)) | 196 | #define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS)) |
diff --git a/include/asm-ia64/system.h b/include/asm-ia64/system.h index cd2cf76b2db1..33256db4a7cf 100644 --- a/include/asm-ia64/system.h +++ b/include/asm-ia64/system.h | |||
@@ -19,12 +19,13 @@ | |||
19 | #include <asm/pal.h> | 19 | #include <asm/pal.h> |
20 | #include <asm/percpu.h> | 20 | #include <asm/percpu.h> |
21 | 21 | ||
22 | #define GATE_ADDR __IA64_UL_CONST(0xa000000000000000) | 22 | #define GATE_ADDR RGN_BASE(RGN_GATE) |
23 | |||
23 | /* | 24 | /* |
24 | * 0xa000000000000000+2*PERCPU_PAGE_SIZE | 25 | * 0xa000000000000000+2*PERCPU_PAGE_SIZE |
25 | * - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page) | 26 | * - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page) |
26 | */ | 27 | */ |
27 | #define KERNEL_START __IA64_UL_CONST(0xa000000100000000) | 28 | #define KERNEL_START (GATE_ADDR+0x100000000) |
28 | #define PERCPU_ADDR (-PERCPU_PAGE_SIZE) | 29 | #define PERCPU_ADDR (-PERCPU_PAGE_SIZE) |
29 | 30 | ||
30 | #ifndef __ASSEMBLY__ | 31 | #ifndef __ASSEMBLY__ |