2 files changed, 29 insertions, 0 deletions

diff --git a/include/asm-ia64/kregs.h b/include/asm-ia64/kregs.h
index 7e55a584975c..aefcdfee7f23 100644
--- a/include/asm-ia64/kregs.h
+++ b/include/asm-ia64/kregs.h
@@ -31,6 +31,9 @@
 #define IA64_TR_PALCODE         1       /* itr1: maps PALcode as required by EFI */
 #define IA64_TR_CURRENT_STACK   1       /* dtr1: maps kernel's memory- & register-stacks */
 
+#define IA64_TR_ALLOC_BASE      2       /* itr&dtr: Base of dynamic TR resource*/
+#define IA64_TR_ALLOC_MAX       32      /* Max number for dynamic use*/
+
 /* Processor status register bits: */
 #define IA64_PSR_BE_BIT         1
 #define IA64_PSR_UP_BIT         2
diff --git a/include/asm-ia64/tlb.h b/include/asm-ia64/tlb.h
index 26edcb750f9f..20d8a39680c2 100644
--- a/include/asm-ia64/tlb.h
+++ b/include/asm-ia64/tlb.h
@@ -64,6 +64,32 @@ struct mmu_gather {
         struct page             *pages[FREE_PTE_NR];
 };
 
+struct ia64_tr_entry {
+        u64 ifa;
+        u64 itir;
+        u64 pte;
+        u64 rr;
+}; /*Record for tr entry!*/
+
+extern int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size);
+extern void ia64_ptr_entry(u64 target_mask, int slot);
+
+extern struct ia64_tr_entry __per_cpu_idtrs[NR_CPUS][2][IA64_TR_ALLOC_MAX];
+
+/*
+ region register macros
+*/
+#define RR_TO_VE(val)   (((val) >> 0) & 0x0000000000000001)
+#define RR_VE(val)      (((val) & 0x0000000000000001) << 0)
+#define RR_VE_MASK      0x0000000000000001L
+#define RR_VE_SHIFT     0
+#define RR_TO_PS(val)   (((val) >> 2) & 0x000000000000003f)
+#define RR_PS(val)      (((val) & 0x000000000000003f) << 2)
+#define RR_PS_MASK      0x00000000000000fcL
+#define RR_PS_SHIFT     2
+#define RR_RID_MASK     0x00000000ffffff00L
+#define RR_TO_RID(val)  ((val >> 8) & 0xffffff)
+
 /* Users of the generic TLB shootdown code must declare this storage space. */
 DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);