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-rw-r--r--include/asm-ia64/uv/uv_mmrs.h266
1 files changed, 266 insertions, 0 deletions
diff --git a/include/asm-ia64/uv/uv_mmrs.h b/include/asm-ia64/uv/uv_mmrs.h
new file mode 100644
index 000000000000..1cc1dbb0182f
--- /dev/null
+++ b/include/asm-ia64/uv/uv_mmrs.h
@@ -0,0 +1,266 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV MMR definitions
7 *
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef __ASM_IA64_UV_MMRS__
12#define __ASM_IA64_UV_MMRS__
13
14/*
15 * AUTO GENERATED - Do not edit
16 */
17
18 #define UV_MMR_ENABLE (1UL << 63)
19
20/* ========================================================================= */
21/* UVH_NODE_ID */
22/* ========================================================================= */
23#define UVH_NODE_ID 0x0UL
24
25#define UVH_NODE_ID_FORCE1_SHFT 0
26#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
27#define UVH_NODE_ID_MANUFACTURER_SHFT 1
28#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
29#define UVH_NODE_ID_PART_NUMBER_SHFT 12
30#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
31#define UVH_NODE_ID_REVISION_SHFT 28
32#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
33#define UVH_NODE_ID_NODE_ID_SHFT 32
34#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
35#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
36#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
37#define UVH_NODE_ID_NI_PORT_SHFT 56
38#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
39
40union uvh_node_id_u {
41 unsigned long v;
42 struct uvh_node_id_s {
43 unsigned long force1 : 1; /* RO */
44 unsigned long manufacturer : 11; /* RO */
45 unsigned long part_number : 16; /* RO */
46 unsigned long revision : 4; /* RO */
47 unsigned long node_id : 15; /* RW */
48 unsigned long rsvd_47 : 1; /* */
49 unsigned long nodes_per_bit : 7; /* RW */
50 unsigned long rsvd_55 : 1; /* */
51 unsigned long ni_port : 4; /* RO */
52 unsigned long rsvd_60_63 : 4; /* */
53 } s;
54};
55
56/* ========================================================================= */
57/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
58/* ========================================================================= */
59#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
60
61#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
62#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
63
64union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
65 unsigned long v;
66 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
67 unsigned long rsvd_0_23 : 24; /* */
68 unsigned long dest_base : 22; /* RW */
69 unsigned long rsvd_46_63: 18; /* */
70 } s;
71};
72
73/* ========================================================================= */
74/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
75/* ========================================================================= */
76#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
77
78#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
79#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
80
81union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
82 unsigned long v;
83 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
84 unsigned long rsvd_0_23 : 24; /* */
85 unsigned long dest_base : 22; /* RW */
86 unsigned long rsvd_46_63: 18; /* */
87 } s;
88};
89
90/* ========================================================================= */
91/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
92/* ========================================================================= */
93#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
94
95#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
96#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
97
98union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
99 unsigned long v;
100 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
101 unsigned long rsvd_0_23 : 24; /* */
102 unsigned long dest_base : 22; /* RW */
103 unsigned long rsvd_46_63: 18; /* */
104 } s;
105};
106
107/* ========================================================================= */
108/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
109/* ========================================================================= */
110#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
111
112#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
113#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
114#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 46
115#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0000400000000000UL
116#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
117#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
118#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
119#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
120
121union uvh_rh_gam_gru_overlay_config_mmr_u {
122 unsigned long v;
123 struct uvh_rh_gam_gru_overlay_config_mmr_s {
124 unsigned long rsvd_0_27: 28; /* */
125 unsigned long base : 18; /* RW */
126 unsigned long gr4 : 1; /* RW */
127 unsigned long rsvd_47_51: 5; /* */
128 unsigned long n_gru : 4; /* RW */
129 unsigned long rsvd_56_62: 7; /* */
130 unsigned long enable : 1; /* RW */
131 } s;
132};
133
134/* ========================================================================= */
135/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
136/* ========================================================================= */
137#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
138
139#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
140#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
141#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
142#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
143#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
144#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
145
146union uvh_rh_gam_mmr_overlay_config_mmr_u {
147 unsigned long v;
148 struct uvh_rh_gam_mmr_overlay_config_mmr_s {
149 unsigned long rsvd_0_25: 26; /* */
150 unsigned long base : 20; /* RW */
151 unsigned long dual_hub : 1; /* RW */
152 unsigned long rsvd_47_62: 16; /* */
153 unsigned long enable : 1; /* RW */
154 } s;
155};
156
157/* ========================================================================= */
158/* UVH_RTC */
159/* ========================================================================= */
160#define UVH_RTC 0x28000UL
161
162#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
163#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
164
165union uvh_rtc_u {
166 unsigned long v;
167 struct uvh_rtc_s {
168 unsigned long real_time_clock : 56; /* RW */
169 unsigned long rsvd_56_63 : 8; /* */
170 } s;
171};
172
173/* ========================================================================= */
174/* UVH_SI_ADDR_MAP_CONFIG */
175/* ========================================================================= */
176#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
177
178#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
179#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
180#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
181#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
182
183union uvh_si_addr_map_config_u {
184 unsigned long v;
185 struct uvh_si_addr_map_config_s {
186 unsigned long m_skt : 6; /* RW */
187 unsigned long rsvd_6_7: 2; /* */
188 unsigned long n_skt : 4; /* RW */
189 unsigned long rsvd_12_63: 52; /* */
190 } s;
191};
192
193/* ========================================================================= */
194/* UVH_SI_ALIAS0_OVERLAY_CONFIG */
195/* ========================================================================= */
196#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
197
198#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
199#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
200#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
201#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
202#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
203#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
204
205union uvh_si_alias0_overlay_config_u {
206 unsigned long v;
207 struct uvh_si_alias0_overlay_config_s {
208 unsigned long rsvd_0_23: 24; /* */
209 unsigned long base : 8; /* RW */
210 unsigned long rsvd_32_47: 16; /* */
211 unsigned long m_alias : 5; /* RW */
212 unsigned long rsvd_53_62: 10; /* */
213 unsigned long enable : 1; /* RW */
214 } s;
215};
216
217/* ========================================================================= */
218/* UVH_SI_ALIAS1_OVERLAY_CONFIG */
219/* ========================================================================= */
220#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
221
222#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
223#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
224#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
225#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
226#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
227#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
228
229union uvh_si_alias1_overlay_config_u {
230 unsigned long v;
231 struct uvh_si_alias1_overlay_config_s {
232 unsigned long rsvd_0_23: 24; /* */
233 unsigned long base : 8; /* RW */
234 unsigned long rsvd_32_47: 16; /* */
235 unsigned long m_alias : 5; /* RW */
236 unsigned long rsvd_53_62: 10; /* */
237 unsigned long enable : 1; /* RW */
238 } s;
239};
240
241/* ========================================================================= */
242/* UVH_SI_ALIAS2_OVERLAY_CONFIG */
243/* ========================================================================= */
244#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
245
246#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
247#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
248#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
249#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
250#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
251#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
252
253union uvh_si_alias2_overlay_config_u {
254 unsigned long v;
255 struct uvh_si_alias2_overlay_config_s {
256 unsigned long rsvd_0_23: 24; /* */
257 unsigned long base : 8; /* RW */
258 unsigned long rsvd_32_47: 16; /* */
259 unsigned long m_alias : 5; /* RW */
260 unsigned long rsvd_53_62: 10; /* */
261 unsigned long enable : 1; /* RW */
262 } s;
263};
264
265
266#endif /* __ASM_IA64_UV_MMRS__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-04 03:39:57 -0400