diff options
Diffstat (limited to 'include/asm-ia64/sn')
| -rw-r--r-- | include/asm-ia64/sn/addrs.h | 8 | ||||
| -rw-r--r-- | include/asm-ia64/sn/arch.h | 17 | ||||
| -rw-r--r-- | include/asm-ia64/sn/fetchop.h | 85 | ||||
| -rw-r--r-- | include/asm-ia64/sn/l1.h | 3 | ||||
| -rw-r--r-- | include/asm-ia64/sn/nodepda.h | 15 | ||||
| -rw-r--r-- | include/asm-ia64/sn/pda.h | 9 | ||||
| -rw-r--r-- | include/asm-ia64/sn/shub_mmr.h | 24 | ||||
| -rw-r--r-- | include/asm-ia64/sn/shubio.h | 3116 | ||||
| -rw-r--r-- | include/asm-ia64/sn/sn_cpuid.h | 25 | ||||
| -rw-r--r-- | include/asm-ia64/sn/sn_fru.h | 44 | ||||
| -rw-r--r-- | include/asm-ia64/sn/sn_sal.h | 93 | ||||
| -rw-r--r-- | include/asm-ia64/sn/sndrv.h | 47 | ||||
| -rw-r--r-- | include/asm-ia64/sn/xp.h | 436 |
13 files changed, 2075 insertions, 1847 deletions
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h index 960d626ee589..1bfdfb4d7b01 100644 --- a/include/asm-ia64/sn/addrs.h +++ b/include/asm-ia64/sn/addrs.h | |||
| @@ -136,6 +136,7 @@ | |||
| 136 | */ | 136 | */ |
| 137 | #define CAC_BASE (CACHED | AS_CAC_SPACE) | 137 | #define CAC_BASE (CACHED | AS_CAC_SPACE) |
| 138 | #define AMO_BASE (UNCACHED | AS_AMO_SPACE) | 138 | #define AMO_BASE (UNCACHED | AS_AMO_SPACE) |
| 139 | #define AMO_PHYS_BASE (UNCACHED_PHYS | AS_AMO_SPACE) | ||
| 139 | #define GET_BASE (CACHED | AS_GET_SPACE) | 140 | #define GET_BASE (CACHED | AS_GET_SPACE) |
| 140 | 141 | ||
| 141 | /* | 142 | /* |
| @@ -161,6 +162,13 @@ | |||
| 161 | 162 | ||
| 162 | 163 | ||
| 163 | /* | 164 | /* |
| 165 | * Macros to test for address type. | ||
| 166 | */ | ||
| 167 | #define IS_AMO_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_BASE) | ||
| 168 | #define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_PHYS_BASE) | ||
| 169 | |||
| 170 | |||
| 171 | /* | ||
| 164 | * The following definitions pertain to the IO special address | 172 | * The following definitions pertain to the IO special address |
| 165 | * space. They define the location of the big and little windows | 173 | * space. They define the location of the big and little windows |
| 166 | * of any given node. | 174 | * of any given node. |
diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h index 7c349f07916a..635fdce854a8 100644 --- a/include/asm-ia64/sn/arch.h +++ b/include/asm-ia64/sn/arch.h | |||
| @@ -5,7 +5,7 @@ | |||
| 5 | * | 5 | * |
| 6 | * SGI specific setup. | 6 | * SGI specific setup. |
| 7 | * | 7 | * |
| 8 | * Copyright (C) 1995-1997,1999,2001-2004 Silicon Graphics, Inc. All rights reserved. | 8 | * Copyright (C) 1995-1997,1999,2001-2005 Silicon Graphics, Inc. All rights reserved. |
| 9 | * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) | 9 | * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) |
| 10 | */ | 10 | */ |
| 11 | #ifndef _ASM_IA64_SN_ARCH_H | 11 | #ifndef _ASM_IA64_SN_ARCH_H |
| @@ -47,6 +47,21 @@ DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info); | |||
| 47 | #define MAX_COMPACT_NODES 2048 | 47 | #define MAX_COMPACT_NODES 2048 |
| 48 | #define CPUS_PER_NODE 4 | 48 | #define CPUS_PER_NODE 4 |
| 49 | 49 | ||
| 50 | |||
| 51 | /* | ||
| 52 | * Compact node ID to nasid mappings kept in the per-cpu data areas of each | ||
| 53 | * cpu. | ||
| 54 | */ | ||
| 55 | DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_NUMNODES]); | ||
| 56 | #define sn_cnodeid_to_nasid (&__get_cpu_var(__sn_cnodeid_to_nasid[0])) | ||
| 57 | |||
| 58 | |||
| 59 | |||
| 60 | extern u8 sn_partition_id; | ||
| 61 | extern u8 sn_system_size; | ||
| 62 | extern u8 sn_sharing_domain_size; | ||
| 63 | extern u8 sn_region_size; | ||
| 64 | |||
| 50 | extern void sn_flush_all_caches(long addr, long bytes); | 65 | extern void sn_flush_all_caches(long addr, long bytes); |
| 51 | 66 | ||
| 52 | #endif /* _ASM_IA64_SN_ARCH_H */ | 67 | #endif /* _ASM_IA64_SN_ARCH_H */ |
diff --git a/include/asm-ia64/sn/fetchop.h b/include/asm-ia64/sn/fetchop.h deleted file mode 100644 index 5f4ad8f4b5d2..000000000000 --- a/include/asm-ia64/sn/fetchop.h +++ /dev/null | |||
| @@ -1,85 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 4 | * License. See the file "COPYING" in the main directory of this archive | ||
| 5 | * for more details. | ||
| 6 | * | ||
| 7 | * Copyright (c) 2001-2004 Silicon Graphics, Inc. All rights reserved. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef _ASM_IA64_SN_FETCHOP_H | ||
| 11 | #define _ASM_IA64_SN_FETCHOP_H | ||
| 12 | |||
| 13 | #include <linux/config.h> | ||
| 14 | |||
| 15 | #define FETCHOP_BASENAME "sgi_fetchop" | ||
| 16 | #define FETCHOP_FULLNAME "/dev/sgi_fetchop" | ||
| 17 | |||
| 18 | |||
| 19 | |||
| 20 | #define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */ | ||
| 21 | |||
| 22 | #define FETCHOP_LOAD 0 | ||
| 23 | #define FETCHOP_INCREMENT 8 | ||
| 24 | #define FETCHOP_DECREMENT 16 | ||
| 25 | #define FETCHOP_CLEAR 24 | ||
| 26 | |||
| 27 | #define FETCHOP_STORE 0 | ||
| 28 | #define FETCHOP_AND 24 | ||
| 29 | #define FETCHOP_OR 32 | ||
| 30 | |||
| 31 | #define FETCHOP_CLEAR_CACHE 56 | ||
| 32 | |||
| 33 | #define FETCHOP_LOAD_OP(addr, op) ( \ | ||
| 34 | *(volatile long *)((char*) (addr) + (op))) | ||
| 35 | |||
| 36 | #define FETCHOP_STORE_OP(addr, op, x) ( \ | ||
| 37 | *(volatile long *)((char*) (addr) + (op)) = (long) (x)) | ||
| 38 | |||
| 39 | #ifdef __KERNEL__ | ||
| 40 | |||
| 41 | /* | ||
| 42 | * Convert a region 6 (kaddr) address to the address of the fetchop variable | ||
| 43 | */ | ||
| 44 | #define FETCHOP_KADDR_TO_MSPEC_ADDR(kaddr) TO_MSPEC(kaddr) | ||
| 45 | |||
| 46 | |||
| 47 | /* | ||
| 48 | * Each Atomic Memory Operation (AMO formerly known as fetchop) | ||
| 49 | * variable is 64 bytes long. The first 8 bytes are used. The | ||
| 50 | * remaining 56 bytes are unaddressable due to the operation taking | ||
| 51 | * that portion of the address. | ||
| 52 | * | ||
| 53 | * NOTE: The AMO_t _MUST_ be placed in either the first or second half | ||
| 54 | * of the cache line. The cache line _MUST NOT_ be used for anything | ||
| 55 | * other than additional AMO_t entries. This is because there are two | ||
| 56 | * addresses which reference the same physical cache line. One will | ||
| 57 | * be a cached entry with the memory type bits all set. This address | ||
| 58 | * may be loaded into processor cache. The AMO_t will be referenced | ||
| 59 | * uncached via the memory special memory type. If any portion of the | ||
| 60 | * cached cache-line is modified, when that line is flushed, it will | ||
| 61 | * overwrite the uncached value in physical memory and lead to | ||
| 62 | * inconsistency. | ||
| 63 | */ | ||
| 64 | typedef struct { | ||
| 65 | u64 variable; | ||
| 66 | u64 unused[7]; | ||
| 67 | } AMO_t; | ||
| 68 | |||
| 69 | |||
| 70 | /* | ||
| 71 | * The following APIs are externalized to the kernel to allocate/free pages of | ||
| 72 | * fetchop variables. | ||
| 73 | * fetchop_kalloc_page - Allocate/initialize 1 fetchop page on the | ||
| 74 | * specified cnode. | ||
| 75 | * fetchop_kfree_page - Free a previously allocated fetchop page | ||
| 76 | */ | ||
| 77 | |||
| 78 | unsigned long fetchop_kalloc_page(int nid); | ||
| 79 | void fetchop_kfree_page(unsigned long maddr); | ||
| 80 | |||
| 81 | |||
| 82 | #endif /* __KERNEL__ */ | ||
| 83 | |||
| 84 | #endif /* _ASM_IA64_SN_FETCHOP_H */ | ||
| 85 | |||
diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h index d5dbd55e44b5..08050d37b662 100644 --- a/include/asm-ia64/sn/l1.h +++ b/include/asm-ia64/sn/l1.h | |||
| @@ -29,8 +29,9 @@ | |||
| 29 | #define L1_BRICKTYPE_CHI_CG 0x76 /* v */ | 29 | #define L1_BRICKTYPE_CHI_CG 0x76 /* v */ |
| 30 | #define L1_BRICKTYPE_X 0x78 /* x */ | 30 | #define L1_BRICKTYPE_X 0x78 /* x */ |
| 31 | #define L1_BRICKTYPE_X2 0x79 /* y */ | 31 | #define L1_BRICKTYPE_X2 0x79 /* y */ |
| 32 | #define L1_BRICKTYPE_SA 0x5e /* ^ */ /* TIO bringup brick */ | 32 | #define L1_BRICKTYPE_SA 0x5e /* ^ */ |
| 33 | #define L1_BRICKTYPE_PA 0x6a /* j */ | 33 | #define L1_BRICKTYPE_PA 0x6a /* j */ |
| 34 | #define L1_BRICKTYPE_IA 0x6b /* k */ | 34 | #define L1_BRICKTYPE_IA 0x6b /* k */ |
| 35 | #define L1_BRICKTYPE_ATHENA 0x2b /* + */ | ||
| 35 | 36 | ||
| 36 | #endif /* _ASM_IA64_SN_L1_H */ | 37 | #endif /* _ASM_IA64_SN_L1_H */ |
diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h index 13cc1002b294..7138b1eafd6b 100644 --- a/include/asm-ia64/sn/nodepda.h +++ b/include/asm-ia64/sn/nodepda.h | |||
| @@ -13,7 +13,6 @@ | |||
| 13 | #include <asm/irq.h> | 13 | #include <asm/irq.h> |
| 14 | #include <asm/sn/arch.h> | 14 | #include <asm/sn/arch.h> |
| 15 | #include <asm/sn/intr.h> | 15 | #include <asm/sn/intr.h> |
| 16 | #include <asm/sn/pda.h> | ||
| 17 | #include <asm/sn/bte.h> | 16 | #include <asm/sn/bte.h> |
| 18 | 17 | ||
| 19 | /* | 18 | /* |
| @@ -67,20 +66,18 @@ typedef struct nodepda_s nodepda_t; | |||
| 67 | * The next set of definitions provides this. | 66 | * The next set of definitions provides this. |
| 68 | * Routines are expected to use | 67 | * Routines are expected to use |
| 69 | * | 68 | * |
| 70 | * nodepda -> to access node PDA for the node on which code is running | 69 | * sn_nodepda - to access node PDA for the node on which code is running |
| 71 | * subnodepda -> to access subnode PDA for the subnode on which code is running | 70 | * NODEPDA(cnodeid) - to access node PDA for cnodeid |
| 72 | * | ||
| 73 | * NODEPDA(cnode) -> to access node PDA for cnodeid | ||
| 74 | * SUBNODEPDA(cnode,sn) -> to access subnode PDA for cnodeid/subnode | ||
| 75 | */ | 71 | */ |
| 76 | 72 | ||
| 77 | #define nodepda pda->p_nodepda /* Ptr to this node's PDA */ | 73 | DECLARE_PER_CPU(struct nodepda_s *, __sn_nodepda); |
| 78 | #define NODEPDA(cnode) (nodepda->pernode_pdaindr[cnode]) | 74 | #define sn_nodepda (__get_cpu_var(__sn_nodepda)) |
| 75 | #define NODEPDA(cnodeid) (sn_nodepda->pernode_pdaindr[cnodeid]) | ||
| 79 | 76 | ||
| 80 | /* | 77 | /* |
| 81 | * Check if given a compact node id the corresponding node has all the | 78 | * Check if given a compact node id the corresponding node has all the |
| 82 | * cpus disabled. | 79 | * cpus disabled. |
| 83 | */ | 80 | */ |
| 84 | #define is_headless_node(cnode) (nr_cpus_node(cnode) == 0) | 81 | #define is_headless_node(cnodeid) (nr_cpus_node(cnodeid) == 0) |
| 85 | 82 | ||
| 86 | #endif /* _ASM_IA64_SN_NODEPDA_H */ | 83 | #endif /* _ASM_IA64_SN_NODEPDA_H */ |
diff --git a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h index cd19f17bf91a..ea5590c76ca4 100644 --- a/include/asm-ia64/sn/pda.h +++ b/include/asm-ia64/sn/pda.h | |||
| @@ -24,14 +24,6 @@ | |||
| 24 | 24 | ||
| 25 | typedef struct pda_s { | 25 | typedef struct pda_s { |
| 26 | 26 | ||
| 27 | /* Having a pointer in the begining of PDA tends to increase | ||
| 28 | * the chance of having this pointer in cache. (Yes something | ||
| 29 | * else gets pushed out). Doing this reduces the number of memory | ||
| 30 | * access to all nodepda variables to be one | ||
| 31 | */ | ||
| 32 | struct nodepda_s *p_nodepda; /* Pointer to Per node PDA */ | ||
| 33 | struct subnodepda_s *p_subnodepda; /* Pointer to CPU subnode PDA */ | ||
| 34 | |||
| 35 | /* | 27 | /* |
| 36 | * Support for SN LEDs | 28 | * Support for SN LEDs |
| 37 | */ | 29 | */ |
| @@ -49,7 +41,6 @@ typedef struct pda_s { | |||
| 49 | 41 | ||
| 50 | unsigned long sn_soft_irr[4]; | 42 | unsigned long sn_soft_irr[4]; |
| 51 | unsigned long sn_in_service_ivecs[4]; | 43 | unsigned long sn_in_service_ivecs[4]; |
| 52 | short cnodeid_to_nasid_table[MAX_NUMNODES]; | ||
| 53 | int sn_lb_int_war_ticks; | 44 | int sn_lb_int_war_ticks; |
| 54 | int sn_last_irq; | 45 | int sn_last_irq; |
| 55 | int sn_first_irq; | 46 | int sn_first_irq; |
diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h index 2f885088e095..323fa0cd8d83 100644 --- a/include/asm-ia64/sn/shub_mmr.h +++ b/include/asm-ia64/sn/shub_mmr.h | |||
| @@ -385,6 +385,17 @@ | |||
| 385 | #define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000 | 385 | #define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000 |
| 386 | 386 | ||
| 387 | /* ==================================================================== */ | 387 | /* ==================================================================== */ |
| 388 | /* Register "SH_IPI_ACCESS" */ | ||
| 389 | /* CPU interrupt Access Permission Bits */ | ||
| 390 | /* ==================================================================== */ | ||
| 391 | |||
| 392 | #define SH1_IPI_ACCESS 0x0000000110060480 | ||
| 393 | #define SH2_IPI_ACCESS0 0x0000000010060c00 | ||
| 394 | #define SH2_IPI_ACCESS1 0x0000000010060c80 | ||
| 395 | #define SH2_IPI_ACCESS2 0x0000000010060d00 | ||
| 396 | #define SH2_IPI_ACCESS3 0x0000000010060d80 | ||
| 397 | |||
| 398 | /* ==================================================================== */ | ||
| 388 | /* Register "SH_INT_CMPB" */ | 399 | /* Register "SH_INT_CMPB" */ |
| 389 | /* RTC Compare Value for Processor B */ | 400 | /* RTC Compare Value for Processor B */ |
| 390 | /* ==================================================================== */ | 401 | /* ==================================================================== */ |
| @@ -429,6 +440,19 @@ | |||
| 429 | #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 | 440 | #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 |
| 430 | #define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff | 441 | #define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff |
| 431 | 442 | ||
| 443 | /* ==================================================================== */ | ||
| 444 | /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ | ||
| 445 | /* privilege vector for acc=0 */ | ||
| 446 | /* ==================================================================== */ | ||
| 447 | |||
| 448 | #define SH1_MD_DQLP_MMR_DIR_PRIVEC0 0x0000000100030300 | ||
| 449 | |||
| 450 | /* ==================================================================== */ | ||
| 451 | /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ | ||
| 452 | /* privilege vector for acc=0 */ | ||
| 453 | /* ==================================================================== */ | ||
| 454 | |||
| 455 | #define SH1_MD_DQRP_MMR_DIR_PRIVEC0 0x0000000100050300 | ||
| 432 | 456 | ||
| 433 | /* ==================================================================== */ | 457 | /* ==================================================================== */ |
| 434 | /* Some MMRs are functionally identical (or close enough) on both SHUB1 */ | 458 | /* Some MMRs are functionally identical (or close enough) on both SHUB1 */ |
diff --git a/include/asm-ia64/sn/shubio.h b/include/asm-ia64/sn/shubio.h index fbd880e6bb96..831b72111fdc 100644 --- a/include/asm-ia64/sn/shubio.h +++ b/include/asm-ia64/sn/shubio.h | |||
| @@ -3,292 +3,287 @@ | |||
| 3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. | 4 | * for more details. |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. | 6 | * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | #ifndef _ASM_IA64_SN_SHUBIO_H | 9 | #ifndef _ASM_IA64_SN_SHUBIO_H |
| 10 | #define _ASM_IA64_SN_SHUBIO_H | 10 | #define _ASM_IA64_SN_SHUBIO_H |
| 11 | 11 | ||
| 12 | #define HUB_WIDGET_ID_MAX 0xf | 12 | #define HUB_WIDGET_ID_MAX 0xf |
| 13 | #define IIO_NUM_ITTES 7 | 13 | #define IIO_NUM_ITTES 7 |
| 14 | #define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) | 14 | #define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) |
| 15 | 15 | ||
| 16 | #define IIO_WID 0x00400000 /* Crosstalk Widget Identification */ | 16 | #define IIO_WID 0x00400000 /* Crosstalk Widget Identification */ |
| 17 | /* This register is also accessible from | 17 | /* This register is also accessible from |
| 18 | * Crosstalk at address 0x0. */ | 18 | * Crosstalk at address 0x0. */ |
| 19 | #define IIO_WSTAT 0x00400008 /* Crosstalk Widget Status */ | 19 | #define IIO_WSTAT 0x00400008 /* Crosstalk Widget Status */ |
| 20 | #define IIO_WCR 0x00400020 /* Crosstalk Widget Control Register */ | 20 | #define IIO_WCR 0x00400020 /* Crosstalk Widget Control Register */ |
| 21 | #define IIO_ILAPR 0x00400100 /* IO Local Access Protection Register */ | 21 | #define IIO_ILAPR 0x00400100 /* IO Local Access Protection Register */ |
| 22 | #define IIO_ILAPO 0x00400108 /* IO Local Access Protection Override */ | 22 | #define IIO_ILAPO 0x00400108 /* IO Local Access Protection Override */ |
| 23 | #define IIO_IOWA 0x00400110 /* IO Outbound Widget Access */ | 23 | #define IIO_IOWA 0x00400110 /* IO Outbound Widget Access */ |
| 24 | #define IIO_IIWA 0x00400118 /* IO Inbound Widget Access */ | 24 | #define IIO_IIWA 0x00400118 /* IO Inbound Widget Access */ |
| 25 | #define IIO_IIDEM 0x00400120 /* IO Inbound Device Error Mask */ | 25 | #define IIO_IIDEM 0x00400120 /* IO Inbound Device Error Mask */ |
| 26 | #define IIO_ILCSR 0x00400128 /* IO LLP Control and Status Register */ | 26 | #define IIO_ILCSR 0x00400128 /* IO LLP Control and Status Register */ |
| 27 | #define IIO_ILLR 0x00400130 /* IO LLP Log Register */ | 27 | #define IIO_ILLR 0x00400130 /* IO LLP Log Register */ |
| 28 | #define IIO_IIDSR 0x00400138 /* IO Interrupt Destination */ | 28 | #define IIO_IIDSR 0x00400138 /* IO Interrupt Destination */ |
| 29 | 29 | ||
| 30 | #define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */ | 30 | #define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */ |
| 31 | #define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */ | 31 | #define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */ |
| 32 | 32 | ||
| 33 | #define IIO_ISCR0 0x00400150 /* IO Scratch Register 0 */ | 33 | #define IIO_ISCR0 0x00400150 /* IO Scratch Register 0 */ |
| 34 | #define IIO_ISCR1 0x00400158 /* IO Scratch Register 1 */ | 34 | #define IIO_ISCR1 0x00400158 /* IO Scratch Register 1 */ |
| 35 | 35 | ||
| 36 | #define IIO_ITTE1 0x00400160 /* IO Translation Table Entry 1 */ | 36 | #define IIO_ITTE1 0x00400160 /* IO Translation Table Entry 1 */ |
| 37 | #define IIO_ITTE2 0x00400168 /* IO Translation Table Entry 2 */ | 37 | #define IIO_ITTE2 0x00400168 /* IO Translation Table Entry 2 */ |
| 38 | #define IIO_ITTE3 0x00400170 /* IO Translation Table Entry 3 */ | 38 | #define IIO_ITTE3 0x00400170 /* IO Translation Table Entry 3 */ |
| 39 | #define IIO_ITTE4 0x00400178 /* IO Translation Table Entry 4 */ | 39 | #define IIO_ITTE4 0x00400178 /* IO Translation Table Entry 4 */ |
| 40 | #define IIO_ITTE5 0x00400180 /* IO Translation Table Entry 5 */ | 40 | #define IIO_ITTE5 0x00400180 /* IO Translation Table Entry 5 */ |
| 41 | #define IIO_ITTE6 0x00400188 /* IO Translation Table Entry 6 */ | 41 | #define IIO_ITTE6 0x00400188 /* IO Translation Table Entry 6 */ |
| 42 | #define IIO_ITTE7 0x00400190 /* IO Translation Table Entry 7 */ | 42 | #define IIO_ITTE7 0x00400190 /* IO Translation Table Entry 7 */ |
| 43 | 43 | ||
| 44 | #define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */ | 44 | #define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */ |
| 45 | #define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */ | 45 | #define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */ |
| 46 | #define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */ | 46 | #define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */ |
| 47 | #define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */ | 47 | #define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */ |
| 48 | #define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */ | 48 | #define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */ |
| 49 | #define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */ | 49 | #define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */ |
| 50 | #define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */ | 50 | #define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */ |
| 51 | #define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */ | 51 | #define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */ |
| 52 | #define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */ | 52 | #define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */ |
| 53 | 53 | ||
| 54 | #define IIO_IXCC 0x004001E0 /* IO Crosstalk Credit Count Timeout */ | 54 | #define IIO_IXCC 0x004001E0 /* IO Crosstalk Credit Count Timeout */ |
| 55 | #define IIO_IMEM 0x004001E8 /* IO Miscellaneous Error Mask */ | 55 | #define IIO_IMEM 0x004001E8 /* IO Miscellaneous Error Mask */ |
| 56 | #define IIO_IXTT 0x004001F0 /* IO Crosstalk Timeout Threshold */ | 56 | #define IIO_IXTT 0x004001F0 /* IO Crosstalk Timeout Threshold */ |
| 57 | #define IIO_IECLR 0x004001F8 /* IO Error Clear Register */ | 57 | #define IIO_IECLR 0x004001F8 /* IO Error Clear Register */ |
| 58 | #define IIO_IBCR 0x00400200 /* IO BTE Control Register */ | 58 | #define IIO_IBCR 0x00400200 /* IO BTE Control Register */ |
| 59 | 59 | ||
| 60 | #define IIO_IXSM 0x00400208 /* IO Crosstalk Spurious Message */ | 60 | #define IIO_IXSM 0x00400208 /* IO Crosstalk Spurious Message */ |
| 61 | #define IIO_IXSS 0x00400210 /* IO Crosstalk Spurious Sideband */ | 61 | #define IIO_IXSS 0x00400210 /* IO Crosstalk Spurious Sideband */ |
| 62 | 62 | ||
| 63 | #define IIO_ILCT 0x00400218 /* IO LLP Channel Test */ | 63 | #define IIO_ILCT 0x00400218 /* IO LLP Channel Test */ |
| 64 | 64 | ||
| 65 | #define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */ | 65 | #define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */ |
| 66 | #define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */ | 66 | #define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */ |
| 67 | 67 | ||
| 68 | 68 | #define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */ | |
| 69 | #define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */ | 69 | #define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */ |
| 70 | #define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */ | 70 | |
| 71 | 71 | #define IIO_IWI 0x00400240 /* IO Wrapper Interrupt Register */ | |
| 72 | #define IIO_IWI 0x00400240 /* IO Wrapper Interrupt Register */ | 72 | #define IIO_IWEL 0x00400248 /* IO Wrapper Error Log Register */ |
| 73 | #define IIO_IWEL 0x00400248 /* IO Wrapper Error Log Register */ | 73 | #define IIO_IWC 0x00400250 /* IO Wrapper Control Register */ |
| 74 | #define IIO_IWC 0x00400250 /* IO Wrapper Control Register */ | 74 | #define IIO_IWS 0x00400258 /* IO Wrapper Status Register */ |
| 75 | #define IIO_IWS 0x00400258 /* IO Wrapper Status Register */ | 75 | #define IIO_IWEIM 0x00400260 /* IO Wrapper Error Interrupt Masking Register */ |
| 76 | #define IIO_IWEIM 0x00400260 /* IO Wrapper Error Interrupt Masking Register */ | 76 | |
| 77 | 77 | #define IIO_IPCA 0x00400300 /* IO PRB Counter Adjust */ | |
| 78 | #define IIO_IPCA 0x00400300 /* IO PRB Counter Adjust */ | 78 | |
| 79 | 79 | #define IIO_IPRTE0_A 0x00400308 /* IO PIO Read Address Table Entry 0, Part A */ | |
| 80 | #define IIO_IPRTE0_A 0x00400308 /* IO PIO Read Address Table Entry 0, Part A */ | 80 | #define IIO_IPRTE1_A 0x00400310 /* IO PIO Read Address Table Entry 1, Part A */ |
| 81 | #define IIO_IPRTE1_A 0x00400310 /* IO PIO Read Address Table Entry 1, Part A */ | 81 | #define IIO_IPRTE2_A 0x00400318 /* IO PIO Read Address Table Entry 2, Part A */ |
| 82 | #define IIO_IPRTE2_A 0x00400318 /* IO PIO Read Address Table Entry 2, Part A */ | 82 | #define IIO_IPRTE3_A 0x00400320 /* IO PIO Read Address Table Entry 3, Part A */ |
| 83 | #define IIO_IPRTE3_A 0x00400320 /* IO PIO Read Address Table Entry 3, Part A */ | 83 | #define IIO_IPRTE4_A 0x00400328 /* IO PIO Read Address Table Entry 4, Part A */ |
| 84 | #define IIO_IPRTE4_A 0x00400328 /* IO PIO Read Address Table Entry 4, Part A */ | 84 | #define IIO_IPRTE5_A 0x00400330 /* IO PIO Read Address Table Entry 5, Part A */ |
| 85 | #define IIO_IPRTE5_A 0x00400330 /* IO PIO Read Address Table Entry 5, Part A */ | 85 | #define IIO_IPRTE6_A 0x00400338 /* IO PIO Read Address Table Entry 6, Part A */ |
| 86 | #define IIO_IPRTE6_A 0x00400338 /* IO PIO Read Address Table Entry 6, Part A */ | 86 | #define IIO_IPRTE7_A 0x00400340 /* IO PIO Read Address Table Entry 7, Part A */ |
| 87 | #define IIO_IPRTE7_A 0x00400340 /* IO PIO Read Address Table Entry 7, Part A */ | 87 | |
| 88 | 88 | #define IIO_IPRTE0_B 0x00400348 /* IO PIO Read Address Table Entry 0, Part B */ | |
| 89 | #define IIO_IPRTE0_B 0x00400348 /* IO PIO Read Address Table Entry 0, Part B */ | 89 | #define IIO_IPRTE1_B 0x00400350 /* IO PIO Read Address Table Entry 1, Part B */ |
| 90 | #define IIO_IPRTE1_B 0x00400350 /* IO PIO Read Address Table Entry 1, Part B */ | 90 | #define IIO_IPRTE2_B 0x00400358 /* IO PIO Read Address Table Entry 2, Part B */ |
| 91 | #define IIO_IPRTE2_B 0x00400358 /* IO PIO Read Address Table Entry 2, Part B */ | 91 | #define IIO_IPRTE3_B 0x00400360 /* IO PIO Read Address Table Entry 3, Part B */ |
| 92 | #define IIO_IPRTE3_B 0x00400360 /* IO PIO Read Address Table Entry 3, Part B */ | 92 | #define IIO_IPRTE4_B 0x00400368 /* IO PIO Read Address Table Entry 4, Part B */ |
| 93 | #define IIO_IPRTE4_B 0x00400368 /* IO PIO Read Address Table Entry 4, Part B */ | 93 | #define IIO_IPRTE5_B 0x00400370 /* IO PIO Read Address Table Entry 5, Part B */ |
| 94 | #define IIO_IPRTE5_B 0x00400370 /* IO PIO Read Address Table Entry 5, Part B */ | 94 | #define IIO_IPRTE6_B 0x00400378 /* IO PIO Read Address Table Entry 6, Part B */ |
| 95 | #define IIO_IPRTE6_B 0x00400378 /* IO PIO Read Address Table Entry 6, Part B */ | 95 | #define IIO_IPRTE7_B 0x00400380 /* IO PIO Read Address Table Entry 7, Part B */ |
| 96 | #define IIO_IPRTE7_B 0x00400380 /* IO PIO Read Address Table Entry 7, Part B */ | 96 | |
| 97 | 97 | #define IIO_IPDR 0x00400388 /* IO PIO Deallocation Register */ | |
| 98 | #define IIO_IPDR 0x00400388 /* IO PIO Deallocation Register */ | 98 | #define IIO_ICDR 0x00400390 /* IO CRB Entry Deallocation Register */ |
| 99 | #define IIO_ICDR 0x00400390 /* IO CRB Entry Deallocation Register */ | 99 | #define IIO_IFDR 0x00400398 /* IO IOQ FIFO Depth Register */ |
| 100 | #define IIO_IFDR 0x00400398 /* IO IOQ FIFO Depth Register */ | 100 | #define IIO_IIAP 0x004003A0 /* IO IIQ Arbitration Parameters */ |
| 101 | #define IIO_IIAP 0x004003A0 /* IO IIQ Arbitration Parameters */ | 101 | #define IIO_ICMR 0x004003A8 /* IO CRB Management Register */ |
| 102 | #define IIO_ICMR 0x004003A8 /* IO CRB Management Register */ | 102 | #define IIO_ICCR 0x004003B0 /* IO CRB Control Register */ |
| 103 | #define IIO_ICCR 0x004003B0 /* IO CRB Control Register */ | 103 | #define IIO_ICTO 0x004003B8 /* IO CRB Timeout */ |
| 104 | #define IIO_ICTO 0x004003B8 /* IO CRB Timeout */ | 104 | #define IIO_ICTP 0x004003C0 /* IO CRB Timeout Prescalar */ |
| 105 | #define IIO_ICTP 0x004003C0 /* IO CRB Timeout Prescalar */ | 105 | |
| 106 | 106 | #define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */ | |
| 107 | #define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */ | 107 | #define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */ |
| 108 | #define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */ | 108 | #define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */ |
| 109 | #define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */ | 109 | #define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */ |
| 110 | #define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */ | 110 | #define IIO_ICRB0_E 0x00400420 /* IO CRB Entry 0_E */ |
| 111 | #define IIO_ICRB0_E 0x00400420 /* IO CRB Entry 0_E */ | 111 | |
| 112 | 112 | #define IIO_ICRB1_A 0x00400430 /* IO CRB Entry 1_A */ | |
| 113 | #define IIO_ICRB1_A 0x00400430 /* IO CRB Entry 1_A */ | 113 | #define IIO_ICRB1_B 0x00400438 /* IO CRB Entry 1_B */ |
| 114 | #define IIO_ICRB1_B 0x00400438 /* IO CRB Entry 1_B */ | 114 | #define IIO_ICRB1_C 0x00400440 /* IO CRB Entry 1_C */ |
| 115 | #define IIO_ICRB1_C 0x00400440 /* IO CRB Entry 1_C */ | 115 | #define IIO_ICRB1_D 0x00400448 /* IO CRB Entry 1_D */ |
| 116 | #define IIO_ICRB1_D 0x00400448 /* IO CRB Entry 1_D */ | 116 | #define IIO_ICRB1_E 0x00400450 /* IO CRB Entry 1_E */ |
| 117 | #define IIO_ICRB1_E 0x00400450 /* IO CRB Entry 1_E */ | 117 | |
| 118 | 118 | #define IIO_ICRB2_A 0x00400460 /* IO CRB Entry 2_A */ | |
| 119 | #define IIO_ICRB2_A 0x00400460 /* IO CRB Entry 2_A */ | 119 | #define IIO_ICRB2_B 0x00400468 /* IO CRB Entry 2_B */ |
| 120 | #define IIO_ICRB2_B 0x00400468 /* IO CRB Entry 2_B */ | 120 | #define IIO_ICRB2_C 0x00400470 /* IO CRB Entry 2_C */ |
| 121 | #define IIO_ICRB2_C 0x00400470 /* IO CRB Entry 2_C */ | 121 | #define IIO_ICRB2_D 0x00400478 /* IO CRB Entry 2_D */ |
| 122 | #define IIO_ICRB2_D 0x00400478 /* IO CRB Entry 2_D */ | 122 | #define IIO_ICRB2_E 0x00400480 /* IO CRB Entry 2_E */ |
| 123 | #define IIO_ICRB2_E 0x00400480 /* IO CRB Entry 2_E */ | 123 | |
| 124 | 124 | #define IIO_ICRB3_A 0x00400490 /* IO CRB Entry 3_A */ | |
| 125 | #define IIO_ICRB3_A 0x00400490 /* IO CRB Entry 3_A */ | 125 | #define IIO_ICRB3_B 0x00400498 /* IO CRB Entry 3_B */ |
| 126 | #define IIO_ICRB3_B 0x00400498 /* IO CRB Entry 3_B */ | 126 | #define IIO_ICRB3_C 0x004004a0 /* IO CRB Entry 3_C */ |
| 127 | #define IIO_ICRB3_C 0x004004a0 /* IO CRB Entry 3_C */ | 127 | #define IIO_ICRB3_D 0x004004a8 /* IO CRB Entry 3_D */ |
| 128 | #define IIO_ICRB3_D 0x004004a8 /* IO CRB Entry 3_D */ | 128 | #define IIO_ICRB3_E 0x004004b0 /* IO CRB Entry 3_E */ |
| 129 | #define IIO_ICRB3_E 0x004004b0 /* IO CRB Entry 3_E */ | 129 | |
| 130 | 130 | #define IIO_ICRB4_A 0x004004c0 /* IO CRB Entry 4_A */ | |
| 131 | #define IIO_ICRB4_A 0x004004c0 /* IO CRB Entry 4_A */ | 131 | #define IIO_ICRB4_B 0x004004c8 /* IO CRB Entry 4_B */ |
| 132 | #define IIO_ICRB4_B 0x004004c8 /* IO CRB Entry 4_B */ | 132 | #define IIO_ICRB4_C 0x004004d0 /* IO CRB Entry 4_C */ |
| 133 | #define IIO_ICRB4_C 0x004004d0 /* IO CRB Entry 4_C */ | 133 | #define IIO_ICRB4_D 0x004004d8 /* IO CRB Entry 4_D */ |
| 134 | #define IIO_ICRB4_D 0x004004d8 /* IO CRB Entry 4_D */ | 134 | #define IIO_ICRB4_E 0x004004e0 /* IO CRB Entry 4_E */ |
| 135 | #define IIO_ICRB4_E 0x004004e0 /* IO CRB Entry 4_E */ | 135 | |
| 136 | 136 | #define IIO_ICRB5_A 0x004004f0 /* IO CRB Entry 5_A */ | |
| 137 | #define IIO_ICRB5_A 0x004004f0 /* IO CRB Entry 5_A */ | 137 | #define IIO_ICRB5_B 0x004004f8 /* IO CRB Entry 5_B */ |
| 138 | #define IIO_ICRB5_B 0x004004f8 /* IO CRB Entry 5_B */ | 138 | #define IIO_ICRB5_C 0x00400500 /* IO CRB Entry 5_C */ |
| 139 | #define IIO_ICRB5_C 0x00400500 /* IO CRB Entry 5_C */ | 139 | #define IIO_ICRB5_D 0x00400508 /* IO CRB Entry 5_D */ |
| 140 | #define IIO_ICRB5_D 0x00400508 /* IO CRB Entry 5_D */ | 140 | #define IIO_ICRB5_E 0x00400510 /* IO CRB Entry 5_E */ |
| 141 | #define IIO_ICRB5_E 0x00400510 /* IO CRB Entry 5_E */ | 141 | |
| 142 | 142 | #define IIO_ICRB6_A 0x00400520 /* IO CRB Entry 6_A */ | |
| 143 | #define IIO_ICRB6_A 0x00400520 /* IO CRB Entry 6_A */ | 143 | #define IIO_ICRB6_B 0x00400528 /* IO CRB Entry 6_B */ |
| 144 | #define IIO_ICRB6_B 0x00400528 /* IO CRB Entry 6_B */ | 144 | #define IIO_ICRB6_C 0x00400530 /* IO CRB Entry 6_C */ |
| 145 | #define IIO_ICRB6_C 0x00400530 /* IO CRB Entry 6_C */ | 145 | #define IIO_ICRB6_D 0x00400538 /* IO CRB Entry 6_D */ |
| 146 | #define IIO_ICRB6_D 0x00400538 /* IO CRB Entry 6_D */ | 146 | #define IIO_ICRB6_E 0x00400540 /* IO CRB Entry 6_E */ |
| 147 | #define IIO_ICRB6_E 0x00400540 /* IO CRB Entry 6_E */ | 147 | |
| 148 | 148 | #define IIO_ICRB7_A 0x00400550 /* IO CRB Entry 7_A */ | |
| 149 | #define IIO_ICRB7_A 0x00400550 /* IO CRB Entry 7_A */ | 149 | #define IIO_ICRB7_B 0x00400558 /* IO CRB Entry 7_B */ |
| 150 | #define IIO_ICRB7_B 0x00400558 /* IO CRB Entry 7_B */ | 150 | #define IIO_ICRB7_C 0x00400560 /* IO CRB Entry 7_C */ |
| 151 | #define IIO_ICRB7_C 0x00400560 /* IO CRB Entry 7_C */ | 151 | #define IIO_ICRB7_D 0x00400568 /* IO CRB Entry 7_D */ |
| 152 | #define IIO_ICRB7_D 0x00400568 /* IO CRB Entry 7_D */ | 152 | #define IIO_ICRB7_E 0x00400570 /* IO CRB Entry 7_E */ |
| 153 | #define IIO_ICRB7_E 0x00400570 /* IO CRB Entry 7_E */ | 153 | |
| 154 | 154 | #define IIO_ICRB8_A 0x00400580 /* IO CRB Entry 8_A */ | |
| 155 | #define IIO_ICRB8_A 0x00400580 /* IO CRB Entry 8_A */ | 155 | #define IIO_ICRB8_B 0x00400588 /* IO CRB Entry 8_B */ |
| 156 | #define IIO_ICRB8_B 0x00400588 /* IO CRB Entry 8_B */ | 156 | #define IIO_ICRB8_C 0x00400590 /* IO CRB Entry 8_C */ |
| 157 | #define IIO_ICRB8_C 0x00400590 /* IO CRB Entry 8_C */ | 157 | #define IIO_ICRB8_D 0x00400598 /* IO CRB Entry 8_D */ |
| 158 | #define IIO_ICRB8_D 0x00400598 /* IO CRB Entry 8_D */ | 158 | #define IIO_ICRB8_E 0x004005a0 /* IO CRB Entry 8_E */ |
| 159 | #define IIO_ICRB8_E 0x004005a0 /* IO CRB Entry 8_E */ | 159 | |
| 160 | 160 | #define IIO_ICRB9_A 0x004005b0 /* IO CRB Entry 9_A */ | |
| 161 | #define IIO_ICRB9_A 0x004005b0 /* IO CRB Entry 9_A */ | 161 | #define IIO_ICRB9_B 0x004005b8 /* IO CRB Entry 9_B */ |
| 162 | #define IIO_ICRB9_B 0x004005b8 /* IO CRB Entry 9_B */ | 162 | #define IIO_ICRB9_C 0x004005c0 /* IO CRB Entry 9_C */ |
| 163 | #define IIO_ICRB9_C 0x004005c0 /* IO CRB Entry 9_C */ | 163 | #define IIO_ICRB9_D 0x004005c8 /* IO CRB Entry 9_D */ |
| 164 | #define IIO_ICRB9_D 0x004005c8 /* IO CRB Entry 9_D */ | 164 | #define IIO_ICRB9_E 0x004005d0 /* IO CRB Entry 9_E */ |
| 165 | #define IIO_ICRB9_E 0x004005d0 /* IO CRB Entry 9_E */ | 165 | |
| 166 | 166 | #define IIO_ICRBA_A 0x004005e0 /* IO CRB Entry A_A */ | |
| 167 | #define IIO_ICRBA_A 0x004005e0 /* IO CRB Entry A_A */ | 167 | #define IIO_ICRBA_B 0x004005e8 /* IO CRB Entry A_B */ |
| 168 | #define IIO_ICRBA_B 0x004005e8 /* IO CRB Entry A_B */ | 168 | #define IIO_ICRBA_C 0x004005f0 /* IO CRB Entry A_C */ |
| 169 | #define IIO_ICRBA_C 0x004005f0 /* IO CRB Entry A_C */ | 169 | #define IIO_ICRBA_D 0x004005f8 /* IO CRB Entry A_D */ |
| 170 | #define IIO_ICRBA_D 0x004005f8 /* IO CRB Entry A_D */ | 170 | #define IIO_ICRBA_E 0x00400600 /* IO CRB Entry A_E */ |
| 171 | #define IIO_ICRBA_E 0x00400600 /* IO CRB Entry A_E */ | 171 | |
| 172 | 172 | #define IIO_ICRBB_A 0x00400610 /* IO CRB Entry B_A */ | |
| 173 | #define IIO_ICRBB_A 0x00400610 /* IO CRB Entry B_A */ | 173 | #define IIO_ICRBB_B 0x00400618 /* IO CRB Entry B_B */ |
| 174 | #define IIO_ICRBB_B 0x00400618 /* IO CRB Entry B_B */ | 174 | #define IIO_ICRBB_C 0x00400620 /* IO CRB Entry B_C */ |
| 175 | #define IIO_ICRBB_C 0x00400620 /* IO CRB Entry B_C */ | 175 | #define IIO_ICRBB_D 0x00400628 /* IO CRB Entry B_D */ |
| 176 | #define IIO_ICRBB_D 0x00400628 /* IO CRB Entry B_D */ | 176 | #define IIO_ICRBB_E 0x00400630 /* IO CRB Entry B_E */ |
| 177 | #define IIO_ICRBB_E 0x00400630 /* IO CRB Entry B_E */ | 177 | |
| 178 | 178 | #define IIO_ICRBC_A 0x00400640 /* IO CRB Entry C_A */ | |
| 179 | #define IIO_ICRBC_A 0x00400640 /* IO CRB Entry C_A */ | 179 | #define IIO_ICRBC_B 0x00400648 /* IO CRB Entry C_B */ |
| 180 | #define IIO_ICRBC_B 0x00400648 /* IO CRB Entry C_B */ | 180 | #define IIO_ICRBC_C 0x00400650 /* IO CRB Entry C_C */ |
| 181 | #define IIO_ICRBC_C 0x00400650 /* IO CRB Entry C_C */ | 181 | #define IIO_ICRBC_D 0x00400658 /* IO CRB Entry C_D */ |
| 182 | #define IIO_ICRBC_D 0x00400658 /* IO CRB Entry C_D */ | 182 | #define IIO_ICRBC_E 0x00400660 /* IO CRB Entry C_E */ |
| 183 | #define IIO_ICRBC_E 0x00400660 /* IO CRB Entry C_E */ | 183 | |
| 184 | 184 | #define IIO_ICRBD_A 0x00400670 /* IO CRB Entry D_A */ | |
| 185 | #define IIO_ICRBD_A 0x00400670 /* IO CRB Entry D_A */ | 185 | #define IIO_ICRBD_B 0x00400678 /* IO CRB Entry D_B */ |
| 186 | #define IIO_ICRBD_B 0x00400678 /* IO CRB Entry D_B */ | 186 | #define IIO_ICRBD_C 0x00400680 /* IO CRB Entry D_C */ |
| 187 | #define IIO_ICRBD_C 0x00400680 /* IO CRB Entry D_C */ | 187 | #define IIO_ICRBD_D 0x00400688 /* IO CRB Entry D_D */ |
| 188 | #define IIO_ICRBD_D 0x00400688 /* IO CRB Entry D_D */ | 188 | #define IIO_ICRBD_E 0x00400690 /* IO CRB Entry D_E */ |
| 189 | #define IIO_ICRBD_E 0x00400690 /* IO CRB Entry D_E */ | 189 | |
| 190 | 190 | #define IIO_ICRBE_A 0x004006a0 /* IO CRB Entry E_A */ | |
| 191 | #define IIO_ICRBE_A 0x004006a0 /* IO CRB Entry E_A */ | 191 | #define IIO_ICRBE_B 0x004006a8 /* IO CRB Entry E_B */ |
| 192 | #define IIO_ICRBE_B 0x004006a8 /* IO CRB Entry E_B */ | 192 | #define IIO_ICRBE_C 0x004006b0 /* IO CRB Entry E_C */ |
| 193 | #define IIO_ICRBE_C 0x004006b0 /* IO CRB Entry E_C */ | 193 | #define IIO_ICRBE_D 0x004006b8 /* IO CRB Entry E_D */ |
| 194 | #define IIO_ICRBE_D 0x004006b8 /* IO CRB Entry E_D */ | 194 | #define IIO_ICRBE_E 0x004006c0 /* IO CRB Entry E_E */ |
| 195 | #define IIO_ICRBE_E 0x004006c0 /* IO CRB Entry E_E */ | 195 | |
| 196 | 196 | #define IIO_ICSML 0x00400700 /* IO CRB Spurious Message Low */ | |
| 197 | #define IIO_ICSML 0x00400700 /* IO CRB Spurious Message Low */ | 197 | #define IIO_ICSMM 0x00400708 /* IO CRB Spurious Message Middle */ |
| 198 | #define IIO_ICSMM 0x00400708 /* IO CRB Spurious Message Middle */ | 198 | #define IIO_ICSMH 0x00400710 /* IO CRB Spurious Message High */ |
| 199 | #define IIO_ICSMH 0x00400710 /* IO CRB Spurious Message High */ | 199 | |
| 200 | 200 | #define IIO_IDBSS 0x00400718 /* IO Debug Submenu Select */ | |
| 201 | #define IIO_IDBSS 0x00400718 /* IO Debug Submenu Select */ | 201 | |
| 202 | 202 | #define IIO_IBLS0 0x00410000 /* IO BTE Length Status 0 */ | |
| 203 | #define IIO_IBLS0 0x00410000 /* IO BTE Length Status 0 */ | 203 | #define IIO_IBSA0 0x00410008 /* IO BTE Source Address 0 */ |
| 204 | #define IIO_IBSA0 0x00410008 /* IO BTE Source Address 0 */ | 204 | #define IIO_IBDA0 0x00410010 /* IO BTE Destination Address 0 */ |
| 205 | #define IIO_IBDA0 0x00410010 /* IO BTE Destination Address 0 */ | 205 | #define IIO_IBCT0 0x00410018 /* IO BTE Control Terminate 0 */ |
| 206 | #define IIO_IBCT0 0x00410018 /* IO BTE Control Terminate 0 */ | 206 | #define IIO_IBNA0 0x00410020 /* IO BTE Notification Address 0 */ |
| 207 | #define IIO_IBNA0 0x00410020 /* IO BTE Notification Address 0 */ | 207 | #define IIO_IBIA0 0x00410028 /* IO BTE Interrupt Address 0 */ |
| 208 | #define IIO_IBIA0 0x00410028 /* IO BTE Interrupt Address 0 */ | 208 | #define IIO_IBLS1 0x00420000 /* IO BTE Length Status 1 */ |
| 209 | #define IIO_IBLS1 0x00420000 /* IO BTE Length Status 1 */ | 209 | #define IIO_IBSA1 0x00420008 /* IO BTE Source Address 1 */ |
| 210 | #define IIO_IBSA1 0x00420008 /* IO BTE Source Address 1 */ | 210 | #define IIO_IBDA1 0x00420010 /* IO BTE Destination Address 1 */ |
| 211 | #define IIO_IBDA1 0x00420010 /* IO BTE Destination Address 1 */ | 211 | #define IIO_IBCT1 0x00420018 /* IO BTE Control Terminate 1 */ |
| 212 | #define IIO_IBCT1 0x00420018 /* IO BTE Control Terminate 1 */ | 212 | #define IIO_IBNA1 0x00420020 /* IO BTE Notification Address 1 */ |
| 213 | #define IIO_IBNA1 0x00420020 /* IO BTE Notification Address 1 */ | 213 | #define IIO_IBIA1 0x00420028 /* IO BTE Interrupt Address 1 */ |
| 214 | #define IIO_IBIA1 0x00420028 /* IO BTE Interrupt Address 1 */ | 214 | |
| 215 | 215 | #define IIO_IPCR 0x00430000 /* IO Performance Control */ | |
| 216 | #define IIO_IPCR 0x00430000 /* IO Performance Control */ | 216 | #define IIO_IPPR 0x00430008 /* IO Performance Profiling */ |
| 217 | #define IIO_IPPR 0x00430008 /* IO Performance Profiling */ | 217 | |
| 218 | 218 | /************************************************************************ | |
| 219 | 219 | * * | |
| 220 | /************************************************************************ | ||
| 221 | * * | ||
| 222 | * Description: This register echoes some information from the * | 220 | * Description: This register echoes some information from the * |
| 223 | * LB_REV_ID register. It is available through Crosstalk as described * | 221 | * LB_REV_ID register. It is available through Crosstalk as described * |
| 224 | * above. The REV_NUM and MFG_NUM fields receive their values from * | 222 | * above. The REV_NUM and MFG_NUM fields receive their values from * |
| 225 | * the REVISION and MANUFACTURER fields in the LB_REV_ID register. * | 223 | * the REVISION and MANUFACTURER fields in the LB_REV_ID register. * |
| 226 | * The PART_NUM field's value is the Crosstalk device ID number that * | 224 | * The PART_NUM field's value is the Crosstalk device ID number that * |
| 227 | * Steve Miller assigned to the SHub chip. * | 225 | * Steve Miller assigned to the SHub chip. * |
| 228 | * * | 226 | * * |
| 229 | ************************************************************************/ | 227 | ************************************************************************/ |
| 230 | 228 | ||
| 231 | typedef union ii_wid_u { | 229 | typedef union ii_wid_u { |
| 232 | uint64_t ii_wid_regval; | 230 | uint64_t ii_wid_regval; |
| 233 | struct { | 231 | struct { |
| 234 | uint64_t w_rsvd_1 : 1; | 232 | uint64_t w_rsvd_1:1; |
| 235 | uint64_t w_mfg_num : 11; | 233 | uint64_t w_mfg_num:11; |
| 236 | uint64_t w_part_num : 16; | 234 | uint64_t w_part_num:16; |
| 237 | uint64_t w_rev_num : 4; | 235 | uint64_t w_rev_num:4; |
| 238 | uint64_t w_rsvd : 32; | 236 | uint64_t w_rsvd:32; |
| 239 | } ii_wid_fld_s; | 237 | } ii_wid_fld_s; |
| 240 | } ii_wid_u_t; | 238 | } ii_wid_u_t; |
| 241 | 239 | ||
| 242 | |||
| 243 | /************************************************************************ | 240 | /************************************************************************ |
| 244 | * * | 241 | * * |
| 245 | * The fields in this register are set upon detection of an error * | 242 | * The fields in this register are set upon detection of an error * |
| 246 | * and cleared by various mechanisms, as explained in the * | 243 | * and cleared by various mechanisms, as explained in the * |
| 247 | * description. * | 244 | * description. * |
| 248 | * * | 245 | * * |
| 249 | ************************************************************************/ | 246 | ************************************************************************/ |
| 250 | 247 | ||
| 251 | typedef union ii_wstat_u { | 248 | typedef union ii_wstat_u { |
| 252 | uint64_t ii_wstat_regval; | 249 | uint64_t ii_wstat_regval; |
| 253 | struct { | 250 | struct { |
| 254 | uint64_t w_pending : 4; | 251 | uint64_t w_pending:4; |
| 255 | uint64_t w_xt_crd_to : 1; | 252 | uint64_t w_xt_crd_to:1; |
| 256 | uint64_t w_xt_tail_to : 1; | 253 | uint64_t w_xt_tail_to:1; |
| 257 | uint64_t w_rsvd_3 : 3; | 254 | uint64_t w_rsvd_3:3; |
| 258 | uint64_t w_tx_mx_rty : 1; | 255 | uint64_t w_tx_mx_rty:1; |
| 259 | uint64_t w_rsvd_2 : 6; | 256 | uint64_t w_rsvd_2:6; |
| 260 | uint64_t w_llp_tx_cnt : 8; | 257 | uint64_t w_llp_tx_cnt:8; |
| 261 | uint64_t w_rsvd_1 : 8; | 258 | uint64_t w_rsvd_1:8; |
| 262 | uint64_t w_crazy : 1; | 259 | uint64_t w_crazy:1; |
| 263 | uint64_t w_rsvd : 31; | 260 | uint64_t w_rsvd:31; |
| 264 | } ii_wstat_fld_s; | 261 | } ii_wstat_fld_s; |
| 265 | } ii_wstat_u_t; | 262 | } ii_wstat_u_t; |
| 266 | 263 | ||
| 267 | |||
| 268 | /************************************************************************ | 264 | /************************************************************************ |
| 269 | * * | 265 | * * |
| 270 | * Description: This is a read-write enabled register. It controls * | 266 | * Description: This is a read-write enabled register. It controls * |
| 271 | * various aspects of the Crosstalk flow control. * | 267 | * various aspects of the Crosstalk flow control. * |
| 272 | * * | 268 | * * |
| 273 | ************************************************************************/ | 269 | ************************************************************************/ |
| 274 | 270 | ||
| 275 | typedef union ii_wcr_u { | 271 | typedef union ii_wcr_u { |
| 276 | uint64_t ii_wcr_regval; | 272 | uint64_t ii_wcr_regval; |
| 277 | struct { | 273 | struct { |
| 278 | uint64_t w_wid : 4; | 274 | uint64_t w_wid:4; |
| 279 | uint64_t w_tag : 1; | 275 | uint64_t w_tag:1; |
| 280 | uint64_t w_rsvd_1 : 8; | 276 | uint64_t w_rsvd_1:8; |
| 281 | uint64_t w_dst_crd : 3; | 277 | uint64_t w_dst_crd:3; |
| 282 | uint64_t w_f_bad_pkt : 1; | 278 | uint64_t w_f_bad_pkt:1; |
| 283 | uint64_t w_dir_con : 1; | 279 | uint64_t w_dir_con:1; |
| 284 | uint64_t w_e_thresh : 5; | 280 | uint64_t w_e_thresh:5; |
| 285 | uint64_t w_rsvd : 41; | 281 | uint64_t w_rsvd:41; |
| 286 | } ii_wcr_fld_s; | 282 | } ii_wcr_fld_s; |
| 287 | } ii_wcr_u_t; | 283 | } ii_wcr_u_t; |
| 288 | 284 | ||
| 289 | |||
| 290 | /************************************************************************ | 285 | /************************************************************************ |
| 291 | * * | 286 | * * |
| 292 | * Description: This register's value is a bit vector that guards * | 287 | * Description: This register's value is a bit vector that guards * |
| 293 | * access to local registers within the II as well as to external * | 288 | * access to local registers within the II as well as to external * |
| 294 | * Crosstalk widgets. Each bit in the register corresponds to a * | 289 | * Crosstalk widgets. Each bit in the register corresponds to a * |
| @@ -311,21 +306,18 @@ typedef union ii_wcr_u { | |||
| 311 | * region ID bits are enabled in this same register. It can also be * | 306 | * region ID bits are enabled in this same register. It can also be * |
| 312 | * accessed through the IAlias space by the local processors. * | 307 | * accessed through the IAlias space by the local processors. * |
| 313 | * The reset value of this register allows access by all nodes. * | 308 | * The reset value of this register allows access by all nodes. * |
| 314 | * * | 309 | * * |
| 315 | ************************************************************************/ | 310 | ************************************************************************/ |
| 316 | 311 | ||
| 317 | typedef union ii_ilapr_u { | 312 | typedef union ii_ilapr_u { |
| 318 | uint64_t ii_ilapr_regval; | 313 | uint64_t ii_ilapr_regval; |
| 319 | struct { | 314 | struct { |
| 320 | uint64_t i_region : 64; | 315 | uint64_t i_region:64; |
| 321 | } ii_ilapr_fld_s; | 316 | } ii_ilapr_fld_s; |
| 322 | } ii_ilapr_u_t; | 317 | } ii_ilapr_u_t; |
| 323 | 318 | ||
| 324 | |||
| 325 | |||
| 326 | |||
| 327 | /************************************************************************ | 319 | /************************************************************************ |
| 328 | * * | 320 | * * |
| 329 | * Description: A write to this register of the 64-bit value * | 321 | * Description: A write to this register of the 64-bit value * |
| 330 | * "SGIrules" in ASCII, will cause the bit in the ILAPR register * | 322 | * "SGIrules" in ASCII, will cause the bit in the ILAPR register * |
| 331 | * corresponding to the region of the requestor to be set (allow * | 323 | * corresponding to the region of the requestor to be set (allow * |
| @@ -334,59 +326,54 @@ typedef union ii_ilapr_u { | |||
| 334 | * This register can also be accessed through the IAlias space. * | 326 | * This register can also be accessed through the IAlias space. * |
| 335 | * However, this access will not change the access permissions in the * | 327 | * However, this access will not change the access permissions in the * |
| 336 | * ILAPR. * | 328 | * ILAPR. * |
| 337 | * * | 329 | * * |
| 338 | ************************************************************************/ | 330 | ************************************************************************/ |
| 339 | 331 | ||
| 340 | typedef union ii_ilapo_u { | 332 | typedef union ii_ilapo_u { |
| 341 | uint64_t ii_ilapo_regval; | 333 | uint64_t ii_ilapo_regval; |
| 342 | struct { | 334 | struct { |
| 343 | uint64_t i_io_ovrride : 64; | 335 | uint64_t i_io_ovrride:64; |
| 344 | } ii_ilapo_fld_s; | 336 | } ii_ilapo_fld_s; |
| 345 | } ii_ilapo_u_t; | 337 | } ii_ilapo_u_t; |
| 346 | 338 | ||
| 347 | |||
| 348 | |||
| 349 | /************************************************************************ | 339 | /************************************************************************ |
| 350 | * * | 340 | * * |
| 351 | * This register qualifies all the PIO and Graphics writes launched * | 341 | * This register qualifies all the PIO and Graphics writes launched * |
| 352 | * from the SHUB towards a widget. * | 342 | * from the SHUB towards a widget. * |
| 353 | * * | 343 | * * |
| 354 | ************************************************************************/ | 344 | ************************************************************************/ |
| 355 | 345 | ||
| 356 | typedef union ii_iowa_u { | 346 | typedef union ii_iowa_u { |
| 357 | uint64_t ii_iowa_regval; | 347 | uint64_t ii_iowa_regval; |
| 358 | struct { | 348 | struct { |
| 359 | uint64_t i_w0_oac : 1; | 349 | uint64_t i_w0_oac:1; |
| 360 | uint64_t i_rsvd_1 : 7; | 350 | uint64_t i_rsvd_1:7; |
| 361 | uint64_t i_wx_oac : 8; | 351 | uint64_t i_wx_oac:8; |
| 362 | uint64_t i_rsvd : 48; | 352 | uint64_t i_rsvd:48; |
| 363 | } ii_iowa_fld_s; | 353 | } ii_iowa_fld_s; |
| 364 | } ii_iowa_u_t; | 354 | } ii_iowa_u_t; |
| 365 | 355 | ||
| 366 | |||
| 367 | /************************************************************************ | 356 | /************************************************************************ |
| 368 | * * | 357 | * * |
| 369 | * Description: This register qualifies all the requests launched * | 358 | * Description: This register qualifies all the requests launched * |
| 370 | * from a widget towards the Shub. This register is intended to be * | 359 | * from a widget towards the Shub. This register is intended to be * |
| 371 | * used by software in case of misbehaving widgets. * | 360 | * used by software in case of misbehaving widgets. * |
| 372 | * * | 361 | * * |
| 373 | * * | 362 | * * |
| 374 | ************************************************************************/ | 363 | ************************************************************************/ |
| 375 | 364 | ||
| 376 | typedef union ii_iiwa_u { | 365 | typedef union ii_iiwa_u { |
| 377 | uint64_t ii_iiwa_regval; | 366 | uint64_t ii_iiwa_regval; |
| 378 | struct { | 367 | struct { |
| 379 | uint64_t i_w0_iac : 1; | 368 | uint64_t i_w0_iac:1; |
| 380 | uint64_t i_rsvd_1 : 7; | 369 | uint64_t i_rsvd_1:7; |
| 381 | uint64_t i_wx_iac : 8; | 370 | uint64_t i_wx_iac:8; |
| 382 | uint64_t i_rsvd : 48; | 371 | uint64_t i_rsvd:48; |
| 383 | } ii_iiwa_fld_s; | 372 | } ii_iiwa_fld_s; |
| 384 | } ii_iiwa_u_t; | 373 | } ii_iiwa_u_t; |
| 385 | 374 | ||
| 386 | |||
| 387 | |||
| 388 | /************************************************************************ | 375 | /************************************************************************ |
| 389 | * * | 376 | * * |
| 390 | * Description: This register qualifies all the operations launched * | 377 | * Description: This register qualifies all the operations launched * |
| 391 | * from a widget towards the SHub. It allows individual access * | 378 | * from a widget towards the SHub. It allows individual access * |
| 392 | * control for up to 8 devices per widget. A device refers to * | 379 | * control for up to 8 devices per widget. A device refers to * |
| @@ -401,72 +388,69 @@ typedef union ii_iiwa_u { | |||
| 401 | * The bits in this field are set by writing a 1 to them. Incoming * | 388 | * The bits in this field are set by writing a 1 to them. Incoming * |
| 402 | * replies from Crosstalk are not subject to this access control * | 389 | * replies from Crosstalk are not subject to this access control * |
| 403 | * mechanism. * | 390 | * mechanism. * |
| 404 | * * | 391 | * * |
| 405 | ************************************************************************/ | 392 | ************************************************************************/ |
| 406 | 393 | ||
| 407 | typedef union ii_iidem_u { | 394 | typedef union ii_iidem_u { |
| 408 | uint64_t ii_iidem_regval; | 395 | uint64_t ii_iidem_regval; |
| 409 | struct { | 396 | struct { |
| 410 | uint64_t i_w8_dxs : 8; | 397 | uint64_t i_w8_dxs:8; |
| 411 | uint64_t i_w9_dxs : 8; | 398 | uint64_t i_w9_dxs:8; |
| 412 | uint64_t i_wa_dxs : 8; | 399 | uint64_t i_wa_dxs:8; |
| 413 | uint64_t i_wb_dxs : 8; | 400 | uint64_t i_wb_dxs:8; |
| 414 | uint64_t i_wc_dxs : 8; | 401 | uint64_t i_wc_dxs:8; |
| 415 | uint64_t i_wd_dxs : 8; | 402 | uint64_t i_wd_dxs:8; |
| 416 | uint64_t i_we_dxs : 8; | 403 | uint64_t i_we_dxs:8; |
| 417 | uint64_t i_wf_dxs : 8; | 404 | uint64_t i_wf_dxs:8; |
| 418 | } ii_iidem_fld_s; | 405 | } ii_iidem_fld_s; |
| 419 | } ii_iidem_u_t; | 406 | } ii_iidem_u_t; |
| 420 | 407 | ||
| 421 | |||
| 422 | /************************************************************************ | 408 | /************************************************************************ |
| 423 | * * | 409 | * * |
| 424 | * This register contains the various programmable fields necessary * | 410 | * This register contains the various programmable fields necessary * |
| 425 | * for controlling and observing the LLP signals. * | 411 | * for controlling and observing the LLP signals. * |
| 426 | * * | 412 | * * |
| 427 | ************************************************************************/ | 413 | ************************************************************************/ |
| 428 | 414 | ||
| 429 | typedef union ii_ilcsr_u { | 415 | typedef union ii_ilcsr_u { |
| 430 | uint64_t ii_ilcsr_regval; | 416 | uint64_t ii_ilcsr_regval; |
| 431 | struct { | 417 | struct { |
| 432 | uint64_t i_nullto : 6; | 418 | uint64_t i_nullto:6; |
| 433 | uint64_t i_rsvd_4 : 2; | 419 | uint64_t i_rsvd_4:2; |
| 434 | uint64_t i_wrmrst : 1; | 420 | uint64_t i_wrmrst:1; |
| 435 | uint64_t i_rsvd_3 : 1; | 421 | uint64_t i_rsvd_3:1; |
| 436 | uint64_t i_llp_en : 1; | 422 | uint64_t i_llp_en:1; |
| 437 | uint64_t i_bm8 : 1; | 423 | uint64_t i_bm8:1; |
| 438 | uint64_t i_llp_stat : 2; | 424 | uint64_t i_llp_stat:2; |
| 439 | uint64_t i_remote_power : 1; | 425 | uint64_t i_remote_power:1; |
| 440 | uint64_t i_rsvd_2 : 1; | 426 | uint64_t i_rsvd_2:1; |
| 441 | uint64_t i_maxrtry : 10; | 427 | uint64_t i_maxrtry:10; |
| 442 | uint64_t i_d_avail_sel : 2; | 428 | uint64_t i_d_avail_sel:2; |
| 443 | uint64_t i_rsvd_1 : 4; | 429 | uint64_t i_rsvd_1:4; |
| 444 | uint64_t i_maxbrst : 10; | 430 | uint64_t i_maxbrst:10; |
| 445 | uint64_t i_rsvd : 22; | 431 | uint64_t i_rsvd:22; |
| 446 | 432 | ||
| 447 | } ii_ilcsr_fld_s; | 433 | } ii_ilcsr_fld_s; |
| 448 | } ii_ilcsr_u_t; | 434 | } ii_ilcsr_u_t; |
| 449 | 435 | ||
| 450 | |||
| 451 | /************************************************************************ | 436 | /************************************************************************ |
| 452 | * * | 437 | * * |
| 453 | * This is simply a status registers that monitors the LLP error * | 438 | * This is simply a status registers that monitors the LLP error * |
| 454 | * rate. * | 439 | * rate. * |
| 455 | * * | 440 | * * |
| 456 | ************************************************************************/ | 441 | ************************************************************************/ |
| 457 | 442 | ||
| 458 | typedef union ii_illr_u { | 443 | typedef union ii_illr_u { |
| 459 | uint64_t ii_illr_regval; | 444 | uint64_t ii_illr_regval; |
| 460 | struct { | 445 | struct { |
| 461 | uint64_t i_sn_cnt : 16; | 446 | uint64_t i_sn_cnt:16; |
| 462 | uint64_t i_cb_cnt : 16; | 447 | uint64_t i_cb_cnt:16; |
| 463 | uint64_t i_rsvd : 32; | 448 | uint64_t i_rsvd:32; |
| 464 | } ii_illr_fld_s; | 449 | } ii_illr_fld_s; |
| 465 | } ii_illr_u_t; | 450 | } ii_illr_u_t; |
| 466 | 451 | ||
| 467 | |||
| 468 | /************************************************************************ | 452 | /************************************************************************ |
| 469 | * * | 453 | * * |
| 470 | * Description: All II-detected non-BTE error interrupts are * | 454 | * Description: All II-detected non-BTE error interrupts are * |
| 471 | * specified via this register. * | 455 | * specified via this register. * |
| 472 | * NOTE: The PI interrupt register address is hardcoded in the II. If * | 456 | * NOTE: The PI interrupt register address is hardcoded in the II. If * |
| @@ -476,107 +460,100 @@ typedef union ii_illr_u { | |||
| 476 | * PI_ID==1, then the II sends the interrupt request to address * | 460 | * PI_ID==1, then the II sends the interrupt request to address * |
| 477 | * offset 0x01A0_0090 within the local register address space of PI1 * | 461 | * offset 0x01A0_0090 within the local register address space of PI1 * |
| 478 | * on the node specified by the NODE field. * | 462 | * on the node specified by the NODE field. * |
| 479 | * * | 463 | * * |
| 480 | ************************************************************************/ | 464 | ************************************************************************/ |
| 481 | 465 | ||
| 482 | typedef union ii_iidsr_u { | 466 | typedef union ii_iidsr_u { |
| 483 | uint64_t ii_iidsr_regval; | 467 | uint64_t ii_iidsr_regval; |
| 484 | struct { | 468 | struct { |
| 485 | uint64_t i_level : 8; | 469 | uint64_t i_level:8; |
| 486 | uint64_t i_pi_id : 1; | 470 | uint64_t i_pi_id:1; |
| 487 | uint64_t i_node : 11; | 471 | uint64_t i_node:11; |
| 488 | uint64_t i_rsvd_3 : 4; | 472 | uint64_t i_rsvd_3:4; |
| 489 | uint64_t i_enable : 1; | 473 | uint64_t i_enable:1; |
| 490 | uint64_t i_rsvd_2 : 3; | 474 | uint64_t i_rsvd_2:3; |
| 491 | uint64_t i_int_sent : 2; | 475 | uint64_t i_int_sent:2; |
| 492 | uint64_t i_rsvd_1 : 2; | 476 | uint64_t i_rsvd_1:2; |
| 493 | uint64_t i_pi0_forward_int : 1; | 477 | uint64_t i_pi0_forward_int:1; |
| 494 | uint64_t i_pi1_forward_int : 1; | 478 | uint64_t i_pi1_forward_int:1; |
| 495 | uint64_t i_rsvd : 30; | 479 | uint64_t i_rsvd:30; |
| 496 | } ii_iidsr_fld_s; | 480 | } ii_iidsr_fld_s; |
| 497 | } ii_iidsr_u_t; | 481 | } ii_iidsr_u_t; |
| 498 | 482 | ||
| 499 | |||
| 500 | |||
| 501 | /************************************************************************ | 483 | /************************************************************************ |
| 502 | * * | 484 | * * |
| 503 | * There are two instances of this register. This register is used * | 485 | * There are two instances of this register. This register is used * |
| 504 | * for matching up the incoming responses from the graphics widget to * | 486 | * for matching up the incoming responses from the graphics widget to * |
| 505 | * the processor that initiated the graphics operation. The * | 487 | * the processor that initiated the graphics operation. The * |
| 506 | * write-responses are converted to graphics credits and returned to * | 488 | * write-responses are converted to graphics credits and returned to * |
| 507 | * the processor so that the processor interface can manage the flow * | 489 | * the processor so that the processor interface can manage the flow * |
| 508 | * control. * | 490 | * control. * |
| 509 | * * | 491 | * * |
| 510 | ************************************************************************/ | 492 | ************************************************************************/ |
| 511 | 493 | ||
| 512 | typedef union ii_igfx0_u { | 494 | typedef union ii_igfx0_u { |
| 513 | uint64_t ii_igfx0_regval; | 495 | uint64_t ii_igfx0_regval; |
| 514 | struct { | 496 | struct { |
| 515 | uint64_t i_w_num : 4; | 497 | uint64_t i_w_num:4; |
| 516 | uint64_t i_pi_id : 1; | 498 | uint64_t i_pi_id:1; |
| 517 | uint64_t i_n_num : 12; | 499 | uint64_t i_n_num:12; |
| 518 | uint64_t i_p_num : 1; | 500 | uint64_t i_p_num:1; |
| 519 | uint64_t i_rsvd : 46; | 501 | uint64_t i_rsvd:46; |
| 520 | } ii_igfx0_fld_s; | 502 | } ii_igfx0_fld_s; |
| 521 | } ii_igfx0_u_t; | 503 | } ii_igfx0_u_t; |
| 522 | 504 | ||
| 523 | |||
| 524 | /************************************************************************ | 505 | /************************************************************************ |
| 525 | * * | 506 | * * |
| 526 | * There are two instances of this register. This register is used * | 507 | * There are two instances of this register. This register is used * |
| 527 | * for matching up the incoming responses from the graphics widget to * | 508 | * for matching up the incoming responses from the graphics widget to * |
| 528 | * the processor that initiated the graphics operation. The * | 509 | * the processor that initiated the graphics operation. The * |
| 529 | * write-responses are converted to graphics credits and returned to * | 510 | * write-responses are converted to graphics credits and returned to * |
| 530 | * the processor so that the processor interface can manage the flow * | 511 | * the processor so that the processor interface can manage the flow * |
| 531 | * control. * | 512 | * control. * |
| 532 | * * | 513 | * * |
| 533 | ************************************************************************/ | 514 | ************************************************************************/ |
| 534 | 515 | ||
| 535 | typedef union ii_igfx1_u { | 516 | typedef union ii_igfx1_u { |
| 536 | uint64_t ii_igfx1_regval; | 517 | uint64_t ii_igfx1_regval; |
| 537 | struct { | 518 | struct { |
| 538 | uint64_t i_w_num : 4; | 519 | uint64_t i_w_num:4; |
| 539 | uint64_t i_pi_id : 1; | 520 | uint64_t i_pi_id:1; |
| 540 | uint64_t i_n_num : 12; | 521 | uint64_t i_n_num:12; |
| 541 | uint64_t i_p_num : 1; | 522 | uint64_t i_p_num:1; |
| 542 | uint64_t i_rsvd : 46; | 523 | uint64_t i_rsvd:46; |
| 543 | } ii_igfx1_fld_s; | 524 | } ii_igfx1_fld_s; |
| 544 | } ii_igfx1_u_t; | 525 | } ii_igfx1_u_t; |
| 545 | 526 | ||
| 546 | |||
| 547 | /************************************************************************ | 527 | /************************************************************************ |
| 548 | * * | 528 | * * |
| 549 | * There are two instances of this registers. These registers are * | 529 | * There are two instances of this registers. These registers are * |
| 550 | * used as scratch registers for software use. * | 530 | * used as scratch registers for software use. * |
| 551 | * * | 531 | * * |
| 552 | ************************************************************************/ | 532 | ************************************************************************/ |
| 553 | 533 | ||
| 554 | typedef union ii_iscr0_u { | 534 | typedef union ii_iscr0_u { |
| 555 | uint64_t ii_iscr0_regval; | 535 | uint64_t ii_iscr0_regval; |
| 556 | struct { | 536 | struct { |
| 557 | uint64_t i_scratch : 64; | 537 | uint64_t i_scratch:64; |
| 558 | } ii_iscr0_fld_s; | 538 | } ii_iscr0_fld_s; |
| 559 | } ii_iscr0_u_t; | 539 | } ii_iscr0_u_t; |
| 560 | 540 | ||
| 561 | |||
| 562 | |||
| 563 | /************************************************************************ | 541 | /************************************************************************ |
| 564 | * * | 542 | * * |
| 565 | * There are two instances of this registers. These registers are * | 543 | * There are two instances of this registers. These registers are * |
| 566 | * used as scratch registers for software use. * | 544 | * used as scratch registers for software use. * |
| 567 | * * | 545 | * * |
| 568 | ************************************************************************/ | 546 | ************************************************************************/ |
| 569 | 547 | ||
| 570 | typedef union ii_iscr1_u { | 548 | typedef union ii_iscr1_u { |
| 571 | uint64_t ii_iscr1_regval; | 549 | uint64_t ii_iscr1_regval; |
| 572 | struct { | 550 | struct { |
| 573 | uint64_t i_scratch : 64; | 551 | uint64_t i_scratch:64; |
| 574 | } ii_iscr1_fld_s; | 552 | } ii_iscr1_fld_s; |
| 575 | } ii_iscr1_u_t; | 553 | } ii_iscr1_u_t; |
| 576 | 554 | ||
| 577 | |||
| 578 | /************************************************************************ | 555 | /************************************************************************ |
| 579 | * * | 556 | * * |
| 580 | * Description: There are seven instances of translation table entry * | 557 | * Description: There are seven instances of translation table entry * |
| 581 | * registers. Each register maps a Shub Big Window to a 48-bit * | 558 | * registers. Each register maps a Shub Big Window to a 48-bit * |
| 582 | * address on Crosstalk. * | 559 | * address on Crosstalk. * |
| @@ -599,23 +576,22 @@ typedef union ii_iscr1_u { | |||
| 599 | * Crosstalk space addressable by the Shub is thus the lower * | 576 | * Crosstalk space addressable by the Shub is thus the lower * |
| 600 | * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * | 577 | * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * |
| 601 | * of this space can be accessed. * | 578 | * of this space can be accessed. * |
| 602 | * * | 579 | * * |
| 603 | ************************************************************************/ | 580 | ************************************************************************/ |
| 604 | 581 | ||
| 605 | typedef union ii_itte1_u { | 582 | typedef union ii_itte1_u { |
| 606 | uint64_t ii_itte1_regval; | 583 | uint64_t ii_itte1_regval; |
| 607 | struct { | 584 | struct { |
| 608 | uint64_t i_offset : 5; | 585 | uint64_t i_offset:5; |
| 609 | uint64_t i_rsvd_1 : 3; | 586 | uint64_t i_rsvd_1:3; |
| 610 | uint64_t i_w_num : 4; | 587 | uint64_t i_w_num:4; |
| 611 | uint64_t i_iosp : 1; | 588 | uint64_t i_iosp:1; |
| 612 | uint64_t i_rsvd : 51; | 589 | uint64_t i_rsvd:51; |
| 613 | } ii_itte1_fld_s; | 590 | } ii_itte1_fld_s; |
| 614 | } ii_itte1_u_t; | 591 | } ii_itte1_u_t; |
| 615 | 592 | ||
| 616 | |||
| 617 | /************************************************************************ | 593 | /************************************************************************ |
| 618 | * * | 594 | * * |
| 619 | * Description: There are seven instances of translation table entry * | 595 | * Description: There are seven instances of translation table entry * |
| 620 | * registers. Each register maps a Shub Big Window to a 48-bit * | 596 | * registers. Each register maps a Shub Big Window to a 48-bit * |
| 621 | * address on Crosstalk. * | 597 | * address on Crosstalk. * |
| @@ -638,23 +614,22 @@ typedef union ii_itte1_u { | |||
| 638 | * Crosstalk space addressable by the Shub is thus the lower * | 614 | * Crosstalk space addressable by the Shub is thus the lower * |
| 639 | * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * | 615 | * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * |
| 640 | * of this space can be accessed. * | 616 | * of this space can be accessed. * |
| 641 | * * | 617 | * * |
| 642 | ************************************************************************/ | 618 | ************************************************************************/ |
| 643 | 619 | ||
| 644 | typedef union ii_itte2_u { | 620 | typedef union ii_itte2_u { |
| 645 | uint64_t ii_itte2_regval; | 621 | uint64_t ii_itte2_regval; |
| 646 | struct { | 622 | struct { |
| 647 | uint64_t i_offset : 5; | 623 | uint64_t i_offset:5; |
| 648 | uint64_t i_rsvd_1 : 3; | 624 | uint64_t i_rsvd_1:3; |
| 649 | uint64_t i_w_num : 4; | 625 | uint64_t i_w_num:4; |
| 650 | uint64_t i_iosp : 1; | 626 | uint64_t i_iosp:1; |
| 651 | uint64_t i_rsvd : 51; | 627 | uint64_t i_rsvd:51; |
| 652 | } ii_itte2_fld_s; | 628 | } ii_itte2_fld_s; |
| 653 | } ii_itte2_u_t; | 629 | } ii_itte2_u_t; |
| 654 | 630 | ||
| 655 | |||
| 656 | /************************************************************************ | 631 | /************************************************************************ |
| 657 | * * | 632 | * * |
| 658 | * Description: There are seven instances of translation table entry * | 633 | * Description: There are seven instances of translation table entry * |
| 659 | * registers. Each register maps a Shub Big Window to a 48-bit * | 634 | * registers. Each register maps a Shub Big Window to a 48-bit * |
| 660 | * address on Crosstalk. * | 635 | * address on Crosstalk. * |
| @@ -677,23 +652,22 @@ typedef union ii_itte2_u { | |||
| 677 | * Crosstalk space addressable by the SHub is thus the lower * | 652 | * Crosstalk space addressable by the SHub is thus the lower * |
| 678 | * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * | 653 | * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * |
| 679 | * of this space can be accessed. * | 654 | * of this space can be accessed. * |
| 680 | * * | 655 | * * |
| 681 | ************************************************************************/ | 656 | ************************************************************************/ |
| 682 | 657 | ||
| 683 | typedef union ii_itte3_u { | 658 | typedef union ii_itte3_u { |
| 684 | uint64_t ii_itte3_regval; | 659 | uint64_t ii_itte3_regval; |
| 685 | struct { | 660 | struct { |
| 686 | uint64_t i_offset : 5; | 661 | uint64_t i_offset:5; |
| 687 | uint64_t i_rsvd_1 : 3; | 662 | uint64_t i_rsvd_1:3; |
| 688 | uint64_t i_w_num : 4; | 663 | uint64_t i_w_num:4; |
| 689 | uint64_t i_iosp : 1; | 664 | uint64_t i_iosp:1; |
| 690 | uint64_t i_rsvd : 51; | 665 | uint64_t i_rsvd:51; |
| 691 | } ii_itte3_fld_s; | 666 | } ii_itte3_fld_s; |
| 692 | } ii_itte3_u_t; | 667 | } ii_itte3_u_t; |
| 693 | 668 | ||
| 694 | |||
| 695 | /************************************************************************ | 669 | /************************************************************************ |
| 696 | * * | 670 | * * |
| 697 | * Description: There are seven instances of translation table entry * | 671 | * Description: There are seven instances of translation table entry * |
| 698 | * registers. Each register maps a SHub Big Window to a 48-bit * | 672 | * registers. Each register maps a SHub Big Window to a 48-bit * |
| 699 | * address on Crosstalk. * | 673 | * address on Crosstalk. * |
| @@ -716,23 +690,22 @@ typedef union ii_itte3_u { | |||
| 716 | * Crosstalk space addressable by the SHub is thus the lower * | 690 | * Crosstalk space addressable by the SHub is thus the lower * |
| 717 | * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * | 691 | * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * |
| 718 | * of this space can be accessed. * | 692 | * of this space can be accessed. * |
| 719 | * * | 693 | * * |
| 720 | ************************************************************************/ | 694 | ************************************************************************/ |
| 721 | 695 | ||
| 722 | typedef union ii_itte4_u { | 696 | typedef union ii_itte4_u { |
| 723 | uint64_t ii_itte4_regval; | 697 | uint64_t ii_itte4_regval; |
| 724 | struct { | 698 | struct { |
| 725 | uint64_t i_offset : 5; | 699 | uint64_t i_offset:5; |
| 726 | uint64_t i_rsvd_1 : 3; | 700 | uint64_t i_rsvd_1:3; |
| 727 | uint64_t i_w_num : 4; | 701 | uint64_t i_w_num:4; |
| 728 | uint64_t i_iosp : 1; | 702 | uint64_t i_iosp:1; |
| 729 | uint64_t i_rsvd : 51; | 703 | uint64_t i_rsvd:51; |
| 730 | } ii_itte4_fld_s; | 704 | } ii_itte4_fld_s; |
| 731 | } ii_itte4_u_t; | 705 | } ii_itte4_u_t; |
| 732 | 706 | ||
| 733 | |||
| 734 | /************************************************************************ | 707 | /************************************************************************ |
| 735 | * * | 708 | * * |
| 736 | * Description: There are seven instances of translation table entry * | 709 | * Description: There are seven instances of translation table entry * |
| 737 | * registers. Each register maps a SHub Big Window to a 48-bit * | 710 | * registers. Each register maps a SHub Big Window to a 48-bit * |
| 738 | * address on Crosstalk. * | 711 | * address on Crosstalk. * |
| @@ -755,23 +728,22 @@ typedef union ii_itte4_u { | |||
| 755 | * Crosstalk space addressable by the Shub is thus the lower * | 728 | * Crosstalk space addressable by the Shub is thus the lower * |
| 756 | * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * | 729 | * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * |
| 757 | * of this space can be accessed. * | 730 | * of this space can be accessed. * |
| 758 | * * | 731 | * * |
| 759 | ************************************************************************/ | 732 | ************************************************************************/ |
| 760 | 733 | ||
| 761 | typedef union ii_itte5_u { | 734 | typedef union ii_itte5_u { |
| 762 | uint64_t ii_itte5_regval; | 735 | uint64_t ii_itte5_regval; |
| 763 | struct { | 736 | struct { |
| 764 | uint64_t i_offset : 5; | 737 | uint64_t i_offset:5; |
| 765 | uint64_t i_rsvd_1 : 3; | 738 | uint64_t i_rsvd_1:3; |
| 766 | uint64_t i_w_num : 4; | 739 | uint64_t i_w_num:4; |
| 767 | uint64_t i_iosp : 1; | 740 | uint64_t i_iosp:1; |
| 768 | uint64_t i_rsvd : 51; | 741 | uint64_t i_rsvd:51; |
| 769 | } ii_itte5_fld_s; | 742 | } ii_itte5_fld_s; |
| 770 | } ii_itte5_u_t; | 743 | } ii_itte5_u_t; |
| 771 | 744 | ||
| 772 | |||
| 773 | /************************************************************************ | 745 | /************************************************************************ |
| 774 | * * | 746 | * * |
| 775 | * Description: There are seven instances of translation table entry * | 747 | * Description: There are seven instances of translation table entry * |
| 776 | * registers. Each register maps a Shub Big Window to a 48-bit * | 748 | * registers. Each register maps a Shub Big Window to a 48-bit * |
| 777 | * address on Crosstalk. * | 749 | * address on Crosstalk. * |
| @@ -794,23 +766,22 @@ typedef union ii_itte5_u { | |||
| 794 | * Crosstalk space addressable by the Shub is thus the lower * | 766 | * Crosstalk space addressable by the Shub is thus the lower * |
| 795 | * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * | 767 | * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * |
| 796 | * of this space can be accessed. * | 768 | * of this space can be accessed. * |
| 797 | * * | 769 | * * |
| 798 | ************************************************************************/ | 770 | ************************************************************************/ |
| 799 | 771 | ||
| 800 | typedef union ii_itte6_u { | 772 | typedef union ii_itte6_u { |
| 801 | uint64_t ii_itte6_regval; | 773 | uint64_t ii_itte6_regval; |
| 802 | struct { | 774 | struct { |
| 803 | uint64_t i_offset : 5; | 775 | uint64_t i_offset:5; |
| 804 | uint64_t i_rsvd_1 : 3; | 776 | uint64_t i_rsvd_1:3; |
| 805 | uint64_t i_w_num : 4; | 777 | uint64_t i_w_num:4; |
| 806 | uint64_t i_iosp : 1; | 778 | uint64_t i_iosp:1; |
| 807 | uint64_t i_rsvd : 51; | 779 | uint64_t i_rsvd:51; |
| 808 | } ii_itte6_fld_s; | 780 | } ii_itte6_fld_s; |
| 809 | } ii_itte6_u_t; | 781 | } ii_itte6_u_t; |
| 810 | 782 | ||
| 811 | |||
| 812 | /************************************************************************ | 783 | /************************************************************************ |
| 813 | * * | 784 | * * |
| 814 | * Description: There are seven instances of translation table entry * | 785 | * Description: There are seven instances of translation table entry * |
| 815 | * registers. Each register maps a Shub Big Window to a 48-bit * | 786 | * registers. Each register maps a Shub Big Window to a 48-bit * |
| 816 | * address on Crosstalk. * | 787 | * address on Crosstalk. * |
| @@ -833,23 +804,22 @@ typedef union ii_itte6_u { | |||
| 833 | * Crosstalk space addressable by the SHub is thus the lower * | 804 | * Crosstalk space addressable by the SHub is thus the lower * |
| 834 | * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * | 805 | * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * |
| 835 | * of this space can be accessed. * | 806 | * of this space can be accessed. * |
| 836 | * * | 807 | * * |
| 837 | ************************************************************************/ | 808 | ************************************************************************/ |
| 838 | 809 | ||
| 839 | typedef union ii_itte7_u { | 810 | typedef union ii_itte7_u { |
| 840 | uint64_t ii_itte7_regval; | 811 | uint64_t ii_itte7_regval; |
| 841 | struct { | 812 | struct { |
| 842 | uint64_t i_offset : 5; | 813 | uint64_t i_offset:5; |
| 843 | uint64_t i_rsvd_1 : 3; | 814 | uint64_t i_rsvd_1:3; |
| 844 | uint64_t i_w_num : 4; | 815 | uint64_t i_w_num:4; |
| 845 | uint64_t i_iosp : 1; | 816 | uint64_t i_iosp:1; |
| 846 | uint64_t i_rsvd : 51; | 817 | uint64_t i_rsvd:51; |
| 847 | } ii_itte7_fld_s; | 818 | } ii_itte7_fld_s; |
| 848 | } ii_itte7_u_t; | 819 | } ii_itte7_u_t; |
| 849 | 820 | ||
| 850 | |||
| 851 | /************************************************************************ | 821 | /************************************************************************ |
| 852 | * * | 822 | * * |
| 853 | * Description: There are 9 instances of this register, one per * | 823 | * Description: There are 9 instances of this register, one per * |
| 854 | * actual widget in this implementation of SHub and Crossbow. * | 824 | * actual widget in this implementation of SHub and Crossbow. * |
| 855 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * | 825 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * |
| @@ -868,33 +838,32 @@ typedef union ii_itte7_u { | |||
| 868 | * register; the write will correct the C field and capture its new * | 838 | * register; the write will correct the C field and capture its new * |
| 869 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * | 839 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * |
| 870 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * | 840 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * |
| 871 | * . * | 841 | * . * |
| 872 | * * | 842 | * * |
| 873 | ************************************************************************/ | 843 | ************************************************************************/ |
| 874 | 844 | ||
| 875 | typedef union ii_iprb0_u { | 845 | typedef union ii_iprb0_u { |
| 876 | uint64_t ii_iprb0_regval; | 846 | uint64_t ii_iprb0_regval; |
| 877 | struct { | 847 | struct { |
| 878 | uint64_t i_c : 8; | 848 | uint64_t i_c:8; |
| 879 | uint64_t i_na : 14; | 849 | uint64_t i_na:14; |
| 880 | uint64_t i_rsvd_2 : 2; | 850 | uint64_t i_rsvd_2:2; |
| 881 | uint64_t i_nb : 14; | 851 | uint64_t i_nb:14; |
| 882 | uint64_t i_rsvd_1 : 2; | 852 | uint64_t i_rsvd_1:2; |
| 883 | uint64_t i_m : 2; | 853 | uint64_t i_m:2; |
| 884 | uint64_t i_f : 1; | 854 | uint64_t i_f:1; |
| 885 | uint64_t i_of_cnt : 5; | 855 | uint64_t i_of_cnt:5; |
| 886 | uint64_t i_error : 1; | 856 | uint64_t i_error:1; |
| 887 | uint64_t i_rd_to : 1; | 857 | uint64_t i_rd_to:1; |
| 888 | uint64_t i_spur_wr : 1; | 858 | uint64_t i_spur_wr:1; |
| 889 | uint64_t i_spur_rd : 1; | 859 | uint64_t i_spur_rd:1; |
| 890 | uint64_t i_rsvd : 11; | 860 | uint64_t i_rsvd:11; |
| 891 | uint64_t i_mult_err : 1; | 861 | uint64_t i_mult_err:1; |
| 892 | } ii_iprb0_fld_s; | 862 | } ii_iprb0_fld_s; |
| 893 | } ii_iprb0_u_t; | 863 | } ii_iprb0_u_t; |
| 894 | 864 | ||
| 895 | |||
| 896 | /************************************************************************ | 865 | /************************************************************************ |
| 897 | * * | 866 | * * |
| 898 | * Description: There are 9 instances of this register, one per * | 867 | * Description: There are 9 instances of this register, one per * |
| 899 | * actual widget in this implementation of SHub and Crossbow. * | 868 | * actual widget in this implementation of SHub and Crossbow. * |
| 900 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * | 869 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * |
| @@ -913,33 +882,32 @@ typedef union ii_iprb0_u { | |||
| 913 | * register; the write will correct the C field and capture its new * | 882 | * register; the write will correct the C field and capture its new * |
| 914 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * | 883 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * |
| 915 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * | 884 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * |
| 916 | * . * | 885 | * . * |
| 917 | * * | 886 | * * |
| 918 | ************************************************************************/ | 887 | ************************************************************************/ |
| 919 | 888 | ||
| 920 | typedef union ii_iprb8_u { | 889 | typedef union ii_iprb8_u { |
| 921 | uint64_t ii_iprb8_regval; | 890 | uint64_t ii_iprb8_regval; |
| 922 | struct { | 891 | struct { |
| 923 | uint64_t i_c : 8; | 892 | uint64_t i_c:8; |
| 924 | uint64_t i_na : 14; | 893 | uint64_t i_na:14; |
| 925 | uint64_t i_rsvd_2 : 2; | 894 | uint64_t i_rsvd_2:2; |
| 926 | uint64_t i_nb : 14; | 895 | uint64_t i_nb:14; |
| 927 | uint64_t i_rsvd_1 : 2; | 896 | uint64_t i_rsvd_1:2; |
| 928 | uint64_t i_m : 2; | 897 | uint64_t i_m:2; |
| 929 | uint64_t i_f : 1; | 898 | uint64_t i_f:1; |
| 930 | uint64_t i_of_cnt : 5; | 899 | uint64_t i_of_cnt:5; |
| 931 | uint64_t i_error : 1; | 900 | uint64_t i_error:1; |
| 932 | uint64_t i_rd_to : 1; | 901 | uint64_t i_rd_to:1; |
| 933 | uint64_t i_spur_wr : 1; | 902 | uint64_t i_spur_wr:1; |
| 934 | uint64_t i_spur_rd : 1; | 903 | uint64_t i_spur_rd:1; |
| 935 | uint64_t i_rsvd : 11; | 904 | uint64_t i_rsvd:11; |
| 936 | uint64_t i_mult_err : 1; | 905 | uint64_t i_mult_err:1; |
| 937 | } ii_iprb8_fld_s; | 906 | } ii_iprb8_fld_s; |
| 938 | } ii_iprb8_u_t; | 907 | } ii_iprb8_u_t; |
| 939 | 908 | ||
| 940 | |||
| 941 | /************************************************************************ | 909 | /************************************************************************ |
| 942 | * * | 910 | * * |
| 943 | * Description: There are 9 instances of this register, one per * | 911 | * Description: There are 9 instances of this register, one per * |
| 944 | * actual widget in this implementation of SHub and Crossbow. * | 912 | * actual widget in this implementation of SHub and Crossbow. * |
| 945 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * | 913 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * |
| @@ -958,33 +926,32 @@ typedef union ii_iprb8_u { | |||
| 958 | * register; the write will correct the C field and capture its new * | 926 | * register; the write will correct the C field and capture its new * |
| 959 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * | 927 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * |
| 960 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * | 928 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * |
| 961 | * . * | 929 | * . * |
| 962 | * * | 930 | * * |
| 963 | ************************************************************************/ | 931 | ************************************************************************/ |
| 964 | 932 | ||
| 965 | typedef union ii_iprb9_u { | 933 | typedef union ii_iprb9_u { |
| 966 | uint64_t ii_iprb9_regval; | 934 | uint64_t ii_iprb9_regval; |
| 967 | struct { | 935 | struct { |
| 968 | uint64_t i_c : 8; | 936 | uint64_t i_c:8; |
| 969 | uint64_t i_na : 14; | 937 | uint64_t i_na:14; |
| 970 | uint64_t i_rsvd_2 : 2; | 938 | uint64_t i_rsvd_2:2; |
| 971 | uint64_t i_nb : 14; | 939 | uint64_t i_nb:14; |
| 972 | uint64_t i_rsvd_1 : 2; | 940 | uint64_t i_rsvd_1:2; |
| 973 | uint64_t i_m : 2; | 941 | uint64_t i_m:2; |
| 974 | uint64_t i_f : 1; | 942 | uint64_t i_f:1; |
| 975 | uint64_t i_of_cnt : 5; | 943 | uint64_t i_of_cnt:5; |
| 976 | uint64_t i_error : 1; | 944 | uint64_t i_error:1; |
| 977 | uint64_t i_rd_to : 1; | 945 | uint64_t i_rd_to:1; |
| 978 | uint64_t i_spur_wr : 1; | 946 | uint64_t i_spur_wr:1; |
| 979 | uint64_t i_spur_rd : 1; | 947 | uint64_t i_spur_rd:1; |
| 980 | uint64_t i_rsvd : 11; | 948 | uint64_t i_rsvd:11; |
| 981 | uint64_t i_mult_err : 1; | 949 | uint64_t i_mult_err:1; |
| 982 | } ii_iprb9_fld_s; | 950 | } ii_iprb9_fld_s; |
| 983 | } ii_iprb9_u_t; | 951 | } ii_iprb9_u_t; |
| 984 | 952 | ||
| 985 | |||
| 986 | /************************************************************************ | 953 | /************************************************************************ |
| 987 | * * | 954 | * * |
| 988 | * Description: There are 9 instances of this register, one per * | 955 | * Description: There are 9 instances of this register, one per * |
| 989 | * actual widget in this implementation of SHub and Crossbow. * | 956 | * actual widget in this implementation of SHub and Crossbow. * |
| 990 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * | 957 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * |
| @@ -1003,33 +970,32 @@ typedef union ii_iprb9_u { | |||
| 1003 | * register; the write will correct the C field and capture its new * | 970 | * register; the write will correct the C field and capture its new * |
| 1004 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * | 971 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * |
| 1005 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * | 972 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * |
| 1006 | * * | 973 | * * |
| 1007 | * * | 974 | * * |
| 1008 | ************************************************************************/ | 975 | ************************************************************************/ |
| 1009 | 976 | ||
| 1010 | typedef union ii_iprba_u { | 977 | typedef union ii_iprba_u { |
| 1011 | uint64_t ii_iprba_regval; | 978 | uint64_t ii_iprba_regval; |
| 1012 | struct { | 979 | struct { |
| 1013 | uint64_t i_c : 8; | 980 | uint64_t i_c:8; |
| 1014 | uint64_t i_na : 14; | 981 | uint64_t i_na:14; |
| 1015 | uint64_t i_rsvd_2 : 2; | 982 | uint64_t i_rsvd_2:2; |
| 1016 | uint64_t i_nb : 14; | 983 | uint64_t i_nb:14; |
| 1017 | uint64_t i_rsvd_1 : 2; | 984 | uint64_t i_rsvd_1:2; |
| 1018 | uint64_t i_m : 2; | 985 | uint64_t i_m:2; |
| 1019 | uint64_t i_f : 1; | 986 | uint64_t i_f:1; |
| 1020 | uint64_t i_of_cnt : 5; | 987 | uint64_t i_of_cnt:5; |
| 1021 | uint64_t i_error : 1; | 988 | uint64_t i_error:1; |
| 1022 | uint64_t i_rd_to : 1; | 989 | uint64_t i_rd_to:1; |
| 1023 | uint64_t i_spur_wr : 1; | 990 | uint64_t i_spur_wr:1; |
| 1024 | uint64_t i_spur_rd : 1; | 991 | uint64_t i_spur_rd:1; |
| 1025 | uint64_t i_rsvd : 11; | 992 | uint64_t i_rsvd:11; |
| 1026 | uint64_t i_mult_err : 1; | 993 | uint64_t i_mult_err:1; |
| 1027 | } ii_iprba_fld_s; | 994 | } ii_iprba_fld_s; |
| 1028 | } ii_iprba_u_t; | 995 | } ii_iprba_u_t; |
| 1029 | 996 | ||
| 1030 | |||
| 1031 | /************************************************************************ | 997 | /************************************************************************ |
| 1032 | * * | 998 | * * |
| 1033 | * Description: There are 9 instances of this register, one per * | 999 | * Description: There are 9 instances of this register, one per * |
| 1034 | * actual widget in this implementation of SHub and Crossbow. * | 1000 | * actual widget in this implementation of SHub and Crossbow. * |
| 1035 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * | 1001 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * |
| @@ -1048,33 +1014,32 @@ typedef union ii_iprba_u { | |||
| 1048 | * register; the write will correct the C field and capture its new * | 1014 | * register; the write will correct the C field and capture its new * |
| 1049 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * | 1015 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * |
| 1050 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * | 1016 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * |
| 1051 | * . * | 1017 | * . * |
| 1052 | * * | 1018 | * * |
| 1053 | ************************************************************************/ | 1019 | ************************************************************************/ |
| 1054 | 1020 | ||
| 1055 | typedef union ii_iprbb_u { | 1021 | typedef union ii_iprbb_u { |
| 1056 | uint64_t ii_iprbb_regval; | 1022 | uint64_t ii_iprbb_regval; |
| 1057 | struct { | 1023 | struct { |
| 1058 | uint64_t i_c : 8; | 1024 | uint64_t i_c:8; |
| 1059 | uint64_t i_na : 14; | 1025 | uint64_t i_na:14; |
| 1060 | uint64_t i_rsvd_2 : 2; | 1026 | uint64_t i_rsvd_2:2; |
| 1061 | uint64_t i_nb : 14; | 1027 | uint64_t i_nb:14; |
| 1062 | uint64_t i_rsvd_1 : 2; | 1028 | uint64_t i_rsvd_1:2; |
| 1063 | uint64_t i_m : 2; | 1029 | uint64_t i_m:2; |
| 1064 | uint64_t i_f : 1; | 1030 | uint64_t i_f:1; |
| 1065 | uint64_t i_of_cnt : 5; | 1031 | uint64_t i_of_cnt:5; |
| 1066 | uint64_t i_error : 1; | 1032 | uint64_t i_error:1; |
| 1067 | uint64_t i_rd_to : 1; | 1033 | uint64_t i_rd_to:1; |
| 1068 | uint64_t i_spur_wr : 1; | 1034 | uint64_t i_spur_wr:1; |
| 1069 | uint64_t i_spur_rd : 1; | 1035 | uint64_t i_spur_rd:1; |
| 1070 | uint64_t i_rsvd : 11; | 1036 | uint64_t i_rsvd:11; |
| 1071 | uint64_t i_mult_err : 1; | 1037 | uint64_t i_mult_err:1; |
| 1072 | } ii_iprbb_fld_s; | 1038 | } ii_iprbb_fld_s; |
| 1073 | } ii_iprbb_u_t; | 1039 | } ii_iprbb_u_t; |
| 1074 | 1040 | ||
| 1075 | |||
| 1076 | /************************************************************************ | 1041 | /************************************************************************ |
| 1077 | * * | 1042 | * * |
| 1078 | * Description: There are 9 instances of this register, one per * | 1043 | * Description: There are 9 instances of this register, one per * |
| 1079 | * actual widget in this implementation of SHub and Crossbow. * | 1044 | * actual widget in this implementation of SHub and Crossbow. * |
| 1080 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * | 1045 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * |
| @@ -1093,33 +1058,32 @@ typedef union ii_iprbb_u { | |||
| 1093 | * register; the write will correct the C field and capture its new * | 1058 | * register; the write will correct the C field and capture its new * |
| 1094 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * | 1059 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * |
| 1095 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * | 1060 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * |
| 1096 | * . * | 1061 | * . * |
| 1097 | * * | 1062 | * * |
| 1098 | ************************************************************************/ | 1063 | ************************************************************************/ |
| 1099 | 1064 | ||
| 1100 | typedef union ii_iprbc_u { | 1065 | typedef union ii_iprbc_u { |
| 1101 | uint64_t ii_iprbc_regval; | 1066 | uint64_t ii_iprbc_regval; |
| 1102 | struct { | 1067 | struct { |
| 1103 | uint64_t i_c : 8; | 1068 | uint64_t i_c:8; |
| 1104 | uint64_t i_na : 14; | 1069 | uint64_t i_na:14; |
| 1105 | uint64_t i_rsvd_2 : 2; | 1070 | uint64_t i_rsvd_2:2; |
| 1106 | uint64_t i_nb : 14; | 1071 | uint64_t i_nb:14; |
| 1107 | uint64_t i_rsvd_1 : 2; | 1072 | uint64_t i_rsvd_1:2; |
| 1108 | uint64_t i_m : 2; | 1073 | uint64_t i_m:2; |
| 1109 | uint64_t i_f : 1; | 1074 | uint64_t i_f:1; |
| 1110 | uint64_t i_of_cnt : 5; | 1075 | uint64_t i_of_cnt:5; |
| 1111 | uint64_t i_error : 1; | 1076 | uint64_t i_error:1; |
| 1112 | uint64_t i_rd_to : 1; | 1077 | uint64_t i_rd_to:1; |
| 1113 | uint64_t i_spur_wr : 1; | 1078 | uint64_t i_spur_wr:1; |
| 1114 | uint64_t i_spur_rd : 1; | 1079 | uint64_t i_spur_rd:1; |
| 1115 | uint64_t i_rsvd : 11; | 1080 | uint64_t i_rsvd:11; |
| 1116 | uint64_t i_mult_err : 1; | 1081 | uint64_t i_mult_err:1; |
| 1117 | } ii_iprbc_fld_s; | 1082 | } ii_iprbc_fld_s; |
| 1118 | } ii_iprbc_u_t; | 1083 | } ii_iprbc_u_t; |
| 1119 | 1084 | ||
| 1120 | |||
| 1121 | /************************************************************************ | 1085 | /************************************************************************ |
| 1122 | * * | 1086 | * * |
| 1123 | * Description: There are 9 instances of this register, one per * | 1087 | * Description: There are 9 instances of this register, one per * |
| 1124 | * actual widget in this implementation of SHub and Crossbow. * | 1088 | * actual widget in this implementation of SHub and Crossbow. * |
| 1125 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * | 1089 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * |
| @@ -1138,33 +1102,32 @@ typedef union ii_iprbc_u { | |||
| 1138 | * register; the write will correct the C field and capture its new * | 1102 | * register; the write will correct the C field and capture its new * |
| 1139 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * | 1103 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * |
| 1140 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * | 1104 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * |
| 1141 | * . * | 1105 | * . * |
| 1142 | * * | 1106 | * * |
| 1143 | ************************************************************************/ | 1107 | ************************************************************************/ |
| 1144 | 1108 | ||
| 1145 | typedef union ii_iprbd_u { | 1109 | typedef union ii_iprbd_u { |
| 1146 | uint64_t ii_iprbd_regval; | 1110 | uint64_t ii_iprbd_regval; |
| 1147 | struct { | 1111 | struct { |
| 1148 | uint64_t i_c : 8; | 1112 | uint64_t i_c:8; |
| 1149 | uint64_t i_na : 14; | 1113 | uint64_t i_na:14; |
| 1150 | uint64_t i_rsvd_2 : 2; | 1114 | uint64_t i_rsvd_2:2; |
| 1151 | uint64_t i_nb : 14; | 1115 | uint64_t i_nb:14; |
| 1152 | uint64_t i_rsvd_1 : 2; | 1116 | uint64_t i_rsvd_1:2; |
| 1153 | uint64_t i_m : 2; | 1117 | uint64_t i_m:2; |
| 1154 | uint64_t i_f : 1; | 1118 | uint64_t i_f:1; |
| 1155 | uint64_t i_of_cnt : 5; | 1119 | uint64_t i_of_cnt:5; |
| 1156 | uint64_t i_error : 1; | 1120 | uint64_t i_error:1; |
| 1157 | uint64_t i_rd_to : 1; | 1121 | uint64_t i_rd_to:1; |
| 1158 | uint64_t i_spur_wr : 1; | 1122 | uint64_t i_spur_wr:1; |
| 1159 | uint64_t i_spur_rd : 1; | 1123 | uint64_t i_spur_rd:1; |
| 1160 | uint64_t i_rsvd : 11; | 1124 | uint64_t i_rsvd:11; |
| 1161 | uint64_t i_mult_err : 1; | 1125 | uint64_t i_mult_err:1; |
| 1162 | } ii_iprbd_fld_s; | 1126 | } ii_iprbd_fld_s; |
| 1163 | } ii_iprbd_u_t; | 1127 | } ii_iprbd_u_t; |
| 1164 | 1128 | ||
| 1165 | |||
| 1166 | /************************************************************************ | 1129 | /************************************************************************ |
| 1167 | * * | 1130 | * * |
| 1168 | * Description: There are 9 instances of this register, one per * | 1131 | * Description: There are 9 instances of this register, one per * |
| 1169 | * actual widget in this implementation of SHub and Crossbow. * | 1132 | * actual widget in this implementation of SHub and Crossbow. * |
| 1170 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * | 1133 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * |
| @@ -1183,33 +1146,32 @@ typedef union ii_iprbd_u { | |||
| 1183 | * register; the write will correct the C field and capture its new * | 1146 | * register; the write will correct the C field and capture its new * |
| 1184 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * | 1147 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * |
| 1185 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * | 1148 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * |
| 1186 | * . * | 1149 | * . * |
| 1187 | * * | 1150 | * * |
| 1188 | ************************************************************************/ | 1151 | ************************************************************************/ |
| 1189 | 1152 | ||
| 1190 | typedef union ii_iprbe_u { | 1153 | typedef union ii_iprbe_u { |
| 1191 | uint64_t ii_iprbe_regval; | 1154 | uint64_t ii_iprbe_regval; |
| 1192 | struct { | 1155 | struct { |
| 1193 | uint64_t i_c : 8; | 1156 | uint64_t i_c:8; |
| 1194 | uint64_t i_na : 14; | 1157 | uint64_t i_na:14; |
| 1195 | uint64_t i_rsvd_2 : 2; | 1158 | uint64_t i_rsvd_2:2; |
| 1196 | uint64_t i_nb : 14; | 1159 | uint64_t i_nb:14; |
| 1197 | uint64_t i_rsvd_1 : 2; | 1160 | uint64_t i_rsvd_1:2; |
| 1198 | uint64_t i_m : 2; | 1161 | uint64_t i_m:2; |
| 1199 | uint64_t i_f : 1; | 1162 | uint64_t i_f:1; |
| 1200 | uint64_t i_of_cnt : 5; | 1163 | uint64_t i_of_cnt:5; |
| 1201 | uint64_t i_error : 1; | 1164 | uint64_t i_error:1; |
| 1202 | uint64_t i_rd_to : 1; | 1165 | uint64_t i_rd_to:1; |
| 1203 | uint64_t i_spur_wr : 1; | 1166 | uint64_t i_spur_wr:1; |
| 1204 | uint64_t i_spur_rd : 1; | 1167 | uint64_t i_spur_rd:1; |
| 1205 | uint64_t i_rsvd : 11; | 1168 | uint64_t i_rsvd:11; |
| 1206 | uint64_t i_mult_err : 1; | 1169 | uint64_t i_mult_err:1; |
| 1207 | } ii_iprbe_fld_s; | 1170 | } ii_iprbe_fld_s; |
| 1208 | } ii_iprbe_u_t; | 1171 | } ii_iprbe_u_t; |
| 1209 | 1172 | ||
| 1210 | |||
| 1211 | /************************************************************************ | 1173 | /************************************************************************ |
| 1212 | * * | 1174 | * * |
| 1213 | * Description: There are 9 instances of this register, one per * | 1175 | * Description: There are 9 instances of this register, one per * |
| 1214 | * actual widget in this implementation of Shub and Crossbow. * | 1176 | * actual widget in this implementation of Shub and Crossbow. * |
| 1215 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * | 1177 | * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * |
| @@ -1228,33 +1190,32 @@ typedef union ii_iprbe_u { | |||
| 1228 | * register; the write will correct the C field and capture its new * | 1190 | * register; the write will correct the C field and capture its new * |
| 1229 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * | 1191 | * value in the internal register. Even if IECLR[E_PRB_x] is set, the * |
| 1230 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * | 1192 | * SPUR_WR bit will persist if IPRBx hasn't yet been written. * |
| 1231 | * . * | 1193 | * . * |
| 1232 | * * | 1194 | * * |
| 1233 | ************************************************************************/ | 1195 | ************************************************************************/ |
| 1234 | 1196 | ||
| 1235 | typedef union ii_iprbf_u { | 1197 | typedef union ii_iprbf_u { |
| 1236 | uint64_t ii_iprbf_regval; | 1198 | uint64_t ii_iprbf_regval; |
| 1237 | struct { | 1199 | struct { |
| 1238 | uint64_t i_c : 8; | 1200 | uint64_t i_c:8; |
| 1239 | uint64_t i_na : 14; | 1201 | uint64_t i_na:14; |
| 1240 | uint64_t i_rsvd_2 : 2; | 1202 | uint64_t i_rsvd_2:2; |
| 1241 | uint64_t i_nb : 14; | 1203 | uint64_t i_nb:14; |
| 1242 | uint64_t i_rsvd_1 : 2; | 1204 | uint64_t i_rsvd_1:2; |
| 1243 | uint64_t i_m : 2; | 1205 | uint64_t i_m:2; |
| 1244 | uint64_t i_f : 1; | 1206 | uint64_t i_f:1; |
| 1245 | uint64_t i_of_cnt : 5; | 1207 | uint64_t i_of_cnt:5; |
| 1246 | uint64_t i_error : 1; | 1208 | uint64_t i_error:1; |
| 1247 | uint64_t i_rd_to : 1; | 1209 | uint64_t i_rd_to:1; |
| 1248 | uint64_t i_spur_wr : 1; | 1210 | uint64_t i_spur_wr:1; |
| 1249 | uint64_t i_spur_rd : 1; | 1211 | uint64_t i_spur_rd:1; |
| 1250 | uint64_t i_rsvd : 11; | 1212 | uint64_t i_rsvd:11; |
| 1251 | uint64_t i_mult_err : 1; | 1213 | uint64_t i_mult_err:1; |
| 1252 | } ii_iprbe_fld_s; | 1214 | } ii_iprbe_fld_s; |
| 1253 | } ii_iprbf_u_t; | 1215 | } ii_iprbf_u_t; |
| 1254 | 1216 | ||
| 1255 | |||
| 1256 | /************************************************************************ | 1217 | /************************************************************************ |
| 1257 | * * | 1218 | * * |
| 1258 | * This register specifies the timeout value to use for monitoring * | 1219 | * This register specifies the timeout value to use for monitoring * |
| 1259 | * Crosstalk credits which are used outbound to Crosstalk. An * | 1220 | * Crosstalk credits which are used outbound to Crosstalk. An * |
| 1260 | * internal counter called the Crosstalk Credit Timeout Counter * | 1221 | * internal counter called the Crosstalk Credit Timeout Counter * |
| @@ -1267,20 +1228,19 @@ typedef union ii_iprbf_u { | |||
| 1267 | * Crosstalk Credit Timeout has occurred. The internal counter is not * | 1228 | * Crosstalk Credit Timeout has occurred. The internal counter is not * |
| 1268 | * readable from software, and stops counting at its maximum value, * | 1229 | * readable from software, and stops counting at its maximum value, * |
| 1269 | * so it cannot cause more than one interrupt. * | 1230 | * so it cannot cause more than one interrupt. * |
| 1270 | * * | 1231 | * * |
| 1271 | ************************************************************************/ | 1232 | ************************************************************************/ |
| 1272 | 1233 | ||
| 1273 | typedef union ii_ixcc_u { | 1234 | typedef union ii_ixcc_u { |
| 1274 | uint64_t ii_ixcc_regval; | 1235 | uint64_t ii_ixcc_regval; |
| 1275 | struct { | 1236 | struct { |
| 1276 | uint64_t i_time_out : 26; | 1237 | uint64_t i_time_out:26; |
| 1277 | uint64_t i_rsvd : 38; | 1238 | uint64_t i_rsvd:38; |
| 1278 | } ii_ixcc_fld_s; | 1239 | } ii_ixcc_fld_s; |
| 1279 | } ii_ixcc_u_t; | 1240 | } ii_ixcc_u_t; |
| 1280 | 1241 | ||
| 1281 | |||
| 1282 | /************************************************************************ | 1242 | /************************************************************************ |
| 1283 | * * | 1243 | * * |
| 1284 | * Description: This register qualifies all the PIO and DMA * | 1244 | * Description: This register qualifies all the PIO and DMA * |
| 1285 | * operations launched from widget 0 towards the SHub. In * | 1245 | * operations launched from widget 0 towards the SHub. In * |
| 1286 | * addition, it also qualifies accesses by the BTE streams. * | 1246 | * addition, it also qualifies accesses by the BTE streams. * |
| @@ -1292,27 +1252,25 @@ typedef union ii_ixcc_u { | |||
| 1292 | * the Wx_IAC field. The bits in this field are set by writing a 1 to * | 1252 | * the Wx_IAC field. The bits in this field are set by writing a 1 to * |
| 1293 | * them. Incoming replies from Crosstalk are not subject to this * | 1253 | * them. Incoming replies from Crosstalk are not subject to this * |
| 1294 | * access control mechanism. * | 1254 | * access control mechanism. * |
| 1295 | * * | 1255 | * * |
| 1296 | ************************************************************************/ | 1256 | ************************************************************************/ |
| 1297 | 1257 | ||
| 1298 | typedef union ii_imem_u { | 1258 | typedef union ii_imem_u { |
| 1299 | uint64_t ii_imem_regval; | 1259 | uint64_t ii_imem_regval; |
| 1300 | struct { | 1260 | struct { |
| 1301 | uint64_t i_w0_esd : 1; | 1261 | uint64_t i_w0_esd:1; |
| 1302 | uint64_t i_rsvd_3 : 3; | 1262 | uint64_t i_rsvd_3:3; |
| 1303 | uint64_t i_b0_esd : 1; | 1263 | uint64_t i_b0_esd:1; |
| 1304 | uint64_t i_rsvd_2 : 3; | 1264 | uint64_t i_rsvd_2:3; |
| 1305 | uint64_t i_b1_esd : 1; | 1265 | uint64_t i_b1_esd:1; |
| 1306 | uint64_t i_rsvd_1 : 3; | 1266 | uint64_t i_rsvd_1:3; |
| 1307 | uint64_t i_clr_precise : 1; | 1267 | uint64_t i_clr_precise:1; |
| 1308 | uint64_t i_rsvd : 51; | 1268 | uint64_t i_rsvd:51; |
| 1309 | } ii_imem_fld_s; | 1269 | } ii_imem_fld_s; |
| 1310 | } ii_imem_u_t; | 1270 | } ii_imem_u_t; |
| 1311 | 1271 | ||
| 1312 | |||
| 1313 | |||
| 1314 | /************************************************************************ | 1272 | /************************************************************************ |
| 1315 | * * | 1273 | * * |
| 1316 | * Description: This register specifies the timeout value to use for * | 1274 | * Description: This register specifies the timeout value to use for * |
| 1317 | * monitoring Crosstalk tail flits coming into the Shub in the * | 1275 | * monitoring Crosstalk tail flits coming into the Shub in the * |
| 1318 | * TAIL_TO field. An internal counter associated with this register * | 1276 | * TAIL_TO field. An internal counter associated with this register * |
| @@ -1332,90 +1290,87 @@ typedef union ii_imem_u { | |||
| 1332 | * the value in the RRSP_TO field, a Read Response Timeout has * | 1290 | * the value in the RRSP_TO field, a Read Response Timeout has * |
| 1333 | * occurred, and error handling occurs as described in the Error * | 1291 | * occurred, and error handling occurs as described in the Error * |
| 1334 | * Handling section of this document. * | 1292 | * Handling section of this document. * |
| 1335 | * * | 1293 | * * |
| 1336 | ************************************************************************/ | 1294 | ************************************************************************/ |
| 1337 | 1295 | ||
| 1338 | typedef union ii_ixtt_u { | 1296 | typedef union ii_ixtt_u { |
| 1339 | uint64_t ii_ixtt_regval; | 1297 | uint64_t ii_ixtt_regval; |
| 1340 | struct { | 1298 | struct { |
| 1341 | uint64_t i_tail_to : 26; | 1299 | uint64_t i_tail_to:26; |
| 1342 | uint64_t i_rsvd_1 : 6; | 1300 | uint64_t i_rsvd_1:6; |
| 1343 | uint64_t i_rrsp_ps : 23; | 1301 | uint64_t i_rrsp_ps:23; |
| 1344 | uint64_t i_rrsp_to : 5; | 1302 | uint64_t i_rrsp_to:5; |
| 1345 | uint64_t i_rsvd : 4; | 1303 | uint64_t i_rsvd:4; |
| 1346 | } ii_ixtt_fld_s; | 1304 | } ii_ixtt_fld_s; |
| 1347 | } ii_ixtt_u_t; | 1305 | } ii_ixtt_u_t; |
| 1348 | 1306 | ||
| 1349 | |||
| 1350 | /************************************************************************ | 1307 | /************************************************************************ |
| 1351 | * * | 1308 | * * |
| 1352 | * Writing a 1 to the fields of this register clears the appropriate * | 1309 | * Writing a 1 to the fields of this register clears the appropriate * |
| 1353 | * error bits in other areas of SHub. Note that when the * | 1310 | * error bits in other areas of SHub. Note that when the * |
| 1354 | * E_PRB_x bits are used to clear error bits in PRB registers, * | 1311 | * E_PRB_x bits are used to clear error bits in PRB registers, * |
| 1355 | * SPUR_RD and SPUR_WR may persist, because they require additional * | 1312 | * SPUR_RD and SPUR_WR may persist, because they require additional * |
| 1356 | * action to clear them. See the IPRBx and IXSS Register * | 1313 | * action to clear them. See the IPRBx and IXSS Register * |
| 1357 | * specifications. * | 1314 | * specifications. * |
| 1358 | * * | 1315 | * * |
| 1359 | ************************************************************************/ | 1316 | ************************************************************************/ |
| 1360 | 1317 | ||
| 1361 | typedef union ii_ieclr_u { | 1318 | typedef union ii_ieclr_u { |
| 1362 | uint64_t ii_ieclr_regval; | 1319 | uint64_t ii_ieclr_regval; |
| 1363 | struct { | 1320 | struct { |
| 1364 | uint64_t i_e_prb_0 : 1; | 1321 | uint64_t i_e_prb_0:1; |
| 1365 | uint64_t i_rsvd : 7; | 1322 | uint64_t i_rsvd:7; |
| 1366 | uint64_t i_e_prb_8 : 1; | 1323 | uint64_t i_e_prb_8:1; |
| 1367 | uint64_t i_e_prb_9 : 1; | 1324 | uint64_t i_e_prb_9:1; |
| 1368 | uint64_t i_e_prb_a : 1; | 1325 | uint64_t i_e_prb_a:1; |
| 1369 | uint64_t i_e_prb_b : 1; | 1326 | uint64_t i_e_prb_b:1; |
| 1370 | uint64_t i_e_prb_c : 1; | 1327 | uint64_t i_e_prb_c:1; |
| 1371 | uint64_t i_e_prb_d : 1; | 1328 | uint64_t i_e_prb_d:1; |
| 1372 | uint64_t i_e_prb_e : 1; | 1329 | uint64_t i_e_prb_e:1; |
| 1373 | uint64_t i_e_prb_f : 1; | 1330 | uint64_t i_e_prb_f:1; |
| 1374 | uint64_t i_e_crazy : 1; | 1331 | uint64_t i_e_crazy:1; |
| 1375 | uint64_t i_e_bte_0 : 1; | 1332 | uint64_t i_e_bte_0:1; |
| 1376 | uint64_t i_e_bte_1 : 1; | 1333 | uint64_t i_e_bte_1:1; |
| 1377 | uint64_t i_reserved_1 : 10; | 1334 | uint64_t i_reserved_1:10; |
| 1378 | uint64_t i_spur_rd_hdr : 1; | 1335 | uint64_t i_spur_rd_hdr:1; |
| 1379 | uint64_t i_cam_intr_to : 1; | 1336 | uint64_t i_cam_intr_to:1; |
| 1380 | uint64_t i_cam_overflow : 1; | 1337 | uint64_t i_cam_overflow:1; |
| 1381 | uint64_t i_cam_read_miss : 1; | 1338 | uint64_t i_cam_read_miss:1; |
| 1382 | uint64_t i_ioq_rep_underflow : 1; | 1339 | uint64_t i_ioq_rep_underflow:1; |
| 1383 | uint64_t i_ioq_req_underflow : 1; | 1340 | uint64_t i_ioq_req_underflow:1; |
| 1384 | uint64_t i_ioq_rep_overflow : 1; | 1341 | uint64_t i_ioq_rep_overflow:1; |
| 1385 | uint64_t i_ioq_req_overflow : 1; | 1342 | uint64_t i_ioq_req_overflow:1; |
| 1386 | uint64_t i_iiq_rep_overflow : 1; | 1343 | uint64_t i_iiq_rep_overflow:1; |
| 1387 | uint64_t i_iiq_req_overflow : 1; | 1344 | uint64_t i_iiq_req_overflow:1; |
| 1388 | uint64_t i_ii_xn_rep_cred_overflow : 1; | 1345 | uint64_t i_ii_xn_rep_cred_overflow:1; |
| 1389 | uint64_t i_ii_xn_req_cred_overflow : 1; | 1346 | uint64_t i_ii_xn_req_cred_overflow:1; |
| 1390 | uint64_t i_ii_xn_invalid_cmd : 1; | 1347 | uint64_t i_ii_xn_invalid_cmd:1; |
| 1391 | uint64_t i_xn_ii_invalid_cmd : 1; | 1348 | uint64_t i_xn_ii_invalid_cmd:1; |
| 1392 | uint64_t i_reserved_2 : 21; | 1349 | uint64_t i_reserved_2:21; |
| 1393 | } ii_ieclr_fld_s; | 1350 | } ii_ieclr_fld_s; |
| 1394 | } ii_ieclr_u_t; | 1351 | } ii_ieclr_u_t; |
| 1395 | 1352 | ||
| 1396 | |||
| 1397 | /************************************************************************ | 1353 | /************************************************************************ |
| 1398 | * * | 1354 | * * |
| 1399 | * This register controls both BTEs. SOFT_RESET is intended for * | 1355 | * This register controls both BTEs. SOFT_RESET is intended for * |
| 1400 | * recovery after an error. COUNT controls the total number of CRBs * | 1356 | * recovery after an error. COUNT controls the total number of CRBs * |
| 1401 | * that both BTEs (combined) can use, which affects total BTE * | 1357 | * that both BTEs (combined) can use, which affects total BTE * |
| 1402 | * bandwidth. * | 1358 | * bandwidth. * |
| 1403 | * * | 1359 | * * |
| 1404 | ************************************************************************/ | 1360 | ************************************************************************/ |
| 1405 | 1361 | ||
| 1406 | typedef union ii_ibcr_u { | 1362 | typedef union ii_ibcr_u { |
| 1407 | uint64_t ii_ibcr_regval; | 1363 | uint64_t ii_ibcr_regval; |
| 1408 | struct { | 1364 | struct { |
| 1409 | uint64_t i_count : 4; | 1365 | uint64_t i_count:4; |
| 1410 | uint64_t i_rsvd_1 : 4; | 1366 | uint64_t i_rsvd_1:4; |
| 1411 | uint64_t i_soft_reset : 1; | 1367 | uint64_t i_soft_reset:1; |
| 1412 | uint64_t i_rsvd : 55; | 1368 | uint64_t i_rsvd:55; |
| 1413 | } ii_ibcr_fld_s; | 1369 | } ii_ibcr_fld_s; |
| 1414 | } ii_ibcr_u_t; | 1370 | } ii_ibcr_u_t; |
| 1415 | 1371 | ||
| 1416 | |||
| 1417 | /************************************************************************ | 1372 | /************************************************************************ |
| 1418 | * * | 1373 | * * |
| 1419 | * This register contains the header of a spurious read response * | 1374 | * This register contains the header of a spurious read response * |
| 1420 | * received from Crosstalk. A spurious read response is defined as a * | 1375 | * received from Crosstalk. A spurious read response is defined as a * |
| 1421 | * read response received by II from a widget for which (1) the SIDN * | 1376 | * read response received by II from a widget for which (1) the SIDN * |
| @@ -1440,49 +1395,47 @@ typedef union ii_ibcr_u { | |||
| 1440 | * will be set. Any SPUR_RD bits in any other PRB registers indicate * | 1395 | * will be set. Any SPUR_RD bits in any other PRB registers indicate * |
| 1441 | * spurious messages from other widets which were detected after the * | 1396 | * spurious messages from other widets which were detected after the * |
| 1442 | * header was captured.. * | 1397 | * header was captured.. * |
| 1443 | * * | 1398 | * * |
| 1444 | ************************************************************************/ | 1399 | ************************************************************************/ |
| 1445 | 1400 | ||
| 1446 | typedef union ii_ixsm_u { | 1401 | typedef union ii_ixsm_u { |
| 1447 | uint64_t ii_ixsm_regval; | 1402 | uint64_t ii_ixsm_regval; |
| 1448 | struct { | 1403 | struct { |
| 1449 | uint64_t i_byte_en : 32; | 1404 | uint64_t i_byte_en:32; |
| 1450 | uint64_t i_reserved : 1; | 1405 | uint64_t i_reserved:1; |
| 1451 | uint64_t i_tag : 3; | 1406 | uint64_t i_tag:3; |
| 1452 | uint64_t i_alt_pactyp : 4; | 1407 | uint64_t i_alt_pactyp:4; |
| 1453 | uint64_t i_bo : 1; | 1408 | uint64_t i_bo:1; |
| 1454 | uint64_t i_error : 1; | 1409 | uint64_t i_error:1; |
| 1455 | uint64_t i_vbpm : 1; | 1410 | uint64_t i_vbpm:1; |
| 1456 | uint64_t i_gbr : 1; | 1411 | uint64_t i_gbr:1; |
| 1457 | uint64_t i_ds : 2; | 1412 | uint64_t i_ds:2; |
| 1458 | uint64_t i_ct : 1; | 1413 | uint64_t i_ct:1; |
| 1459 | uint64_t i_tnum : 5; | 1414 | uint64_t i_tnum:5; |
| 1460 | uint64_t i_pactyp : 4; | 1415 | uint64_t i_pactyp:4; |
| 1461 | uint64_t i_sidn : 4; | 1416 | uint64_t i_sidn:4; |
| 1462 | uint64_t i_didn : 4; | 1417 | uint64_t i_didn:4; |
| 1463 | } ii_ixsm_fld_s; | 1418 | } ii_ixsm_fld_s; |
| 1464 | } ii_ixsm_u_t; | 1419 | } ii_ixsm_u_t; |
| 1465 | 1420 | ||
| 1466 | |||
| 1467 | /************************************************************************ | 1421 | /************************************************************************ |
| 1468 | * * | 1422 | * * |
| 1469 | * This register contains the sideband bits of a spurious read * | 1423 | * This register contains the sideband bits of a spurious read * |
| 1470 | * response received from Crosstalk. * | 1424 | * response received from Crosstalk. * |
| 1471 | * * | 1425 | * * |
| 1472 | ************************************************************************/ | 1426 | ************************************************************************/ |
| 1473 | 1427 | ||
| 1474 | typedef union ii_ixss_u { | 1428 | typedef union ii_ixss_u { |
| 1475 | uint64_t ii_ixss_regval; | 1429 | uint64_t ii_ixss_regval; |
| 1476 | struct { | 1430 | struct { |
| 1477 | uint64_t i_sideband : 8; | 1431 | uint64_t i_sideband:8; |
| 1478 | uint64_t i_rsvd : 55; | 1432 | uint64_t i_rsvd:55; |
| 1479 | uint64_t i_valid : 1; | 1433 | uint64_t i_valid:1; |
| 1480 | } ii_ixss_fld_s; | 1434 | } ii_ixss_fld_s; |
| 1481 | } ii_ixss_u_t; | 1435 | } ii_ixss_u_t; |
| 1482 | 1436 | ||
| 1483 | |||
| 1484 | /************************************************************************ | 1437 | /************************************************************************ |
| 1485 | * * | 1438 | * * |
| 1486 | * This register enables software to access the II LLP's test port. * | 1439 | * This register enables software to access the II LLP's test port. * |
| 1487 | * Refer to the LLP 2.5 documentation for an explanation of the test * | 1440 | * Refer to the LLP 2.5 documentation for an explanation of the test * |
| 1488 | * port. Software can write to this register to program the values * | 1441 | * port. Software can write to this register to program the values * |
| @@ -1490,27 +1443,26 @@ typedef union ii_ixss_u { | |||
| 1490 | * TestMask and TestSeed). Similarly, software can read from this * | 1443 | * TestMask and TestSeed). Similarly, software can read from this * |
| 1491 | * register to obtain the values of the test port's status outputs * | 1444 | * register to obtain the values of the test port's status outputs * |
| 1492 | * (TestCBerr, TestValid and TestData). * | 1445 | * (TestCBerr, TestValid and TestData). * |
| 1493 | * * | 1446 | * * |
| 1494 | ************************************************************************/ | 1447 | ************************************************************************/ |
| 1495 | 1448 | ||
| 1496 | typedef union ii_ilct_u { | 1449 | typedef union ii_ilct_u { |
| 1497 | uint64_t ii_ilct_regval; | 1450 | uint64_t ii_ilct_regval; |
| 1498 | struct { | 1451 | struct { |
| 1499 | uint64_t i_test_seed : 20; | 1452 | uint64_t i_test_seed:20; |
| 1500 | uint64_t i_test_mask : 8; | 1453 | uint64_t i_test_mask:8; |
| 1501 | uint64_t i_test_data : 20; | 1454 | uint64_t i_test_data:20; |
| 1502 | uint64_t i_test_valid : 1; | 1455 | uint64_t i_test_valid:1; |
| 1503 | uint64_t i_test_cberr : 1; | 1456 | uint64_t i_test_cberr:1; |
| 1504 | uint64_t i_test_flit : 3; | 1457 | uint64_t i_test_flit:3; |
| 1505 | uint64_t i_test_clear : 1; | 1458 | uint64_t i_test_clear:1; |
| 1506 | uint64_t i_test_err_capture : 1; | 1459 | uint64_t i_test_err_capture:1; |
| 1507 | uint64_t i_rsvd : 9; | 1460 | uint64_t i_rsvd:9; |
| 1508 | } ii_ilct_fld_s; | 1461 | } ii_ilct_fld_s; |
| 1509 | } ii_ilct_u_t; | 1462 | } ii_ilct_u_t; |
| 1510 | 1463 | ||
| 1511 | |||
| 1512 | /************************************************************************ | 1464 | /************************************************************************ |
| 1513 | * * | 1465 | * * |
| 1514 | * If the II detects an illegal incoming Duplonet packet (request or * | 1466 | * If the II detects an illegal incoming Duplonet packet (request or * |
| 1515 | * reply) when VALID==0 in the IIEPH1 register, then it saves the * | 1467 | * reply) when VALID==0 in the IIEPH1 register, then it saves the * |
| 1516 | * contents of the packet's header flit in the IIEPH1 and IIEPH2 * | 1468 | * contents of the packet's header flit in the IIEPH1 and IIEPH2 * |
| @@ -1526,575 +1478,549 @@ typedef union ii_ilct_u { | |||
| 1526 | * packet when VALID==1 in the IIEPH1 register, then it merely sets * | 1478 | * packet when VALID==1 in the IIEPH1 register, then it merely sets * |
| 1527 | * the OVERRUN bit to indicate that a subsequent error has happened, * | 1479 | * the OVERRUN bit to indicate that a subsequent error has happened, * |
| 1528 | * and does nothing further. * | 1480 | * and does nothing further. * |
| 1529 | * * | 1481 | * * |
| 1530 | ************************************************************************/ | 1482 | ************************************************************************/ |
| 1531 | 1483 | ||
| 1532 | typedef union ii_iieph1_u { | 1484 | typedef union ii_iieph1_u { |
| 1533 | uint64_t ii_iieph1_regval; | 1485 | uint64_t ii_iieph1_regval; |
| 1534 | struct { | 1486 | struct { |
| 1535 | uint64_t i_command : 7; | 1487 | uint64_t i_command:7; |
| 1536 | uint64_t i_rsvd_5 : 1; | 1488 | uint64_t i_rsvd_5:1; |
| 1537 | uint64_t i_suppl : 14; | 1489 | uint64_t i_suppl:14; |
| 1538 | uint64_t i_rsvd_4 : 1; | 1490 | uint64_t i_rsvd_4:1; |
| 1539 | uint64_t i_source : 14; | 1491 | uint64_t i_source:14; |
| 1540 | uint64_t i_rsvd_3 : 1; | 1492 | uint64_t i_rsvd_3:1; |
| 1541 | uint64_t i_err_type : 4; | 1493 | uint64_t i_err_type:4; |
| 1542 | uint64_t i_rsvd_2 : 4; | 1494 | uint64_t i_rsvd_2:4; |
| 1543 | uint64_t i_overrun : 1; | 1495 | uint64_t i_overrun:1; |
| 1544 | uint64_t i_rsvd_1 : 3; | 1496 | uint64_t i_rsvd_1:3; |
| 1545 | uint64_t i_valid : 1; | 1497 | uint64_t i_valid:1; |
| 1546 | uint64_t i_rsvd : 13; | 1498 | uint64_t i_rsvd:13; |
| 1547 | } ii_iieph1_fld_s; | 1499 | } ii_iieph1_fld_s; |
| 1548 | } ii_iieph1_u_t; | 1500 | } ii_iieph1_u_t; |
| 1549 | 1501 | ||
| 1550 | |||
| 1551 | /************************************************************************ | 1502 | /************************************************************************ |
| 1552 | * * | 1503 | * * |
| 1553 | * This register holds the Address field from the header flit of an * | 1504 | * This register holds the Address field from the header flit of an * |
| 1554 | * incoming erroneous Duplonet packet, along with the tail bit which * | 1505 | * incoming erroneous Duplonet packet, along with the tail bit which * |
| 1555 | * accompanied this header flit. This register is essentially an * | 1506 | * accompanied this header flit. This register is essentially an * |
| 1556 | * extension of IIEPH1. Two registers were necessary because the 64 * | 1507 | * extension of IIEPH1. Two registers were necessary because the 64 * |
| 1557 | * bits available in only a single register were insufficient to * | 1508 | * bits available in only a single register were insufficient to * |
| 1558 | * capture the entire header flit of an erroneous packet. * | 1509 | * capture the entire header flit of an erroneous packet. * |
| 1559 | * * | 1510 | * * |
| 1560 | ************************************************************************/ | 1511 | ************************************************************************/ |
| 1561 | 1512 | ||
| 1562 | typedef union ii_iieph2_u { | 1513 | typedef union ii_iieph2_u { |
| 1563 | uint64_t ii_iieph2_regval; | 1514 | uint64_t ii_iieph2_regval; |
| 1564 | struct { | 1515 | struct { |
| 1565 | uint64_t i_rsvd_0 : 3; | 1516 | uint64_t i_rsvd_0:3; |
| 1566 | uint64_t i_address : 47; | 1517 | uint64_t i_address:47; |
| 1567 | uint64_t i_rsvd_1 : 10; | 1518 | uint64_t i_rsvd_1:10; |
| 1568 | uint64_t i_tail : 1; | 1519 | uint64_t i_tail:1; |
| 1569 | uint64_t i_rsvd : 3; | 1520 | uint64_t i_rsvd:3; |
| 1570 | } ii_iieph2_fld_s; | 1521 | } ii_iieph2_fld_s; |
| 1571 | } ii_iieph2_u_t; | 1522 | } ii_iieph2_u_t; |
| 1572 | 1523 | ||
| 1573 | |||
| 1574 | /******************************/ | 1524 | /******************************/ |
| 1575 | 1525 | ||
| 1576 | |||
| 1577 | |||
| 1578 | /************************************************************************ | 1526 | /************************************************************************ |
| 1579 | * * | 1527 | * * |
| 1580 | * This register's value is a bit vector that guards access from SXBs * | 1528 | * This register's value is a bit vector that guards access from SXBs * |
| 1581 | * to local registers within the II as well as to external Crosstalk * | 1529 | * to local registers within the II as well as to external Crosstalk * |
| 1582 | * widgets * | 1530 | * widgets * |
| 1583 | * * | 1531 | * * |
| 1584 | ************************************************************************/ | 1532 | ************************************************************************/ |
| 1585 | 1533 | ||
| 1586 | typedef union ii_islapr_u { | 1534 | typedef union ii_islapr_u { |
| 1587 | uint64_t ii_islapr_regval; | 1535 | uint64_t ii_islapr_regval; |
| 1588 | struct { | 1536 | struct { |
| 1589 | uint64_t i_region : 64; | 1537 | uint64_t i_region:64; |
| 1590 | } ii_islapr_fld_s; | 1538 | } ii_islapr_fld_s; |
| 1591 | } ii_islapr_u_t; | 1539 | } ii_islapr_u_t; |
| 1592 | 1540 | ||
| 1593 | |||
| 1594 | /************************************************************************ | 1541 | /************************************************************************ |
| 1595 | * * | 1542 | * * |
| 1596 | * A write to this register of the 56-bit value "Pup+Bun" will cause * | 1543 | * A write to this register of the 56-bit value "Pup+Bun" will cause * |
| 1597 | * the bit in the ISLAPR register corresponding to the region of the * | 1544 | * the bit in the ISLAPR register corresponding to the region of the * |
| 1598 | * requestor to be set (access allowed). ( | 1545 | * requestor to be set (access allowed). ( |
| 1599 | * * | 1546 | * * |
| 1600 | ************************************************************************/ | 1547 | ************************************************************************/ |
| 1601 | 1548 | ||
| 1602 | typedef union ii_islapo_u { | 1549 | typedef union ii_islapo_u { |
| 1603 | uint64_t ii_islapo_regval; | 1550 | uint64_t ii_islapo_regval; |
| 1604 | struct { | 1551 | struct { |
| 1605 | uint64_t i_io_sbx_ovrride : 56; | 1552 | uint64_t i_io_sbx_ovrride:56; |
| 1606 | uint64_t i_rsvd : 8; | 1553 | uint64_t i_rsvd:8; |
| 1607 | } ii_islapo_fld_s; | 1554 | } ii_islapo_fld_s; |
| 1608 | } ii_islapo_u_t; | 1555 | } ii_islapo_u_t; |
| 1609 | 1556 | ||
| 1610 | /************************************************************************ | 1557 | /************************************************************************ |
| 1611 | * * | 1558 | * * |
| 1612 | * Determines how long the wrapper will wait aftr an interrupt is * | 1559 | * Determines how long the wrapper will wait aftr an interrupt is * |
| 1613 | * initially issued from the II before it times out the outstanding * | 1560 | * initially issued from the II before it times out the outstanding * |
| 1614 | * interrupt and drops it from the interrupt queue. * | 1561 | * interrupt and drops it from the interrupt queue. * |
| 1615 | * * | 1562 | * * |
| 1616 | ************************************************************************/ | 1563 | ************************************************************************/ |
| 1617 | 1564 | ||
| 1618 | typedef union ii_iwi_u { | 1565 | typedef union ii_iwi_u { |
| 1619 | uint64_t ii_iwi_regval; | 1566 | uint64_t ii_iwi_regval; |
| 1620 | struct { | 1567 | struct { |
| 1621 | uint64_t i_prescale : 24; | 1568 | uint64_t i_prescale:24; |
| 1622 | uint64_t i_rsvd : 8; | 1569 | uint64_t i_rsvd:8; |
| 1623 | uint64_t i_timeout : 8; | 1570 | uint64_t i_timeout:8; |
| 1624 | uint64_t i_rsvd1 : 8; | 1571 | uint64_t i_rsvd1:8; |
| 1625 | uint64_t i_intrpt_retry_period : 8; | 1572 | uint64_t i_intrpt_retry_period:8; |
| 1626 | uint64_t i_rsvd2 : 8; | 1573 | uint64_t i_rsvd2:8; |
| 1627 | } ii_iwi_fld_s; | 1574 | } ii_iwi_fld_s; |
| 1628 | } ii_iwi_u_t; | 1575 | } ii_iwi_u_t; |
| 1629 | 1576 | ||
| 1630 | /************************************************************************ | 1577 | /************************************************************************ |
| 1631 | * * | 1578 | * * |
| 1632 | * Log errors which have occurred in the II wrapper. The errors are * | 1579 | * Log errors which have occurred in the II wrapper. The errors are * |
| 1633 | * cleared by writing to the IECLR register. * | 1580 | * cleared by writing to the IECLR register. * |
| 1634 | * * | 1581 | * * |
| 1635 | ************************************************************************/ | 1582 | ************************************************************************/ |
| 1636 | 1583 | ||
| 1637 | typedef union ii_iwel_u { | 1584 | typedef union ii_iwel_u { |
| 1638 | uint64_t ii_iwel_regval; | 1585 | uint64_t ii_iwel_regval; |
| 1639 | struct { | 1586 | struct { |
| 1640 | uint64_t i_intr_timed_out : 1; | 1587 | uint64_t i_intr_timed_out:1; |
| 1641 | uint64_t i_rsvd : 7; | 1588 | uint64_t i_rsvd:7; |
| 1642 | uint64_t i_cam_overflow : 1; | 1589 | uint64_t i_cam_overflow:1; |
| 1643 | uint64_t i_cam_read_miss : 1; | 1590 | uint64_t i_cam_read_miss:1; |
| 1644 | uint64_t i_rsvd1 : 2; | 1591 | uint64_t i_rsvd1:2; |
| 1645 | uint64_t i_ioq_rep_underflow : 1; | 1592 | uint64_t i_ioq_rep_underflow:1; |
| 1646 | uint64_t i_ioq_req_underflow : 1; | 1593 | uint64_t i_ioq_req_underflow:1; |
| 1647 | uint64_t i_ioq_rep_overflow : 1; | 1594 | uint64_t i_ioq_rep_overflow:1; |
| 1648 | uint64_t i_ioq_req_overflow : 1; | 1595 | uint64_t i_ioq_req_overflow:1; |
| 1649 | uint64_t i_iiq_rep_overflow : 1; | 1596 | uint64_t i_iiq_rep_overflow:1; |
| 1650 | uint64_t i_iiq_req_overflow : 1; | 1597 | uint64_t i_iiq_req_overflow:1; |
| 1651 | uint64_t i_rsvd2 : 6; | 1598 | uint64_t i_rsvd2:6; |
| 1652 | uint64_t i_ii_xn_rep_cred_over_under: 1; | 1599 | uint64_t i_ii_xn_rep_cred_over_under:1; |
| 1653 | uint64_t i_ii_xn_req_cred_over_under: 1; | 1600 | uint64_t i_ii_xn_req_cred_over_under:1; |
| 1654 | uint64_t i_rsvd3 : 6; | 1601 | uint64_t i_rsvd3:6; |
| 1655 | uint64_t i_ii_xn_invalid_cmd : 1; | 1602 | uint64_t i_ii_xn_invalid_cmd:1; |
| 1656 | uint64_t i_xn_ii_invalid_cmd : 1; | 1603 | uint64_t i_xn_ii_invalid_cmd:1; |
| 1657 | uint64_t i_rsvd4 : 30; | 1604 | uint64_t i_rsvd4:30; |
| 1658 | } ii_iwel_fld_s; | 1605 | } ii_iwel_fld_s; |
| 1659 | } ii_iwel_u_t; | 1606 | } ii_iwel_u_t; |
| 1660 | 1607 | ||
| 1661 | /************************************************************************ | 1608 | /************************************************************************ |
| 1662 | * * | 1609 | * * |
| 1663 | * Controls the II wrapper. * | 1610 | * Controls the II wrapper. * |
| 1664 | * * | 1611 | * * |
| 1665 | ************************************************************************/ | 1612 | ************************************************************************/ |
| 1666 | 1613 | ||
| 1667 | typedef union ii_iwc_u { | 1614 | typedef union ii_iwc_u { |
| 1668 | uint64_t ii_iwc_regval; | 1615 | uint64_t ii_iwc_regval; |
| 1669 | struct { | 1616 | struct { |
| 1670 | uint64_t i_dma_byte_swap : 1; | 1617 | uint64_t i_dma_byte_swap:1; |
| 1671 | uint64_t i_rsvd : 3; | 1618 | uint64_t i_rsvd:3; |
| 1672 | uint64_t i_cam_read_lines_reset : 1; | 1619 | uint64_t i_cam_read_lines_reset:1; |
| 1673 | uint64_t i_rsvd1 : 3; | 1620 | uint64_t i_rsvd1:3; |
| 1674 | uint64_t i_ii_xn_cred_over_under_log: 1; | 1621 | uint64_t i_ii_xn_cred_over_under_log:1; |
| 1675 | uint64_t i_rsvd2 : 19; | 1622 | uint64_t i_rsvd2:19; |
| 1676 | uint64_t i_xn_rep_iq_depth : 5; | 1623 | uint64_t i_xn_rep_iq_depth:5; |
| 1677 | uint64_t i_rsvd3 : 3; | 1624 | uint64_t i_rsvd3:3; |
| 1678 | uint64_t i_xn_req_iq_depth : 5; | 1625 | uint64_t i_xn_req_iq_depth:5; |
| 1679 | uint64_t i_rsvd4 : 3; | 1626 | uint64_t i_rsvd4:3; |
| 1680 | uint64_t i_iiq_depth : 6; | 1627 | uint64_t i_iiq_depth:6; |
| 1681 | uint64_t i_rsvd5 : 12; | 1628 | uint64_t i_rsvd5:12; |
| 1682 | uint64_t i_force_rep_cred : 1; | 1629 | uint64_t i_force_rep_cred:1; |
| 1683 | uint64_t i_force_req_cred : 1; | 1630 | uint64_t i_force_req_cred:1; |
| 1684 | } ii_iwc_fld_s; | 1631 | } ii_iwc_fld_s; |
| 1685 | } ii_iwc_u_t; | 1632 | } ii_iwc_u_t; |
| 1686 | 1633 | ||
| 1687 | /************************************************************************ | 1634 | /************************************************************************ |
| 1688 | * * | 1635 | * * |
| 1689 | * Status in the II wrapper. * | 1636 | * Status in the II wrapper. * |
| 1690 | * * | 1637 | * * |
| 1691 | ************************************************************************/ | 1638 | ************************************************************************/ |
| 1692 | 1639 | ||
| 1693 | typedef union ii_iws_u { | 1640 | typedef union ii_iws_u { |
| 1694 | uint64_t ii_iws_regval; | 1641 | uint64_t ii_iws_regval; |
| 1695 | struct { | 1642 | struct { |
| 1696 | uint64_t i_xn_rep_iq_credits : 5; | 1643 | uint64_t i_xn_rep_iq_credits:5; |
| 1697 | uint64_t i_rsvd : 3; | 1644 | uint64_t i_rsvd:3; |
| 1698 | uint64_t i_xn_req_iq_credits : 5; | 1645 | uint64_t i_xn_req_iq_credits:5; |
| 1699 | uint64_t i_rsvd1 : 51; | 1646 | uint64_t i_rsvd1:51; |
| 1700 | } ii_iws_fld_s; | 1647 | } ii_iws_fld_s; |
| 1701 | } ii_iws_u_t; | 1648 | } ii_iws_u_t; |
| 1702 | 1649 | ||
| 1703 | /************************************************************************ | 1650 | /************************************************************************ |
| 1704 | * * | 1651 | * * |
| 1705 | * Masks errors in the IWEL register. * | 1652 | * Masks errors in the IWEL register. * |
| 1706 | * * | 1653 | * * |
| 1707 | ************************************************************************/ | 1654 | ************************************************************************/ |
| 1708 | 1655 | ||
| 1709 | typedef union ii_iweim_u { | 1656 | typedef union ii_iweim_u { |
| 1710 | uint64_t ii_iweim_regval; | 1657 | uint64_t ii_iweim_regval; |
| 1711 | struct { | 1658 | struct { |
| 1712 | uint64_t i_intr_timed_out : 1; | 1659 | uint64_t i_intr_timed_out:1; |
| 1713 | uint64_t i_rsvd : 7; | 1660 | uint64_t i_rsvd:7; |
| 1714 | uint64_t i_cam_overflow : 1; | 1661 | uint64_t i_cam_overflow:1; |
| 1715 | uint64_t i_cam_read_miss : 1; | 1662 | uint64_t i_cam_read_miss:1; |
| 1716 | uint64_t i_rsvd1 : 2; | 1663 | uint64_t i_rsvd1:2; |
| 1717 | uint64_t i_ioq_rep_underflow : 1; | 1664 | uint64_t i_ioq_rep_underflow:1; |
| 1718 | uint64_t i_ioq_req_underflow : 1; | 1665 | uint64_t i_ioq_req_underflow:1; |
| 1719 | uint64_t i_ioq_rep_overflow : 1; | 1666 | uint64_t i_ioq_rep_overflow:1; |
| 1720 | uint64_t i_ioq_req_overflow : 1; | 1667 | uint64_t i_ioq_req_overflow:1; |
| 1721 | uint64_t i_iiq_rep_overflow : 1; | 1668 | uint64_t i_iiq_rep_overflow:1; |
| 1722 | uint64_t i_iiq_req_overflow : 1; | 1669 | uint64_t i_iiq_req_overflow:1; |
| 1723 | uint64_t i_rsvd2 : 6; | 1670 | uint64_t i_rsvd2:6; |
| 1724 | uint64_t i_ii_xn_rep_cred_overflow : 1; | 1671 | uint64_t i_ii_xn_rep_cred_overflow:1; |
| 1725 | uint64_t i_ii_xn_req_cred_overflow : 1; | 1672 | uint64_t i_ii_xn_req_cred_overflow:1; |
| 1726 | uint64_t i_rsvd3 : 6; | 1673 | uint64_t i_rsvd3:6; |
| 1727 | uint64_t i_ii_xn_invalid_cmd : 1; | 1674 | uint64_t i_ii_xn_invalid_cmd:1; |
| 1728 | uint64_t i_xn_ii_invalid_cmd : 1; | 1675 | uint64_t i_xn_ii_invalid_cmd:1; |
| 1729 | uint64_t i_rsvd4 : 30; | 1676 | uint64_t i_rsvd4:30; |
| 1730 | } ii_iweim_fld_s; | 1677 | } ii_iweim_fld_s; |
| 1731 | } ii_iweim_u_t; | 1678 | } ii_iweim_u_t; |
| 1732 | 1679 | ||
| 1733 | |||
| 1734 | /************************************************************************ | 1680 | /************************************************************************ |
| 1735 | * * | 1681 | * * |
| 1736 | * A write to this register causes a particular field in the * | 1682 | * A write to this register causes a particular field in the * |
| 1737 | * corresponding widget's PRB entry to be adjusted up or down by 1. * | 1683 | * corresponding widget's PRB entry to be adjusted up or down by 1. * |
| 1738 | * This counter should be used when recovering from error and reset * | 1684 | * This counter should be used when recovering from error and reset * |
| 1739 | * conditions. Note that software would be capable of causing * | 1685 | * conditions. Note that software would be capable of causing * |
| 1740 | * inadvertent overflow or underflow of these counters. * | 1686 | * inadvertent overflow or underflow of these counters. * |
| 1741 | * * | 1687 | * * |
| 1742 | ************************************************************************/ | 1688 | ************************************************************************/ |
| 1743 | 1689 | ||
| 1744 | typedef union ii_ipca_u { | 1690 | typedef union ii_ipca_u { |
| 1745 | uint64_t ii_ipca_regval; | 1691 | uint64_t ii_ipca_regval; |
| 1746 | struct { | 1692 | struct { |
| 1747 | uint64_t i_wid : 4; | 1693 | uint64_t i_wid:4; |
| 1748 | uint64_t i_adjust : 1; | 1694 | uint64_t i_adjust:1; |
| 1749 | uint64_t i_rsvd_1 : 3; | 1695 | uint64_t i_rsvd_1:3; |
| 1750 | uint64_t i_field : 2; | 1696 | uint64_t i_field:2; |
| 1751 | uint64_t i_rsvd : 54; | 1697 | uint64_t i_rsvd:54; |
| 1752 | } ii_ipca_fld_s; | 1698 | } ii_ipca_fld_s; |
| 1753 | } ii_ipca_u_t; | 1699 | } ii_ipca_u_t; |
| 1754 | 1700 | ||
| 1755 | |||
| 1756 | /************************************************************************ | 1701 | /************************************************************************ |
| 1757 | * * | 1702 | * * |
| 1758 | * There are 8 instances of this register. This register contains * | 1703 | * There are 8 instances of this register. This register contains * |
| 1759 | * the information that the II has to remember once it has launched a * | 1704 | * the information that the II has to remember once it has launched a * |
| 1760 | * PIO Read operation. The contents are used to form the correct * | 1705 | * PIO Read operation. The contents are used to form the correct * |
| 1761 | * Router Network packet and direct the Crosstalk reply to the * | 1706 | * Router Network packet and direct the Crosstalk reply to the * |
| 1762 | * appropriate processor. * | 1707 | * appropriate processor. * |
| 1763 | * * | 1708 | * * |
| 1764 | ************************************************************************/ | 1709 | ************************************************************************/ |
| 1765 | 1710 | ||
| 1766 | |||
| 1767 | typedef union ii_iprte0a_u { | 1711 | typedef union ii_iprte0a_u { |
| 1768 | uint64_t ii_iprte0a_regval; | 1712 | uint64_t ii_iprte0a_regval; |
| 1769 | struct { | 1713 | struct { |
| 1770 | uint64_t i_rsvd_1 : 54; | 1714 | uint64_t i_rsvd_1:54; |
| 1771 | uint64_t i_widget : 4; | 1715 | uint64_t i_widget:4; |
| 1772 | uint64_t i_to_cnt : 5; | 1716 | uint64_t i_to_cnt:5; |
| 1773 | uint64_t i_vld : 1; | 1717 | uint64_t i_vld:1; |
| 1774 | } ii_iprte0a_fld_s; | 1718 | } ii_iprte0a_fld_s; |
| 1775 | } ii_iprte0a_u_t; | 1719 | } ii_iprte0a_u_t; |
| 1776 | 1720 | ||
| 1777 | |||
| 1778 | /************************************************************************ | 1721 | /************************************************************************ |
| 1779 | * * | 1722 | * * |
| 1780 | * There are 8 instances of this register. This register contains * | 1723 | * There are 8 instances of this register. This register contains * |
| 1781 | * the information that the II has to remember once it has launched a * | 1724 | * the information that the II has to remember once it has launched a * |
| 1782 | * PIO Read operation. The contents are used to form the correct * | 1725 | * PIO Read operation. The contents are used to form the correct * |
| 1783 | * Router Network packet and direct the Crosstalk reply to the * | 1726 | * Router Network packet and direct the Crosstalk reply to the * |
| 1784 | * appropriate processor. * | 1727 | * appropriate processor. * |
| 1785 | * * | 1728 | * * |
| 1786 | ************************************************************************/ | 1729 | ************************************************************************/ |
| 1787 | 1730 | ||
| 1788 | typedef union ii_iprte1a_u { | 1731 | typedef union ii_iprte1a_u { |
| 1789 | uint64_t ii_iprte1a_regval; | 1732 | uint64_t ii_iprte1a_regval; |
| 1790 | struct { | 1733 | struct { |
| 1791 | uint64_t i_rsvd_1 : 54; | 1734 | uint64_t i_rsvd_1:54; |
| 1792 | uint64_t i_widget : 4; | 1735 | uint64_t i_widget:4; |
| 1793 | uint64_t i_to_cnt : 5; | 1736 | uint64_t i_to_cnt:5; |
| 1794 | uint64_t i_vld : 1; | 1737 | uint64_t i_vld:1; |
| 1795 | } ii_iprte1a_fld_s; | 1738 | } ii_iprte1a_fld_s; |
| 1796 | } ii_iprte1a_u_t; | 1739 | } ii_iprte1a_u_t; |
| 1797 | 1740 | ||
| 1798 | |||
| 1799 | /************************************************************************ | 1741 | /************************************************************************ |
| 1800 | * * | 1742 | * * |
| 1801 | * There are 8 instances of this register. This register contains * | 1743 | * There are 8 instances of this register. This register contains * |
| 1802 | * the information that the II has to remember once it has launched a * | 1744 | * the information that the II has to remember once it has launched a * |
| 1803 | * PIO Read operation. The contents are used to form the correct * | 1745 | * PIO Read operation. The contents are used to form the correct * |
| 1804 | * Router Network packet and direct the Crosstalk reply to the * | 1746 | * Router Network packet and direct the Crosstalk reply to the * |
| 1805 | * appropriate processor. * | 1747 | * appropriate processor. * |
| 1806 | * * | 1748 | * * |
| 1807 | ************************************************************************/ | 1749 | ************************************************************************/ |
| 1808 | 1750 | ||
| 1809 | typedef union ii_iprte2a_u { | 1751 | typedef union ii_iprte2a_u { |
| 1810 | uint64_t ii_iprte2a_regval; | 1752 | uint64_t ii_iprte2a_regval; |
| 1811 | struct { | 1753 | struct { |
| 1812 | uint64_t i_rsvd_1 : 54; | 1754 | uint64_t i_rsvd_1:54; |
| 1813 | uint64_t i_widget : 4; | 1755 | uint64_t i_widget:4; |
| 1814 | uint64_t i_to_cnt : 5; | 1756 | uint64_t i_to_cnt:5; |
| 1815 | uint64_t i_vld : 1; | 1757 | uint64_t i_vld:1; |
| 1816 | } ii_iprte2a_fld_s; | 1758 | } ii_iprte2a_fld_s; |
| 1817 | } ii_iprte2a_u_t; | 1759 | } ii_iprte2a_u_t; |
| 1818 | 1760 | ||
| 1819 | |||
| 1820 | /************************************************************************ | 1761 | /************************************************************************ |
| 1821 | * * | 1762 | * * |
| 1822 | * There are 8 instances of this register. This register contains * | 1763 | * There are 8 instances of this register. This register contains * |
| 1823 | * the information that the II has to remember once it has launched a * | 1764 | * the information that the II has to remember once it has launched a * |
| 1824 | * PIO Read operation. The contents are used to form the correct * | 1765 | * PIO Read operation. The contents are used to form the correct * |
| 1825 | * Router Network packet and direct the Crosstalk reply to the * | 1766 | * Router Network packet and direct the Crosstalk reply to the * |
| 1826 | * appropriate processor. * | 1767 | * appropriate processor. * |
| 1827 | * * | 1768 | * * |
| 1828 | ************************************************************************/ | 1769 | ************************************************************************/ |
| 1829 | 1770 | ||
| 1830 | typedef union ii_iprte3a_u { | 1771 | typedef union ii_iprte3a_u { |
| 1831 | uint64_t ii_iprte3a_regval; | 1772 | uint64_t ii_iprte3a_regval; |
| 1832 | struct { | 1773 | struct { |
| 1833 | uint64_t i_rsvd_1 : 54; | 1774 | uint64_t i_rsvd_1:54; |
| 1834 | uint64_t i_widget : 4; | 1775 | uint64_t i_widget:4; |
| 1835 | uint64_t i_to_cnt : 5; | 1776 | uint64_t i_to_cnt:5; |
| 1836 | uint64_t i_vld : 1; | 1777 | uint64_t i_vld:1; |
| 1837 | } ii_iprte3a_fld_s; | 1778 | } ii_iprte3a_fld_s; |
| 1838 | } ii_iprte3a_u_t; | 1779 | } ii_iprte3a_u_t; |
| 1839 | 1780 | ||
| 1840 | |||
| 1841 | /************************************************************************ | 1781 | /************************************************************************ |
| 1842 | * * | 1782 | * * |
| 1843 | * There are 8 instances of this register. This register contains * | 1783 | * There are 8 instances of this register. This register contains * |
| 1844 | * the information that the II has to remember once it has launched a * | 1784 | * the information that the II has to remember once it has launched a * |
| 1845 | * PIO Read operation. The contents are used to form the correct * | 1785 | * PIO Read operation. The contents are used to form the correct * |
| 1846 | * Router Network packet and direct the Crosstalk reply to the * | 1786 | * Router Network packet and direct the Crosstalk reply to the * |
| 1847 | * appropriate processor. * | 1787 | * appropriate processor. * |
| 1848 | * * | 1788 | * * |
| 1849 | ************************************************************************/ | 1789 | ************************************************************************/ |
| 1850 | 1790 | ||
| 1851 | typedef union ii_iprte4a_u { | 1791 | typedef union ii_iprte4a_u { |
| 1852 | uint64_t ii_iprte4a_regval; | 1792 | uint64_t ii_iprte4a_regval; |
| 1853 | struct { | 1793 | struct { |
| 1854 | uint64_t i_rsvd_1 : 54; | 1794 | uint64_t i_rsvd_1:54; |
| 1855 | uint64_t i_widget : 4; | 1795 | uint64_t i_widget:4; |
| 1856 | uint64_t i_to_cnt : 5; | 1796 | uint64_t i_to_cnt:5; |
| 1857 | uint64_t i_vld : 1; | 1797 | uint64_t i_vld:1; |
| 1858 | } ii_iprte4a_fld_s; | 1798 | } ii_iprte4a_fld_s; |
| 1859 | } ii_iprte4a_u_t; | 1799 | } ii_iprte4a_u_t; |
| 1860 | 1800 | ||
| 1861 | |||
| 1862 | /************************************************************************ | 1801 | /************************************************************************ |
| 1863 | * * | 1802 | * * |
| 1864 | * There are 8 instances of this register. This register contains * | 1803 | * There are 8 instances of this register. This register contains * |
| 1865 | * the information that the II has to remember once it has launched a * | 1804 | * the information that the II has to remember once it has launched a * |
| 1866 | * PIO Read operation. The contents are used to form the correct * | 1805 | * PIO Read operation. The contents are used to form the correct * |
| 1867 | * Router Network packet and direct the Crosstalk reply to the * | 1806 | * Router Network packet and direct the Crosstalk reply to the * |
| 1868 | * appropriate processor. * | 1807 | * appropriate processor. * |
| 1869 | * * | 1808 | * * |
| 1870 | ************************************************************************/ | 1809 | ************************************************************************/ |
| 1871 | 1810 | ||
| 1872 | typedef union ii_iprte5a_u { | 1811 | typedef union ii_iprte5a_u { |
| 1873 | uint64_t ii_iprte5a_regval; | 1812 | uint64_t ii_iprte5a_regval; |
| 1874 | struct { | 1813 | struct { |
| 1875 | uint64_t i_rsvd_1 : 54; | 1814 | uint64_t i_rsvd_1:54; |
| 1876 | uint64_t i_widget : 4; | 1815 | uint64_t i_widget:4; |
| 1877 | uint64_t i_to_cnt : 5; | 1816 | uint64_t i_to_cnt:5; |
| 1878 | uint64_t i_vld : 1; | 1817 | uint64_t i_vld:1; |
| 1879 | } ii_iprte5a_fld_s; | 1818 | } ii_iprte5a_fld_s; |
| 1880 | } ii_iprte5a_u_t; | 1819 | } ii_iprte5a_u_t; |
| 1881 | 1820 | ||
| 1882 | |||
| 1883 | /************************************************************************ | 1821 | /************************************************************************ |
| 1884 | * * | 1822 | * * |
| 1885 | * There are 8 instances of this register. This register contains * | 1823 | * There are 8 instances of this register. This register contains * |
| 1886 | * the information that the II has to remember once it has launched a * | 1824 | * the information that the II has to remember once it has launched a * |
| 1887 | * PIO Read operation. The contents are used to form the correct * | 1825 | * PIO Read operation. The contents are used to form the correct * |
| 1888 | * Router Network packet and direct the Crosstalk reply to the * | 1826 | * Router Network packet and direct the Crosstalk reply to the * |
| 1889 | * appropriate processor. * | 1827 | * appropriate processor. * |
| 1890 | * * | 1828 | * * |
| 1891 | ************************************************************************/ | 1829 | ************************************************************************/ |
| 1892 | 1830 | ||
| 1893 | typedef union ii_iprte6a_u { | 1831 | typedef union ii_iprte6a_u { |
| 1894 | uint64_t ii_iprte6a_regval; | 1832 | uint64_t ii_iprte6a_regval; |
| 1895 | struct { | 1833 | struct { |
| 1896 | uint64_t i_rsvd_1 : 54; | 1834 | uint64_t i_rsvd_1:54; |
| 1897 | uint64_t i_widget : 4; | 1835 | uint64_t i_widget:4; |
| 1898 | uint64_t i_to_cnt : 5; | 1836 | uint64_t i_to_cnt:5; |
| 1899 | uint64_t i_vld : 1; | 1837 | uint64_t i_vld:1; |
| 1900 | } ii_iprte6a_fld_s; | 1838 | } ii_iprte6a_fld_s; |
| 1901 | } ii_iprte6a_u_t; | 1839 | } ii_iprte6a_u_t; |
| 1902 | 1840 | ||
| 1903 | |||
| 1904 | /************************************************************************ | 1841 | /************************************************************************ |
| 1905 | * * | 1842 | * * |
| 1906 | * There are 8 instances of this register. This register contains * | 1843 | * There are 8 instances of this register. This register contains * |
| 1907 | * the information that the II has to remember once it has launched a * | 1844 | * the information that the II has to remember once it has launched a * |
| 1908 | * PIO Read operation. The contents are used to form the correct * | 1845 | * PIO Read operation. The contents are used to form the correct * |
| 1909 | * Router Network packet and direct the Crosstalk reply to the * | 1846 | * Router Network packet and direct the Crosstalk reply to the * |
| 1910 | * appropriate processor. * | 1847 | * appropriate processor. * |
| 1911 | * * | 1848 | * * |
| 1912 | ************************************************************************/ | 1849 | ************************************************************************/ |
| 1913 | 1850 | ||
| 1914 | typedef union ii_iprte7a_u { | 1851 | typedef union ii_iprte7a_u { |
| 1915 | uint64_t ii_iprte7a_regval; | 1852 | uint64_t ii_iprte7a_regval; |
| 1916 | struct { | 1853 | struct { |
| 1917 | uint64_t i_rsvd_1 : 54; | 1854 | uint64_t i_rsvd_1:54; |
| 1918 | uint64_t i_widget : 4; | 1855 | uint64_t i_widget:4; |
| 1919 | uint64_t i_to_cnt : 5; | 1856 | uint64_t i_to_cnt:5; |
| 1920 | uint64_t i_vld : 1; | 1857 | uint64_t i_vld:1; |
| 1921 | } ii_iprtea7_fld_s; | 1858 | } ii_iprtea7_fld_s; |
| 1922 | } ii_iprte7a_u_t; | 1859 | } ii_iprte7a_u_t; |
| 1923 | 1860 | ||
| 1924 | |||
| 1925 | |||
| 1926 | /************************************************************************ | 1861 | /************************************************************************ |
| 1927 | * * | 1862 | * * |
| 1928 | * There are 8 instances of this register. This register contains * | 1863 | * There are 8 instances of this register. This register contains * |
| 1929 | * the information that the II has to remember once it has launched a * | 1864 | * the information that the II has to remember once it has launched a * |
| 1930 | * PIO Read operation. The contents are used to form the correct * | 1865 | * PIO Read operation. The contents are used to form the correct * |
| 1931 | * Router Network packet and direct the Crosstalk reply to the * | 1866 | * Router Network packet and direct the Crosstalk reply to the * |
| 1932 | * appropriate processor. * | 1867 | * appropriate processor. * |
| 1933 | * * | 1868 | * * |
| 1934 | ************************************************************************/ | 1869 | ************************************************************************/ |
| 1935 | 1870 | ||
| 1936 | |||
| 1937 | typedef union ii_iprte0b_u { | 1871 | typedef union ii_iprte0b_u { |
| 1938 | uint64_t ii_iprte0b_regval; | 1872 | uint64_t ii_iprte0b_regval; |
| 1939 | struct { | 1873 | struct { |
| 1940 | uint64_t i_rsvd_1 : 3; | 1874 | uint64_t i_rsvd_1:3; |
| 1941 | uint64_t i_address : 47; | 1875 | uint64_t i_address:47; |
| 1942 | uint64_t i_init : 3; | 1876 | uint64_t i_init:3; |
| 1943 | uint64_t i_source : 11; | 1877 | uint64_t i_source:11; |
| 1944 | } ii_iprte0b_fld_s; | 1878 | } ii_iprte0b_fld_s; |
| 1945 | } ii_iprte0b_u_t; | 1879 | } ii_iprte0b_u_t; |
| 1946 | 1880 | ||
| 1947 | |||
| 1948 | /************************************************************************ | 1881 | /************************************************************************ |
| 1949 | * * | 1882 | * * |
| 1950 | * There are 8 instances of this register. This register contains * | 1883 | * There are 8 instances of this register. This register contains * |
| 1951 | * the information that the II has to remember once it has launched a * | 1884 | * the information that the II has to remember once it has launched a * |
| 1952 | * PIO Read operation. The contents are used to form the correct * | 1885 | * PIO Read operation. The contents are used to form the correct * |
| 1953 | * Router Network packet and direct the Crosstalk reply to the * | 1886 | * Router Network packet and direct the Crosstalk reply to the * |
| 1954 | * appropriate processor. * | 1887 | * appropriate processor. * |
| 1955 | * * | 1888 | * * |
| 1956 | ************************************************************************/ | 1889 | ************************************************************************/ |
| 1957 | 1890 | ||
| 1958 | typedef union ii_iprte1b_u { | 1891 | typedef union ii_iprte1b_u { |
| 1959 | uint64_t ii_iprte1b_regval; | 1892 | uint64_t ii_iprte1b_regval; |
| 1960 | struct { | 1893 | struct { |
| 1961 | uint64_t i_rsvd_1 : 3; | 1894 | uint64_t i_rsvd_1:3; |
| 1962 | uint64_t i_address : 47; | 1895 | uint64_t i_address:47; |
| 1963 | uint64_t i_init : 3; | 1896 | uint64_t i_init:3; |
| 1964 | uint64_t i_source : 11; | 1897 | uint64_t i_source:11; |
| 1965 | } ii_iprte1b_fld_s; | 1898 | } ii_iprte1b_fld_s; |
| 1966 | } ii_iprte1b_u_t; | 1899 | } ii_iprte1b_u_t; |
| 1967 | 1900 | ||
| 1968 | |||
| 1969 | /************************************************************************ | 1901 | /************************************************************************ |
| 1970 | * * | 1902 | * * |
| 1971 | * There are 8 instances of this register. This register contains * | 1903 | * There are 8 instances of this register. This register contains * |
| 1972 | * the information that the II has to remember once it has launched a * | 1904 | * the information that the II has to remember once it has launched a * |
| 1973 | * PIO Read operation. The contents are used to form the correct * | 1905 | * PIO Read operation. The contents are used to form the correct * |
| 1974 | * Router Network packet and direct the Crosstalk reply to the * | 1906 | * Router Network packet and direct the Crosstalk reply to the * |
| 1975 | * appropriate processor. * | 1907 | * appropriate processor. * |
| 1976 | * * | 1908 | * * |
| 1977 | ************************************************************************/ | 1909 | ************************************************************************/ |
| 1978 | 1910 | ||
| 1979 | typedef union ii_iprte2b_u { | 1911 | typedef union ii_iprte2b_u { |
| 1980 | uint64_t ii_iprte2b_regval; | 1912 | uint64_t ii_iprte2b_regval; |
| 1981 | struct { | 1913 | struct { |
| 1982 | uint64_t i_rsvd_1 : 3; | 1914 | uint64_t i_rsvd_1:3; |
| 1983 | uint64_t i_address : 47; | 1915 | uint64_t i_address:47; |
| 1984 | uint64_t i_init : 3; | 1916 | uint64_t i_init:3; |
| 1985 | uint64_t i_source : 11; | 1917 | uint64_t i_source:11; |
| 1986 | } ii_iprte2b_fld_s; | 1918 | } ii_iprte2b_fld_s; |
| 1987 | } ii_iprte2b_u_t; | 1919 | } ii_iprte2b_u_t; |
| 1988 | 1920 | ||
| 1989 | |||
| 1990 | /************************************************************************ | 1921 | /************************************************************************ |
| 1991 | * * | 1922 | * * |
| 1992 | * There are 8 instances of this register. This register contains * | 1923 | * There are 8 instances of this register. This register contains * |
| 1993 | * the information that the II has to remember once it has launched a * | 1924 | * the information that the II has to remember once it has launched a * |
| 1994 | * PIO Read operation. The contents are used to form the correct * | 1925 | * PIO Read operation. The contents are used to form the correct * |
| 1995 | * Router Network packet and direct the Crosstalk reply to the * | 1926 | * Router Network packet and direct the Crosstalk reply to the * |
| 1996 | * appropriate processor. * | 1927 | * appropriate processor. * |
| 1997 | * * | 1928 | * * |
| 1998 | ************************************************************************/ | 1929 | ************************************************************************/ |
| 1999 | 1930 | ||
| 2000 | typedef union ii_iprte3b_u { | 1931 | typedef union ii_iprte3b_u { |
| 2001 | uint64_t ii_iprte3b_regval; | 1932 | uint64_t ii_iprte3b_regval; |
| 2002 | struct { | 1933 | struct { |
| 2003 | uint64_t i_rsvd_1 : 3; | 1934 | uint64_t i_rsvd_1:3; |
| 2004 | uint64_t i_address : 47; | 1935 | uint64_t i_address:47; |
| 2005 | uint64_t i_init : 3; | 1936 | uint64_t i_init:3; |
| 2006 | uint64_t i_source : 11; | 1937 | uint64_t i_source:11; |
| 2007 | } ii_iprte3b_fld_s; | 1938 | } ii_iprte3b_fld_s; |
| 2008 | } ii_iprte3b_u_t; | 1939 | } ii_iprte3b_u_t; |
| 2009 | 1940 | ||
| 2010 | |||
| 2011 | /************************************************************************ | 1941 | /************************************************************************ |
| 2012 | * * | 1942 | * * |
| 2013 | * There are 8 instances of this register. This register contains * | 1943 | * There are 8 instances of this register. This register contains * |
| 2014 | * the information that the II has to remember once it has launched a * | 1944 | * the information that the II has to remember once it has launched a * |
| 2015 | * PIO Read operation. The contents are used to form the correct * | 1945 | * PIO Read operation. The contents are used to form the correct * |
| 2016 | * Router Network packet and direct the Crosstalk reply to the * | 1946 | * Router Network packet and direct the Crosstalk reply to the * |
| 2017 | * appropriate processor. * | 1947 | * appropriate processor. * |
| 2018 | * * | 1948 | * * |
| 2019 | ************************************************************************/ | 1949 | ************************************************************************/ |
| 2020 | 1950 | ||
| 2021 | typedef union ii_iprte4b_u { | 1951 | typedef union ii_iprte4b_u { |
| 2022 | uint64_t ii_iprte4b_regval; | 1952 | uint64_t ii_iprte4b_regval; |
| 2023 | struct { | 1953 | struct { |
| 2024 | uint64_t i_rsvd_1 : 3; | 1954 | uint64_t i_rsvd_1:3; |
| 2025 | uint64_t i_address : 47; | 1955 | uint64_t i_address:47; |
| 2026 | uint64_t i_init : 3; | 1956 | uint64_t i_init:3; |
| 2027 | uint64_t i_source : 11; | 1957 | uint64_t i_source:11; |
| 2028 | } ii_iprte4b_fld_s; | 1958 | } ii_iprte4b_fld_s; |
| 2029 | } ii_iprte4b_u_t; | 1959 | } ii_iprte4b_u_t; |
| 2030 | 1960 | ||
| 2031 | |||
| 2032 | /************************************************************************ | 1961 | /************************************************************************ |
| 2033 | * * | 1962 | * * |
| 2034 | * There are 8 instances of this register. This register contains * | 1963 | * There are 8 instances of this register. This register contains * |
| 2035 | * the information that the II has to remember once it has launched a * | 1964 | * the information that the II has to remember once it has launched a * |
| 2036 | * PIO Read operation. The contents are used to form the correct * | 1965 | * PIO Read operation. The contents are used to form the correct * |
| 2037 | * Router Network packet and direct the Crosstalk reply to the * | 1966 | * Router Network packet and direct the Crosstalk reply to the * |
| 2038 | * appropriate processor. * | 1967 | * appropriate processor. * |
| 2039 | * * | 1968 | * * |
| 2040 | ************************************************************************/ | 1969 | ************************************************************************/ |
| 2041 | 1970 | ||
| 2042 | typedef union ii_iprte5b_u { | 1971 | typedef union ii_iprte5b_u { |
| 2043 | uint64_t ii_iprte5b_regval; | 1972 | uint64_t ii_iprte5b_regval; |
| 2044 | struct { | 1973 | struct { |
| 2045 | uint64_t i_rsvd_1 : 3; | 1974 | uint64_t i_rsvd_1:3; |
| 2046 | uint64_t i_address : 47; | 1975 | uint64_t i_address:47; |
| 2047 | uint64_t i_init : 3; | 1976 | uint64_t i_init:3; |
| 2048 | uint64_t i_source : 11; | 1977 | uint64_t i_source:11; |
| 2049 | } ii_iprte5b_fld_s; | 1978 | } ii_iprte5b_fld_s; |
| 2050 | } ii_iprte5b_u_t; | 1979 | } ii_iprte5b_u_t; |
| 2051 | 1980 | ||
| 2052 | |||
| 2053 | /************************************************************************ | 1981 | /************************************************************************ |
| 2054 | * * | 1982 | * * |
| 2055 | * There are 8 instances of this register. This register contains * | 1983 | * There are 8 instances of this register. This register contains * |
| 2056 | * the information that the II has to remember once it has launched a * | 1984 | * the information that the II has to remember once it has launched a * |
| 2057 | * PIO Read operation. The contents are used to form the correct * | 1985 | * PIO Read operation. The contents are used to form the correct * |
| 2058 | * Router Network packet and direct the Crosstalk reply to the * | 1986 | * Router Network packet and direct the Crosstalk reply to the * |
| 2059 | * appropriate processor. * | 1987 | * appropriate processor. * |
| 2060 | * * | 1988 | * * |
| 2061 | ************************************************************************/ | 1989 | ************************************************************************/ |
| 2062 | 1990 | ||
| 2063 | typedef union ii_iprte6b_u { | 1991 | typedef union ii_iprte6b_u { |
| 2064 | uint64_t ii_iprte6b_regval; | 1992 | uint64_t ii_iprte6b_regval; |
| 2065 | struct { | 1993 | struct { |
| 2066 | uint64_t i_rsvd_1 : 3; | 1994 | uint64_t i_rsvd_1:3; |
| 2067 | uint64_t i_address : 47; | 1995 | uint64_t i_address:47; |
| 2068 | uint64_t i_init : 3; | 1996 | uint64_t i_init:3; |
| 2069 | uint64_t i_source : 11; | 1997 | uint64_t i_source:11; |
| 2070 | 1998 | ||
| 2071 | } ii_iprte6b_fld_s; | 1999 | } ii_iprte6b_fld_s; |
| 2072 | } ii_iprte6b_u_t; | 2000 | } ii_iprte6b_u_t; |
| 2073 | 2001 | ||
| 2074 | |||
| 2075 | /************************************************************************ | 2002 | /************************************************************************ |
| 2076 | * * | 2003 | * * |
| 2077 | * There are 8 instances of this register. This register contains * | 2004 | * There are 8 instances of this register. This register contains * |
| 2078 | * the information that the II has to remember once it has launched a * | 2005 | * the information that the II has to remember once it has launched a * |
| 2079 | * PIO Read operation. The contents are used to form the correct * | 2006 | * PIO Read operation. The contents are used to form the correct * |
| 2080 | * Router Network packet and direct the Crosstalk reply to the * | 2007 | * Router Network packet and direct the Crosstalk reply to the * |
| 2081 | * appropriate processor. * | 2008 | * appropriate processor. * |
| 2082 | * * | 2009 | * * |
| 2083 | ************************************************************************/ | 2010 | ************************************************************************/ |
| 2084 | 2011 | ||
| 2085 | typedef union ii_iprte7b_u { | 2012 | typedef union ii_iprte7b_u { |
| 2086 | uint64_t ii_iprte7b_regval; | 2013 | uint64_t ii_iprte7b_regval; |
| 2087 | struct { | 2014 | struct { |
| 2088 | uint64_t i_rsvd_1 : 3; | 2015 | uint64_t i_rsvd_1:3; |
| 2089 | uint64_t i_address : 47; | 2016 | uint64_t i_address:47; |
| 2090 | uint64_t i_init : 3; | 2017 | uint64_t i_init:3; |
| 2091 | uint64_t i_source : 11; | 2018 | uint64_t i_source:11; |
| 2092 | } ii_iprte7b_fld_s; | 2019 | } ii_iprte7b_fld_s; |
| 2093 | } ii_iprte7b_u_t; | 2020 | } ii_iprte7b_u_t; |
| 2094 | 2021 | ||
| 2095 | |||
| 2096 | /************************************************************************ | 2022 | /************************************************************************ |
| 2097 | * * | 2023 | * * |
| 2098 | * Description: SHub II contains a feature which did not exist in * | 2024 | * Description: SHub II contains a feature which did not exist in * |
| 2099 | * the Hub which automatically cleans up after a Read Response * | 2025 | * the Hub which automatically cleans up after a Read Response * |
| 2100 | * timeout, including deallocation of the IPRTE and recovery of IBuf * | 2026 | * timeout, including deallocation of the IPRTE and recovery of IBuf * |
| @@ -2108,23 +2034,22 @@ typedef union ii_iprte7b_u { | |||
| 2108 | * Note that this register does not affect the contents of the IPRTE * | 2034 | * Note that this register does not affect the contents of the IPRTE * |
| 2109 | * registers. The Valid bits in those registers have to be * | 2035 | * registers. The Valid bits in those registers have to be * |
| 2110 | * specifically turned off by software. * | 2036 | * specifically turned off by software. * |
| 2111 | * * | 2037 | * * |
| 2112 | ************************************************************************/ | 2038 | ************************************************************************/ |
| 2113 | 2039 | ||
| 2114 | typedef union ii_ipdr_u { | 2040 | typedef union ii_ipdr_u { |
| 2115 | uint64_t ii_ipdr_regval; | 2041 | uint64_t ii_ipdr_regval; |
| 2116 | struct { | 2042 | struct { |
| 2117 | uint64_t i_te : 3; | 2043 | uint64_t i_te:3; |
| 2118 | uint64_t i_rsvd_1 : 1; | 2044 | uint64_t i_rsvd_1:1; |
| 2119 | uint64_t i_pnd : 1; | 2045 | uint64_t i_pnd:1; |
| 2120 | uint64_t i_init_rpcnt : 1; | 2046 | uint64_t i_init_rpcnt:1; |
| 2121 | uint64_t i_rsvd : 58; | 2047 | uint64_t i_rsvd:58; |
| 2122 | } ii_ipdr_fld_s; | 2048 | } ii_ipdr_fld_s; |
| 2123 | } ii_ipdr_u_t; | 2049 | } ii_ipdr_u_t; |
| 2124 | 2050 | ||
| 2125 | |||
| 2126 | /************************************************************************ | 2051 | /************************************************************************ |
| 2127 | * * | 2052 | * * |
| 2128 | * A write to this register causes a CRB entry to be returned to the * | 2053 | * A write to this register causes a CRB entry to be returned to the * |
| 2129 | * queue of free CRBs. The entry should have previously been cleared * | 2054 | * queue of free CRBs. The entry should have previously been cleared * |
| 2130 | * (mark bit) via backdoor access to the pertinent CRB entry. This * | 2055 | * (mark bit) via backdoor access to the pertinent CRB entry. This * |
| @@ -2137,21 +2062,20 @@ typedef union ii_ipdr_u { | |||
| 2137 | * software clears the mark bit, and finally 4) software writes to * | 2062 | * software clears the mark bit, and finally 4) software writes to * |
| 2138 | * the ICDR register to return the CRB entry to the list of free CRB * | 2063 | * the ICDR register to return the CRB entry to the list of free CRB * |
| 2139 | * entries. * | 2064 | * entries. * |
| 2140 | * * | 2065 | * * |
| 2141 | ************************************************************************/ | 2066 | ************************************************************************/ |
| 2142 | 2067 | ||
| 2143 | typedef union ii_icdr_u { | 2068 | typedef union ii_icdr_u { |
| 2144 | uint64_t ii_icdr_regval; | 2069 | uint64_t ii_icdr_regval; |
| 2145 | struct { | 2070 | struct { |
| 2146 | uint64_t i_crb_num : 4; | 2071 | uint64_t i_crb_num:4; |
| 2147 | uint64_t i_pnd : 1; | 2072 | uint64_t i_pnd:1; |
| 2148 | uint64_t i_rsvd : 59; | 2073 | uint64_t i_rsvd:59; |
| 2149 | } ii_icdr_fld_s; | 2074 | } ii_icdr_fld_s; |
| 2150 | } ii_icdr_u_t; | 2075 | } ii_icdr_u_t; |
| 2151 | 2076 | ||
| 2152 | |||
| 2153 | /************************************************************************ | 2077 | /************************************************************************ |
| 2154 | * * | 2078 | * * |
| 2155 | * This register provides debug access to two FIFOs inside of II. * | 2079 | * This register provides debug access to two FIFOs inside of II. * |
| 2156 | * Both IOQ_MAX* fields of this register contain the instantaneous * | 2080 | * Both IOQ_MAX* fields of this register contain the instantaneous * |
| 2157 | * depth (in units of the number of available entries) of the * | 2081 | * depth (in units of the number of available entries) of the * |
| @@ -2164,130 +2088,124 @@ typedef union ii_icdr_u { | |||
| 2164 | * this register is written. If there are any active entries in any * | 2088 | * this register is written. If there are any active entries in any * |
| 2165 | * of these FIFOs when this register is written, the results are * | 2089 | * of these FIFOs when this register is written, the results are * |
| 2166 | * undefined. * | 2090 | * undefined. * |
| 2167 | * * | 2091 | * * |
| 2168 | ************************************************************************/ | 2092 | ************************************************************************/ |
| 2169 | 2093 | ||
| 2170 | typedef union ii_ifdr_u { | 2094 | typedef union ii_ifdr_u { |
| 2171 | uint64_t ii_ifdr_regval; | 2095 | uint64_t ii_ifdr_regval; |
| 2172 | struct { | 2096 | struct { |
| 2173 | uint64_t i_ioq_max_rq : 7; | 2097 | uint64_t i_ioq_max_rq:7; |
| 2174 | uint64_t i_set_ioq_rq : 1; | 2098 | uint64_t i_set_ioq_rq:1; |
| 2175 | uint64_t i_ioq_max_rp : 7; | 2099 | uint64_t i_ioq_max_rp:7; |
| 2176 | uint64_t i_set_ioq_rp : 1; | 2100 | uint64_t i_set_ioq_rp:1; |
| 2177 | uint64_t i_rsvd : 48; | 2101 | uint64_t i_rsvd:48; |
| 2178 | } ii_ifdr_fld_s; | 2102 | } ii_ifdr_fld_s; |
| 2179 | } ii_ifdr_u_t; | 2103 | } ii_ifdr_u_t; |
| 2180 | 2104 | ||
| 2181 | |||
| 2182 | /************************************************************************ | 2105 | /************************************************************************ |
| 2183 | * * | 2106 | * * |
| 2184 | * This register allows the II to become sluggish in removing * | 2107 | * This register allows the II to become sluggish in removing * |
| 2185 | * messages from its inbound queue (IIQ). This will cause messages to * | 2108 | * messages from its inbound queue (IIQ). This will cause messages to * |
| 2186 | * back up in either virtual channel. Disabling the "molasses" mode * | 2109 | * back up in either virtual channel. Disabling the "molasses" mode * |
| 2187 | * subsequently allows the II to be tested under stress. In the * | 2110 | * subsequently allows the II to be tested under stress. In the * |
| 2188 | * sluggish ("Molasses") mode, the localized effects of congestion * | 2111 | * sluggish ("Molasses") mode, the localized effects of congestion * |
| 2189 | * can be observed. * | 2112 | * can be observed. * |
| 2190 | * * | 2113 | * * |
| 2191 | ************************************************************************/ | 2114 | ************************************************************************/ |
| 2192 | 2115 | ||
| 2193 | typedef union ii_iiap_u { | 2116 | typedef union ii_iiap_u { |
| 2194 | uint64_t ii_iiap_regval; | 2117 | uint64_t ii_iiap_regval; |
| 2195 | struct { | 2118 | struct { |
| 2196 | uint64_t i_rq_mls : 6; | 2119 | uint64_t i_rq_mls:6; |
| 2197 | uint64_t i_rsvd_1 : 2; | 2120 | uint64_t i_rsvd_1:2; |
| 2198 | uint64_t i_rp_mls : 6; | 2121 | uint64_t i_rp_mls:6; |
| 2199 | uint64_t i_rsvd : 50; | 2122 | uint64_t i_rsvd:50; |
| 2200 | } ii_iiap_fld_s; | 2123 | } ii_iiap_fld_s; |
| 2201 | } ii_iiap_u_t; | 2124 | } ii_iiap_u_t; |
| 2202 | 2125 | ||
| 2203 | |||
| 2204 | /************************************************************************ | 2126 | /************************************************************************ |
| 2205 | * * | 2127 | * * |
| 2206 | * This register allows several parameters of CRB operation to be * | 2128 | * This register allows several parameters of CRB operation to be * |
| 2207 | * set. Note that writing to this register can have catastrophic side * | 2129 | * set. Note that writing to this register can have catastrophic side * |
| 2208 | * effects, if the CRB is not quiescent, i.e. if the CRB is * | 2130 | * effects, if the CRB is not quiescent, i.e. if the CRB is * |
| 2209 | * processing protocol messages when the write occurs. * | 2131 | * processing protocol messages when the write occurs. * |
| 2210 | * * | 2132 | * * |
| 2211 | ************************************************************************/ | 2133 | ************************************************************************/ |
| 2212 | 2134 | ||
| 2213 | typedef union ii_icmr_u { | 2135 | typedef union ii_icmr_u { |
| 2214 | uint64_t ii_icmr_regval; | 2136 | uint64_t ii_icmr_regval; |
| 2215 | struct { | 2137 | struct { |
| 2216 | uint64_t i_sp_msg : 1; | 2138 | uint64_t i_sp_msg:1; |
| 2217 | uint64_t i_rd_hdr : 1; | 2139 | uint64_t i_rd_hdr:1; |
| 2218 | uint64_t i_rsvd_4 : 2; | 2140 | uint64_t i_rsvd_4:2; |
| 2219 | uint64_t i_c_cnt : 4; | 2141 | uint64_t i_c_cnt:4; |
| 2220 | uint64_t i_rsvd_3 : 4; | 2142 | uint64_t i_rsvd_3:4; |
| 2221 | uint64_t i_clr_rqpd : 1; | 2143 | uint64_t i_clr_rqpd:1; |
| 2222 | uint64_t i_clr_rppd : 1; | 2144 | uint64_t i_clr_rppd:1; |
| 2223 | uint64_t i_rsvd_2 : 2; | 2145 | uint64_t i_rsvd_2:2; |
| 2224 | uint64_t i_fc_cnt : 4; | 2146 | uint64_t i_fc_cnt:4; |
| 2225 | uint64_t i_crb_vld : 15; | 2147 | uint64_t i_crb_vld:15; |
| 2226 | uint64_t i_crb_mark : 15; | 2148 | uint64_t i_crb_mark:15; |
| 2227 | uint64_t i_rsvd_1 : 2; | 2149 | uint64_t i_rsvd_1:2; |
| 2228 | uint64_t i_precise : 1; | 2150 | uint64_t i_precise:1; |
| 2229 | uint64_t i_rsvd : 11; | 2151 | uint64_t i_rsvd:11; |
| 2230 | } ii_icmr_fld_s; | 2152 | } ii_icmr_fld_s; |
| 2231 | } ii_icmr_u_t; | 2153 | } ii_icmr_u_t; |
| 2232 | 2154 | ||
| 2233 | |||
| 2234 | /************************************************************************ | 2155 | /************************************************************************ |
| 2235 | * * | 2156 | * * |
| 2236 | * This register allows control of the table portion of the CRB * | 2157 | * This register allows control of the table portion of the CRB * |
| 2237 | * logic via software. Control operations from this register have * | 2158 | * logic via software. Control operations from this register have * |
| 2238 | * priority over all incoming Crosstalk or BTE requests. * | 2159 | * priority over all incoming Crosstalk or BTE requests. * |
| 2239 | * * | 2160 | * * |
| 2240 | ************************************************************************/ | 2161 | ************************************************************************/ |
| 2241 | 2162 | ||
| 2242 | typedef union ii_iccr_u { | 2163 | typedef union ii_iccr_u { |
| 2243 | uint64_t ii_iccr_regval; | 2164 | uint64_t ii_iccr_regval; |
| 2244 | struct { | 2165 | struct { |
| 2245 | uint64_t i_crb_num : 4; | 2166 | uint64_t i_crb_num:4; |
| 2246 | uint64_t i_rsvd_1 : 4; | 2167 | uint64_t i_rsvd_1:4; |
| 2247 | uint64_t i_cmd : 8; | 2168 | uint64_t i_cmd:8; |
| 2248 | uint64_t i_pending : 1; | 2169 | uint64_t i_pending:1; |
| 2249 | uint64_t i_rsvd : 47; | 2170 | uint64_t i_rsvd:47; |
| 2250 | } ii_iccr_fld_s; | 2171 | } ii_iccr_fld_s; |
| 2251 | } ii_iccr_u_t; | 2172 | } ii_iccr_u_t; |
| 2252 | 2173 | ||
| 2253 | |||
| 2254 | /************************************************************************ | 2174 | /************************************************************************ |
| 2255 | * * | 2175 | * * |
| 2256 | * This register allows the maximum timeout value to be programmed. * | 2176 | * This register allows the maximum timeout value to be programmed. * |
| 2257 | * * | 2177 | * * |
| 2258 | ************************************************************************/ | 2178 | ************************************************************************/ |
| 2259 | 2179 | ||
| 2260 | typedef union ii_icto_u { | 2180 | typedef union ii_icto_u { |
| 2261 | uint64_t ii_icto_regval; | 2181 | uint64_t ii_icto_regval; |
| 2262 | struct { | 2182 | struct { |
| 2263 | uint64_t i_timeout : 8; | 2183 | uint64_t i_timeout:8; |
| 2264 | uint64_t i_rsvd : 56; | 2184 | uint64_t i_rsvd:56; |
| 2265 | } ii_icto_fld_s; | 2185 | } ii_icto_fld_s; |
| 2266 | } ii_icto_u_t; | 2186 | } ii_icto_u_t; |
| 2267 | 2187 | ||
| 2268 | |||
| 2269 | /************************************************************************ | 2188 | /************************************************************************ |
| 2270 | * * | 2189 | * * |
| 2271 | * This register allows the timeout prescalar to be programmed. An * | 2190 | * This register allows the timeout prescalar to be programmed. An * |
| 2272 | * internal counter is associated with this register. When the * | 2191 | * internal counter is associated with this register. When the * |
| 2273 | * internal counter reaches the value of the PRESCALE field, the * | 2192 | * internal counter reaches the value of the PRESCALE field, the * |
| 2274 | * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] * | 2193 | * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] * |
| 2275 | * field). The internal counter resets to zero, and then continues * | 2194 | * field). The internal counter resets to zero, and then continues * |
| 2276 | * counting. * | 2195 | * counting. * |
| 2277 | * * | 2196 | * * |
| 2278 | ************************************************************************/ | 2197 | ************************************************************************/ |
| 2279 | 2198 | ||
| 2280 | typedef union ii_ictp_u { | 2199 | typedef union ii_ictp_u { |
| 2281 | uint64_t ii_ictp_regval; | 2200 | uint64_t ii_ictp_regval; |
| 2282 | struct { | 2201 | struct { |
| 2283 | uint64_t i_prescale : 24; | 2202 | uint64_t i_prescale:24; |
| 2284 | uint64_t i_rsvd : 40; | 2203 | uint64_t i_rsvd:40; |
| 2285 | } ii_ictp_fld_s; | 2204 | } ii_ictp_fld_s; |
| 2286 | } ii_ictp_u_t; | 2205 | } ii_ictp_u_t; |
| 2287 | 2206 | ||
| 2288 | |||
| 2289 | /************************************************************************ | 2207 | /************************************************************************ |
| 2290 | * * | 2208 | * * |
| 2291 | * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * | 2209 | * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * |
| 2292 | * used for Crosstalk operations (both cacheline and partial * | 2210 | * used for Crosstalk operations (both cacheline and partial * |
| 2293 | * operations) or BTE/IO. Because the CRB entries are very wide, five * | 2211 | * operations) or BTE/IO. Because the CRB entries are very wide, five * |
| @@ -2306,243 +2224,234 @@ typedef union ii_ictp_u { | |||
| 2306 | * recovering any potential error state from before the reset). * | 2224 | * recovering any potential error state from before the reset). * |
| 2307 | * The following four tables summarize the format for the four * | 2225 | * The following four tables summarize the format for the four * |
| 2308 | * registers that are used for each ICRB# Entry. * | 2226 | * registers that are used for each ICRB# Entry. * |
| 2309 | * * | 2227 | * * |
| 2310 | ************************************************************************/ | 2228 | ************************************************************************/ |
| 2311 | 2229 | ||
| 2312 | typedef union ii_icrb0_a_u { | 2230 | typedef union ii_icrb0_a_u { |
| 2313 | uint64_t ii_icrb0_a_regval; | 2231 | uint64_t ii_icrb0_a_regval; |
| 2314 | struct { | 2232 | struct { |
| 2315 | uint64_t ia_iow : 1; | 2233 | uint64_t ia_iow:1; |
| 2316 | uint64_t ia_vld : 1; | 2234 | uint64_t ia_vld:1; |
| 2317 | uint64_t ia_addr : 47; | 2235 | uint64_t ia_addr:47; |
| 2318 | uint64_t ia_tnum : 5; | 2236 | uint64_t ia_tnum:5; |
| 2319 | uint64_t ia_sidn : 4; | 2237 | uint64_t ia_sidn:4; |
| 2320 | uint64_t ia_rsvd : 6; | 2238 | uint64_t ia_rsvd:6; |
| 2321 | } ii_icrb0_a_fld_s; | 2239 | } ii_icrb0_a_fld_s; |
| 2322 | } ii_icrb0_a_u_t; | 2240 | } ii_icrb0_a_u_t; |
| 2323 | 2241 | ||
| 2324 | |||
| 2325 | /************************************************************************ | 2242 | /************************************************************************ |
| 2326 | * * | 2243 | * * |
| 2327 | * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * | 2244 | * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * |
| 2328 | * used for Crosstalk operations (both cacheline and partial * | 2245 | * used for Crosstalk operations (both cacheline and partial * |
| 2329 | * operations) or BTE/IO. Because the CRB entries are very wide, five * | 2246 | * operations) or BTE/IO. Because the CRB entries are very wide, five * |
| 2330 | * registers (_A to _E) are required to read and write each entry. * | 2247 | * registers (_A to _E) are required to read and write each entry. * |
| 2331 | * * | 2248 | * * |
| 2332 | ************************************************************************/ | 2249 | ************************************************************************/ |
| 2333 | 2250 | ||
| 2334 | typedef union ii_icrb0_b_u { | 2251 | typedef union ii_icrb0_b_u { |
| 2335 | uint64_t ii_icrb0_b_regval; | 2252 | uint64_t ii_icrb0_b_regval; |
| 2336 | struct { | 2253 | struct { |
| 2337 | uint64_t ib_xt_err : 1; | 2254 | uint64_t ib_xt_err:1; |
| 2338 | uint64_t ib_mark : 1; | 2255 | uint64_t ib_mark:1; |
| 2339 | uint64_t ib_ln_uce : 1; | 2256 | uint64_t ib_ln_uce:1; |
| 2340 | uint64_t ib_errcode : 3; | 2257 | uint64_t ib_errcode:3; |
| 2341 | uint64_t ib_error : 1; | 2258 | uint64_t ib_error:1; |
| 2342 | uint64_t ib_stall__bte_1 : 1; | 2259 | uint64_t ib_stall__bte_1:1; |
| 2343 | uint64_t ib_stall__bte_0 : 1; | 2260 | uint64_t ib_stall__bte_0:1; |
| 2344 | uint64_t ib_stall__intr : 1; | 2261 | uint64_t ib_stall__intr:1; |
| 2345 | uint64_t ib_stall_ib : 1; | 2262 | uint64_t ib_stall_ib:1; |
| 2346 | uint64_t ib_intvn : 1; | 2263 | uint64_t ib_intvn:1; |
| 2347 | uint64_t ib_wb : 1; | 2264 | uint64_t ib_wb:1; |
| 2348 | uint64_t ib_hold : 1; | 2265 | uint64_t ib_hold:1; |
| 2349 | uint64_t ib_ack : 1; | 2266 | uint64_t ib_ack:1; |
| 2350 | uint64_t ib_resp : 1; | 2267 | uint64_t ib_resp:1; |
| 2351 | uint64_t ib_ack_cnt : 11; | 2268 | uint64_t ib_ack_cnt:11; |
| 2352 | uint64_t ib_rsvd : 7; | 2269 | uint64_t ib_rsvd:7; |
| 2353 | uint64_t ib_exc : 5; | 2270 | uint64_t ib_exc:5; |
| 2354 | uint64_t ib_init : 3; | 2271 | uint64_t ib_init:3; |
| 2355 | uint64_t ib_imsg : 8; | 2272 | uint64_t ib_imsg:8; |
| 2356 | uint64_t ib_imsgtype : 2; | 2273 | uint64_t ib_imsgtype:2; |
| 2357 | uint64_t ib_use_old : 1; | 2274 | uint64_t ib_use_old:1; |
| 2358 | uint64_t ib_rsvd_1 : 11; | 2275 | uint64_t ib_rsvd_1:11; |
| 2359 | } ii_icrb0_b_fld_s; | 2276 | } ii_icrb0_b_fld_s; |
| 2360 | } ii_icrb0_b_u_t; | 2277 | } ii_icrb0_b_u_t; |
| 2361 | 2278 | ||
| 2362 | |||
| 2363 | /************************************************************************ | 2279 | /************************************************************************ |
| 2364 | * * | 2280 | * * |
| 2365 | * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * | 2281 | * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * |
| 2366 | * used for Crosstalk operations (both cacheline and partial * | 2282 | * used for Crosstalk operations (both cacheline and partial * |
| 2367 | * operations) or BTE/IO. Because the CRB entries are very wide, five * | 2283 | * operations) or BTE/IO. Because the CRB entries are very wide, five * |
| 2368 | * registers (_A to _E) are required to read and write each entry. * | 2284 | * registers (_A to _E) are required to read and write each entry. * |
| 2369 | * * | 2285 | * * |
| 2370 | ************************************************************************/ | 2286 | ************************************************************************/ |
| 2371 | 2287 | ||
| 2372 | typedef union ii_icrb0_c_u { | 2288 | typedef union ii_icrb0_c_u { |
| 2373 | uint64_t ii_icrb0_c_regval; | 2289 | uint64_t ii_icrb0_c_regval; |
| 2374 | struct { | 2290 | struct { |
| 2375 | uint64_t ic_source : 15; | 2291 | uint64_t ic_source:15; |
| 2376 | uint64_t ic_size : 2; | 2292 | uint64_t ic_size:2; |
| 2377 | uint64_t ic_ct : 1; | 2293 | uint64_t ic_ct:1; |
| 2378 | uint64_t ic_bte_num : 1; | 2294 | uint64_t ic_bte_num:1; |
| 2379 | uint64_t ic_gbr : 1; | 2295 | uint64_t ic_gbr:1; |
| 2380 | uint64_t ic_resprqd : 1; | 2296 | uint64_t ic_resprqd:1; |
| 2381 | uint64_t ic_bo : 1; | 2297 | uint64_t ic_bo:1; |
| 2382 | uint64_t ic_suppl : 15; | 2298 | uint64_t ic_suppl:15; |
| 2383 | uint64_t ic_rsvd : 27; | 2299 | uint64_t ic_rsvd:27; |
| 2384 | } ii_icrb0_c_fld_s; | 2300 | } ii_icrb0_c_fld_s; |
| 2385 | } ii_icrb0_c_u_t; | 2301 | } ii_icrb0_c_u_t; |
| 2386 | 2302 | ||
| 2387 | |||
| 2388 | /************************************************************************ | 2303 | /************************************************************************ |
| 2389 | * * | 2304 | * * |
| 2390 | * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * | 2305 | * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * |
| 2391 | * used for Crosstalk operations (both cacheline and partial * | 2306 | * used for Crosstalk operations (both cacheline and partial * |
| 2392 | * operations) or BTE/IO. Because the CRB entries are very wide, five * | 2307 | * operations) or BTE/IO. Because the CRB entries are very wide, five * |
| 2393 | * registers (_A to _E) are required to read and write each entry. * | 2308 | * registers (_A to _E) are required to read and write each entry. * |
| 2394 | * * | 2309 | * * |
| 2395 | ************************************************************************/ | 2310 | ************************************************************************/ |
| 2396 | 2311 | ||
| 2397 | typedef union ii_icrb0_d_u { | 2312 | typedef union ii_icrb0_d_u { |
| 2398 | uint64_t ii_icrb0_d_regval; | 2313 | uint64_t ii_icrb0_d_regval; |
| 2399 | struct { | 2314 | struct { |
| 2400 | uint64_t id_pa_be : 43; | 2315 | uint64_t id_pa_be:43; |
| 2401 | uint64_t id_bte_op : 1; | 2316 | uint64_t id_bte_op:1; |
| 2402 | uint64_t id_pr_psc : 4; | 2317 | uint64_t id_pr_psc:4; |
| 2403 | uint64_t id_pr_cnt : 4; | 2318 | uint64_t id_pr_cnt:4; |
| 2404 | uint64_t id_sleep : 1; | 2319 | uint64_t id_sleep:1; |
| 2405 | uint64_t id_rsvd : 11; | 2320 | uint64_t id_rsvd:11; |
| 2406 | } ii_icrb0_d_fld_s; | 2321 | } ii_icrb0_d_fld_s; |
| 2407 | } ii_icrb0_d_u_t; | 2322 | } ii_icrb0_d_u_t; |
| 2408 | 2323 | ||
| 2409 | |||
| 2410 | /************************************************************************ | 2324 | /************************************************************************ |
| 2411 | * * | 2325 | * * |
| 2412 | * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * | 2326 | * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * |
| 2413 | * used for Crosstalk operations (both cacheline and partial * | 2327 | * used for Crosstalk operations (both cacheline and partial * |
| 2414 | * operations) or BTE/IO. Because the CRB entries are very wide, five * | 2328 | * operations) or BTE/IO. Because the CRB entries are very wide, five * |
| 2415 | * registers (_A to _E) are required to read and write each entry. * | 2329 | * registers (_A to _E) are required to read and write each entry. * |
| 2416 | * * | 2330 | * * |
| 2417 | ************************************************************************/ | 2331 | ************************************************************************/ |
| 2418 | 2332 | ||
| 2419 | typedef union ii_icrb0_e_u { | 2333 | typedef union ii_icrb0_e_u { |
| 2420 | uint64_t ii_icrb0_e_regval; | 2334 | uint64_t ii_icrb0_e_regval; |
| 2421 | struct { | 2335 | struct { |
| 2422 | uint64_t ie_timeout : 8; | 2336 | uint64_t ie_timeout:8; |
| 2423 | uint64_t ie_context : 15; | 2337 | uint64_t ie_context:15; |
| 2424 | uint64_t ie_rsvd : 1; | 2338 | uint64_t ie_rsvd:1; |
| 2425 | uint64_t ie_tvld : 1; | 2339 | uint64_t ie_tvld:1; |
| 2426 | uint64_t ie_cvld : 1; | 2340 | uint64_t ie_cvld:1; |
| 2427 | uint64_t ie_rsvd_0 : 38; | 2341 | uint64_t ie_rsvd_0:38; |
| 2428 | } ii_icrb0_e_fld_s; | 2342 | } ii_icrb0_e_fld_s; |
| 2429 | } ii_icrb0_e_u_t; | 2343 | } ii_icrb0_e_u_t; |
| 2430 | 2344 | ||
| 2431 | |||
| 2432 | /************************************************************************ | 2345 | /************************************************************************ |
| 2433 | * * | 2346 | * * |
| 2434 | * This register contains the lower 64 bits of the header of the * | 2347 | * This register contains the lower 64 bits of the header of the * |
| 2435 | * spurious message captured by II. Valid when the SP_MSG bit in ICMR * | 2348 | * spurious message captured by II. Valid when the SP_MSG bit in ICMR * |
| 2436 | * register is set. * | 2349 | * register is set. * |
| 2437 | * * | 2350 | * * |
| 2438 | ************************************************************************/ | 2351 | ************************************************************************/ |
| 2439 | 2352 | ||
| 2440 | typedef union ii_icsml_u { | 2353 | typedef union ii_icsml_u { |
| 2441 | uint64_t ii_icsml_regval; | 2354 | uint64_t ii_icsml_regval; |
| 2442 | struct { | 2355 | struct { |
| 2443 | uint64_t i_tt_addr : 47; | 2356 | uint64_t i_tt_addr:47; |
| 2444 | uint64_t i_newsuppl_ex : 14; | 2357 | uint64_t i_newsuppl_ex:14; |
| 2445 | uint64_t i_reserved : 2; | 2358 | uint64_t i_reserved:2; |
| 2446 | uint64_t i_overflow : 1; | 2359 | uint64_t i_overflow:1; |
| 2447 | } ii_icsml_fld_s; | 2360 | } ii_icsml_fld_s; |
| 2448 | } ii_icsml_u_t; | 2361 | } ii_icsml_u_t; |
| 2449 | 2362 | ||
| 2450 | |||
| 2451 | /************************************************************************ | 2363 | /************************************************************************ |
| 2452 | * * | 2364 | * * |
| 2453 | * This register contains the middle 64 bits of the header of the * | 2365 | * This register contains the middle 64 bits of the header of the * |
| 2454 | * spurious message captured by II. Valid when the SP_MSG bit in ICMR * | 2366 | * spurious message captured by II. Valid when the SP_MSG bit in ICMR * |
| 2455 | * register is set. * | 2367 | * register is set. * |
| 2456 | * * | 2368 | * * |
| 2457 | ************************************************************************/ | 2369 | ************************************************************************/ |
| 2458 | 2370 | ||
| 2459 | typedef union ii_icsmm_u { | 2371 | typedef union ii_icsmm_u { |
| 2460 | uint64_t ii_icsmm_regval; | 2372 | uint64_t ii_icsmm_regval; |
| 2461 | struct { | 2373 | struct { |
| 2462 | uint64_t i_tt_ack_cnt : 11; | 2374 | uint64_t i_tt_ack_cnt:11; |
| 2463 | uint64_t i_reserved : 53; | 2375 | uint64_t i_reserved:53; |
| 2464 | } ii_icsmm_fld_s; | 2376 | } ii_icsmm_fld_s; |
| 2465 | } ii_icsmm_u_t; | 2377 | } ii_icsmm_u_t; |
| 2466 | 2378 | ||
| 2467 | |||
| 2468 | /************************************************************************ | 2379 | /************************************************************************ |
| 2469 | * * | 2380 | * * |
| 2470 | * This register contains the microscopic state, all the inputs to * | 2381 | * This register contains the microscopic state, all the inputs to * |
| 2471 | * the protocol table, captured with the spurious message. Valid when * | 2382 | * the protocol table, captured with the spurious message. Valid when * |
| 2472 | * the SP_MSG bit in the ICMR register is set. * | 2383 | * the SP_MSG bit in the ICMR register is set. * |
| 2473 | * * | 2384 | * * |
| 2474 | ************************************************************************/ | 2385 | ************************************************************************/ |
| 2475 | 2386 | ||
| 2476 | typedef union ii_icsmh_u { | 2387 | typedef union ii_icsmh_u { |
| 2477 | uint64_t ii_icsmh_regval; | 2388 | uint64_t ii_icsmh_regval; |
| 2478 | struct { | 2389 | struct { |
| 2479 | uint64_t i_tt_vld : 1; | 2390 | uint64_t i_tt_vld:1; |
| 2480 | uint64_t i_xerr : 1; | 2391 | uint64_t i_xerr:1; |
| 2481 | uint64_t i_ft_cwact_o : 1; | 2392 | uint64_t i_ft_cwact_o:1; |
| 2482 | uint64_t i_ft_wact_o : 1; | 2393 | uint64_t i_ft_wact_o:1; |
| 2483 | uint64_t i_ft_active_o : 1; | 2394 | uint64_t i_ft_active_o:1; |
| 2484 | uint64_t i_sync : 1; | 2395 | uint64_t i_sync:1; |
| 2485 | uint64_t i_mnusg : 1; | 2396 | uint64_t i_mnusg:1; |
| 2486 | uint64_t i_mnusz : 1; | 2397 | uint64_t i_mnusz:1; |
| 2487 | uint64_t i_plusz : 1; | 2398 | uint64_t i_plusz:1; |
| 2488 | uint64_t i_plusg : 1; | 2399 | uint64_t i_plusg:1; |
| 2489 | uint64_t i_tt_exc : 5; | 2400 | uint64_t i_tt_exc:5; |
| 2490 | uint64_t i_tt_wb : 1; | 2401 | uint64_t i_tt_wb:1; |
| 2491 | uint64_t i_tt_hold : 1; | 2402 | uint64_t i_tt_hold:1; |
| 2492 | uint64_t i_tt_ack : 1; | 2403 | uint64_t i_tt_ack:1; |
| 2493 | uint64_t i_tt_resp : 1; | 2404 | uint64_t i_tt_resp:1; |
| 2494 | uint64_t i_tt_intvn : 1; | 2405 | uint64_t i_tt_intvn:1; |
| 2495 | uint64_t i_g_stall_bte1 : 1; | 2406 | uint64_t i_g_stall_bte1:1; |
| 2496 | uint64_t i_g_stall_bte0 : 1; | 2407 | uint64_t i_g_stall_bte0:1; |
| 2497 | uint64_t i_g_stall_il : 1; | 2408 | uint64_t i_g_stall_il:1; |
| 2498 | uint64_t i_g_stall_ib : 1; | 2409 | uint64_t i_g_stall_ib:1; |
| 2499 | uint64_t i_tt_imsg : 8; | 2410 | uint64_t i_tt_imsg:8; |
| 2500 | uint64_t i_tt_imsgtype : 2; | 2411 | uint64_t i_tt_imsgtype:2; |
| 2501 | uint64_t i_tt_use_old : 1; | 2412 | uint64_t i_tt_use_old:1; |
| 2502 | uint64_t i_tt_respreqd : 1; | 2413 | uint64_t i_tt_respreqd:1; |
| 2503 | uint64_t i_tt_bte_num : 1; | 2414 | uint64_t i_tt_bte_num:1; |
| 2504 | uint64_t i_cbn : 1; | 2415 | uint64_t i_cbn:1; |
| 2505 | uint64_t i_match : 1; | 2416 | uint64_t i_match:1; |
| 2506 | uint64_t i_rpcnt_lt_34 : 1; | 2417 | uint64_t i_rpcnt_lt_34:1; |
| 2507 | uint64_t i_rpcnt_ge_34 : 1; | 2418 | uint64_t i_rpcnt_ge_34:1; |
| 2508 | uint64_t i_rpcnt_lt_18 : 1; | 2419 | uint64_t i_rpcnt_lt_18:1; |
| 2509 | uint64_t i_rpcnt_ge_18 : 1; | 2420 | uint64_t i_rpcnt_ge_18:1; |
| 2510 | uint64_t i_rpcnt_lt_2 : 1; | 2421 | uint64_t i_rpcnt_lt_2:1; |
| 2511 | uint64_t i_rpcnt_ge_2 : 1; | 2422 | uint64_t i_rpcnt_ge_2:1; |
| 2512 | uint64_t i_rqcnt_lt_18 : 1; | 2423 | uint64_t i_rqcnt_lt_18:1; |
| 2513 | uint64_t i_rqcnt_ge_18 : 1; | 2424 | uint64_t i_rqcnt_ge_18:1; |
| 2514 | uint64_t i_rqcnt_lt_2 : 1; | 2425 | uint64_t i_rqcnt_lt_2:1; |
| 2515 | uint64_t i_rqcnt_ge_2 : 1; | 2426 | uint64_t i_rqcnt_ge_2:1; |
| 2516 | uint64_t i_tt_device : 7; | 2427 | uint64_t i_tt_device:7; |
| 2517 | uint64_t i_tt_init : 3; | 2428 | uint64_t i_tt_init:3; |
| 2518 | uint64_t i_reserved : 5; | 2429 | uint64_t i_reserved:5; |
| 2519 | } ii_icsmh_fld_s; | 2430 | } ii_icsmh_fld_s; |
| 2520 | } ii_icsmh_u_t; | 2431 | } ii_icsmh_u_t; |
| 2521 | 2432 | ||
| 2522 | |||
| 2523 | /************************************************************************ | 2433 | /************************************************************************ |
| 2524 | * * | 2434 | * * |
| 2525 | * The Shub DEBUG unit provides a 3-bit selection signal to the * | 2435 | * The Shub DEBUG unit provides a 3-bit selection signal to the * |
| 2526 | * II core and a 3-bit selection signal to the fsbclk domain in the II * | 2436 | * II core and a 3-bit selection signal to the fsbclk domain in the II * |
| 2527 | * wrapper. * | 2437 | * wrapper. * |
| 2528 | * * | 2438 | * * |
| 2529 | ************************************************************************/ | 2439 | ************************************************************************/ |
| 2530 | 2440 | ||
| 2531 | typedef union ii_idbss_u { | 2441 | typedef union ii_idbss_u { |
| 2532 | uint64_t ii_idbss_regval; | 2442 | uint64_t ii_idbss_regval; |
| 2533 | struct { | 2443 | struct { |
| 2534 | uint64_t i_iioclk_core_submenu : 3; | 2444 | uint64_t i_iioclk_core_submenu:3; |
| 2535 | uint64_t i_rsvd : 5; | 2445 | uint64_t i_rsvd:5; |
| 2536 | uint64_t i_fsbclk_wrapper_submenu : 3; | 2446 | uint64_t i_fsbclk_wrapper_submenu:3; |
| 2537 | uint64_t i_rsvd_1 : 5; | 2447 | uint64_t i_rsvd_1:5; |
| 2538 | uint64_t i_iioclk_menu : 5; | 2448 | uint64_t i_iioclk_menu:5; |
| 2539 | uint64_t i_rsvd_2 : 43; | 2449 | uint64_t i_rsvd_2:43; |
| 2540 | } ii_idbss_fld_s; | 2450 | } ii_idbss_fld_s; |
| 2541 | } ii_idbss_u_t; | 2451 | } ii_idbss_u_t; |
| 2542 | 2452 | ||
| 2543 | |||
| 2544 | /************************************************************************ | 2453 | /************************************************************************ |
| 2545 | * * | 2454 | * * |
| 2546 | * Description: This register is used to set up the length for a * | 2455 | * Description: This register is used to set up the length for a * |
| 2547 | * transfer and then to monitor the progress of that transfer. This * | 2456 | * transfer and then to monitor the progress of that transfer. This * |
| 2548 | * register needs to be initialized before a transfer is started. A * | 2457 | * register needs to be initialized before a transfer is started. A * |
| @@ -2553,63 +2462,60 @@ typedef union ii_idbss_u { | |||
| 2553 | * transfer completes, hardware will clear the Busy bit. The length * | 2462 | * transfer completes, hardware will clear the Busy bit. The length * |
| 2554 | * field will also contain the number of cache lines left to be * | 2463 | * field will also contain the number of cache lines left to be * |
| 2555 | * transferred. * | 2464 | * transferred. * |
| 2556 | * * | 2465 | * * |
| 2557 | ************************************************************************/ | 2466 | ************************************************************************/ |
| 2558 | 2467 | ||
| 2559 | typedef union ii_ibls0_u { | 2468 | typedef union ii_ibls0_u { |
| 2560 | uint64_t ii_ibls0_regval; | 2469 | uint64_t ii_ibls0_regval; |
| 2561 | struct { | 2470 | struct { |
| 2562 | uint64_t i_length : 16; | 2471 | uint64_t i_length:16; |
| 2563 | uint64_t i_error : 1; | 2472 | uint64_t i_error:1; |
| 2564 | uint64_t i_rsvd_1 : 3; | 2473 | uint64_t i_rsvd_1:3; |
| 2565 | uint64_t i_busy : 1; | 2474 | uint64_t i_busy:1; |
| 2566 | uint64_t i_rsvd : 43; | 2475 | uint64_t i_rsvd:43; |
| 2567 | } ii_ibls0_fld_s; | 2476 | } ii_ibls0_fld_s; |
| 2568 | } ii_ibls0_u_t; | 2477 | } ii_ibls0_u_t; |
| 2569 | 2478 | ||
| 2570 | |||
| 2571 | /************************************************************************ | 2479 | /************************************************************************ |
| 2572 | * * | 2480 | * * |
| 2573 | * This register should be loaded before a transfer is started. The * | 2481 | * This register should be loaded before a transfer is started. The * |
| 2574 | * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * | 2482 | * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * |
| 2575 | * address as described in Section 1.3, Figure2 and Figure3. Since * | 2483 | * address as described in Section 1.3, Figure2 and Figure3. Since * |
| 2576 | * the bottom 7 bits of the address are always taken to be zero, BTE * | 2484 | * the bottom 7 bits of the address are always taken to be zero, BTE * |
| 2577 | * transfers are always cacheline-aligned. * | 2485 | * transfers are always cacheline-aligned. * |
| 2578 | * * | 2486 | * * |
| 2579 | ************************************************************************/ | 2487 | ************************************************************************/ |
| 2580 | 2488 | ||
| 2581 | typedef union ii_ibsa0_u { | 2489 | typedef union ii_ibsa0_u { |
| 2582 | uint64_t ii_ibsa0_regval; | 2490 | uint64_t ii_ibsa0_regval; |
| 2583 | struct { | 2491 | struct { |
| 2584 | uint64_t i_rsvd_1 : 7; | 2492 | uint64_t i_rsvd_1:7; |
| 2585 | uint64_t i_addr : 42; | 2493 | uint64_t i_addr:42; |
| 2586 | uint64_t i_rsvd : 15; | 2494 | uint64_t i_rsvd:15; |
| 2587 | } ii_ibsa0_fld_s; | 2495 | } ii_ibsa0_fld_s; |
| 2588 | } ii_ibsa0_u_t; | 2496 | } ii_ibsa0_u_t; |
| 2589 | 2497 | ||
| 2590 | |||
| 2591 | /************************************************************************ | 2498 | /************************************************************************ |
| 2592 | * * | 2499 | * * |
| 2593 | * This register should be loaded before a transfer is started. The * | 2500 | * This register should be loaded before a transfer is started. The * |
| 2594 | * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * | 2501 | * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * |
| 2595 | * address as described in Section 1.3, Figure2 and Figure3. Since * | 2502 | * address as described in Section 1.3, Figure2 and Figure3. Since * |
| 2596 | * the bottom 7 bits of the address are always taken to be zero, BTE * | 2503 | * the bottom 7 bits of the address are always taken to be zero, BTE * |
| 2597 | * transfers are always cacheline-aligned. * | 2504 | * transfers are always cacheline-aligned. * |
| 2598 | * * | 2505 | * * |
| 2599 | ************************************************************************/ | 2506 | ************************************************************************/ |
| 2600 | 2507 | ||
| 2601 | typedef union ii_ibda0_u { | 2508 | typedef union ii_ibda0_u { |
| 2602 | uint64_t ii_ibda0_regval; | 2509 | uint64_t ii_ibda0_regval; |
| 2603 | struct { | 2510 | struct { |
| 2604 | uint64_t i_rsvd_1 : 7; | 2511 | uint64_t i_rsvd_1:7; |
| 2605 | uint64_t i_addr : 42; | 2512 | uint64_t i_addr:42; |
| 2606 | uint64_t i_rsvd : 15; | 2513 | uint64_t i_rsvd:15; |
| 2607 | } ii_ibda0_fld_s; | 2514 | } ii_ibda0_fld_s; |
| 2608 | } ii_ibda0_u_t; | 2515 | } ii_ibda0_u_t; |
| 2609 | 2516 | ||
| 2610 | |||
| 2611 | /************************************************************************ | 2517 | /************************************************************************ |
| 2612 | * * | 2518 | * * |
| 2613 | * Writing to this register sets up the attributes of the transfer * | 2519 | * Writing to this register sets up the attributes of the transfer * |
| 2614 | * and initiates the transfer operation. Reading this register has * | 2520 | * and initiates the transfer operation. Reading this register has * |
| 2615 | * the side effect of terminating any transfer in progress. Note: * | 2521 | * the side effect of terminating any transfer in progress. Note: * |
| @@ -2617,61 +2523,58 @@ typedef union ii_ibda0_u { | |||
| 2617 | * other BTE. If a BTE stream has to be stopped (due to error * | 2523 | * other BTE. If a BTE stream has to be stopped (due to error * |
| 2618 | * handling for example), both BTE streams should be stopped and * | 2524 | * handling for example), both BTE streams should be stopped and * |
| 2619 | * their transfers discarded. * | 2525 | * their transfers discarded. * |
| 2620 | * * | 2526 | * * |
| 2621 | ************************************************************************/ | 2527 | ************************************************************************/ |
| 2622 | 2528 | ||
| 2623 | typedef union ii_ibct0_u { | 2529 | typedef union ii_ibct0_u { |
| 2624 | uint64_t ii_ibct0_regval; | 2530 | uint64_t ii_ibct0_regval; |
| 2625 | struct { | 2531 | struct { |
| 2626 | uint64_t i_zerofill : 1; | 2532 | uint64_t i_zerofill:1; |
| 2627 | uint64_t i_rsvd_2 : 3; | 2533 | uint64_t i_rsvd_2:3; |
| 2628 | uint64_t i_notify : 1; | 2534 | uint64_t i_notify:1; |
| 2629 | uint64_t i_rsvd_1 : 3; | 2535 | uint64_t i_rsvd_1:3; |
| 2630 | uint64_t i_poison : 1; | 2536 | uint64_t i_poison:1; |
| 2631 | uint64_t i_rsvd : 55; | 2537 | uint64_t i_rsvd:55; |
| 2632 | } ii_ibct0_fld_s; | 2538 | } ii_ibct0_fld_s; |
| 2633 | } ii_ibct0_u_t; | 2539 | } ii_ibct0_u_t; |
| 2634 | 2540 | ||
| 2635 | |||
| 2636 | /************************************************************************ | 2541 | /************************************************************************ |
| 2637 | * * | 2542 | * * |
| 2638 | * This register contains the address to which the WINV is sent. * | 2543 | * This register contains the address to which the WINV is sent. * |
| 2639 | * This address has to be cache line aligned. * | 2544 | * This address has to be cache line aligned. * |
| 2640 | * * | 2545 | * * |
| 2641 | ************************************************************************/ | 2546 | ************************************************************************/ |
| 2642 | 2547 | ||
| 2643 | typedef union ii_ibna0_u { | 2548 | typedef union ii_ibna0_u { |
| 2644 | uint64_t ii_ibna0_regval; | 2549 | uint64_t ii_ibna0_regval; |
| 2645 | struct { | 2550 | struct { |
| 2646 | uint64_t i_rsvd_1 : 7; | 2551 | uint64_t i_rsvd_1:7; |
| 2647 | uint64_t i_addr : 42; | 2552 | uint64_t i_addr:42; |
| 2648 | uint64_t i_rsvd : 15; | 2553 | uint64_t i_rsvd:15; |
| 2649 | } ii_ibna0_fld_s; | 2554 | } ii_ibna0_fld_s; |
| 2650 | } ii_ibna0_u_t; | 2555 | } ii_ibna0_u_t; |
| 2651 | 2556 | ||
| 2652 | |||
| 2653 | /************************************************************************ | 2557 | /************************************************************************ |
| 2654 | * * | 2558 | * * |
| 2655 | * This register contains the programmable level as well as the node * | 2559 | * This register contains the programmable level as well as the node * |
| 2656 | * ID and PI unit of the processor to which the interrupt will be * | 2560 | * ID and PI unit of the processor to which the interrupt will be * |
| 2657 | * sent. * | 2561 | * sent. * |
| 2658 | * * | 2562 | * * |
| 2659 | ************************************************************************/ | 2563 | ************************************************************************/ |
| 2660 | 2564 | ||
| 2661 | typedef union ii_ibia0_u { | 2565 | typedef union ii_ibia0_u { |
| 2662 | uint64_t ii_ibia0_regval; | 2566 | uint64_t ii_ibia0_regval; |
| 2663 | struct { | 2567 | struct { |
| 2664 | uint64_t i_rsvd_2 : 1; | 2568 | uint64_t i_rsvd_2:1; |
| 2665 | uint64_t i_node_id : 11; | 2569 | uint64_t i_node_id:11; |
| 2666 | uint64_t i_rsvd_1 : 4; | 2570 | uint64_t i_rsvd_1:4; |
| 2667 | uint64_t i_level : 7; | 2571 | uint64_t i_level:7; |
| 2668 | uint64_t i_rsvd : 41; | 2572 | uint64_t i_rsvd:41; |
| 2669 | } ii_ibia0_fld_s; | 2573 | } ii_ibia0_fld_s; |
| 2670 | } ii_ibia0_u_t; | 2574 | } ii_ibia0_u_t; |
| 2671 | 2575 | ||
| 2672 | |||
| 2673 | /************************************************************************ | 2576 | /************************************************************************ |
| 2674 | * * | 2577 | * * |
| 2675 | * Description: This register is used to set up the length for a * | 2578 | * Description: This register is used to set up the length for a * |
| 2676 | * transfer and then to monitor the progress of that transfer. This * | 2579 | * transfer and then to monitor the progress of that transfer. This * |
| 2677 | * register needs to be initialized before a transfer is started. A * | 2580 | * register needs to be initialized before a transfer is started. A * |
| @@ -2682,63 +2585,60 @@ typedef union ii_ibia0_u { | |||
| 2682 | * transfer completes, hardware will clear the Busy bit. The length * | 2585 | * transfer completes, hardware will clear the Busy bit. The length * |
| 2683 | * field will also contain the number of cache lines left to be * | 2586 | * field will also contain the number of cache lines left to be * |
| 2684 | * transferred. * | 2587 | * transferred. * |
| 2685 | * * | 2588 | * * |
| 2686 | ************************************************************************/ | 2589 | ************************************************************************/ |
| 2687 | 2590 | ||
| 2688 | typedef union ii_ibls1_u { | 2591 | typedef union ii_ibls1_u { |
| 2689 | uint64_t ii_ibls1_regval; | 2592 | uint64_t ii_ibls1_regval; |
| 2690 | struct { | 2593 | struct { |
| 2691 | uint64_t i_length : 16; | 2594 | uint64_t i_length:16; |
| 2692 | uint64_t i_error : 1; | 2595 | uint64_t i_error:1; |
| 2693 | uint64_t i_rsvd_1 : 3; | 2596 | uint64_t i_rsvd_1:3; |
| 2694 | uint64_t i_busy : 1; | 2597 | uint64_t i_busy:1; |
| 2695 | uint64_t i_rsvd : 43; | 2598 | uint64_t i_rsvd:43; |
| 2696 | } ii_ibls1_fld_s; | 2599 | } ii_ibls1_fld_s; |
| 2697 | } ii_ibls1_u_t; | 2600 | } ii_ibls1_u_t; |
| 2698 | 2601 | ||
| 2699 | |||
| 2700 | /************************************************************************ | 2602 | /************************************************************************ |
| 2701 | * * | 2603 | * * |
| 2702 | * This register should be loaded before a transfer is started. The * | 2604 | * This register should be loaded before a transfer is started. The * |
| 2703 | * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * | 2605 | * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * |
| 2704 | * address as described in Section 1.3, Figure2 and Figure3. Since * | 2606 | * address as described in Section 1.3, Figure2 and Figure3. Since * |
| 2705 | * the bottom 7 bits of the address are always taken to be zero, BTE * | 2607 | * the bottom 7 bits of the address are always taken to be zero, BTE * |
| 2706 | * transfers are always cacheline-aligned. * | 2608 | * transfers are always cacheline-aligned. * |
| 2707 | * * | 2609 | * * |
| 2708 | ************************************************************************/ | 2610 | ************************************************************************/ |
| 2709 | 2611 | ||
| 2710 | typedef union ii_ibsa1_u { | 2612 | typedef union ii_ibsa1_u { |
| 2711 | uint64_t ii_ibsa1_regval; | 2613 | uint64_t ii_ibsa1_regval; |
| 2712 | struct { | 2614 | struct { |
| 2713 | uint64_t i_rsvd_1 : 7; | 2615 | uint64_t i_rsvd_1:7; |
| 2714 | uint64_t i_addr : 33; | 2616 | uint64_t i_addr:33; |
| 2715 | uint64_t i_rsvd : 24; | 2617 | uint64_t i_rsvd:24; |
| 2716 | } ii_ibsa1_fld_s; | 2618 | } ii_ibsa1_fld_s; |
| 2717 | } ii_ibsa1_u_t; | 2619 | } ii_ibsa1_u_t; |
| 2718 | 2620 | ||
| 2719 | |||
| 2720 | /************************************************************************ | 2621 | /************************************************************************ |
| 2721 | * * | 2622 | * * |
| 2722 | * This register should be loaded before a transfer is started. The * | 2623 | * This register should be loaded before a transfer is started. The * |
| 2723 | * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * | 2624 | * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * |
| 2724 | * address as described in Section 1.3, Figure2 and Figure3. Since * | 2625 | * address as described in Section 1.3, Figure2 and Figure3. Since * |
| 2725 | * the bottom 7 bits of the address are always taken to be zero, BTE * | 2626 | * the bottom 7 bits of the address are always taken to be zero, BTE * |
| 2726 | * transfers are always cacheline-aligned. * | 2627 | * transfers are always cacheline-aligned. * |
| 2727 | * * | 2628 | * * |
| 2728 | ************************************************************************/ | 2629 | ************************************************************************/ |
| 2729 | 2630 | ||
| 2730 | typedef union ii_ibda1_u { | 2631 | typedef union ii_ibda1_u { |
| 2731 | uint64_t ii_ibda1_regval; | 2632 | uint64_t ii_ibda1_regval; |
| 2732 | struct { | 2633 | struct { |
| 2733 | uint64_t i_rsvd_1 : 7; | 2634 | uint64_t i_rsvd_1:7; |
| 2734 | uint64_t i_addr : 33; | 2635 | uint64_t i_addr:33; |
| 2735 | uint64_t i_rsvd : 24; | 2636 | uint64_t i_rsvd:24; |
| 2736 | } ii_ibda1_fld_s; | 2637 | } ii_ibda1_fld_s; |
| 2737 | } ii_ibda1_u_t; | 2638 | } ii_ibda1_u_t; |
| 2738 | 2639 | ||
| 2739 | |||
| 2740 | /************************************************************************ | 2640 | /************************************************************************ |
| 2741 | * * | 2641 | * * |
| 2742 | * Writing to this register sets up the attributes of the transfer * | 2642 | * Writing to this register sets up the attributes of the transfer * |
| 2743 | * and initiates the transfer operation. Reading this register has * | 2643 | * and initiates the transfer operation. Reading this register has * |
| 2744 | * the side effect of terminating any transfer in progress. Note: * | 2644 | * the side effect of terminating any transfer in progress. Note: * |
| @@ -2746,61 +2646,58 @@ typedef union ii_ibda1_u { | |||
| 2746 | * other BTE. If a BTE stream has to be stopped (due to error * | 2646 | * other BTE. If a BTE stream has to be stopped (due to error * |
| 2747 | * handling for example), both BTE streams should be stopped and * | 2647 | * handling for example), both BTE streams should be stopped and * |
| 2748 | * their transfers discarded. * | 2648 | * their transfers discarded. * |
| 2749 | * * | 2649 | * * |
| 2750 | ************************************************************************/ | 2650 | ************************************************************************/ |
| 2751 | 2651 | ||
| 2752 | typedef union ii_ibct1_u { | 2652 | typedef union ii_ibct1_u { |
| 2753 | uint64_t ii_ibct1_regval; | 2653 | uint64_t ii_ibct1_regval; |
| 2754 | struct { | 2654 | struct { |
| 2755 | uint64_t i_zerofill : 1; | 2655 | uint64_t i_zerofill:1; |
| 2756 | uint64_t i_rsvd_2 : 3; | 2656 | uint64_t i_rsvd_2:3; |
| 2757 | uint64_t i_notify : 1; | 2657 | uint64_t i_notify:1; |
| 2758 | uint64_t i_rsvd_1 : 3; | 2658 | uint64_t i_rsvd_1:3; |
| 2759 | uint64_t i_poison : 1; | 2659 | uint64_t i_poison:1; |
| 2760 | uint64_t i_rsvd : 55; | 2660 | uint64_t i_rsvd:55; |
| 2761 | } ii_ibct1_fld_s; | 2661 | } ii_ibct1_fld_s; |
| 2762 | } ii_ibct1_u_t; | 2662 | } ii_ibct1_u_t; |
| 2763 | 2663 | ||
| 2764 | |||
| 2765 | /************************************************************************ | 2664 | /************************************************************************ |
| 2766 | * * | 2665 | * * |
| 2767 | * This register contains the address to which the WINV is sent. * | 2666 | * This register contains the address to which the WINV is sent. * |
| 2768 | * This address has to be cache line aligned. * | 2667 | * This address has to be cache line aligned. * |
| 2769 | * * | 2668 | * * |
| 2770 | ************************************************************************/ | 2669 | ************************************************************************/ |
| 2771 | 2670 | ||
| 2772 | typedef union ii_ibna1_u { | 2671 | typedef union ii_ibna1_u { |
| 2773 | uint64_t ii_ibna1_regval; | 2672 | uint64_t ii_ibna1_regval; |
| 2774 | struct { | 2673 | struct { |
| 2775 | uint64_t i_rsvd_1 : 7; | 2674 | uint64_t i_rsvd_1:7; |
| 2776 | uint64_t i_addr : 33; | 2675 | uint64_t i_addr:33; |
| 2777 | uint64_t i_rsvd : 24; | 2676 | uint64_t i_rsvd:24; |
| 2778 | } ii_ibna1_fld_s; | 2677 | } ii_ibna1_fld_s; |
| 2779 | } ii_ibna1_u_t; | 2678 | } ii_ibna1_u_t; |
| 2780 | 2679 | ||
| 2781 | |||
| 2782 | /************************************************************************ | 2680 | /************************************************************************ |
| 2783 | * * | 2681 | * * |
| 2784 | * This register contains the programmable level as well as the node * | 2682 | * This register contains the programmable level as well as the node * |
| 2785 | * ID and PI unit of the processor to which the interrupt will be * | 2683 | * ID and PI unit of the processor to which the interrupt will be * |
| 2786 | * sent. * | 2684 | * sent. * |
| 2787 | * * | 2685 | * * |
| 2788 | ************************************************************************/ | 2686 | ************************************************************************/ |
| 2789 | 2687 | ||
| 2790 | typedef union ii_ibia1_u { | 2688 | typedef union ii_ibia1_u { |
| 2791 | uint64_t ii_ibia1_regval; | 2689 | uint64_t ii_ibia1_regval; |
| 2792 | struct { | 2690 | struct { |
| 2793 | uint64_t i_pi_id : 1; | 2691 | uint64_t i_pi_id:1; |
| 2794 | uint64_t i_node_id : 8; | 2692 | uint64_t i_node_id:8; |
| 2795 | uint64_t i_rsvd_1 : 7; | 2693 | uint64_t i_rsvd_1:7; |
| 2796 | uint64_t i_level : 7; | 2694 | uint64_t i_level:7; |
| 2797 | uint64_t i_rsvd : 41; | 2695 | uint64_t i_rsvd:41; |
| 2798 | } ii_ibia1_fld_s; | 2696 | } ii_ibia1_fld_s; |
| 2799 | } ii_ibia1_u_t; | 2697 | } ii_ibia1_u_t; |
| 2800 | 2698 | ||
| 2801 | |||
| 2802 | /************************************************************************ | 2699 | /************************************************************************ |
| 2803 | * * | 2700 | * * |
| 2804 | * This register defines the resources that feed information into * | 2701 | * This register defines the resources that feed information into * |
| 2805 | * the two performance counters located in the IO Performance * | 2702 | * the two performance counters located in the IO Performance * |
| 2806 | * Profiling Register. There are 17 different quantities that can be * | 2703 | * Profiling Register. There are 17 different quantities that can be * |
| @@ -2811,133 +2708,129 @@ typedef union ii_ibia1_u { | |||
| 2811 | * other is available from the other performance counter. Hence, the * | 2708 | * other is available from the other performance counter. Hence, the * |
| 2812 | * II supports all 17*16=272 possible combinations of quantities to * | 2709 | * II supports all 17*16=272 possible combinations of quantities to * |
| 2813 | * measure. * | 2710 | * measure. * |
| 2814 | * * | 2711 | * * |
| 2815 | ************************************************************************/ | 2712 | ************************************************************************/ |
| 2816 | 2713 | ||
| 2817 | typedef union ii_ipcr_u { | 2714 | typedef union ii_ipcr_u { |
| 2818 | uint64_t ii_ipcr_regval; | 2715 | uint64_t ii_ipcr_regval; |
| 2819 | struct { | 2716 | struct { |
| 2820 | uint64_t i_ippr0_c : 4; | 2717 | uint64_t i_ippr0_c:4; |
| 2821 | uint64_t i_ippr1_c : 4; | 2718 | uint64_t i_ippr1_c:4; |
| 2822 | uint64_t i_icct : 8; | 2719 | uint64_t i_icct:8; |
| 2823 | uint64_t i_rsvd : 48; | 2720 | uint64_t i_rsvd:48; |
| 2824 | } ii_ipcr_fld_s; | 2721 | } ii_ipcr_fld_s; |
| 2825 | } ii_ipcr_u_t; | 2722 | } ii_ipcr_u_t; |
| 2826 | 2723 | ||
| 2827 | |||
| 2828 | /************************************************************************ | 2724 | /************************************************************************ |
| 2829 | * * | 2725 | * * |
| 2830 | * * | 2726 | * * |
| 2831 | * * | 2727 | * * |
| 2832 | ************************************************************************/ | 2728 | ************************************************************************/ |
| 2833 | 2729 | ||
| 2834 | typedef union ii_ippr_u { | 2730 | typedef union ii_ippr_u { |
| 2835 | uint64_t ii_ippr_regval; | 2731 | uint64_t ii_ippr_regval; |
| 2836 | struct { | 2732 | struct { |
| 2837 | uint64_t i_ippr0 : 32; | 2733 | uint64_t i_ippr0:32; |
| 2838 | uint64_t i_ippr1 : 32; | 2734 | uint64_t i_ippr1:32; |
| 2839 | } ii_ippr_fld_s; | 2735 | } ii_ippr_fld_s; |
| 2840 | } ii_ippr_u_t; | 2736 | } ii_ippr_u_t; |
| 2841 | 2737 | ||
| 2842 | 2738 | /************************************************************************ | |
| 2843 | 2739 | * * | |
| 2844 | /************************************************************************** | 2740 | * The following defines which were not formed into structures are * |
| 2845 | * * | 2741 | * probably indentical to another register, and the name of the * |
| 2846 | * The following defines which were not formed into structures are * | 2742 | * register is provided against each of these registers. This * |
| 2847 | * probably indentical to another register, and the name of the * | 2743 | * information needs to be checked carefully * |
| 2848 | * register is provided against each of these registers. This * | 2744 | * * |
| 2849 | * information needs to be checked carefully * | 2745 | * IIO_ICRB1_A IIO_ICRB0_A * |
| 2850 | * * | 2746 | * IIO_ICRB1_B IIO_ICRB0_B * |
| 2851 | * IIO_ICRB1_A IIO_ICRB0_A * | 2747 | * IIO_ICRB1_C IIO_ICRB0_C * |
| 2852 | * IIO_ICRB1_B IIO_ICRB0_B * | 2748 | * IIO_ICRB1_D IIO_ICRB0_D * |
| 2853 | * IIO_ICRB1_C IIO_ICRB0_C * | 2749 | * IIO_ICRB1_E IIO_ICRB0_E * |
| 2854 | * IIO_ICRB1_D IIO_ICRB0_D * | 2750 | * IIO_ICRB2_A IIO_ICRB0_A * |
| 2855 | * IIO_ICRB1_E IIO_ICRB0_E * | 2751 | * IIO_ICRB2_B IIO_ICRB0_B * |
| 2856 | * IIO_ICRB2_A IIO_ICRB0_A * | 2752 | * IIO_ICRB2_C IIO_ICRB0_C * |
| 2857 | * IIO_ICRB2_B IIO_ICRB0_B * | 2753 | * IIO_ICRB2_D IIO_ICRB0_D * |
| 2858 | * IIO_ICRB2_C IIO_ICRB0_C * | 2754 | * IIO_ICRB2_E IIO_ICRB0_E * |
| 2859 | * IIO_ICRB2_D IIO_ICRB0_D * | 2755 | * IIO_ICRB3_A IIO_ICRB0_A * |
| 2860 | * IIO_ICRB2_E IIO_ICRB0_E * | 2756 | * IIO_ICRB3_B IIO_ICRB0_B * |
| 2861 | * IIO_ICRB3_A IIO_ICRB0_A * | 2757 | * IIO_ICRB3_C IIO_ICRB0_C * |
| 2862 | * IIO_ICRB3_B IIO_ICRB0_B * | 2758 | * IIO_ICRB3_D IIO_ICRB0_D * |
| 2863 | * IIO_ICRB3_C IIO_ICRB0_C * | 2759 | * IIO_ICRB3_E IIO_ICRB0_E * |
| 2864 | * IIO_ICRB3_D IIO_ICRB0_D * | 2760 | * IIO_ICRB4_A IIO_ICRB0_A * |
| 2865 | * IIO_ICRB3_E IIO_ICRB0_E * | 2761 | * IIO_ICRB4_B IIO_ICRB0_B * |
| 2866 | * IIO_ICRB4_A IIO_ICRB0_A * | 2762 | * IIO_ICRB4_C IIO_ICRB0_C * |
| 2867 | * IIO_ICRB4_B IIO_ICRB0_B * | 2763 | * IIO_ICRB4_D IIO_ICRB0_D * |
| 2868 | * IIO_ICRB4_C IIO_ICRB0_C * | 2764 | * IIO_ICRB4_E IIO_ICRB0_E * |
| 2869 | * IIO_ICRB4_D IIO_ICRB0_D * | 2765 | * IIO_ICRB5_A IIO_ICRB0_A * |
| 2870 | * IIO_ICRB4_E IIO_ICRB0_E * | 2766 | * IIO_ICRB5_B IIO_ICRB0_B * |
| 2871 | * IIO_ICRB5_A IIO_ICRB0_A * | 2767 | * IIO_ICRB5_C IIO_ICRB0_C * |
| 2872 | * IIO_ICRB5_B IIO_ICRB0_B * | 2768 | * IIO_ICRB5_D IIO_ICRB0_D * |
| 2873 | * IIO_ICRB5_C IIO_ICRB0_C * | 2769 | * IIO_ICRB5_E IIO_ICRB0_E * |
| 2874 | * IIO_ICRB5_D IIO_ICRB0_D * | 2770 | * IIO_ICRB6_A IIO_ICRB0_A * |
| 2875 | * IIO_ICRB5_E IIO_ICRB0_E * | 2771 | * IIO_ICRB6_B IIO_ICRB0_B * |
| 2876 | * IIO_ICRB6_A IIO_ICRB0_A * | 2772 | * IIO_ICRB6_C IIO_ICRB0_C * |
| 2877 | * IIO_ICRB6_B IIO_ICRB0_B * | 2773 | * IIO_ICRB6_D IIO_ICRB0_D * |
| 2878 | * IIO_ICRB6_C IIO_ICRB0_C * | 2774 | * IIO_ICRB6_E IIO_ICRB0_E * |
| 2879 | * IIO_ICRB6_D IIO_ICRB0_D * | 2775 | * IIO_ICRB7_A IIO_ICRB0_A * |
| 2880 | * IIO_ICRB6_E IIO_ICRB0_E * | 2776 | * IIO_ICRB7_B IIO_ICRB0_B * |
| 2881 | * IIO_ICRB7_A IIO_ICRB0_A * | 2777 | * IIO_ICRB7_C IIO_ICRB0_C * |
| 2882 | * IIO_ICRB7_B IIO_ICRB0_B * | 2778 | * IIO_ICRB7_D IIO_ICRB0_D * |
| 2883 | * IIO_ICRB7_C IIO_ICRB0_C * | 2779 | * IIO_ICRB7_E IIO_ICRB0_E * |
| 2884 | * IIO_ICRB7_D IIO_ICRB0_D * | 2780 | * IIO_ICRB8_A IIO_ICRB0_A * |
| 2885 | * IIO_ICRB7_E IIO_ICRB0_E * | 2781 | * IIO_ICRB8_B IIO_ICRB0_B * |
| 2886 | * IIO_ICRB8_A IIO_ICRB0_A * | 2782 | * IIO_ICRB8_C IIO_ICRB0_C * |
| 2887 | * IIO_ICRB8_B IIO_ICRB0_B * | 2783 | * IIO_ICRB8_D IIO_ICRB0_D * |
| 2888 | * IIO_ICRB8_C IIO_ICRB0_C * | 2784 | * IIO_ICRB8_E IIO_ICRB0_E * |
| 2889 | * IIO_ICRB8_D IIO_ICRB0_D * | 2785 | * IIO_ICRB9_A IIO_ICRB0_A * |
| 2890 | * IIO_ICRB8_E IIO_ICRB0_E * | 2786 | * IIO_ICRB9_B IIO_ICRB0_B * |
| 2891 | * IIO_ICRB9_A IIO_ICRB0_A * | 2787 | * IIO_ICRB9_C IIO_ICRB0_C * |
| 2892 | * IIO_ICRB9_B IIO_ICRB0_B * | 2788 | * IIO_ICRB9_D IIO_ICRB0_D * |
| 2893 | * IIO_ICRB9_C IIO_ICRB0_C * | 2789 | * IIO_ICRB9_E IIO_ICRB0_E * |
| 2894 | * IIO_ICRB9_D IIO_ICRB0_D * | 2790 | * IIO_ICRBA_A IIO_ICRB0_A * |
| 2895 | * IIO_ICRB9_E IIO_ICRB0_E * | 2791 | * IIO_ICRBA_B IIO_ICRB0_B * |
| 2896 | * IIO_ICRBA_A IIO_ICRB0_A * | 2792 | * IIO_ICRBA_C IIO_ICRB0_C * |
| 2897 | * IIO_ICRBA_B IIO_ICRB0_B * | 2793 | * IIO_ICRBA_D IIO_ICRB0_D * |
| 2898 | * IIO_ICRBA_C IIO_ICRB0_C * | 2794 | * IIO_ICRBA_E IIO_ICRB0_E * |
| 2899 | * IIO_ICRBA_D IIO_ICRB0_D * | 2795 | * IIO_ICRBB_A IIO_ICRB0_A * |
| 2900 | * IIO_ICRBA_E IIO_ICRB0_E * | 2796 | * IIO_ICRBB_B IIO_ICRB0_B * |
| 2901 | * IIO_ICRBB_A IIO_ICRB0_A * | 2797 | * IIO_ICRBB_C IIO_ICRB0_C * |
| 2902 | * IIO_ICRBB_B IIO_ICRB0_B * | 2798 | * IIO_ICRBB_D IIO_ICRB0_D * |
| 2903 | * IIO_ICRBB_C IIO_ICRB0_C * | 2799 | * IIO_ICRBB_E IIO_ICRB0_E * |
| 2904 | * IIO_ICRBB_D IIO_ICRB0_D * | 2800 | * IIO_ICRBC_A IIO_ICRB0_A * |
| 2905 | * IIO_ICRBB_E IIO_ICRB0_E * | 2801 | * IIO_ICRBC_B IIO_ICRB0_B * |
| 2906 | * IIO_ICRBC_A IIO_ICRB0_A * | 2802 | * IIO_ICRBC_C IIO_ICRB0_C * |
| 2907 | * IIO_ICRBC_B IIO_ICRB0_B * | 2803 | * IIO_ICRBC_D IIO_ICRB0_D * |
| 2908 | * IIO_ICRBC_C IIO_ICRB0_C * | 2804 | * IIO_ICRBC_E IIO_ICRB0_E * |
| 2909 | * IIO_ICRBC_D IIO_ICRB0_D * | 2805 | * IIO_ICRBD_A IIO_ICRB0_A * |
| 2910 | * IIO_ICRBC_E IIO_ICRB0_E * | 2806 | * IIO_ICRBD_B IIO_ICRB0_B * |
| 2911 | * IIO_ICRBD_A IIO_ICRB0_A * | 2807 | * IIO_ICRBD_C IIO_ICRB0_C * |
| 2912 | * IIO_ICRBD_B IIO_ICRB0_B * | 2808 | * IIO_ICRBD_D IIO_ICRB0_D * |
| 2913 | * IIO_ICRBD_C IIO_ICRB0_C * | 2809 | * IIO_ICRBD_E IIO_ICRB0_E * |
| 2914 | * IIO_ICRBD_D IIO_ICRB0_D * | 2810 | * IIO_ICRBE_A IIO_ICRB0_A * |
| 2915 | * IIO_ICRBD_E IIO_ICRB0_E * | 2811 | * IIO_ICRBE_B IIO_ICRB0_B * |
| 2916 | * IIO_ICRBE_A IIO_ICRB0_A * | 2812 | * IIO_ICRBE_C IIO_ICRB0_C * |
| 2917 | * IIO_ICRBE_B IIO_ICRB0_B * | 2813 | * IIO_ICRBE_D IIO_ICRB0_D * |
| 2918 | * IIO_ICRBE_C IIO_ICRB0_C * | 2814 | * IIO_ICRBE_E IIO_ICRB0_E * |
| 2919 | * IIO_ICRBE_D IIO_ICRB0_D * | 2815 | * * |
| 2920 | * IIO_ICRBE_E IIO_ICRB0_E * | 2816 | ************************************************************************/ |
| 2921 | * * | ||
| 2922 | **************************************************************************/ | ||
| 2923 | |||
| 2924 | 2817 | ||
| 2925 | /* | 2818 | /* |
| 2926 | * Slightly friendlier names for some common registers. | 2819 | * Slightly friendlier names for some common registers. |
| 2927 | */ | 2820 | */ |
| 2928 | #define IIO_WIDGET IIO_WID /* Widget identification */ | 2821 | #define IIO_WIDGET IIO_WID /* Widget identification */ |
| 2929 | #define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */ | 2822 | #define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */ |
| 2930 | #define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */ | 2823 | #define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */ |
| 2931 | #define IIO_PROTECT IIO_ILAPR /* IO interface protection */ | 2824 | #define IIO_PROTECT IIO_ILAPR /* IO interface protection */ |
| 2932 | #define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */ | 2825 | #define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */ |
| 2933 | #define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */ | 2826 | #define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */ |
| 2934 | #define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */ | 2827 | #define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */ |
| 2935 | #define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */ | 2828 | #define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */ |
| 2936 | #define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */ | 2829 | #define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */ |
| 2937 | #define IIO_LLP_LOG IIO_ILLR /* LLP log */ | 2830 | #define IIO_LLP_LOG IIO_ILLR /* LLP log */ |
| 2938 | #define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/ | 2831 | #define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout */ |
| 2939 | #define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */ | 2832 | #define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */ |
| 2940 | #define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */ | 2833 | #define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */ |
| 2941 | #define IIO_IGFX_0 IIO_IGFX0 | 2834 | #define IIO_IGFX_0 IIO_IGFX0 |
| 2942 | #define IIO_IGFX_1 IIO_IGFX1 | 2835 | #define IIO_IGFX_1 IIO_IGFX1 |
| 2943 | #define IIO_IBCT_0 IIO_IBCT0 | 2836 | #define IIO_IBCT_0 IIO_IBCT0 |
| @@ -2957,12 +2850,12 @@ typedef union ii_ippr_u { | |||
| 2957 | #define IIO_PRTE_A(_x) (IIO_IPRTE0_A + (8 * (_x))) | 2850 | #define IIO_PRTE_A(_x) (IIO_IPRTE0_A + (8 * (_x))) |
| 2958 | #define IIO_PRTE_B(_x) (IIO_IPRTE0_B + (8 * (_x))) | 2851 | #define IIO_PRTE_B(_x) (IIO_IPRTE0_B + (8 * (_x))) |
| 2959 | #define IIO_NUM_PRTES 8 /* Total number of PRB table entries */ | 2852 | #define IIO_NUM_PRTES 8 /* Total number of PRB table entries */ |
| 2960 | #define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */ | 2853 | #define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */ |
| 2961 | #define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */ | 2854 | #define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */ |
| 2962 | 2855 | ||
| 2963 | #define IIO_NUM_IPRBS (9) | 2856 | #define IIO_NUM_IPRBS 9 |
| 2964 | 2857 | ||
| 2965 | #define IIO_LLP_CSR_IS_UP 0x00002000 | 2858 | #define IIO_LLP_CSR_IS_UP 0x00002000 |
| 2966 | #define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000 | 2859 | #define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000 |
| 2967 | #define IIO_LLP_CSR_LLP_STAT_SHFT 12 | 2860 | #define IIO_LLP_CSR_LLP_STAT_SHFT 12 |
| 2968 | 2861 | ||
| @@ -2970,30 +2863,29 @@ typedef union ii_ippr_u { | |||
| 2970 | #define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */ | 2863 | #define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */ |
| 2971 | 2864 | ||
| 2972 | /* key to IIO_PROTECT_OVRRD */ | 2865 | /* key to IIO_PROTECT_OVRRD */ |
| 2973 | #define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */ | 2866 | #define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */ |
| 2974 | 2867 | ||
| 2975 | /* BTE register names */ | 2868 | /* BTE register names */ |
| 2976 | #define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */ | 2869 | #define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */ |
| 2977 | #define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */ | 2870 | #define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */ |
| 2978 | #define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */ | 2871 | #define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */ |
| 2979 | #define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */ | 2872 | #define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */ |
| 2980 | #define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */ | 2873 | #define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */ |
| 2981 | #define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */ | 2874 | #define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */ |
| 2982 | #define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */ | 2875 | #define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */ |
| 2983 | #define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */ | 2876 | #define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */ |
| 2984 | 2877 | ||
| 2985 | /* BTE register offsets from base */ | 2878 | /* BTE register offsets from base */ |
| 2986 | #define BTEOFF_STAT 0 | 2879 | #define BTEOFF_STAT 0 |
| 2987 | #define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0) | 2880 | #define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0) |
| 2988 | #define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0) | 2881 | #define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0) |
| 2989 | #define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0) | 2882 | #define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0) |
| 2990 | #define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0) | 2883 | #define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0) |
| 2991 | #define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0) | 2884 | #define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0) |
| 2992 | |||
| 2993 | 2885 | ||
| 2994 | /* names used in shub diags */ | 2886 | /* names used in shub diags */ |
| 2995 | #define IIO_BASE_BTE0 IIO_IBLS_0 | 2887 | #define IIO_BASE_BTE0 IIO_IBLS_0 |
| 2996 | #define IIO_BASE_BTE1 IIO_IBLS_1 | 2888 | #define IIO_BASE_BTE1 IIO_IBLS_1 |
| 2997 | 2889 | ||
| 2998 | /* | 2890 | /* |
| 2999 | * Macro which takes the widget number, and returns the | 2891 | * Macro which takes the widget number, and returns the |
| @@ -3001,10 +2893,9 @@ typedef union ii_ippr_u { | |||
| 3001 | * value _x is expected to be a widget number in the range | 2893 | * value _x is expected to be a widget number in the range |
| 3002 | * 0, 8 - 0xF | 2894 | * 0, 8 - 0xF |
| 3003 | */ | 2895 | */ |
| 3004 | #define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ | 2896 | #define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ |
| 3005 | (_x) : \ | 2897 | (_x) : \ |
| 3006 | (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) | 2898 | (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) |
| 3007 | |||
| 3008 | 2899 | ||
| 3009 | /* GFX Flow Control Node/Widget Register */ | 2900 | /* GFX Flow Control Node/Widget Register */ |
| 3010 | #define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */ | 2901 | #define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */ |
| @@ -3025,7 +2916,6 @@ typedef union ii_ippr_u { | |||
| 3025 | (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \ | 2916 | (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \ |
| 3026 | (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT)) | 2917 | (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT)) |
| 3027 | 2918 | ||
| 3028 | |||
| 3029 | /* Scratch registers (all bits available) */ | 2919 | /* Scratch registers (all bits available) */ |
| 3030 | #define IIO_SCRATCH_REG0 IIO_ISCR0 | 2920 | #define IIO_SCRATCH_REG0 IIO_ISCR0 |
| 3031 | #define IIO_SCRATCH_REG1 IIO_ISCR1 | 2921 | #define IIO_SCRATCH_REG1 IIO_ISCR1 |
| @@ -3046,21 +2936,21 @@ typedef union ii_ippr_u { | |||
| 3046 | #define IIO_SCRATCH_BIT1_0 0x0000000000000001UL | 2936 | #define IIO_SCRATCH_BIT1_0 0x0000000000000001UL |
| 3047 | #define IIO_SCRATCH_BIT1_1 0x0000000000000002UL | 2937 | #define IIO_SCRATCH_BIT1_1 0x0000000000000002UL |
| 3048 | /* IO Translation Table Entries */ | 2938 | /* IO Translation Table Entries */ |
| 3049 | #define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */ | 2939 | #define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */ |
| 3050 | /* Hw manuals number them 1..7! */ | 2940 | /* Hw manuals number them 1..7! */ |
| 3051 | /* | 2941 | /* |
| 3052 | * IIO_IMEM Register fields. | 2942 | * IIO_IMEM Register fields. |
| 3053 | */ | 2943 | */ |
| 3054 | #define IIO_IMEM_W0ESD 0x1UL /* Widget 0 shut down due to error */ | 2944 | #define IIO_IMEM_W0ESD 0x1UL /* Widget 0 shut down due to error */ |
| 3055 | #define IIO_IMEM_B0ESD (1UL << 4) /* BTE 0 shut down due to error */ | 2945 | #define IIO_IMEM_B0ESD (1UL << 4) /* BTE 0 shut down due to error */ |
| 3056 | #define IIO_IMEM_B1ESD (1UL << 8) /* BTE 1 Shut down due to error */ | 2946 | #define IIO_IMEM_B1ESD (1UL << 8) /* BTE 1 Shut down due to error */ |
| 3057 | 2947 | ||
| 3058 | /* | 2948 | /* |
| 3059 | * As a permanent workaround for a bug in the PI side of the shub, we've | 2949 | * As a permanent workaround for a bug in the PI side of the shub, we've |
| 3060 | * redefined big window 7 as small window 0. | 2950 | * redefined big window 7 as small window 0. |
| 3061 | XXX does this still apply for SN1?? | 2951 | XXX does this still apply for SN1?? |
| 3062 | */ | 2952 | */ |
| 3063 | #define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) | 2953 | #define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) |
| 3064 | 2954 | ||
| 3065 | /* | 2955 | /* |
| 3066 | * Use the top big window as a surrogate for the first small window | 2956 | * Use the top big window as a surrogate for the first small window |
| @@ -3071,11 +2961,11 @@ typedef union ii_ippr_u { | |||
| 3071 | 2961 | ||
| 3072 | /* | 2962 | /* |
| 3073 | * CRB manipulation macros | 2963 | * CRB manipulation macros |
| 3074 | * The CRB macros are slightly complicated, since there are up to | 2964 | * The CRB macros are slightly complicated, since there are up to |
| 3075 | * four registers associated with each CRB entry. | 2965 | * four registers associated with each CRB entry. |
| 3076 | */ | 2966 | */ |
| 3077 | #define IIO_NUM_CRBS 15 /* Number of CRBs */ | 2967 | #define IIO_NUM_CRBS 15 /* Number of CRBs */ |
| 3078 | #define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */ | 2968 | #define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */ |
| 3079 | #define IIO_ICRB_OFFSET 8 | 2969 | #define IIO_ICRB_OFFSET 8 |
| 3080 | #define IIO_ICRB_0 IIO_ICRB0_A | 2970 | #define IIO_ICRB_0 IIO_ICRB0_A |
| 3081 | #define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */ | 2971 | #define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */ |
| @@ -3083,43 +2973,43 @@ typedef union ii_ippr_u { | |||
| 3083 | #define IIO_FIRST_PC_ENTRY 12 | 2973 | #define IIO_FIRST_PC_ENTRY 12 |
| 3084 | */ | 2974 | */ |
| 3085 | 2975 | ||
| 3086 | #define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x)))) | 2976 | #define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x)))) |
| 3087 | #define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)) | 2977 | #define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)) |
| 3088 | #define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)) | 2978 | #define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)) |
| 3089 | #define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)) | 2979 | #define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)) |
| 3090 | #define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET)) | 2980 | #define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET)) |
| 3091 | 2981 | ||
| 3092 | #define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7) | 2982 | #define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7) |
| 3093 | 2983 | ||
| 3094 | /* | 2984 | /* |
| 3095 | * values for "ecode" field | 2985 | * values for "ecode" field |
| 3096 | */ | 2986 | */ |
| 3097 | #define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */ | 2987 | #define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */ |
| 3098 | #define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */ | 2988 | #define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */ |
| 3099 | #define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access | 2989 | #define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access |
| 3100 | * e.g. WINV to a Read only line. */ | 2990 | * e.g. WINV to a Read only line. */ |
| 3101 | #define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */ | 2991 | #define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */ |
| 3102 | #define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */ | 2992 | #define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */ |
| 3103 | #define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */ | 2993 | #define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */ |
| 3104 | #define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */ | 2994 | #define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */ |
| 3105 | #define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */ | 2995 | #define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */ |
| 3106 | 2996 | ||
| 3107 | /* | 2997 | /* |
| 3108 | * Values for field imsgtype | 2998 | * Values for field imsgtype |
| 3109 | */ | 2999 | */ |
| 3110 | #define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */ | 3000 | #define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */ |
| 3111 | #define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */ | 3001 | #define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */ |
| 3112 | #define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */ | 3002 | #define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */ |
| 3113 | #define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */ | 3003 | #define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */ |
| 3114 | 3004 | ||
| 3115 | /* | 3005 | /* |
| 3116 | * values for field initiator. | 3006 | * values for field initiator. |
| 3117 | */ | 3007 | */ |
| 3118 | #define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */ | 3008 | #define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */ |
| 3119 | #define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */ | 3009 | #define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */ |
| 3120 | #define IIO_ICRB_INIT_SN1NET 0x2 /* Message originated in SN1net */ | 3010 | #define IIO_ICRB_INIT_SN1NET 0x2 /* Message originated in SN1net */ |
| 3121 | #define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */ | 3011 | #define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */ |
| 3122 | #define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */ | 3012 | #define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */ |
| 3123 | 3013 | ||
| 3124 | /* | 3014 | /* |
| 3125 | * Number of credits Hub widget has while sending req/response to | 3015 | * Number of credits Hub widget has while sending req/response to |
| @@ -3127,8 +3017,8 @@ typedef union ii_ippr_u { | |||
| 3127 | * Value of 3 is required by Xbow 1.1 | 3017 | * Value of 3 is required by Xbow 1.1 |
| 3128 | * We may be able to increase this to 4 with Xbow 1.2. | 3018 | * We may be able to increase this to 4 with Xbow 1.2. |
| 3129 | */ | 3019 | */ |
| 3130 | #define HUBII_XBOW_CREDIT 3 | 3020 | #define HUBII_XBOW_CREDIT 3 |
| 3131 | #define HUBII_XBOW_REV2_CREDIT 4 | 3021 | #define HUBII_XBOW_REV2_CREDIT 4 |
| 3132 | 3022 | ||
| 3133 | /* | 3023 | /* |
| 3134 | * Number of credits that xtalk devices should use when communicating | 3024 | * Number of credits that xtalk devices should use when communicating |
| @@ -3159,28 +3049,28 @@ typedef union ii_ippr_u { | |||
| 3159 | */ | 3049 | */ |
| 3160 | 3050 | ||
| 3161 | #define IIO_ICMR_CRB_VLD_SHFT 20 | 3051 | #define IIO_ICMR_CRB_VLD_SHFT 20 |
| 3162 | #define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT) | 3052 | #define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT) |
| 3163 | 3053 | ||
| 3164 | #define IIO_ICMR_FC_CNT_SHFT 16 | 3054 | #define IIO_ICMR_FC_CNT_SHFT 16 |
| 3165 | #define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT) | 3055 | #define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT) |
| 3166 | 3056 | ||
| 3167 | #define IIO_ICMR_C_CNT_SHFT 4 | 3057 | #define IIO_ICMR_C_CNT_SHFT 4 |
| 3168 | #define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT) | 3058 | #define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT) |
| 3169 | 3059 | ||
| 3170 | #define IIO_ICMR_PRECISE (1UL << 52) | 3060 | #define IIO_ICMR_PRECISE (1UL << 52) |
| 3171 | #define IIO_ICMR_CLR_RPPD (1UL << 13) | 3061 | #define IIO_ICMR_CLR_RPPD (1UL << 13) |
| 3172 | #define IIO_ICMR_CLR_RQPD (1UL << 12) | 3062 | #define IIO_ICMR_CLR_RQPD (1UL << 12) |
| 3173 | 3063 | ||
| 3174 | /* | 3064 | /* |
| 3175 | * IIO PIO Deallocation register field masks : (IIO_IPDR) | 3065 | * IIO PIO Deallocation register field masks : (IIO_IPDR) |
| 3176 | XXX present but not needed in bedrock? See the manual. | 3066 | XXX present but not needed in bedrock? See the manual. |
| 3177 | */ | 3067 | */ |
| 3178 | #define IIO_IPDR_PND (1 << 4) | 3068 | #define IIO_IPDR_PND (1 << 4) |
| 3179 | 3069 | ||
| 3180 | /* | 3070 | /* |
| 3181 | * IIO CRB deallocation register field masks: (IIO_ICDR) | 3071 | * IIO CRB deallocation register field masks: (IIO_ICDR) |
| 3182 | */ | 3072 | */ |
| 3183 | #define IIO_ICDR_PND (1 << 4) | 3073 | #define IIO_ICDR_PND (1 << 4) |
| 3184 | 3074 | ||
| 3185 | /* | 3075 | /* |
| 3186 | * IO BTE Length/Status (IIO_IBLS) register bit field definitions | 3076 | * IO BTE Length/Status (IIO_IBLS) register bit field definitions |
| @@ -3223,35 +3113,35 @@ typedef union ii_ippr_u { | |||
| 3223 | /* | 3113 | /* |
| 3224 | * IO Error Clear register bit field definitions | 3114 | * IO Error Clear register bit field definitions |
| 3225 | */ | 3115 | */ |
| 3226 | #define IECLR_PI1_FWD_INT (1UL << 31) /* clear PI1_FORWARD_INT in iidsr */ | 3116 | #define IECLR_PI1_FWD_INT (1UL << 31) /* clear PI1_FORWARD_INT in iidsr */ |
| 3227 | #define IECLR_PI0_FWD_INT (1UL << 30) /* clear PI0_FORWARD_INT in iidsr */ | 3117 | #define IECLR_PI0_FWD_INT (1UL << 30) /* clear PI0_FORWARD_INT in iidsr */ |
| 3228 | #define IECLR_SPUR_RD_HDR (1UL << 29) /* clear valid bit in ixss reg */ | 3118 | #define IECLR_SPUR_RD_HDR (1UL << 29) /* clear valid bit in ixss reg */ |
| 3229 | #define IECLR_BTE1 (1UL << 18) /* clear bte error 1 */ | 3119 | #define IECLR_BTE1 (1UL << 18) /* clear bte error 1 */ |
| 3230 | #define IECLR_BTE0 (1UL << 17) /* clear bte error 0 */ | 3120 | #define IECLR_BTE0 (1UL << 17) /* clear bte error 0 */ |
| 3231 | #define IECLR_CRAZY (1UL << 16) /* clear crazy bit in wstat reg */ | 3121 | #define IECLR_CRAZY (1UL << 16) /* clear crazy bit in wstat reg */ |
| 3232 | #define IECLR_PRB_F (1UL << 15) /* clear err bit in PRB_F reg */ | 3122 | #define IECLR_PRB_F (1UL << 15) /* clear err bit in PRB_F reg */ |
| 3233 | #define IECLR_PRB_E (1UL << 14) /* clear err bit in PRB_E reg */ | 3123 | #define IECLR_PRB_E (1UL << 14) /* clear err bit in PRB_E reg */ |
| 3234 | #define IECLR_PRB_D (1UL << 13) /* clear err bit in PRB_D reg */ | 3124 | #define IECLR_PRB_D (1UL << 13) /* clear err bit in PRB_D reg */ |
| 3235 | #define IECLR_PRB_C (1UL << 12) /* clear err bit in PRB_C reg */ | 3125 | #define IECLR_PRB_C (1UL << 12) /* clear err bit in PRB_C reg */ |
| 3236 | #define IECLR_PRB_B (1UL << 11) /* clear err bit in PRB_B reg */ | 3126 | #define IECLR_PRB_B (1UL << 11) /* clear err bit in PRB_B reg */ |
| 3237 | #define IECLR_PRB_A (1UL << 10) /* clear err bit in PRB_A reg */ | 3127 | #define IECLR_PRB_A (1UL << 10) /* clear err bit in PRB_A reg */ |
| 3238 | #define IECLR_PRB_9 (1UL << 9) /* clear err bit in PRB_9 reg */ | 3128 | #define IECLR_PRB_9 (1UL << 9) /* clear err bit in PRB_9 reg */ |
| 3239 | #define IECLR_PRB_8 (1UL << 8) /* clear err bit in PRB_8 reg */ | 3129 | #define IECLR_PRB_8 (1UL << 8) /* clear err bit in PRB_8 reg */ |
| 3240 | #define IECLR_PRB_0 (1UL << 0) /* clear err bit in PRB_0 reg */ | 3130 | #define IECLR_PRB_0 (1UL << 0) /* clear err bit in PRB_0 reg */ |
| 3241 | 3131 | ||
| 3242 | /* | 3132 | /* |
| 3243 | * IIO CRB control register Fields: IIO_ICCR | 3133 | * IIO CRB control register Fields: IIO_ICCR |
| 3244 | */ | 3134 | */ |
| 3245 | #define IIO_ICCR_PENDING (0x10000) | 3135 | #define IIO_ICCR_PENDING 0x10000 |
| 3246 | #define IIO_ICCR_CMD_MASK (0xFF) | 3136 | #define IIO_ICCR_CMD_MASK 0xFF |
| 3247 | #define IIO_ICCR_CMD_SHFT (7) | 3137 | #define IIO_ICCR_CMD_SHFT 7 |
| 3248 | #define IIO_ICCR_CMD_NOP (0x0) /* No Op */ | 3138 | #define IIO_ICCR_CMD_NOP 0x0 /* No Op */ |
| 3249 | #define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */ | 3139 | #define IIO_ICCR_CMD_WAKE 0x100 /* Reactivate CRB entry and process */ |
| 3250 | #define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */ | 3140 | #define IIO_ICCR_CMD_TIMEOUT 0x200 /* Make CRB timeout & mark invalid */ |
| 3251 | #define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory | 3141 | #define IIO_ICCR_CMD_EJECT 0x400 /* Contents of entry written to memory |
| 3252 | * via a WB | 3142 | * via a WB |
| 3253 | */ | 3143 | */ |
| 3254 | #define IIO_ICCR_CMD_FLUSH (0x800) | 3144 | #define IIO_ICCR_CMD_FLUSH 0x800 |
| 3255 | 3145 | ||
| 3256 | /* | 3146 | /* |
| 3257 | * | 3147 | * |
| @@ -3283,8 +3173,8 @@ typedef union ii_ippr_u { | |||
| 3283 | * Easy access macros for CRBs, all 5 registers (A-E) | 3173 | * Easy access macros for CRBs, all 5 registers (A-E) |
| 3284 | */ | 3174 | */ |
| 3285 | typedef ii_icrb0_a_u_t icrba_t; | 3175 | typedef ii_icrb0_a_u_t icrba_t; |
| 3286 | #define a_sidn ii_icrb0_a_fld_s.ia_sidn | 3176 | #define a_sidn ii_icrb0_a_fld_s.ia_sidn |
| 3287 | #define a_tnum ii_icrb0_a_fld_s.ia_tnum | 3177 | #define a_tnum ii_icrb0_a_fld_s.ia_tnum |
| 3288 | #define a_addr ii_icrb0_a_fld_s.ia_addr | 3178 | #define a_addr ii_icrb0_a_fld_s.ia_addr |
| 3289 | #define a_valid ii_icrb0_a_fld_s.ia_vld | 3179 | #define a_valid ii_icrb0_a_fld_s.ia_vld |
| 3290 | #define a_iow ii_icrb0_a_fld_s.ia_iow | 3180 | #define a_iow ii_icrb0_a_fld_s.ia_iow |
| @@ -3324,14 +3214,13 @@ typedef ii_icrb0_c_u_t icrbc_t; | |||
| 3324 | #define c_source ii_icrb0_c_fld_s.ic_source | 3214 | #define c_source ii_icrb0_c_fld_s.ic_source |
| 3325 | #define c_regvalue ii_icrb0_c_regval | 3215 | #define c_regvalue ii_icrb0_c_regval |
| 3326 | 3216 | ||
| 3327 | |||
| 3328 | typedef ii_icrb0_d_u_t icrbd_t; | 3217 | typedef ii_icrb0_d_u_t icrbd_t; |
| 3329 | #define d_sleep ii_icrb0_d_fld_s.id_sleep | 3218 | #define d_sleep ii_icrb0_d_fld_s.id_sleep |
| 3330 | #define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt | 3219 | #define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt |
| 3331 | #define d_pripsc ii_icrb0_d_fld_s.id_pr_psc | 3220 | #define d_pripsc ii_icrb0_d_fld_s.id_pr_psc |
| 3332 | #define d_bteop ii_icrb0_d_fld_s.id_bte_op | 3221 | #define d_bteop ii_icrb0_d_fld_s.id_bte_op |
| 3333 | #define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/ | 3222 | #define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */ |
| 3334 | #define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/ | 3223 | #define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */ |
| 3335 | #define d_regvalue ii_icrb0_d_regval | 3224 | #define d_regvalue ii_icrb0_d_regval |
| 3336 | 3225 | ||
| 3337 | typedef ii_icrb0_e_u_t icrbe_t; | 3226 | typedef ii_icrb0_e_u_t icrbe_t; |
| @@ -3341,7 +3230,6 @@ typedef ii_icrb0_e_u_t icrbe_t; | |||
| 3341 | #define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout | 3230 | #define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout |
| 3342 | #define e_regvalue ii_icrb0_e_regval | 3231 | #define e_regvalue ii_icrb0_e_regval |
| 3343 | 3232 | ||
| 3344 | |||
| 3345 | /* Number of widgets supported by shub */ | 3233 | /* Number of widgets supported by shub */ |
| 3346 | #define HUB_NUM_WIDGET 9 | 3234 | #define HUB_NUM_WIDGET 9 |
| 3347 | #define HUB_WIDGET_ID_MIN 0x8 | 3235 | #define HUB_WIDGET_ID_MIN 0x8 |
| @@ -3367,27 +3255,27 @@ typedef ii_icrb0_e_u_t icrbe_t; | |||
| 3367 | 3255 | ||
| 3368 | #define LNK_STAT_WORKING 0x2 /* LLP is working */ | 3256 | #define LNK_STAT_WORKING 0x2 /* LLP is working */ |
| 3369 | 3257 | ||
| 3370 | #define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */ | 3258 | #define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */ |
| 3371 | #define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */ | 3259 | #define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */ |
| 3372 | #define IIO_WSTAT_TXRETRY_MASK (0x7F) /* should be 0xFF?? */ | 3260 | #define IIO_WSTAT_TXRETRY_MASK 0x7F /* should be 0xFF?? */ |
| 3373 | #define IIO_WSTAT_TXRETRY_SHFT (16) | 3261 | #define IIO_WSTAT_TXRETRY_SHFT 16 |
| 3374 | #define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \ | 3262 | #define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \ |
| 3375 | IIO_WSTAT_TXRETRY_MASK) | 3263 | IIO_WSTAT_TXRETRY_MASK) |
| 3376 | 3264 | ||
| 3377 | /* Number of II perf. counters we can multiplex at once */ | 3265 | /* Number of II perf. counters we can multiplex at once */ |
| 3378 | 3266 | ||
| 3379 | #define IO_PERF_SETS 32 | 3267 | #define IO_PERF_SETS 32 |
| 3380 | 3268 | ||
| 3381 | /* Bit for the widget in inbound access register */ | 3269 | /* Bit for the widget in inbound access register */ |
| 3382 | #define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) | 3270 | #define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) |
| 3383 | /* Bit for the widget in outbound access register */ | 3271 | /* Bit for the widget in outbound access register */ |
| 3384 | #define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) | 3272 | #define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) |
| 3385 | 3273 | ||
| 3386 | /* NOTE: The following define assumes that we are going to get | 3274 | /* NOTE: The following define assumes that we are going to get |
| 3387 | * widget numbers from 8 thru F and the device numbers within | 3275 | * widget numbers from 8 thru F and the device numbers within |
| 3388 | * widget from 0 thru 7. | 3276 | * widget from 0 thru 7. |
| 3389 | */ | 3277 | */ |
| 3390 | #define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d)))) | 3278 | #define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d)))) |
| 3391 | 3279 | ||
| 3392 | /* IO Interrupt Destination Register */ | 3280 | /* IO Interrupt Destination Register */ |
| 3393 | #define IIO_IIDSR_SENT_SHIFT 28 | 3281 | #define IIO_IIDSR_SENT_SHIFT 28 |
| @@ -3402,11 +3290,11 @@ typedef ii_icrb0_e_u_t icrbe_t; | |||
| 3402 | #define IIO_IIDSR_LVL_MASK 0x000000ff | 3290 | #define IIO_IIDSR_LVL_MASK 0x000000ff |
| 3403 | 3291 | ||
| 3404 | /* Xtalk timeout threshhold register (IIO_IXTT) */ | 3292 | /* Xtalk timeout threshhold register (IIO_IXTT) */ |
| 3405 | #define IXTT_RRSP_TO_SHFT 55 /* read response timeout */ | 3293 | #define IXTT_RRSP_TO_SHFT 55 /* read response timeout */ |
| 3406 | #define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT) | 3294 | #define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT) |
| 3407 | #define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */ | 3295 | #define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */ |
| 3408 | #define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT) | 3296 | #define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT) |
| 3409 | #define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */ | 3297 | #define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */ |
| 3410 | #define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT) | 3298 | #define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT) |
| 3411 | 3299 | ||
| 3412 | /* | 3300 | /* |
| @@ -3414,17 +3302,17 @@ typedef ii_icrb0_e_u_t icrbe_t; | |||
| 3414 | */ | 3302 | */ |
| 3415 | 3303 | ||
| 3416 | typedef union hubii_wcr_u { | 3304 | typedef union hubii_wcr_u { |
| 3417 | uint64_t wcr_reg_value; | 3305 | uint64_t wcr_reg_value; |
| 3418 | struct { | 3306 | struct { |
| 3419 | uint64_t wcr_widget_id: 4, /* LLP crossbar credit */ | 3307 | uint64_t wcr_widget_id:4, /* LLP crossbar credit */ |
| 3420 | wcr_tag_mode: 1, /* Tag mode */ | 3308 | wcr_tag_mode:1, /* Tag mode */ |
| 3421 | wcr_rsvd1: 8, /* Reserved */ | 3309 | wcr_rsvd1:8, /* Reserved */ |
| 3422 | wcr_xbar_crd: 3, /* LLP crossbar credit */ | 3310 | wcr_xbar_crd:3, /* LLP crossbar credit */ |
| 3423 | wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */ | 3311 | wcr_f_bad_pkt:1, /* Force bad llp pkt enable */ |
| 3424 | wcr_dir_con: 1, /* widget direct connect */ | 3312 | wcr_dir_con:1, /* widget direct connect */ |
| 3425 | wcr_e_thresh: 5, /* elasticity threshold */ | 3313 | wcr_e_thresh:5, /* elasticity threshold */ |
| 3426 | wcr_rsvd: 41; /* unused */ | 3314 | wcr_rsvd:41; /* unused */ |
| 3427 | } wcr_fields_s; | 3315 | } wcr_fields_s; |
| 3428 | } hubii_wcr_t; | 3316 | } hubii_wcr_t; |
| 3429 | 3317 | ||
| 3430 | #define iwcr_dir_con wcr_fields_s.wcr_dir_con | 3318 | #define iwcr_dir_con wcr_fields_s.wcr_dir_con |
| @@ -3436,41 +3324,35 @@ performance registers */ | |||
| 3436 | performed */ | 3324 | performed */ |
| 3437 | 3325 | ||
| 3438 | typedef union io_perf_sel { | 3326 | typedef union io_perf_sel { |
| 3439 | uint64_t perf_sel_reg; | 3327 | uint64_t perf_sel_reg; |
| 3440 | struct { | 3328 | struct { |
| 3441 | uint64_t perf_ippr0 : 4, | 3329 | uint64_t perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48; |
| 3442 | perf_ippr1 : 4, | 3330 | } perf_sel_bits; |
| 3443 | perf_icct : 8, | ||
| 3444 | perf_rsvd : 48; | ||
| 3445 | } perf_sel_bits; | ||
| 3446 | } io_perf_sel_t; | 3331 | } io_perf_sel_t; |
| 3447 | 3332 | ||
| 3448 | /* io_perf_cnt is to extract the count from the shub registers. Due to | 3333 | /* io_perf_cnt is to extract the count from the shub registers. Due to |
| 3449 | hardware problems there is only one counter, not two. */ | 3334 | hardware problems there is only one counter, not two. */ |
| 3450 | 3335 | ||
| 3451 | typedef union io_perf_cnt { | 3336 | typedef union io_perf_cnt { |
| 3452 | uint64_t perf_cnt; | 3337 | uint64_t perf_cnt; |
| 3453 | struct { | 3338 | struct { |
| 3454 | uint64_t perf_cnt : 20, | 3339 | uint64_t perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32; |
| 3455 | perf_rsvd2 : 12, | 3340 | } perf_cnt_bits; |
| 3456 | perf_rsvd1 : 32; | ||
| 3457 | } perf_cnt_bits; | ||
| 3458 | 3341 | ||
| 3459 | } io_perf_cnt_t; | 3342 | } io_perf_cnt_t; |
| 3460 | 3343 | ||
| 3461 | typedef union iprte_a { | 3344 | typedef union iprte_a { |
| 3462 | uint64_t entry; | 3345 | uint64_t entry; |
| 3463 | struct { | 3346 | struct { |
| 3464 | uint64_t i_rsvd_1 : 3; | 3347 | uint64_t i_rsvd_1:3; |
| 3465 | uint64_t i_addr : 38; | 3348 | uint64_t i_addr:38; |
| 3466 | uint64_t i_init : 3; | 3349 | uint64_t i_init:3; |
| 3467 | uint64_t i_source : 8; | 3350 | uint64_t i_source:8; |
| 3468 | uint64_t i_rsvd : 2; | 3351 | uint64_t i_rsvd:2; |
| 3469 | uint64_t i_widget : 4; | 3352 | uint64_t i_widget:4; |
| 3470 | uint64_t i_to_cnt : 5; | 3353 | uint64_t i_to_cnt:5; |
| 3471 | uint64_t i_vld : 1; | 3354 | uint64_t i_vld:1; |
| 3472 | } iprte_fields; | 3355 | } iprte_fields; |
| 3473 | } iprte_a_t; | 3356 | } iprte_a_t; |
| 3474 | 3357 | ||
| 3475 | #endif /* _ASM_IA64_SN_SHUBIO_H */ | 3358 | #endif /* _ASM_IA64_SN_SHUBIO_H */ |
| 3476 | |||
diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h index 685435af170d..20b300187669 100644 --- a/include/asm-ia64/sn/sn_cpuid.h +++ b/include/asm-ia64/sn/sn_cpuid.h | |||
| @@ -4,7 +4,7 @@ | |||
| 4 | * License. See the file "COPYING" in the main directory of this archive | 4 | * License. See the file "COPYING" in the main directory of this archive |
| 5 | * for more details. | 5 | * for more details. |
| 6 | * | 6 | * |
| 7 | * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. | 7 | * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved. |
| 8 | */ | 8 | */ |
| 9 | 9 | ||
| 10 | 10 | ||
| @@ -92,24 +92,24 @@ | |||
| 92 | * NOTE: on non-MP systems, only cpuid 0 exists | 92 | * NOTE: on non-MP systems, only cpuid 0 exists |
| 93 | */ | 93 | */ |
| 94 | 94 | ||
| 95 | extern short physical_node_map[]; /* indexed by nasid to get cnode */ | 95 | extern short physical_node_map[]; /* indexed by nasid to get cnode */ |
| 96 | 96 | ||
| 97 | /* | 97 | /* |
| 98 | * Macros for retrieving info about current cpu | 98 | * Macros for retrieving info about current cpu |
| 99 | */ | 99 | */ |
| 100 | #define get_nasid() (nodepda->phys_cpuid[smp_processor_id()].nasid) | 100 | #define get_nasid() (sn_nodepda->phys_cpuid[smp_processor_id()].nasid) |
| 101 | #define get_subnode() (nodepda->phys_cpuid[smp_processor_id()].subnode) | 101 | #define get_subnode() (sn_nodepda->phys_cpuid[smp_processor_id()].subnode) |
| 102 | #define get_slice() (nodepda->phys_cpuid[smp_processor_id()].slice) | 102 | #define get_slice() (sn_nodepda->phys_cpuid[smp_processor_id()].slice) |
| 103 | #define get_cnode() (nodepda->phys_cpuid[smp_processor_id()].cnode) | 103 | #define get_cnode() (sn_nodepda->phys_cpuid[smp_processor_id()].cnode) |
| 104 | #define get_sapicid() ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff) | 104 | #define get_sapicid() ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff) |
| 105 | 105 | ||
| 106 | /* | 106 | /* |
| 107 | * Macros for retrieving info about an arbitrary cpu | 107 | * Macros for retrieving info about an arbitrary cpu |
| 108 | * cpuid - logical cpu id | 108 | * cpuid - logical cpu id |
| 109 | */ | 109 | */ |
| 110 | #define cpuid_to_nasid(cpuid) (nodepda->phys_cpuid[cpuid].nasid) | 110 | #define cpuid_to_nasid(cpuid) (sn_nodepda->phys_cpuid[cpuid].nasid) |
| 111 | #define cpuid_to_subnode(cpuid) (nodepda->phys_cpuid[cpuid].subnode) | 111 | #define cpuid_to_subnode(cpuid) (sn_nodepda->phys_cpuid[cpuid].subnode) |
| 112 | #define cpuid_to_slice(cpuid) (nodepda->phys_cpuid[cpuid].slice) | 112 | #define cpuid_to_slice(cpuid) (sn_nodepda->phys_cpuid[cpuid].slice) |
| 113 | #define cpuid_to_cnodeid(cpuid) (physical_node_map[cpuid_to_nasid(cpuid)]) | 113 | #define cpuid_to_cnodeid(cpuid) (physical_node_map[cpuid_to_nasid(cpuid)]) |
| 114 | 114 | ||
| 115 | 115 | ||
| @@ -123,11 +123,8 @@ extern int nasid_slice_to_cpuid(int, int); | |||
| 123 | 123 | ||
| 124 | /* | 124 | /* |
| 125 | * cnodeid_to_nasid - convert a cnodeid to a NASID | 125 | * cnodeid_to_nasid - convert a cnodeid to a NASID |
| 126 | * Macro relies on pg_data for a node being on the node itself. | ||
| 127 | * Just extract the NASID from the pointer. | ||
| 128 | * | ||
| 129 | */ | 126 | */ |
| 130 | #define cnodeid_to_nasid(cnodeid) pda->cnodeid_to_nasid_table[cnodeid] | 127 | #define cnodeid_to_nasid(cnodeid) (sn_cnodeid_to_nasid[cnodeid]) |
| 131 | 128 | ||
| 132 | /* | 129 | /* |
| 133 | * nasid_to_cnodeid - convert a NASID to a cnodeid | 130 | * nasid_to_cnodeid - convert a NASID to a cnodeid |
diff --git a/include/asm-ia64/sn/sn_fru.h b/include/asm-ia64/sn/sn_fru.h deleted file mode 100644 index 8c21ac3f0156..000000000000 --- a/include/asm-ia64/sn/sn_fru.h +++ /dev/null | |||
| @@ -1,44 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 1992-1997,1999-2004 Silicon Graphics, Inc. All rights reserved. | ||
| 7 | */ | ||
| 8 | #ifndef _ASM_IA64_SN_SN_FRU_H | ||
| 9 | #define _ASM_IA64_SN_SN_FRU_H | ||
| 10 | |||
| 11 | #define MAX_DIMMS 8 /* max # of dimm banks */ | ||
| 12 | #define MAX_PCIDEV 8 /* max # of pci devices on a pci bus */ | ||
| 13 | |||
| 14 | typedef unsigned char confidence_t; | ||
| 15 | |||
| 16 | typedef struct kf_mem_s { | ||
| 17 | confidence_t km_confidence; /* confidence level that the memory is bad | ||
| 18 | * is this necessary ? | ||
| 19 | */ | ||
| 20 | confidence_t km_dimm[MAX_DIMMS]; | ||
| 21 | /* confidence level that dimm[i] is bad | ||
| 22 | *I think this is the right number | ||
| 23 | */ | ||
| 24 | |||
| 25 | } kf_mem_t; | ||
| 26 | |||
| 27 | typedef struct kf_cpu_s { | ||
| 28 | confidence_t kc_confidence; /* confidence level that cpu is bad */ | ||
| 29 | confidence_t kc_icache; /* confidence level that instr. cache is bad */ | ||
| 30 | confidence_t kc_dcache; /* confidence level that data cache is bad */ | ||
| 31 | confidence_t kc_scache; /* confidence level that sec. cache is bad */ | ||
| 32 | confidence_t kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */ | ||
| 33 | } kf_cpu_t; | ||
| 34 | |||
| 35 | |||
| 36 | typedef struct kf_pci_bus_s { | ||
| 37 | confidence_t kpb_belief; /* confidence level that the pci bus is bad */ | ||
| 38 | confidence_t kpb_pcidev_belief[MAX_PCIDEV]; | ||
| 39 | /* confidence level that the pci dev is bad */ | ||
| 40 | } kf_pci_bus_t; | ||
| 41 | |||
| 42 | |||
| 43 | #endif /* _ASM_IA64_SN_SN_FRU_H */ | ||
| 44 | |||
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h index f914f6da077c..eb0395ad0d6a 100644 --- a/include/asm-ia64/sn/sn_sal.h +++ b/include/asm-ia64/sn/sn_sal.h | |||
| @@ -115,6 +115,13 @@ | |||
| 115 | #define SAL_IROUTER_INTR_XMIT SAL_CONSOLE_INTR_XMIT | 115 | #define SAL_IROUTER_INTR_XMIT SAL_CONSOLE_INTR_XMIT |
| 116 | #define SAL_IROUTER_INTR_RECV SAL_CONSOLE_INTR_RECV | 116 | #define SAL_IROUTER_INTR_RECV SAL_CONSOLE_INTR_RECV |
| 117 | 117 | ||
| 118 | /* | ||
| 119 | * Error Handling Features | ||
| 120 | */ | ||
| 121 | #define SAL_ERR_FEAT_MCA_SLV_TO_OS_INIT_SLV 0x1 | ||
| 122 | #define SAL_ERR_FEAT_LOG_SBES 0x2 | ||
| 123 | #define SAL_ERR_FEAT_MFR_OVERRIDE 0x4 | ||
| 124 | #define SAL_ERR_FEAT_SBE_THRESHOLD 0xffff0000 | ||
| 118 | 125 | ||
| 119 | /* | 126 | /* |
| 120 | * SAL Error Codes | 127 | * SAL Error Codes |
| @@ -342,6 +349,25 @@ ia64_sn_plat_cpei_handler(void) | |||
| 342 | } | 349 | } |
| 343 | 350 | ||
| 344 | /* | 351 | /* |
| 352 | * Set Error Handling Features | ||
| 353 | */ | ||
| 354 | static inline u64 | ||
| 355 | ia64_sn_plat_set_error_handling_features(void) | ||
| 356 | { | ||
| 357 | struct ia64_sal_retval ret_stuff; | ||
| 358 | |||
| 359 | ret_stuff.status = 0; | ||
| 360 | ret_stuff.v0 = 0; | ||
| 361 | ret_stuff.v1 = 0; | ||
| 362 | ret_stuff.v2 = 0; | ||
| 363 | SAL_CALL_REENTRANT(ret_stuff, SN_SAL_SET_ERROR_HANDLING_FEATURES, | ||
| 364 | (SAL_ERR_FEAT_MCA_SLV_TO_OS_INIT_SLV | SAL_ERR_FEAT_LOG_SBES), | ||
| 365 | 0, 0, 0, 0, 0, 0); | ||
| 366 | |||
| 367 | return ret_stuff.status; | ||
| 368 | } | ||
| 369 | |||
| 370 | /* | ||
| 345 | * Checks for console input. | 371 | * Checks for console input. |
| 346 | */ | 372 | */ |
| 347 | static inline u64 | 373 | static inline u64 |
| @@ -472,7 +498,7 @@ static inline u64 | |||
| 472 | ia64_sn_pod_mode(void) | 498 | ia64_sn_pod_mode(void) |
| 473 | { | 499 | { |
| 474 | struct ia64_sal_retval isrv; | 500 | struct ia64_sal_retval isrv; |
| 475 | SAL_CALL(isrv, SN_SAL_POD_MODE, 0, 0, 0, 0, 0, 0, 0); | 501 | SAL_CALL_REENTRANT(isrv, SN_SAL_POD_MODE, 0, 0, 0, 0, 0, 0, 0); |
| 476 | if (isrv.status) | 502 | if (isrv.status) |
| 477 | return 0; | 503 | return 0; |
| 478 | return isrv.v0; | 504 | return isrv.v0; |
| @@ -557,7 +583,8 @@ static inline u64 | |||
| 557 | ia64_sn_partition_serial_get(void) | 583 | ia64_sn_partition_serial_get(void) |
| 558 | { | 584 | { |
| 559 | struct ia64_sal_retval ret_stuff; | 585 | struct ia64_sal_retval ret_stuff; |
| 560 | SAL_CALL(ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0, 0, 0, 0, 0, 0, 0); | 586 | ia64_sal_oemcall_reentrant(&ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0, |
| 587 | 0, 0, 0, 0, 0, 0); | ||
| 561 | if (ret_stuff.status != 0) | 588 | if (ret_stuff.status != 0) |
| 562 | return 0; | 589 | return 0; |
| 563 | return ret_stuff.v0; | 590 | return ret_stuff.v0; |
| @@ -565,11 +592,10 @@ ia64_sn_partition_serial_get(void) | |||
| 565 | 592 | ||
| 566 | static inline u64 | 593 | static inline u64 |
| 567 | sn_partition_serial_number_val(void) { | 594 | sn_partition_serial_number_val(void) { |
| 568 | if (sn_partition_serial_number) { | 595 | if (unlikely(sn_partition_serial_number == 0)) { |
| 569 | return(sn_partition_serial_number); | 596 | sn_partition_serial_number = ia64_sn_partition_serial_get(); |
| 570 | } else { | ||
| 571 | return(sn_partition_serial_number = ia64_sn_partition_serial_get()); | ||
| 572 | } | 597 | } |
| 598 | return sn_partition_serial_number; | ||
| 573 | } | 599 | } |
| 574 | 600 | ||
| 575 | /* | 601 | /* |
| @@ -580,8 +606,8 @@ static inline partid_t | |||
| 580 | ia64_sn_sysctl_partition_get(nasid_t nasid) | 606 | ia64_sn_sysctl_partition_get(nasid_t nasid) |
| 581 | { | 607 | { |
| 582 | struct ia64_sal_retval ret_stuff; | 608 | struct ia64_sal_retval ret_stuff; |
| 583 | SAL_CALL(ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid, | 609 | ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid, |
| 584 | 0, 0, 0, 0, 0, 0); | 610 | 0, 0, 0, 0, 0, 0); |
| 585 | if (ret_stuff.status != 0) | 611 | if (ret_stuff.status != 0) |
| 586 | return INVALID_PARTID; | 612 | return INVALID_PARTID; |
| 587 | return ((partid_t)ret_stuff.v0); | 613 | return ((partid_t)ret_stuff.v0); |
| @@ -595,11 +621,38 @@ extern partid_t sn_partid; | |||
| 595 | 621 | ||
| 596 | static inline partid_t | 622 | static inline partid_t |
| 597 | sn_local_partid(void) { | 623 | sn_local_partid(void) { |
| 598 | if (sn_partid < 0) { | 624 | if (unlikely(sn_partid < 0)) { |
| 599 | return (sn_partid = ia64_sn_sysctl_partition_get(cpuid_to_nasid(smp_processor_id()))); | 625 | sn_partid = ia64_sn_sysctl_partition_get(cpuid_to_nasid(smp_processor_id())); |
| 600 | } else { | ||
| 601 | return sn_partid; | ||
| 602 | } | 626 | } |
| 627 | return sn_partid; | ||
| 628 | } | ||
| 629 | |||
| 630 | /* | ||
| 631 | * Returns the physical address of the partition's reserved page through | ||
| 632 | * an iterative number of calls. | ||
| 633 | * | ||
| 634 | * On first call, 'cookie' and 'len' should be set to 0, and 'addr' | ||
| 635 | * set to the nasid of the partition whose reserved page's address is | ||
| 636 | * being sought. | ||
| 637 | * On subsequent calls, pass the values, that were passed back on the | ||
| 638 | * previous call. | ||
| 639 | * | ||
| 640 | * While the return status equals SALRET_MORE_PASSES, keep calling | ||
| 641 | * this function after first copying 'len' bytes starting at 'addr' | ||
| 642 | * into 'buf'. Once the return status equals SALRET_OK, 'addr' will | ||
| 643 | * be the physical address of the partition's reserved page. If the | ||
| 644 | * return status equals neither of these, an error as occurred. | ||
| 645 | */ | ||
| 646 | static inline s64 | ||
| 647 | sn_partition_reserved_page_pa(u64 buf, u64 *cookie, u64 *addr, u64 *len) | ||
| 648 | { | ||
| 649 | struct ia64_sal_retval rv; | ||
| 650 | ia64_sal_oemcall_reentrant(&rv, SN_SAL_GET_PARTITION_ADDR, *cookie, | ||
| 651 | *addr, buf, *len, 0, 0, 0); | ||
| 652 | *cookie = rv.v0; | ||
| 653 | *addr = rv.v1; | ||
| 654 | *len = rv.v2; | ||
| 655 | return rv.status; | ||
| 603 | } | 656 | } |
| 604 | 657 | ||
| 605 | /* | 658 | /* |
| @@ -621,8 +674,8 @@ static inline int | |||
| 621 | sn_register_xp_addr_region(u64 paddr, u64 len, int operation) | 674 | sn_register_xp_addr_region(u64 paddr, u64 len, int operation) |
| 622 | { | 675 | { |
| 623 | struct ia64_sal_retval ret_stuff; | 676 | struct ia64_sal_retval ret_stuff; |
| 624 | SAL_CALL(ret_stuff, SN_SAL_XP_ADDR_REGION, paddr, len, (u64)operation, | 677 | ia64_sal_oemcall(&ret_stuff, SN_SAL_XP_ADDR_REGION, paddr, len, |
| 625 | 0, 0, 0, 0); | 678 | (u64)operation, 0, 0, 0, 0); |
| 626 | return ret_stuff.status; | 679 | return ret_stuff.status; |
| 627 | } | 680 | } |
| 628 | 681 | ||
| @@ -646,8 +699,8 @@ sn_register_nofault_code(u64 start_addr, u64 end_addr, u64 return_addr, | |||
| 646 | } else { | 699 | } else { |
| 647 | call = SN_SAL_NO_FAULT_ZONE_PHYSICAL; | 700 | call = SN_SAL_NO_FAULT_ZONE_PHYSICAL; |
| 648 | } | 701 | } |
| 649 | SAL_CALL(ret_stuff, call, start_addr, end_addr, return_addr, (u64)1, | 702 | ia64_sal_oemcall(&ret_stuff, call, start_addr, end_addr, return_addr, |
| 650 | 0, 0, 0); | 703 | (u64)1, 0, 0, 0); |
| 651 | return ret_stuff.status; | 704 | return ret_stuff.status; |
| 652 | } | 705 | } |
| 653 | 706 | ||
| @@ -668,8 +721,8 @@ static inline int | |||
| 668 | sn_change_coherence(u64 *new_domain, u64 *old_domain) | 721 | sn_change_coherence(u64 *new_domain, u64 *old_domain) |
| 669 | { | 722 | { |
| 670 | struct ia64_sal_retval ret_stuff; | 723 | struct ia64_sal_retval ret_stuff; |
| 671 | SAL_CALL(ret_stuff, SN_SAL_COHERENCE, new_domain, old_domain, 0, 0, | 724 | ia64_sal_oemcall(&ret_stuff, SN_SAL_COHERENCE, (u64)new_domain, |
| 672 | 0, 0, 0); | 725 | (u64)old_domain, 0, 0, 0, 0, 0); |
| 673 | return ret_stuff.status; | 726 | return ret_stuff.status; |
| 674 | } | 727 | } |
| 675 | 728 | ||
| @@ -688,8 +741,8 @@ sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array) | |||
| 688 | cnodeid = nasid_to_cnodeid(get_node_number(paddr)); | 741 | cnodeid = nasid_to_cnodeid(get_node_number(paddr)); |
| 689 | // spin_lock(&NODEPDA(cnodeid)->bist_lock); | 742 | // spin_lock(&NODEPDA(cnodeid)->bist_lock); |
| 690 | local_irq_save(irq_flags); | 743 | local_irq_save(irq_flags); |
| 691 | SAL_CALL_NOLOCK(ret_stuff, SN_SAL_MEMPROTECT, paddr, len, nasid_array, | 744 | ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_MEMPROTECT, paddr, len, |
| 692 | perms, 0, 0, 0); | 745 | (u64)nasid_array, perms, 0, 0, 0); |
| 693 | local_irq_restore(irq_flags); | 746 | local_irq_restore(irq_flags); |
| 694 | // spin_unlock(&NODEPDA(cnodeid)->bist_lock); | 747 | // spin_unlock(&NODEPDA(cnodeid)->bist_lock); |
| 695 | return ret_stuff.status; | 748 | return ret_stuff.status; |
diff --git a/include/asm-ia64/sn/sndrv.h b/include/asm-ia64/sn/sndrv.h deleted file mode 100644 index aa00d42cde32..000000000000 --- a/include/asm-ia64/sn/sndrv.h +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (c) 2002-2004 Silicon Graphics, Inc. All Rights Reserved. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef _ASM_IA64_SN_SNDRV_H | ||
| 10 | #define _ASM_IA64_SN_SNDRV_H | ||
| 11 | |||
| 12 | /* ioctl commands */ | ||
| 13 | #define SNDRV_GET_ROUTERINFO 1 | ||
| 14 | #define SNDRV_GET_INFOSIZE 2 | ||
| 15 | #define SNDRV_GET_HUBINFO 3 | ||
| 16 | #define SNDRV_GET_FLASHLOGSIZE 4 | ||
| 17 | #define SNDRV_SET_FLASHSYNC 5 | ||
| 18 | #define SNDRV_GET_FLASHLOGDATA 6 | ||
| 19 | #define SNDRV_GET_FLASHLOGALL 7 | ||
| 20 | |||
| 21 | #define SNDRV_SET_HISTOGRAM_TYPE 14 | ||
| 22 | |||
| 23 | #define SNDRV_ELSC_COMMAND 19 | ||
| 24 | #define SNDRV_CLEAR_LOG 20 | ||
| 25 | #define SNDRV_INIT_LOG 21 | ||
| 26 | #define SNDRV_GET_PIMM_PSC 22 | ||
| 27 | #define SNDRV_SET_PARTITION 23 | ||
| 28 | #define SNDRV_GET_PARTITION 24 | ||
| 29 | |||
| 30 | /* see synergy_perf_ioctl() */ | ||
| 31 | #define SNDRV_GET_SYNERGY_VERSION 30 | ||
| 32 | #define SNDRV_GET_SYNERGY_STATUS 31 | ||
| 33 | #define SNDRV_GET_SYNERGYINFO 32 | ||
| 34 | #define SNDRV_SYNERGY_APPEND 33 | ||
| 35 | #define SNDRV_SYNERGY_ENABLE 34 | ||
| 36 | #define SNDRV_SYNERGY_FREQ 35 | ||
| 37 | |||
| 38 | /* Devices */ | ||
| 39 | #define SNDRV_UKNOWN_DEVICE -1 | ||
| 40 | #define SNDRV_ROUTER_DEVICE 1 | ||
| 41 | #define SNDRV_HUB_DEVICE 2 | ||
| 42 | #define SNDRV_ELSC_NVRAM_DEVICE 3 | ||
| 43 | #define SNDRV_ELSC_CONTROLLER_DEVICE 4 | ||
| 44 | #define SNDRV_SYSCTL_SUBCH 5 | ||
| 45 | #define SNDRV_SYNERGY_DEVICE 6 | ||
| 46 | |||
| 47 | #endif /* _ASM_IA64_SN_SNDRV_H */ | ||
diff --git a/include/asm-ia64/sn/xp.h b/include/asm-ia64/sn/xp.h new file mode 100644 index 000000000000..9902185c0288 --- /dev/null +++ b/include/asm-ia64/sn/xp.h | |||
| @@ -0,0 +1,436 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004-2005 Silicon Graphics, Inc. All rights reserved. | ||
| 7 | */ | ||
| 8 | |||
| 9 | |||
| 10 | /* | ||
| 11 | * External Cross Partition (XP) structures and defines. | ||
| 12 | */ | ||
| 13 | |||
| 14 | |||
| 15 | #ifndef _ASM_IA64_SN_XP_H | ||
| 16 | #define _ASM_IA64_SN_XP_H | ||
| 17 | |||
| 18 | |||
| 19 | #include <linux/version.h> | ||
| 20 | #include <linux/cache.h> | ||
| 21 | #include <linux/hardirq.h> | ||
| 22 | #include <asm/sn/types.h> | ||
| 23 | #include <asm/sn/bte.h> | ||
| 24 | |||
| 25 | |||
| 26 | #ifdef USE_DBUG_ON | ||
| 27 | #define DBUG_ON(condition) BUG_ON(condition) | ||
| 28 | #else | ||
| 29 | #define DBUG_ON(condition) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | |||
| 33 | /* | ||
| 34 | * Define the maximum number of logically defined partitions the system | ||
| 35 | * can support. It is constrained by the maximum number of hardware | ||
| 36 | * partitionable regions. The term 'region' in this context refers to the | ||
| 37 | * minimum number of nodes that can comprise an access protection grouping. | ||
| 38 | * The access protection is in regards to memory, IPI and IOI. | ||
| 39 | * | ||
| 40 | * The maximum number of hardware partitionable regions is equal to the | ||
| 41 | * maximum number of nodes in the entire system divided by the minimum number | ||
| 42 | * of nodes that comprise an access protection grouping. | ||
| 43 | */ | ||
| 44 | #define XP_MAX_PARTITIONS 64 | ||
| 45 | |||
| 46 | |||
| 47 | /* | ||
| 48 | * Define the number of u64s required to represent all the C-brick nasids | ||
| 49 | * as a bitmap. The cross-partition kernel modules deal only with | ||
| 50 | * C-brick nasids, thus the need for bitmaps which don't account for | ||
| 51 | * odd-numbered (non C-brick) nasids. | ||
| 52 | */ | ||
| 53 | #define XP_MAX_PHYSNODE_ID (MAX_PHYSNODE_ID / 2) | ||
| 54 | #define XP_NASID_MASK_BYTES ((XP_MAX_PHYSNODE_ID + 7) / 8) | ||
| 55 | #define XP_NASID_MASK_WORDS ((XP_MAX_PHYSNODE_ID + 63) / 64) | ||
| 56 | |||
| 57 | |||
| 58 | /* | ||
| 59 | * Wrapper for bte_copy() that should it return a failure status will retry | ||
| 60 | * the bte_copy() once in the hope that the failure was due to a temporary | ||
| 61 | * aberration (i.e., the link going down temporarily). | ||
| 62 | * | ||
| 63 | * See bte_copy for definition of the input parameters. | ||
| 64 | * | ||
| 65 | * Note: xp_bte_copy() should never be called while holding a spinlock. | ||
| 66 | */ | ||
| 67 | static inline bte_result_t | ||
| 68 | xp_bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification) | ||
| 69 | { | ||
| 70 | bte_result_t ret; | ||
| 71 | |||
| 72 | |||
| 73 | ret = bte_copy(src, dest, len, mode, notification); | ||
| 74 | |||
| 75 | if (ret != BTE_SUCCESS) { | ||
| 76 | if (!in_interrupt()) { | ||
| 77 | cond_resched(); | ||
| 78 | } | ||
| 79 | ret = bte_copy(src, dest, len, mode, notification); | ||
| 80 | } | ||
| 81 | |||
| 82 | return ret; | ||
| 83 | } | ||
| 84 | |||
| 85 | |||
| 86 | /* | ||
| 87 | * XPC establishes channel connections between the local partition and any | ||
| 88 | * other partition that is currently up. Over these channels, kernel-level | ||
| 89 | * `users' can communicate with their counterparts on the other partitions. | ||
| 90 | * | ||
| 91 | * The maxinum number of channels is limited to eight. For performance reasons, | ||
| 92 | * the internal cross partition structures require sixteen bytes per channel, | ||
| 93 | * and eight allows all of this interface-shared info to fit in one cache line. | ||
| 94 | * | ||
| 95 | * XPC_NCHANNELS reflects the total number of channels currently defined. | ||
| 96 | * If the need for additional channels arises, one can simply increase | ||
| 97 | * XPC_NCHANNELS accordingly. If the day should come where that number | ||
| 98 | * exceeds the MAXIMUM number of channels allowed (eight), then one will need | ||
| 99 | * to make changes to the XPC code to allow for this. | ||
| 100 | */ | ||
| 101 | #define XPC_MEM_CHANNEL 0 /* memory channel number */ | ||
| 102 | #define XPC_NET_CHANNEL 1 /* network channel number */ | ||
| 103 | |||
| 104 | #define XPC_NCHANNELS 2 /* #of defined channels */ | ||
| 105 | #define XPC_MAX_NCHANNELS 8 /* max #of channels allowed */ | ||
| 106 | |||
| 107 | #if XPC_NCHANNELS > XPC_MAX_NCHANNELS | ||
| 108 | #error XPC_NCHANNELS exceeds MAXIMUM allowed. | ||
| 109 | #endif | ||
| 110 | |||
| 111 | |||
| 112 | /* | ||
| 113 | * The format of an XPC message is as follows: | ||
| 114 | * | ||
| 115 | * +-------+--------------------------------+ | ||
| 116 | * | flags |////////////////////////////////| | ||
| 117 | * +-------+--------------------------------+ | ||
| 118 | * | message # | | ||
| 119 | * +----------------------------------------+ | ||
| 120 | * | payload (user-defined message) | | ||
| 121 | * | | | ||
| 122 | * : | ||
| 123 | * | | | ||
| 124 | * +----------------------------------------+ | ||
| 125 | * | ||
| 126 | * The size of the payload is defined by the user via xpc_connect(). A user- | ||
| 127 | * defined message resides in the payload area. | ||
| 128 | * | ||
| 129 | * The user should have no dealings with the message header, but only the | ||
| 130 | * message's payload. When a message entry is allocated (via xpc_allocate()) | ||
| 131 | * a pointer to the payload area is returned and not the actual beginning of | ||
| 132 | * the XPC message. The user then constructs a message in the payload area | ||
| 133 | * and passes that pointer as an argument on xpc_send() or xpc_send_notify(). | ||
| 134 | * | ||
| 135 | * The size of a message entry (within a message queue) must be a cacheline | ||
| 136 | * sized multiple in order to facilitate the BTE transfer of messages from one | ||
| 137 | * message queue to another. A macro, XPC_MSG_SIZE(), is provided for the user | ||
| 138 | * that wants to fit as many msg entries as possible in a given memory size | ||
| 139 | * (e.g. a memory page). | ||
| 140 | */ | ||
| 141 | struct xpc_msg { | ||
| 142 | u8 flags; /* FOR XPC INTERNAL USE ONLY */ | ||
| 143 | u8 reserved[7]; /* FOR XPC INTERNAL USE ONLY */ | ||
| 144 | s64 number; /* FOR XPC INTERNAL USE ONLY */ | ||
| 145 | |||
| 146 | u64 payload; /* user defined portion of message */ | ||
| 147 | }; | ||
| 148 | |||
| 149 | |||
| 150 | #define XPC_MSG_PAYLOAD_OFFSET (u64) (&((struct xpc_msg *)0)->payload) | ||
| 151 | #define XPC_MSG_SIZE(_payload_size) \ | ||
| 152 | L1_CACHE_ALIGN(XPC_MSG_PAYLOAD_OFFSET + (_payload_size)) | ||
| 153 | |||
| 154 | |||
| 155 | /* | ||
| 156 | * Define the return values and values passed to user's callout functions. | ||
| 157 | * (It is important to add new value codes at the end just preceding | ||
| 158 | * xpcUnknownReason, which must have the highest numerical value.) | ||
| 159 | */ | ||
| 160 | enum xpc_retval { | ||
| 161 | xpcSuccess = 0, | ||
| 162 | |||
| 163 | xpcNotConnected, /* 1: channel is not connected */ | ||
| 164 | xpcConnected, /* 2: channel connected (opened) */ | ||
| 165 | xpcRETIRED1, /* 3: (formerly xpcDisconnected) */ | ||
| 166 | |||
| 167 | xpcMsgReceived, /* 4: message received */ | ||
| 168 | xpcMsgDelivered, /* 5: message delivered and acknowledged */ | ||
| 169 | |||
| 170 | xpcRETIRED2, /* 6: (formerly xpcTransferFailed) */ | ||
| 171 | |||
| 172 | xpcNoWait, /* 7: operation would require wait */ | ||
| 173 | xpcRetry, /* 8: retry operation */ | ||
| 174 | xpcTimeout, /* 9: timeout in xpc_allocate_msg_wait() */ | ||
| 175 | xpcInterrupted, /* 10: interrupted wait */ | ||
| 176 | |||
| 177 | xpcUnequalMsgSizes, /* 11: message size disparity between sides */ | ||
| 178 | xpcInvalidAddress, /* 12: invalid address */ | ||
| 179 | |||
| 180 | xpcNoMemory, /* 13: no memory available for XPC structures */ | ||
| 181 | xpcLackOfResources, /* 14: insufficient resources for operation */ | ||
| 182 | xpcUnregistered, /* 15: channel is not registered */ | ||
| 183 | xpcAlreadyRegistered, /* 16: channel is already registered */ | ||
| 184 | |||
| 185 | xpcPartitionDown, /* 17: remote partition is down */ | ||
| 186 | xpcNotLoaded, /* 18: XPC module is not loaded */ | ||
| 187 | xpcUnloading, /* 19: this side is unloading XPC module */ | ||
| 188 | |||
| 189 | xpcBadMagic, /* 20: XPC MAGIC string not found */ | ||
| 190 | |||
| 191 | xpcReactivating, /* 21: remote partition was reactivated */ | ||
| 192 | |||
| 193 | xpcUnregistering, /* 22: this side is unregistering channel */ | ||
| 194 | xpcOtherUnregistering, /* 23: other side is unregistering channel */ | ||
| 195 | |||
| 196 | xpcCloneKThread, /* 24: cloning kernel thread */ | ||
| 197 | xpcCloneKThreadFailed, /* 25: cloning kernel thread failed */ | ||
| 198 | |||
| 199 | xpcNoHeartbeat, /* 26: remote partition has no heartbeat */ | ||
| 200 | |||
| 201 | xpcPioReadError, /* 27: PIO read error */ | ||
| 202 | xpcPhysAddrRegFailed, /* 28: registration of phys addr range failed */ | ||
| 203 | |||
| 204 | xpcBteDirectoryError, /* 29: maps to BTEFAIL_DIR */ | ||
| 205 | xpcBtePoisonError, /* 30: maps to BTEFAIL_POISON */ | ||
| 206 | xpcBteWriteError, /* 31: maps to BTEFAIL_WERR */ | ||
| 207 | xpcBteAccessError, /* 32: maps to BTEFAIL_ACCESS */ | ||
| 208 | xpcBtePWriteError, /* 33: maps to BTEFAIL_PWERR */ | ||
| 209 | xpcBtePReadError, /* 34: maps to BTEFAIL_PRERR */ | ||
| 210 | xpcBteTimeOutError, /* 35: maps to BTEFAIL_TOUT */ | ||
| 211 | xpcBteXtalkError, /* 36: maps to BTEFAIL_XTERR */ | ||
| 212 | xpcBteNotAvailable, /* 37: maps to BTEFAIL_NOTAVAIL */ | ||
| 213 | xpcBteUnmappedError, /* 38: unmapped BTEFAIL_ error */ | ||
| 214 | |||
| 215 | xpcBadVersion, /* 39: bad version number */ | ||
| 216 | xpcVarsNotSet, /* 40: the XPC variables are not set up */ | ||
| 217 | xpcNoRsvdPageAddr, /* 41: unable to get rsvd page's phys addr */ | ||
| 218 | xpcInvalidPartid, /* 42: invalid partition ID */ | ||
| 219 | xpcLocalPartid, /* 43: local partition ID */ | ||
| 220 | |||
| 221 | xpcUnknownReason /* 44: unknown reason -- must be last in list */ | ||
| 222 | }; | ||
| 223 | |||
| 224 | |||
| 225 | /* | ||
| 226 | * Define the callout function types used by XPC to update the user on | ||
| 227 | * connection activity and state changes (via the user function registered by | ||
| 228 | * xpc_connect()) and to notify them of messages received and delivered (via | ||
| 229 | * the user function registered by xpc_send_notify()). | ||
| 230 | * | ||
| 231 | * The two function types are xpc_channel_func and xpc_notify_func and | ||
| 232 | * both share the following arguments, with the exception of "data", which | ||
| 233 | * only xpc_channel_func has. | ||
| 234 | * | ||
| 235 | * Arguments: | ||
| 236 | * | ||
| 237 | * reason - reason code. (See following table.) | ||
| 238 | * partid - partition ID associated with condition. | ||
| 239 | * ch_number - channel # associated with condition. | ||
| 240 | * data - pointer to optional data. (See following table.) | ||
| 241 | * key - pointer to optional user-defined value provided as the "key" | ||
| 242 | * argument to xpc_connect() or xpc_send_notify(). | ||
| 243 | * | ||
| 244 | * In the following table the "Optional Data" column applies to callouts made | ||
| 245 | * to functions registered by xpc_connect(). A "NA" in that column indicates | ||
| 246 | * that this reason code can be passed to functions registered by | ||
| 247 | * xpc_send_notify() (i.e. they don't have data arguments). | ||
| 248 | * | ||
| 249 | * Also, the first three reason codes in the following table indicate | ||
| 250 | * success, whereas the others indicate failure. When a failure reason code | ||
| 251 | * is received, one can assume that the channel is not connected. | ||
| 252 | * | ||
| 253 | * | ||
| 254 | * Reason Code | Cause | Optional Data | ||
| 255 | * =====================+================================+===================== | ||
| 256 | * xpcConnected | connection has been established| max #of entries | ||
| 257 | * | to the specified partition on | allowed in message | ||
| 258 | * | the specified channel | queue | ||
| 259 | * ---------------------+--------------------------------+--------------------- | ||
| 260 | * xpcMsgReceived | an XPC message arrived from | address of payload | ||
| 261 | * | the specified partition on the | | ||
| 262 | * | specified channel | [the user must call | ||
| 263 | * | | xpc_received() when | ||
| 264 | * | | finished with the | ||
| 265 | * | | payload] | ||
| 266 | * ---------------------+--------------------------------+--------------------- | ||
| 267 | * xpcMsgDelivered | notification that the message | NA | ||
| 268 | * | was delivered to the intended | | ||
| 269 | * | recipient and that they have | | ||
| 270 | * | acknowledged its receipt by | | ||
| 271 | * | calling xpc_received() | | ||
| 272 | * =====================+================================+===================== | ||
| 273 | * xpcUnequalMsgSizes | can't connect to the specified | NULL | ||
| 274 | * | partition on the specified | | ||
| 275 | * | channel because of mismatched | | ||
| 276 | * | message sizes | | ||
| 277 | * ---------------------+--------------------------------+--------------------- | ||
| 278 | * xpcNoMemory | insufficient memory avaiable | NULL | ||
| 279 | * | to allocate message queue | | ||
| 280 | * ---------------------+--------------------------------+--------------------- | ||
| 281 | * xpcLackOfResources | lack of resources to create | NULL | ||
| 282 | * | the necessary kthreads to | | ||
| 283 | * | support the channel | | ||
| 284 | * ---------------------+--------------------------------+--------------------- | ||
| 285 | * xpcUnregistering | this side's user has | NULL or NA | ||
| 286 | * | unregistered by calling | | ||
| 287 | * | xpc_disconnect() | | ||
| 288 | * ---------------------+--------------------------------+--------------------- | ||
| 289 | * xpcOtherUnregistering| the other side's user has | NULL or NA | ||
| 290 | * | unregistered by calling | | ||
| 291 | * | xpc_disconnect() | | ||
| 292 | * ---------------------+--------------------------------+--------------------- | ||
| 293 | * xpcNoHeartbeat | the other side's XPC is no | NULL or NA | ||
| 294 | * | longer heartbeating | | ||
| 295 | * | | | ||
| 296 | * ---------------------+--------------------------------+--------------------- | ||
| 297 | * xpcUnloading | this side's XPC module is | NULL or NA | ||
| 298 | * | being unloaded | | ||
| 299 | * | | | ||
| 300 | * ---------------------+--------------------------------+--------------------- | ||
| 301 | * xpcOtherUnloading | the other side's XPC module is | NULL or NA | ||
| 302 | * | is being unloaded | | ||
| 303 | * | | | ||
| 304 | * ---------------------+--------------------------------+--------------------- | ||
| 305 | * xpcPioReadError | xp_nofault_PIOR() returned an | NULL or NA | ||
| 306 | * | error while sending an IPI | | ||
| 307 | * | | | ||
| 308 | * ---------------------+--------------------------------+--------------------- | ||
| 309 | * xpcInvalidAddress | the address either received or | NULL or NA | ||
| 310 | * | sent by the specified partition| | ||
| 311 | * | is invalid | | ||
| 312 | * ---------------------+--------------------------------+--------------------- | ||
| 313 | * xpcBteNotAvailable | attempt to pull data from the | NULL or NA | ||
| 314 | * xpcBtePoisonError | specified partition over the | | ||
| 315 | * xpcBteWriteError | specified channel via a | | ||
| 316 | * xpcBteAccessError | bte_copy() failed | | ||
| 317 | * xpcBteTimeOutError | | | ||
| 318 | * xpcBteXtalkError | | | ||
| 319 | * xpcBteDirectoryError | | | ||
| 320 | * xpcBteGenericError | | | ||
| 321 | * xpcBteUnmappedError | | | ||
| 322 | * ---------------------+--------------------------------+--------------------- | ||
| 323 | * xpcUnknownReason | the specified channel to the | NULL or NA | ||
| 324 | * | specified partition was | | ||
| 325 | * | unavailable for unknown reasons| | ||
| 326 | * =====================+================================+===================== | ||
| 327 | */ | ||
| 328 | |||
| 329 | typedef void (*xpc_channel_func)(enum xpc_retval reason, partid_t partid, | ||
| 330 | int ch_number, void *data, void *key); | ||
| 331 | |||
| 332 | typedef void (*xpc_notify_func)(enum xpc_retval reason, partid_t partid, | ||
| 333 | int ch_number, void *key); | ||
| 334 | |||
| 335 | |||
| 336 | /* | ||
| 337 | * The following is a registration entry. There is a global array of these, | ||
| 338 | * one per channel. It is used to record the connection registration made | ||
| 339 | * by the users of XPC. As long as a registration entry exists, for any | ||
| 340 | * partition that comes up, XPC will attempt to establish a connection on | ||
| 341 | * that channel. Notification that a connection has been made will occur via | ||
| 342 | * the xpc_channel_func function. | ||
| 343 | * | ||
| 344 | * The 'func' field points to the function to call when aynchronous | ||
| 345 | * notification is required for such events as: a connection established/lost, | ||
| 346 | * or an incomming message received, or an error condition encountered. A | ||
| 347 | * non-NULL 'func' field indicates that there is an active registration for | ||
| 348 | * the channel. | ||
| 349 | */ | ||
| 350 | struct xpc_registration { | ||
| 351 | struct semaphore sema; | ||
| 352 | xpc_channel_func func; /* function to call */ | ||
| 353 | void *key; /* pointer to user's key */ | ||
| 354 | u16 nentries; /* #of msg entries in local msg queue */ | ||
| 355 | u16 msg_size; /* message queue's message size */ | ||
| 356 | u32 assigned_limit; /* limit on #of assigned kthreads */ | ||
| 357 | u32 idle_limit; /* limit on #of idle kthreads */ | ||
| 358 | } ____cacheline_aligned; | ||
| 359 | |||
| 360 | |||
| 361 | #define XPC_CHANNEL_REGISTERED(_c) (xpc_registrations[_c].func != NULL) | ||
| 362 | |||
| 363 | |||
| 364 | /* the following are valid xpc_allocate() flags */ | ||
| 365 | #define XPC_WAIT 0 /* wait flag */ | ||
| 366 | #define XPC_NOWAIT 1 /* no wait flag */ | ||
| 367 | |||
| 368 | |||
| 369 | struct xpc_interface { | ||
| 370 | void (*connect)(int); | ||
| 371 | void (*disconnect)(int); | ||
| 372 | enum xpc_retval (*allocate)(partid_t, int, u32, void **); | ||
| 373 | enum xpc_retval (*send)(partid_t, int, void *); | ||
| 374 | enum xpc_retval (*send_notify)(partid_t, int, void *, | ||
| 375 | xpc_notify_func, void *); | ||
| 376 | void (*received)(partid_t, int, void *); | ||
| 377 | enum xpc_retval (*partid_to_nasids)(partid_t, void *); | ||
| 378 | }; | ||
| 379 | |||
| 380 | |||
| 381 | extern struct xpc_interface xpc_interface; | ||
| 382 | |||
| 383 | extern void xpc_set_interface(void (*)(int), | ||
| 384 | void (*)(int), | ||
| 385 | enum xpc_retval (*)(partid_t, int, u32, void **), | ||
| 386 | enum xpc_retval (*)(partid_t, int, void *), | ||
| 387 | enum xpc_retval (*)(partid_t, int, void *, xpc_notify_func, | ||
| 388 | void *), | ||
| 389 | void (*)(partid_t, int, void *), | ||
| 390 | enum xpc_retval (*)(partid_t, void *)); | ||
| 391 | extern void xpc_clear_interface(void); | ||
| 392 | |||
| 393 | |||
| 394 | extern enum xpc_retval xpc_connect(int, xpc_channel_func, void *, u16, | ||
| 395 | u16, u32, u32); | ||
| 396 | extern void xpc_disconnect(int); | ||
| 397 | |||
| 398 | static inline enum xpc_retval | ||
| 399 | xpc_allocate(partid_t partid, int ch_number, u32 flags, void **payload) | ||
| 400 | { | ||
| 401 | return xpc_interface.allocate(partid, ch_number, flags, payload); | ||
| 402 | } | ||
| 403 | |||
| 404 | static inline enum xpc_retval | ||
| 405 | xpc_send(partid_t partid, int ch_number, void *payload) | ||
| 406 | { | ||
| 407 | return xpc_interface.send(partid, ch_number, payload); | ||
| 408 | } | ||
| 409 | |||
| 410 | static inline enum xpc_retval | ||
| 411 | xpc_send_notify(partid_t partid, int ch_number, void *payload, | ||
| 412 | xpc_notify_func func, void *key) | ||
| 413 | { | ||
| 414 | return xpc_interface.send_notify(partid, ch_number, payload, func, key); | ||
| 415 | } | ||
| 416 | |||
| 417 | static inline void | ||
| 418 | xpc_received(partid_t partid, int ch_number, void *payload) | ||
| 419 | { | ||
| 420 | return xpc_interface.received(partid, ch_number, payload); | ||
| 421 | } | ||
| 422 | |||
| 423 | static inline enum xpc_retval | ||
| 424 | xpc_partid_to_nasids(partid_t partid, void *nasids) | ||
| 425 | { | ||
| 426 | return xpc_interface.partid_to_nasids(partid, nasids); | ||
| 427 | } | ||
| 428 | |||
| 429 | |||
| 430 | extern u64 xp_nofault_PIOR_target; | ||
| 431 | extern int xp_nofault_PIOR(void *); | ||
| 432 | extern int xp_error_PIOR(void); | ||
| 433 | |||
| 434 | |||
| 435 | #endif /* _ASM_IA64_SN_XP_H */ | ||
| 436 | |||