24 files changed, 7149 insertions, 0 deletions

diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
new file mode 100644
index 000000000000..c916bd22767a
--- /dev/null
+++ b/include/asm-ia64/sn/addrs.h
@@ -0,0 +1,238 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1992-1999,2001-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_ADDRS_H
+#define _ASM_IA64_SN_ADDRS_H
+
+#include <asm/percpu.h>
+#include <asm/sn/types.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/pda.h>
+
+/*
+ *  Memory/SHUB Address Format:
+ *  +-+---------+--+--------------+
+ *  |0|  NASID  |AS| NodeOffset   |
+ *  +-+---------+--+--------------+
+ *
+ *  NASID: (low NASID bit is 0) Memory and SHUB MMRs
+ *   AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
+ *     00: Local Resources and MMR space
+ *           Top bit of NodeOffset
+ *               0: Local resources space
+ *                  node id:
+ *                        0: IA64/NT compatibility space
+ *                        2: Local MMR Space
+ *                        4: Local memory, regardless of local node id
+ *               1: Global MMR space
+ *     01: GET space.
+ *     10: AMO space.
+ *     11: Cacheable memory space.
+ *
+ *   NodeOffset: byte offset
+ *
+ *
+ *  TIO address format:
+ *  +-+----------+--+--------------+
+ *  |0|  NASID   |AS| Nodeoffset   |
+ *  +-+----------+--+--------------+
+ *
+ *  NASID: (low NASID bit is 1) TIO
+ *   AS: 2-bit Chiplet Identifier
+ *     00: TIO LB (Indicates TIO MMR access.)
+ *     01: TIO ICE (indicates coretalk space access.)
+ * 
+ *   NodeOffset: top bit must be set.
+ *
+ *
+ * Note that in both of the above address formats, the low
+ * NASID bit indicates if the reference is to the SHUB or TIO MMRs.
+ */
+
+
+/*
+ * Define basic shift & mask constants for manipulating NASIDs and AS values.
+ */
+#define NASID_BITMASK           (sn_hub_info->nasid_bitmask)
+#define NASID_SHIFT             (sn_hub_info->nasid_shift)
+#define AS_SHIFT                (sn_hub_info->as_shift)
+#define AS_BITMASK              0x3UL
+
+#define NASID_MASK              ((u64)NASID_BITMASK << NASID_SHIFT)
+#define AS_MASK                 ((u64)AS_BITMASK << AS_SHIFT)
+#define REGION_BITS             0xe000000000000000UL
+
+
+/*
+ * AS values. These are the same on both SHUB1 & SHUB2.
+ */
+#define AS_GET_VAL              1UL
+#define AS_AMO_VAL              2UL
+#define AS_CAC_VAL              3UL
+#define AS_GET_SPACE            (AS_GET_VAL << AS_SHIFT)
+#define AS_AMO_SPACE            (AS_AMO_VAL << AS_SHIFT)
+#define AS_CAC_SPACE            (AS_CAC_VAL << AS_SHIFT)
+
+
+/*
+ * Base addresses for various address ranges.
+ */
+#define CACHED                  0xe000000000000000UL
+#define UNCACHED                0xc000000000000000UL
+#define UNCACHED_PHYS           0x8000000000000000UL
+
+
+/* 
+ * Virtual Mode Local & Global MMR space.  
+ */
+#define SH1_LOCAL_MMR_OFFSET    0x8000000000UL
+#define SH2_LOCAL_MMR_OFFSET    0x0200000000UL
+#define LOCAL_MMR_OFFSET        (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
+#define LOCAL_MMR_SPACE         (UNCACHED | LOCAL_MMR_OFFSET)
+#define LOCAL_PHYS_MMR_SPACE    (UNCACHED_PHYS | LOCAL_MMR_OFFSET)
+
+#define SH1_GLOBAL_MMR_OFFSET   0x0800000000UL
+#define SH2_GLOBAL_MMR_OFFSET   0x0300000000UL
+#define GLOBAL_MMR_OFFSET       (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
+#define GLOBAL_MMR_SPACE        (UNCACHED | GLOBAL_MMR_OFFSET)
+
+/*
+ * Physical mode addresses
+ */
+#define GLOBAL_PHYS_MMR_SPACE   (UNCACHED_PHYS | GLOBAL_MMR_OFFSET)
+
+
+/*
+ * Clear region & AS bits.
+ */
+#define TO_PHYS_MASK            (~(REGION_BITS | AS_MASK))
+
+
+/*
+ * Misc NASID manipulation.
+ */
+#define NASID_SPACE(n)          ((u64)(n) << NASID_SHIFT)
+#define REMOTE_ADDR(n,a)        (NASID_SPACE(n) | (a))
+#define NODE_OFFSET(x)          ((x) & (NODE_ADDRSPACE_SIZE - 1))
+#define NODE_ADDRSPACE_SIZE     (1UL << AS_SHIFT)
+#define NASID_GET(x)            (int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
+#define LOCAL_MMR_ADDR(a)       (LOCAL_MMR_SPACE | (a))
+#define GLOBAL_MMR_ADDR(n,a)    (GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
+#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
+#define GLOBAL_CAC_ADDR(n,a)    (CAC_BASE | REMOTE_ADDR(n,a))
+#define CHANGE_NASID(n,x)       ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
+
+
+/* non-II mmr's start at top of big window space (4G) */
+#define BWIN_TOP                0x0000000100000000UL
+
+/*
+ * general address defines
+ */
+#define CAC_BASE                (CACHED   | AS_CAC_SPACE)
+#define AMO_BASE                (UNCACHED | AS_AMO_SPACE)
+#define GET_BASE                (CACHED   | AS_GET_SPACE)
+
+/*
+ * Convert Memory addresses between various addressing modes.
+ */
+#define TO_PHYS(x)              (TO_PHYS_MASK & (x))
+#define TO_CAC(x)               (CAC_BASE     | TO_PHYS(x))
+#define TO_AMO(x)               (AMO_BASE     | TO_PHYS(x))
+#define TO_GET(x)               (GET_BASE     | TO_PHYS(x))
+
+
+/*
+ * Covert from processor physical address to II/TIO physical address:
+ *      II - squeeze out the AS bits
+ *      TIO- requires a chiplet id in bits 38-39.  For DMA to memory,
+ *           the chiplet id is zero.  If we implement TIO-TIO dma, we might need
+ *           to insert a chiplet id into this macro.  However, it is our belief
+ *           right now that this chiplet id will be ICE, which is also zero.
+ */
+#define PHYS_TO_TIODMA(x)       ( (((u64)(x) & NASID_MASK) << 2) | NODE_OFFSET(x))
+#define PHYS_TO_DMA(x)          ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
+
+
+/*
+ * The following definitions pertain to the IO special address
+ * space.  They define the location of the big and little windows
+ * of any given node.
+ */
+#define BWIN_SIZE_BITS                  29      /* big window size: 512M */
+#define TIO_BWIN_SIZE_BITS              30      /* big window size: 1G */
+#define NODE_SWIN_BASE(n, w)            ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
+                : RAW_NODE_SWIN_BASE(n, w))
+#define NODE_IO_BASE(n)                 (GLOBAL_MMR_SPACE | NASID_SPACE(n))
+#define BWIN_SIZE                       (1UL << BWIN_SIZE_BITS)
+#define NODE_BWIN_BASE0(n)              (NODE_IO_BASE(n) + BWIN_SIZE)
+#define NODE_BWIN_BASE(n, w)            (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
+#define RAW_NODE_SWIN_BASE(n, w)        (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
+#define BWIN_WIDGET_MASK                0x7
+#define BWIN_WINDOWNUM(x)               (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
+
+#define TIO_BWIN_WINDOW_SELECT_MASK     0x7
+#define TIO_BWIN_WINDOWNUM(x)           (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
+
+
+
+/*
+ * The following definitions pertain to the IO special address
+ * space.  They define the location of the big and little windows
+ * of any given node.
+ */
+
+#define SWIN_SIZE_BITS                  24
+#define SWIN_WIDGET_MASK                0xF
+
+#define TIO_SWIN_SIZE_BITS              28
+#define TIO_SWIN_SIZE                   (1UL << TIO_SWIN_SIZE_BITS)
+#define TIO_SWIN_WIDGET_MASK            0x3
+
+/*
+ * Convert smallwindow address to xtalk address.
+ *
+ * 'addr' can be physical or virtual address, but will be converted
+ * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
+ */
+#define SWIN_WIDGETNUM(x)               (((x)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
+#define TIO_SWIN_WIDGETNUM(x)           (((x)  >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
+
+
+/*
+ * The following macros produce the correct base virtual address for
+ * the hub registers. The REMOTE_HUB_* macro produce
+ * the address for the specified hub's registers.  The intent is
+ * that the appropriate PI, MD, NI, or II register would be substituted
+ * for x.
+ *
+ *   WARNING:
+ *      When certain Hub chip workaround are defined, it's not sufficient
+ *      to dereference the *_HUB_ADDR() macros.  You should instead use
+ *      HUB_L() and HUB_S() if you must deal with pointers to hub registers.
+ *      Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
+ *      They're always safe.
+ */
+#define REMOTE_HUB_ADDR(n,x)                                            \
+        ((n & 1) ?                                                      \
+        /* TIO: */                                                      \
+        ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x)))                        \
+        : /* SHUB: */                                                   \
+        (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x)))\
+        : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x)))))
+
+
+
+#define HUB_L(x)                        (*((volatile typeof(*x) *)x))
+#define HUB_S(x,d)                      (*((volatile typeof(*x) *)x) = (d))
+
+#define REMOTE_HUB_L(n, a)              HUB_L(REMOTE_HUB_ADDR((n), (a)))
+#define REMOTE_HUB_S(n, a, d)           HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
+
+
+#endif /* _ASM_IA64_SN_ADDRS_H */
diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h
new file mode 100644
index 000000000000..7c349f07916a
--- /dev/null
+++ b/include/asm-ia64/sn/arch.h
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI specific setup.
+ *
+ * Copyright (C) 1995-1997,1999,2001-2004 Silicon Graphics, Inc.  All rights reserved.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_IA64_SN_ARCH_H
+#define _ASM_IA64_SN_ARCH_H
+
+#include <asm/types.h>
+#include <asm/percpu.h>
+#include <asm/sn/types.h>
+#include <asm/sn/sn_cpuid.h>
+
+/*
+ * The following defines attributes of the HUB chip. These attributes are
+ * frequently referenced. They are kept in the per-cpu data areas of each cpu.
+ * They are kept together in a struct to minimize cache misses.
+ */
+struct sn_hub_info_s {
+        u8 shub2;
+        u8 nasid_shift;
+        u8 as_shift;
+        u8 shub_1_1_found;
+        u16 nasid_bitmask;
+};
+DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
+#define sn_hub_info     (&__get_cpu_var(__sn_hub_info))
+#define is_shub2()      (sn_hub_info->shub2)
+#define is_shub1()      (sn_hub_info->shub2 == 0)
+
+/*
+ * Use this macro to test if shub 1.1 wars should be enabled
+ */
+#define enable_shub_wars_1_1()  (sn_hub_info->shub_1_1_found)
+
+
+/*
+ * This is the maximum number of nodes that can be part of a kernel.
+ * Effectively, it's the maximum number of compact node ids (cnodeid_t).
+ * This is not necessarily the same as MAX_NASIDS.
+ */
+#define MAX_COMPACT_NODES       2048
+#define CPUS_PER_NODE           4
+
+extern void sn_flush_all_caches(long addr, long bytes);
+
+#endif /* _ASM_IA64_SN_ARCH_H */
diff --git a/include/asm-ia64/sn/bte.h b/include/asm-ia64/sn/bte.h
new file mode 100644
index 000000000000..0ec27f99c181
--- /dev/null
+++ b/include/asm-ia64/sn/bte.h
@@ -0,0 +1,148 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2000-2004 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+
+
+#ifndef _ASM_IA64_SN_BTE_H
+#define _ASM_IA64_SN_BTE_H
+
+#include <linux/timer.h>
+#include <linux/spinlock.h>
+#include <linux/cache.h>
+#include <asm/sn/types.h>
+
+
+/* #define BTE_DEBUG */
+/* #define BTE_DEBUG_VERBOSE */
+
+#ifdef BTE_DEBUG
+#  define BTE_PRINTK(x) printk x        /* Terse */
+#  ifdef BTE_DEBUG_VERBOSE
+#    define BTE_PRINTKV(x) printk x     /* Verbose */
+#  else
+#    define BTE_PRINTKV(x)
+#  endif /* BTE_DEBUG_VERBOSE */
+#else
+#  define BTE_PRINTK(x)
+#  define BTE_PRINTKV(x)
+#endif  /* BTE_DEBUG */
+
+
+/* BTE status register only supports 16 bits for length field */
+#define BTE_LEN_BITS (16)
+#define BTE_LEN_MASK ((1 << BTE_LEN_BITS) - 1)
+#define BTE_MAX_XFER ((1 << BTE_LEN_BITS) * L1_CACHE_BYTES)
+
+
+/* Define hardware */
+#define BTES_PER_NODE 2
+
+
+/* Define hardware modes */
+#define BTE_NOTIFY (IBCT_NOTIFY)
+#define BTE_NORMAL BTE_NOTIFY
+#define BTE_ZERO_FILL (BTE_NOTIFY | IBCT_ZFIL_MODE)
+/* Use a reserved bit to let the caller specify a wait for any BTE */
+#define BTE_WACQUIRE (0x4000)
+/* Use the BTE on the node with the destination memory */
+#define BTE_USE_DEST (BTE_WACQUIRE << 1)
+/* Use any available BTE interface on any node for the transfer */
+#define BTE_USE_ANY (BTE_USE_DEST << 1)
+/* macro to force the IBCT0 value valid */
+#define BTE_VALID_MODE(x) ((x) & (IBCT_NOTIFY | IBCT_ZFIL_MODE))
+
+#define BTE_ACTIVE              (IBLS_BUSY | IBLS_ERROR)
+#define BTE_WORD_AVAILABLE      (IBLS_BUSY << 1)
+#define BTE_WORD_BUSY           (~BTE_WORD_AVAILABLE)
+
+/*
+ * Some macros to simplify reading.
+ * Start with macros to locate the BTE control registers.
+ */
+#define BTE_LNSTAT_LOAD(_bte)                                           \
+                        HUB_L(_bte->bte_base_addr)
+#define BTE_LNSTAT_STORE(_bte, _x)                                      \
+                        HUB_S(_bte->bte_base_addr, (_x))
+#define BTE_SRC_STORE(_bte, _x)                                         \
+                        HUB_S(_bte->bte_base_addr + (BTEOFF_SRC/8), (_x))
+#define BTE_DEST_STORE(_bte, _x)                                        \
+                        HUB_S(_bte->bte_base_addr + (BTEOFF_DEST/8), (_x))
+#define BTE_CTRL_STORE(_bte, _x)                                        \
+                        HUB_S(_bte->bte_base_addr + (BTEOFF_CTRL/8), (_x))
+#define BTE_NOTIF_STORE(_bte, _x)                                       \
+                        HUB_S(_bte->bte_base_addr + (BTEOFF_NOTIFY/8), (_x))
+
+
+/* Possible results from bte_copy and bte_unaligned_copy */
+/* The following error codes map into the BTE hardware codes
+ * IIO_ICRB_ECODE_* (in shubio.h). The hardware uses
+ * an error code of 0 (IIO_ICRB_ECODE_DERR), but we want zero
+ * to mean BTE_SUCCESS, so add one (BTEFAIL_OFFSET) to the error
+ * codes to give the following error codes.
+ */
+#define BTEFAIL_OFFSET  1
+
+typedef enum {
+        BTE_SUCCESS,            /* 0 is success */
+        BTEFAIL_DIR,            /* Directory error due to IIO access*/
+        BTEFAIL_POISON,         /* poison error on IO access (write to poison page) */
+        BTEFAIL_WERR,           /* Write error (ie WINV to a Read only line) */
+        BTEFAIL_ACCESS,         /* access error (protection violation) */
+        BTEFAIL_PWERR,          /* Partial Write Error */
+        BTEFAIL_PRERR,          /* Partial Read Error */
+        BTEFAIL_TOUT,           /* CRB Time out */
+        BTEFAIL_XTERR,          /* Incoming xtalk pkt had error bit */
+        BTEFAIL_NOTAVAIL,       /* BTE not available */
+} bte_result_t;
+
+
+/*
+ * Structure defining a bte.  An instance of this
+ * structure is created in the nodepda for each
+ * bte on that node (as defined by BTES_PER_NODE)
+ * This structure contains everything necessary
+ * to work with a BTE.
+ */
+struct bteinfo_s {
+        volatile u64 notify ____cacheline_aligned;
+        u64 *bte_base_addr ____cacheline_aligned;
+        spinlock_t spinlock;
+        cnodeid_t bte_cnode;    /* cnode                            */
+        int bte_error_count;    /* Number of errors encountered     */
+        int bte_num;            /* 0 --> BTE0, 1 --> BTE1           */
+        int cleanup_active;     /* Interface is locked for cleanup  */
+        volatile bte_result_t bh_error; /* error while processing   */
+        volatile u64 *most_rcnt_na;
+};
+
+
+/*
+ * Function prototypes (functions defined in bte.c, used elsewhere)
+ */
+extern bte_result_t bte_copy(u64, u64, u64, u64, void *);
+extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64);
+extern void bte_error_handler(unsigned long);
+
+#define bte_zero(dest, len, mode, notification) \
+        bte_copy(0, dest, len, ((mode) | BTE_ZERO_FILL), notification)
+
+/*
+ * The following is the prefered way of calling bte_unaligned_copy
+ * If the copy is fully cache line aligned, then bte_copy is
+ * used instead.  Since bte_copy is inlined, this saves a call
+ * stack.  NOTE: bte_copy is called synchronously and does block
+ * until the transfer is complete.  In order to get the asynch
+ * version of bte_copy, you must perform this check yourself.
+ */
+#define BTE_UNALIGNED_COPY(src, dest, len, mode)                        \
+        (((len & L1_CACHE_MASK) || (src & L1_CACHE_MASK) ||             \
+          (dest & L1_CACHE_MASK)) ?                                     \
+         bte_unaligned_copy(src, dest, len, mode) :                     \
+         bte_copy(src, dest, len, mode, NULL))
+
+
+#endif  /* _ASM_IA64_SN_BTE_H */
diff --git a/include/asm-ia64/sn/clksupport.h b/include/asm-ia64/sn/clksupport.h
new file mode 100644
index 000000000000..d340c365a824
--- /dev/null
+++ b/include/asm-ia64/sn/clksupport.h
@@ -0,0 +1,28 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+/*
+ * This file contains definitions for accessing a platform supported high resolution
+ * clock. The clock is monitonically increasing and can be accessed from any node
+ * in the system. The clock is synchronized across nodes - all nodes see the
+ * same value.
+ * 
+ *      RTC_COUNTER_ADDR - contains the address of the counter 
+ *
+ */
+
+#ifndef _ASM_IA64_SN_CLKSUPPORT_H
+#define _ASM_IA64_SN_CLKSUPPORT_H
+
+extern unsigned long sn_rtc_cycles_per_second;
+
+#define RTC_COUNTER_ADDR        ((long *)LOCAL_MMR_ADDR(SH_RTC))
+
+#define rtc_time()              (*RTC_COUNTER_ADDR)
+
+#endif /* _ASM_IA64_SN_CLKSUPPORT_H */
diff --git a/include/asm-ia64/sn/fetchop.h b/include/asm-ia64/sn/fetchop.h
new file mode 100644
index 000000000000..5f4ad8f4b5d2
--- /dev/null
+++ b/include/asm-ia64/sn/fetchop.h
@@ -0,0 +1,85 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001-2004 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_FETCHOP_H
+#define _ASM_IA64_SN_FETCHOP_H
+
+#include <linux/config.h>
+
+#define FETCHOP_BASENAME        "sgi_fetchop"
+#define FETCHOP_FULLNAME        "/dev/sgi_fetchop"
+
+
+
+#define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */
+
+#define FETCHOP_LOAD            0
+#define FETCHOP_INCREMENT       8
+#define FETCHOP_DECREMENT       16
+#define FETCHOP_CLEAR           24
+
+#define FETCHOP_STORE           0
+#define FETCHOP_AND             24
+#define FETCHOP_OR              32
+
+#define FETCHOP_CLEAR_CACHE     56
+
+#define FETCHOP_LOAD_OP(addr, op) ( \
+         *(volatile long *)((char*) (addr) + (op)))
+
+#define FETCHOP_STORE_OP(addr, op, x) ( \
+         *(volatile long *)((char*) (addr) + (op)) = (long) (x))
+
+#ifdef __KERNEL__
+
+/*
+ * Convert a region 6 (kaddr) address to the address of the fetchop variable
+ */
+#define FETCHOP_KADDR_TO_MSPEC_ADDR(kaddr)      TO_MSPEC(kaddr)
+
+
+/*
+ * Each Atomic Memory Operation (AMO formerly known as fetchop)
+ * variable is 64 bytes long.  The first 8 bytes are used.  The
+ * remaining 56 bytes are unaddressable due to the operation taking
+ * that portion of the address.
+ * 
+ * NOTE: The AMO_t _MUST_ be placed in either the first or second half
+ * of the cache line.  The cache line _MUST NOT_ be used for anything
+ * other than additional AMO_t entries.  This is because there are two
+ * addresses which reference the same physical cache line.  One will
+ * be a cached entry with the memory type bits all set.  This address
+ * may be loaded into processor cache.  The AMO_t will be referenced
+ * uncached via the memory special memory type.  If any portion of the
+ * cached cache-line is modified, when that line is flushed, it will
+ * overwrite the uncached value in physical memory and lead to
+ * inconsistency.
+ */
+typedef struct {
+        u64 variable;
+        u64 unused[7];
+} AMO_t;
+
+
+/*
+ * The following APIs are externalized to the kernel to allocate/free pages of
+ * fetchop variables.
+ *      fetchop_kalloc_page     - Allocate/initialize 1 fetchop page on the
+ *                                specified cnode. 
+ *      fetchop_kfree_page      - Free a previously allocated fetchop page
+ */
+
+unsigned long fetchop_kalloc_page(int nid);
+void fetchop_kfree_page(unsigned long maddr);
+
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IA64_SN_FETCHOP_H */
+
diff --git a/include/asm-ia64/sn/geo.h b/include/asm-ia64/sn/geo.h
new file mode 100644
index 000000000000..f566343d25f8
--- /dev/null
+++ b/include/asm-ia64/sn/geo.h
@@ -0,0 +1,124 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_GEO_H
+#define _ASM_IA64_SN_GEO_H
+
+/* The geoid_t implementation below is based loosely on the pcfg_t
+   implementation in sys/SN/promcfg.h. */
+
+/* Type declaractions */
+
+/* Size of a geoid_t structure (must be before decl. of geoid_u) */
+#define GEOID_SIZE      8       /* Would 16 be better?  The size can
+                                   be different on different platforms. */
+
+#define MAX_SLABS       0xe     /* slabs per module */
+
+typedef unsigned char   geo_type_t;
+
+/* Fields common to all substructures */
+typedef struct geo_any_s {
+    moduleid_t  module;         /* The module (box) this h/w lives in */
+    geo_type_t  type;           /* What type of h/w is named by this geoid_t */
+    slabid_t    slab;           /* The logical assembly within the module */
+} geo_any_t;
+
+/* Additional fields for particular types of hardware */
+typedef struct geo_node_s {
+    geo_any_t   any;            /* No additional fields needed */
+} geo_node_t;
+
+typedef struct geo_rtr_s {
+    geo_any_t   any;            /* No additional fields needed */
+} geo_rtr_t;
+
+typedef struct geo_iocntl_s {
+    geo_any_t   any;            /* No additional fields needed */
+} geo_iocntl_t;
+
+typedef struct geo_pcicard_s {
+    geo_iocntl_t        any;
+    char                bus;    /* Bus/widget number */
+    char                slot;   /* PCI slot number */
+} geo_pcicard_t;
+
+/* Subcomponents of a node */
+typedef struct geo_cpu_s {
+    geo_node_t  node;
+    char        slice;          /* Which CPU on the node */
+} geo_cpu_t;
+
+typedef struct geo_mem_s {
+    geo_node_t  node;
+    char        membus;         /* The memory bus on the node */
+    char        memslot;        /* The memory slot on the bus */
+} geo_mem_t;
+
+
+typedef union geoid_u {
+    geo_any_t   any;
+    geo_node_t  node;
+    geo_iocntl_t        iocntl;
+    geo_pcicard_t       pcicard;
+    geo_rtr_t   rtr;
+    geo_cpu_t   cpu;
+    geo_mem_t   mem;
+    char        padsize[GEOID_SIZE];
+} geoid_t;
+
+
+/* Preprocessor macros */
+
+#define GEO_MAX_LEN     48      /* max. formatted length, plus some pad:
+                                   module/001c07/slab/5/node/memory/2/slot/4 */
+
+/* Values for geo_type_t */
+#define GEO_TYPE_INVALID        0
+#define GEO_TYPE_MODULE         1
+#define GEO_TYPE_NODE           2
+#define GEO_TYPE_RTR            3
+#define GEO_TYPE_IOCNTL         4
+#define GEO_TYPE_IOCARD         5
+#define GEO_TYPE_CPU            6
+#define GEO_TYPE_MEM            7
+#define GEO_TYPE_MAX            (GEO_TYPE_MEM+1)
+
+/* Parameter for hwcfg_format_geoid_compt() */
+#define GEO_COMPT_MODULE        1
+#define GEO_COMPT_SLAB          2
+#define GEO_COMPT_IOBUS         3
+#define GEO_COMPT_IOSLOT        4
+#define GEO_COMPT_CPU           5
+#define GEO_COMPT_MEMBUS        6
+#define GEO_COMPT_MEMSLOT       7
+
+#define GEO_INVALID_STR         "<invalid>"
+
+#define INVALID_NASID           ((nasid_t)-1)
+#define INVALID_CNODEID         ((cnodeid_t)-1)
+#define INVALID_PNODEID         ((pnodeid_t)-1)
+#define INVALID_SLAB            (slabid_t)-1
+#define INVALID_MODULE          ((moduleid_t)-1)
+#define INVALID_PARTID          ((partid_t)-1)
+
+static inline slabid_t geo_slab(geoid_t g)
+{
+        return (g.any.type == GEO_TYPE_INVALID) ?
+                INVALID_SLAB : g.any.slab;
+}
+
+static inline moduleid_t geo_module(geoid_t g)
+{
+        return (g.any.type == GEO_TYPE_INVALID) ?
+                INVALID_MODULE : g.any.module;
+}
+
+extern geoid_t cnodeid_get_geoid(cnodeid_t cnode);
+
+#endif /* _ASM_IA64_SN_GEO_H */
diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h
new file mode 100644
index 000000000000..e51471fb0867
--- /dev/null
+++ b/include/asm-ia64/sn/intr.h
@@ -0,0 +1,56 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_INTR_H
+#define _ASM_IA64_SN_INTR_H
+
+#define SGI_UART_VECTOR         (0xe9)
+#define SGI_PCIBR_ERROR         (0x33)
+
+/* Reserved IRQs : Note, not to exceed IA64_SN2_FIRST_DEVICE_VECTOR */
+#define SGI_XPC_ACTIVATE                (0x30)
+#define SGI_II_ERROR                    (0x31)
+#define SGI_XBOW_ERROR                  (0x32)
+#define SGI_PCIBR_ERROR                 (0x33)
+#define SGI_ACPI_SCI_INT                (0x34)
+#define SGI_TIOCA_ERROR                 (0x35)
+#define SGI_TIO_ERROR                   (0x36)
+#define SGI_TIOCX_ERROR                 (0x37)
+#define SGI_MMTIMER_VECTOR              (0x38)
+#define SGI_XPC_NOTIFY                  (0xe7)
+
+#define IA64_SN2_FIRST_DEVICE_VECTOR    (0x3c)
+#define IA64_SN2_LAST_DEVICE_VECTOR     (0xe6)
+
+#define SN2_IRQ_RESERVED        (0x1)
+#define SN2_IRQ_CONNECTED       (0x2)
+#define SN2_IRQ_SHARED          (0x4)
+
+// The SN PROM irq struct
+struct sn_irq_info {
+        struct sn_irq_info *irq_next;   /* sharing irq list          */
+        short           irq_nasid;      /* Nasid IRQ is assigned to  */
+        int             irq_slice;      /* slice IRQ is assigned to  */
+        int             irq_cpuid;      /* kernel logical cpuid      */
+        int             irq_irq;        /* the IRQ number */
+        int             irq_int_bit;    /* Bridge interrupt pin */
+        uint64_t        irq_xtalkaddr;  /* xtalkaddr IRQ is sent to  */
+        int             irq_bridge_type;/* pciio asic type (pciio.h) */
+        void           *irq_bridge;     /* bridge generating irq     */
+        void           *irq_pciioinfo;  /* associated pciio_info_t   */
+        int             irq_last_intr;  /* For Shub lb lost intr WAR */
+        int             irq_cookie;     /* unique cookie             */
+        int             irq_flags;      /* flags */
+        int             irq_share_cnt;  /* num devices sharing IRQ   */
+};
+
+extern void sn_send_IPI_phys(int, long, int, int);
+
+#define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector)
+
+#endif /* _ASM_IA64_SN_INTR_H */
diff --git a/include/asm-ia64/sn/io.h b/include/asm-ia64/sn/io.h
new file mode 100644
index 000000000000..42209733f6b1
--- /dev/null
+++ b/include/asm-ia64/sn/io.h
@@ -0,0 +1,265 @@
+/* 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_SN_IO_H
+#define _ASM_SN_IO_H
+#include <linux/compiler.h>
+#include <asm/intrinsics.h>
+
+extern void * sn_io_addr(unsigned long port) __attribute_const__; /* Forward definition */
+extern void __sn_mmiowb(void); /* Forward definition */
+
+extern int numionodes;
+
+#define __sn_mf_a()   ia64_mfa()
+
+extern void sn_dma_flush(unsigned long);
+
+#define __sn_inb ___sn_inb
+#define __sn_inw ___sn_inw
+#define __sn_inl ___sn_inl
+#define __sn_outb ___sn_outb
+#define __sn_outw ___sn_outw
+#define __sn_outl ___sn_outl
+#define __sn_readb ___sn_readb
+#define __sn_readw ___sn_readw
+#define __sn_readl ___sn_readl
+#define __sn_readq ___sn_readq
+#define __sn_readb_relaxed ___sn_readb_relaxed
+#define __sn_readw_relaxed ___sn_readw_relaxed
+#define __sn_readl_relaxed ___sn_readl_relaxed
+#define __sn_readq_relaxed ___sn_readq_relaxed
+
+/*
+ * The following routines are SN Platform specific, called when
+ * a reference is made to inX/outX set macros.  SN Platform
+ * inX set of macros ensures that Posted DMA writes on the
+ * Bridge is flushed.
+ *
+ * The routines should be self explainatory.
+ */
+
+static inline unsigned int
+___sn_inb (unsigned long port)
+{
+        volatile unsigned char *addr;
+        unsigned char ret = -1;
+
+        if ((addr = sn_io_addr(port))) {
+                ret = *addr;
+                __sn_mf_a();
+                sn_dma_flush((unsigned long)addr);
+        }
+        return ret;
+}
+
+static inline unsigned int
+___sn_inw (unsigned long port)
+{
+        volatile unsigned short *addr;
+        unsigned short ret = -1;
+
+        if ((addr = sn_io_addr(port))) {
+                ret = *addr;
+                __sn_mf_a();
+                sn_dma_flush((unsigned long)addr);
+        }
+        return ret;
+}
+
+static inline unsigned int
+___sn_inl (unsigned long port)
+{
+        volatile unsigned int *addr;
+        unsigned int ret = -1;
+
+        if ((addr = sn_io_addr(port))) {
+                ret = *addr;
+                __sn_mf_a();
+                sn_dma_flush((unsigned long)addr);
+        }
+        return ret;
+}
+
+static inline void
+___sn_outb (unsigned char val, unsigned long port)
+{
+        volatile unsigned char *addr;
+
+        if ((addr = sn_io_addr(port))) {
+                *addr = val;
+                __sn_mmiowb();
+        }
+}
+
+static inline void
+___sn_outw (unsigned short val, unsigned long port)
+{
+        volatile unsigned short *addr;
+
+        if ((addr = sn_io_addr(port))) {
+                *addr = val;
+                __sn_mmiowb();
+        }
+}
+
+static inline void
+___sn_outl (unsigned int val, unsigned long port)
+{
+        volatile unsigned int *addr;
+
+        if ((addr = sn_io_addr(port))) {
+                *addr = val;
+                __sn_mmiowb();
+        }
+}
+
+/*
+ * The following routines are SN Platform specific, called when 
+ * a reference is made to readX/writeX set macros.  SN Platform 
+ * readX set of macros ensures that Posted DMA writes on the 
+ * Bridge is flushed.
+ * 
+ * The routines should be self explainatory.
+ */
+
+static inline unsigned char
+___sn_readb (const volatile void __iomem *addr)
+{
+        unsigned char val;
+
+        val = *(volatile unsigned char __force *)addr;
+        __sn_mf_a();
+        sn_dma_flush((unsigned long)addr);
+        return val;
+}
+
+static inline unsigned short
+___sn_readw (const volatile void __iomem *addr)
+{
+        unsigned short val;
+
+        val = *(volatile unsigned short __force *)addr;
+        __sn_mf_a();
+        sn_dma_flush((unsigned long)addr);
+        return val;
+}
+
+static inline unsigned int
+___sn_readl (const volatile void __iomem *addr)
+{
+        unsigned int val;
+
+        val = *(volatile unsigned int __force *)addr;
+        __sn_mf_a();
+        sn_dma_flush((unsigned long)addr);
+        return val;
+}
+
+static inline unsigned long
+___sn_readq (const volatile void __iomem *addr)
+{
+        unsigned long val;
+
+        val = *(volatile unsigned long __force *)addr;
+        __sn_mf_a();
+        sn_dma_flush((unsigned long)addr);
+        return val;
+}
+
+/*
+ * For generic and SN2 kernels, we have a set of fast access
+ * PIO macros.  These macros are provided on SN Platform
+ * because the normal inX and readX macros perform an
+ * additional task of flushing Post DMA request on the Bridge.
+ *
+ * These routines should be self explainatory.
+ */
+
+static inline unsigned int
+sn_inb_fast (unsigned long port)
+{
+        volatile unsigned char *addr = (unsigned char *)port;
+        unsigned char ret;
+
+        ret = *addr;
+        __sn_mf_a();
+        return ret;
+}
+
+static inline unsigned int
+sn_inw_fast (unsigned long port)
+{
+        volatile unsigned short *addr = (unsigned short *)port;
+        unsigned short ret;
+
+        ret = *addr;
+        __sn_mf_a();
+        return ret;
+}
+
+static inline unsigned int
+sn_inl_fast (unsigned long port)
+{
+        volatile unsigned int *addr = (unsigned int *)port;
+        unsigned int ret;
+
+        ret = *addr;
+        __sn_mf_a();
+        return ret;
+}
+
+static inline unsigned char
+___sn_readb_relaxed (const volatile void __iomem *addr)
+{
+        return *(volatile unsigned char __force *)addr;
+}
+
+static inline unsigned short
+___sn_readw_relaxed (const volatile void __iomem *addr)
+{
+        return *(volatile unsigned short __force *)addr;
+}
+
+static inline unsigned int
+___sn_readl_relaxed (const volatile void __iomem *addr)
+{
+        return *(volatile unsigned int __force *) addr;
+}
+
+static inline unsigned long
+___sn_readq_relaxed (const volatile void __iomem *addr)
+{
+        return *(volatile unsigned long __force *) addr;
+}
+
+struct pci_dev;
+
+static inline int
+sn_pci_set_vchan(struct pci_dev *pci_dev, unsigned long *addr, int vchan)
+{
+
+        if (vchan > 1) {
+                return -1;
+        }
+
+        if (!(*addr >> 32))     /* Using a mask here would be cleaner */
+                return 0;       /* but this generates better code */
+
+        if (vchan == 1) {
+                /* Set Bit 57 */
+                *addr |= (1UL << 57);
+        } else {
+                /* Clear Bit 57 */
+                *addr &= ~(1UL << 57);
+        }
+
+        return 0;
+}
+
+#endif  /* _ASM_SN_IO_H */
diff --git a/include/asm-ia64/sn/klconfig.h b/include/asm-ia64/sn/klconfig.h
new file mode 100644
index 000000000000..9f920c70a62a
--- /dev/null
+++ b/include/asm-ia64/sn/klconfig.h
@@ -0,0 +1,272 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/klconfig.h>.
+ *
+ * Copyright (C) 1992-1997,1999,2001-2004 Silicon Graphics, Inc.  All Rights Reserved.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_IA64_SN_KLCONFIG_H
+#define _ASM_IA64_SN_KLCONFIG_H
+
+/*
+ * The KLCONFIG structures store info about the various BOARDs found
+ * during Hardware Discovery. In addition, it stores info about the
+ * components found on the BOARDs.
+ */
+
+typedef s32 klconf_off_t;
+
+
+/* Functions/macros needed to use this structure */
+
+typedef struct kl_config_hdr {
+        char            pad[20];
+        klconf_off_t    ch_board_info;  /* the link list of boards */
+        char            pad0[88];
+} kl_config_hdr_t;
+
+
+#define NODE_OFFSET_TO_LBOARD(nasid,off)        (lboard_t*)(GLOBAL_CAC_ADDR((nasid), (off)))
+
+/*
+ * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
+ * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to 
+ * the LOCAL/current NODE. REMOTE means it is attached to a different
+ * node.(TBD - Need a way to treat ROUTER boards.)
+ *
+ * There are 2 different structures to represent these boards -
+ * lboard - Local board, rboard - remote board. These 2 structures
+ * can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer
+ * Figure below). The first byte of the rboard or lboard structure
+ * is used to find out its type - no unions are used.
+ * If it is a lboard, then the config info of this board will be found
+ * on the local node. (LOCAL NODE BASE + offset value gives pointer to 
+ * the structure.
+ * If it is a rboard, the local structure contains the node number
+ * and the offset of the beginning of the LINKED LIST on the remote node.
+ * The details of the hardware on a remote node can be built locally,
+ * if required, by reading the LINKED LIST on the remote node and 
+ * ignoring all the rboards on that node.
+ *
+ * The local node uses the REMOTE NODE NUMBER + OFFSET to point to the 
+ * First board info on the remote node. The remote node list is 
+ * traversed as the local list, using the REMOTE BASE ADDRESS and not
+ * the local base address and ignoring all rboard values.
+ *
+ * 
+ KLCONFIG
+
+ +------------+      +------------+      +------------+      +------------+
+ |  lboard    |  +-->|   lboard   |  +-->|   rboard   |  +-->|   lboard   |
+ +------------+  |   +------------+  |   +------------+  |   +------------+
+ | board info |  |   | board info |  |   |errinfo,bptr|  |   | board info |
+ +------------+  |   +------------+  |   +------------+  |   +------------+
+ | offset     |--+   |  offset    |--+   |  offset    |--+   |offset=NULL |
+ +------------+      +------------+      +------------+      +------------+
+
+
+ +------------+
+ | board info |
+ +------------+       +--------------------------------+
+ | compt 1    |------>| type, rev, diaginfo, size ...  |  (CPU)
+ +------------+       +--------------------------------+
+ | compt 2    |--+
+ +------------+  |    +--------------------------------+
+ |  ...       |  +--->| type, rev, diaginfo, size ...  |  (MEM_BANK)
+ +------------+       +--------------------------------+
+ | errinfo    |--+
+ +------------+  |    +--------------------------------+
+                 +--->|r/l brd errinfo,compt err flags |
+                      +--------------------------------+
+
+ *
+ * Each BOARD consists of COMPONENTs and the BOARD structure has 
+ * pointers (offsets) to its COMPONENT structure.
+ * The COMPONENT structure has version info, size and speed info, revision,
+ * error info and the NIC info. This structure can accommodate any
+ * BOARD with arbitrary COMPONENT composition.
+ *
+ * The ERRORINFO part of each BOARD has error information
+ * that describes errors about the BOARD itself. It also has flags to
+ * indicate the COMPONENT(s) on the board that have errors. The error 
+ * information specific to the COMPONENT is present in the respective 
+ * COMPONENT structure.
+ *
+ * The ERRORINFO structure is also treated like a COMPONENT, ie. the 
+ * BOARD has pointers(offset) to the ERRORINFO structure. The rboard
+ * structure also has a pointer to the ERRORINFO structure. This is 
+ * the place to store ERRORINFO about a REMOTE NODE, if the HUB on
+ * that NODE is not working or if the REMOTE MEMORY is BAD. In cases where 
+ * only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can
+ * be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info 
+ * which is present on the REMOTE NODE.(TBD)
+ * REMOTE ERRINFO can be stored on any of the nearest nodes 
+ * or on all the nearest nodes.(TBD)
+ * Like BOARD structures, REMOTE ERRINFO structures can be built locally
+ * using the rboard errinfo pointer.
+ *
+ * In order to get useful information from this Data organization, a set of
+ * interface routines are provided (TBD). The important thing to remember while
+ * manipulating the structures, is that, the NODE number information should
+ * be used. If the NODE is non-zero (remote) then each offset should
+ * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR. 
+ * This includes offsets for BOARDS, COMPONENTS and ERRORINFO.
+ * 
+ * Note that these structures do not provide much info about connectivity.
+ * That info will be part of HWGRAPH, which is an extension of the cfg_t
+ * data structure. (ref IP27prom/cfg.h) It has to be extended to include
+ * the IO part of the Network(TBD).
+ *
+ * The data structures below define the above concepts.
+ */
+
+
+/*
+ * BOARD classes
+ */
+
+#define KLCLASS_MASK    0xf0   
+#define KLCLASS_NONE    0x00
+#define KLCLASS_NODE    0x10             /* CPU, Memory and HUB board */
+#define KLCLASS_CPU     KLCLASS_NODE    
+#define KLCLASS_IO      0x20             /* BaseIO, 4 ch SCSI, ethernet, FDDI 
+                                            and the non-graphics widget boards */
+#define KLCLASS_ROUTER  0x30             /* Router board */
+#define KLCLASS_MIDPLANE 0x40            /* We need to treat this as a board
+                                            so that we can record error info */
+#define KLCLASS_IOBRICK 0x70            /* IP35 iobrick */
+#define KLCLASS_MAX     8               /* Bump this if a new CLASS is added */
+
+#define KLCLASS(_x) ((_x) & KLCLASS_MASK)
+
+
+/*
+ * board types
+ */
+
+#define KLTYPE_MASK     0x0f
+#define KLTYPE(_x)      ((_x) & KLTYPE_MASK)
+
+#define KLTYPE_SNIA     (KLCLASS_CPU | 0x1)
+#define KLTYPE_TIO      (KLCLASS_CPU | 0x2)
+
+#define KLTYPE_ROUTER     (KLCLASS_ROUTER | 0x1)
+#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
+#define KLTYPE_REPEATER_ROUTER (KLCLASS_ROUTER | 0x4)
+
+#define KLTYPE_IOBRICK_XBOW     (KLCLASS_MIDPLANE | 0x2)
+
+#define KLTYPE_IOBRICK          (KLCLASS_IOBRICK | 0x0)
+#define KLTYPE_NBRICK           (KLCLASS_IOBRICK | 0x4)
+#define KLTYPE_PXBRICK          (KLCLASS_IOBRICK | 0x6)
+#define KLTYPE_IXBRICK          (KLCLASS_IOBRICK | 0x7)
+#define KLTYPE_CGBRICK          (KLCLASS_IOBRICK | 0x8)
+#define KLTYPE_OPUSBRICK        (KLCLASS_IOBRICK | 0x9)
+#define KLTYPE_SABRICK          (KLCLASS_IOBRICK | 0xa)
+#define KLTYPE_IABRICK          (KLCLASS_IOBRICK | 0xb)
+#define KLTYPE_PABRICK          (KLCLASS_IOBRICK | 0xc)
+#define KLTYPE_GABRICK          (KLCLASS_IOBRICK | 0xd)
+
+
+/* 
+ * board structures
+ */
+
+#define MAX_COMPTS_PER_BRD 24
+
+typedef struct lboard_s {
+        klconf_off_t    brd_next_any;     /* Next BOARD */
+        unsigned char   struct_type;      /* type of structure, local or remote */
+        unsigned char   brd_type;         /* type+class */
+        unsigned char   brd_sversion;     /* version of this structure */
+        unsigned char   brd_brevision;    /* board revision */
+        unsigned char   brd_promver;      /* board prom version, if any */
+        unsigned char   brd_flags;        /* Enabled, Disabled etc */
+        unsigned char   brd_slot;         /* slot number */
+        unsigned short  brd_debugsw;      /* Debug switches */
+        geoid_t         brd_geoid;        /* geo id */
+        partid_t        brd_partition;    /* Partition number */
+        unsigned short  brd_diagval;      /* diagnostic value */
+        unsigned short  brd_diagparm;     /* diagnostic parameter */
+        unsigned char   brd_inventory;    /* inventory history */
+        unsigned char   brd_numcompts;    /* Number of components */
+        nic_t           brd_nic;          /* Number in CAN */
+        nasid_t         brd_nasid;        /* passed parameter */
+        klconf_off_t    brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
+        klconf_off_t    brd_errinfo;      /* Board's error information */
+        struct lboard_s *brd_parent;      /* Logical parent for this brd */
+        char            pad0[4];
+        unsigned char   brd_confidence;   /* confidence that the board is bad */
+        nasid_t         brd_owner;        /* who owns this board */
+        unsigned char   brd_nic_flags;    /* To handle 8 more NICs */
+        char            pad1[24];         /* future expansion */
+        char            brd_name[32];
+        nasid_t         brd_next_same_host; /* host of next brd w/same nasid */
+        klconf_off_t    brd_next_same;    /* Next BOARD with same nasid */
+} lboard_t;
+
+#define KLCF_NUM_COMPS(_brd)    ((_brd)->brd_numcompts)
+#define NODE_OFFSET_TO_KLINFO(n,off)    ((klinfo_t*) TO_NODE_CAC(n,off))
+#define KLCF_NEXT(_brd)         \
+        ((_brd)->brd_next_same ?     \
+         (NODE_OFFSET_TO_LBOARD((_brd)->brd_next_same_host, (_brd)->brd_next_same)): NULL)
+#define KLCF_NEXT_ANY(_brd)         \
+        ((_brd)->brd_next_any ?     \
+         (NODE_OFFSET_TO_LBOARD(NASID_GET(_brd), (_brd)->brd_next_any)): NULL)
+#define KLCF_COMP(_brd, _ndx)   \
+                ((((_brd)->brd_compts[(_ndx)]) == 0) ? 0 : \
+                        (NODE_OFFSET_TO_KLINFO(NASID_GET(_brd), (_brd)->brd_compts[(_ndx)])))
+
+
+/*
+ * Generic info structure. This stores common info about a 
+ * component.
+ */
+ 
+typedef struct klinfo_s {                  /* Generic info */
+        unsigned char   struct_type;       /* type of this structure */
+        unsigned char   struct_version;    /* version of this structure */
+        unsigned char   flags;            /* Enabled, disabled etc */
+        unsigned char   revision;         /* component revision */
+        unsigned short  diagval;          /* result of diagnostics */
+        unsigned short  diagparm;         /* diagnostic parameter */
+        unsigned char   inventory;        /* previous inventory status */
+        unsigned short  partid;            /* widget part number */
+        nic_t           nic;              /* MUst be aligned properly */
+        unsigned char   physid;           /* physical id of component */
+        unsigned int    virtid;           /* virtual id as seen by system */
+        unsigned char   widid;            /* Widget id - if applicable */
+        nasid_t         nasid;            /* node number - from parent */
+        char            pad1;             /* pad out structure. */
+        char            pad2;             /* pad out structure. */
+        void            *data;
+        klconf_off_t    errinfo;          /* component specific errors */
+        unsigned short  pad3;             /* pci fields have moved over to */
+        unsigned short  pad4;             /* klbri_t */
+} klinfo_t ;
+
+
+static inline lboard_t *find_lboard_any(lboard_t * start, unsigned char brd_type)
+{
+        /* Search all boards stored on this node. */
+
+        while (start) {
+                if (start->brd_type == brd_type)
+                        return start;
+                start = KLCF_NEXT_ANY(start);
+        }
+        /* Didn't find it. */
+        return (lboard_t *) NULL;
+}
+
+
+/* external declarations of Linux kernel functions. */
+
+extern lboard_t *root_lboard[];
+extern klinfo_t *find_component(lboard_t *brd, klinfo_t *kli, unsigned char type);
+extern klinfo_t *find_first_component(lboard_t *brd, unsigned char type);
+
+#endif /* _ASM_IA64_SN_KLCONFIG_H */
diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h
new file mode 100644
index 000000000000..d5dbd55e44b5
--- /dev/null
+++ b/include/asm-ia64/sn/l1.h
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+
+#ifndef _ASM_IA64_SN_L1_H
+#define _ASM_IA64_SN_L1_H
+
+/* brick type response codes */
+#define L1_BRICKTYPE_PX         0x23            /* # */
+#define L1_BRICKTYPE_PE         0x25            /* % */
+#define L1_BRICKTYPE_N_p0       0x26            /* & */
+#define L1_BRICKTYPE_IP45       0x34            /* 4 */
+#define L1_BRICKTYPE_IP41       0x35            /* 5 */
+#define L1_BRICKTYPE_TWISTER    0x36            /* 6 */ /* IP53 & ROUTER */
+#define L1_BRICKTYPE_IX         0x3d            /* = */
+#define L1_BRICKTYPE_IP34       0x61            /* a */
+#define L1_BRICKTYPE_GA         0x62            /* b */
+#define L1_BRICKTYPE_C          0x63            /* c */
+#define L1_BRICKTYPE_OPUS_TIO   0x66            /* f */
+#define L1_BRICKTYPE_I          0x69            /* i */
+#define L1_BRICKTYPE_N          0x6e            /* n */
+#define L1_BRICKTYPE_OPUS       0x6f            /* o */
+#define L1_BRICKTYPE_P          0x70            /* p */
+#define L1_BRICKTYPE_R          0x72            /* r */
+#define L1_BRICKTYPE_CHI_CG     0x76            /* v */
+#define L1_BRICKTYPE_X          0x78            /* x */
+#define L1_BRICKTYPE_X2         0x79            /* y */
+#define L1_BRICKTYPE_SA         0x5e            /* ^ */ /* TIO bringup brick */
+#define L1_BRICKTYPE_PA         0x6a            /* j */
+#define L1_BRICKTYPE_IA         0x6b            /* k */
+
+#endif /* _ASM_IA64_SN_L1_H */
diff --git a/include/asm-ia64/sn/leds.h b/include/asm-ia64/sn/leds.h
new file mode 100644
index 000000000000..66cf8c4d92c9
--- /dev/null
+++ b/include/asm-ia64/sn/leds.h
@@ -0,0 +1,33 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_LEDS_H
+#define _ASM_IA64_SN_LEDS_H
+
+#include <asm/sn/addrs.h>
+#include <asm/sn/pda.h>
+#include <asm/sn/shub_mmr.h>
+
+#define LED0            (LOCAL_MMR_ADDR(SH_REAL_JUNK_BUS_LED0))
+#define LED_CPU_SHIFT   16
+
+#define LED_CPU_HEARTBEAT       0x01
+#define LED_CPU_ACTIVITY        0x02
+#define LED_ALWAYS_SET          0x00
+
+/*
+ * Basic macros for flashing the LEDS on an SGI SN.
+ */
+
+static __inline__ void
+set_led_bits(u8 value, u8 mask)
+{
+        pda->led_state = (pda->led_state & ~mask) | (value & mask);
+        *pda->led_address = (short) pda->led_state;
+}
+
+#endif /* _ASM_IA64_SN_LEDS_H */
+
diff --git a/include/asm-ia64/sn/module.h b/include/asm-ia64/sn/module.h
new file mode 100644
index 000000000000..734e980ece2f
--- /dev/null
+++ b/include/asm-ia64/sn/module.h
@@ -0,0 +1,127 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_MODULE_H
+#define _ASM_IA64_SN_MODULE_H
+
+/* parameter for format_module_id() */
+#define MODULE_FORMAT_BRIEF     1
+#define MODULE_FORMAT_LONG      2
+#define MODULE_FORMAT_LCD       3
+
+/*
+ *      Module id format
+ *
+ *      31-16   Rack ID (encoded class, group, number - 16-bit unsigned int)
+ *       15-8   Brick type (8-bit ascii character)
+ *        7-0   Bay (brick position in rack (0-63) - 8-bit unsigned int)
+ *
+ */
+
+/*
+ * Macros for getting the brick type
+ */
+#define MODULE_BTYPE_MASK       0xff00
+#define MODULE_BTYPE_SHFT       8
+#define MODULE_GET_BTYPE(_m)    (((_m) & MODULE_BTYPE_MASK) >> MODULE_BTYPE_SHFT)
+#define MODULE_BT_TO_CHAR(_b)   ((char)(_b))
+#define MODULE_GET_BTCHAR(_m)   (MODULE_BT_TO_CHAR(MODULE_GET_BTYPE(_m)))
+
+/*
+ * Macros for getting the rack ID.
+ */
+#define MODULE_RACK_MASK        0xffff0000
+#define MODULE_RACK_SHFT        16
+#define MODULE_GET_RACK(_m)     (((_m) & MODULE_RACK_MASK) >> MODULE_RACK_SHFT)
+
+/*
+ * Macros for getting the brick position
+ */
+#define MODULE_BPOS_MASK        0x00ff
+#define MODULE_BPOS_SHFT        0
+#define MODULE_GET_BPOS(_m)     (((_m) & MODULE_BPOS_MASK) >> MODULE_BPOS_SHFT)
+
+/*
+ * Macros for encoding and decoding rack IDs
+ * A rack number consists of three parts:
+ *   class (0==CPU/mixed, 1==I/O), group, number
+ *
+ * Rack number is stored just as it is displayed on the screen:
+ * a 3-decimal-digit number.
+ */
+#define RACK_CLASS_DVDR         100
+#define RACK_GROUP_DVDR         10
+#define RACK_NUM_DVDR           1
+
+#define RACK_CREATE_RACKID(_c, _g, _n)  ((_c) * RACK_CLASS_DVDR +       \
+        (_g) * RACK_GROUP_DVDR + (_n) * RACK_NUM_DVDR)
+
+#define RACK_GET_CLASS(_r)              ((_r) / RACK_CLASS_DVDR)
+#define RACK_GET_GROUP(_r)              (((_r) - RACK_GET_CLASS(_r) *   \
+            RACK_CLASS_DVDR) / RACK_GROUP_DVDR)
+#define RACK_GET_NUM(_r)                (((_r) - RACK_GET_CLASS(_r) *   \
+            RACK_CLASS_DVDR - RACK_GET_GROUP(_r) *      \
+            RACK_GROUP_DVDR) / RACK_NUM_DVDR)
+
+/*
+ * Macros for encoding and decoding rack IDs
+ * A rack number consists of three parts:
+ *   class      1 bit, 0==CPU/mixed, 1==I/O
+ *   group      2 bits for CPU/mixed, 3 bits for I/O
+ *   number     3 bits for CPU/mixed, 2 bits for I/O (1 based)
+ */
+#define RACK_GROUP_BITS(_r)     (RACK_GET_CLASS(_r) ? 3 : 2)
+#define RACK_NUM_BITS(_r)       (RACK_GET_CLASS(_r) ? 2 : 3)
+
+#define RACK_CLASS_MASK(_r)     0x20
+#define RACK_CLASS_SHFT(_r)     5
+#define RACK_ADD_CLASS(_r, _c)  \
+        ((_r) |= (_c) << RACK_CLASS_SHFT(_r) & RACK_CLASS_MASK(_r))
+
+#define RACK_GROUP_SHFT(_r)     RACK_NUM_BITS(_r)
+#define RACK_GROUP_MASK(_r)     \
+        ( (((unsigned)1<<RACK_GROUP_BITS(_r)) - 1) << RACK_GROUP_SHFT(_r) )
+#define RACK_ADD_GROUP(_r, _g)  \
+        ((_r) |= (_g) << RACK_GROUP_SHFT(_r) & RACK_GROUP_MASK(_r))
+
+#define RACK_NUM_SHFT(_r)       0
+#define RACK_NUM_MASK(_r)       \
+        ( (((unsigned)1<<RACK_NUM_BITS(_r)) - 1) << RACK_NUM_SHFT(_r) )
+#define RACK_ADD_NUM(_r, _n)    \
+        ((_r) |= ((_n) - 1) << RACK_NUM_SHFT(_r) & RACK_NUM_MASK(_r))
+
+
+/*
+ * Brick type definitions
+ */
+#define MAX_BRICK_TYPES         256 /* brick type is stored as uchar */
+
+extern char brick_types[];
+
+#define MODULE_CBRICK           0
+#define MODULE_RBRICK           1
+#define MODULE_IBRICK           2
+#define MODULE_KBRICK           3
+#define MODULE_XBRICK           4
+#define MODULE_DBRICK           5
+#define MODULE_PBRICK           6
+#define MODULE_NBRICK           7
+#define MODULE_PEBRICK          8
+#define MODULE_PXBRICK          9
+#define MODULE_IXBRICK          10
+#define MODULE_CGBRICK          11
+#define MODULE_OPUSBRICK        12
+#define MODULE_SABRICK          13      /* TIO BringUp Brick */
+#define MODULE_IABRICK          14
+#define MODULE_PABRICK          15
+#define MODULE_GABRICK          16
+#define MODULE_OPUS_TIO         17      /* OPUS TIO Riser */
+
+extern char brick_types[];
+extern void format_module_id(char *, moduleid_t, int);
+
+#endif /* _ASM_IA64_SN_MODULE_H */
diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h
new file mode 100644
index 000000000000..2fbde33656e6
--- /dev/null
+++ b/include/asm-ia64/sn/nodepda.h
@@ -0,0 +1,86 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_NODEPDA_H
+#define _ASM_IA64_SN_NODEPDA_H
+
+
+#include <asm/semaphore.h>
+#include <asm/irq.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/pda.h>
+#include <asm/sn/bte.h>
+
+/*
+ * NUMA Node-Specific Data structures are defined in this file.
+ * In particular, this is the location of the node PDA.
+ * A pointer to the right node PDA is saved in each CPU PDA.
+ */
+
+/*
+ * Node-specific data structure.
+ *
+ * One of these structures is allocated on each node of a NUMA system.
+ *
+ * This structure provides a convenient way of keeping together 
+ * all per-node data structures. 
+ */
+struct phys_cpuid {
+        short                   nasid;
+        char                    subnode;
+        char                    slice;
+};
+
+struct nodepda_s {
+        void            *pdinfo;        /* Platform-dependent per-node info */
+        spinlock_t              bist_lock;
+
+        /*
+         * The BTEs on this node are shared by the local cpus
+         */
+        struct bteinfo_s        bte_if[BTES_PER_NODE];  /* Virtual Interface */
+        struct timer_list       bte_recovery_timer;
+        spinlock_t              bte_recovery_lock;
+
+        /* 
+         * Array of pointers to the nodepdas for each node.
+         */
+        struct nodepda_s        *pernode_pdaindr[MAX_COMPACT_NODES]; 
+
+        /*
+         * Array of physical cpu identifiers. Indexed by cpuid.
+         */
+        struct phys_cpuid       phys_cpuid[NR_CPUS];
+};
+
+typedef struct nodepda_s nodepda_t;
+
+/*
+ * Access Functions for node PDA.
+ * Since there is one nodepda for each node, we need a convenient mechanism
+ * to access these nodepdas without cluttering code with #ifdefs.
+ * The next set of definitions provides this.
+ * Routines are expected to use 
+ *
+ *      nodepda                 -> to access node PDA for the node on which code is running
+ *      subnodepda              -> to access subnode PDA for the subnode on which code is running
+ *
+ *      NODEPDA(cnode)          -> to access node PDA for cnodeid 
+ *      SUBNODEPDA(cnode,sn)    -> to access subnode PDA for cnodeid/subnode
+ */
+
+#define nodepda         pda->p_nodepda          /* Ptr to this node's PDA */
+#define NODEPDA(cnode)          (nodepda->pernode_pdaindr[cnode])
+
+/*
+ * Check if given a compact node id the corresponding node has all the
+ * cpus disabled. 
+ */
+#define is_headless_node(cnode)         (nr_cpus_node(cnode) == 0)
+
+#endif /* _ASM_IA64_SN_NODEPDA_H */
diff --git a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h
new file mode 100644
index 000000000000..e940d3647c80
--- /dev/null
+++ b/include/asm-ia64/sn/pda.h
@@ -0,0 +1,80 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PDA_H
+#define _ASM_IA64_SN_PDA_H
+
+#include <linux/cache.h>
+#include <asm/percpu.h>
+#include <asm/system.h>
+#include <asm/sn/bte.h>
+
+
+/*
+ * CPU-specific data structure.
+ *
+ * One of these structures is allocated for each cpu of a NUMA system.
+ *
+ * This structure provides a convenient way of keeping together 
+ * all SN per-cpu data structures. 
+ */
+
+typedef struct pda_s {
+
+        /* Having a pointer in the begining of PDA tends to increase
+         * the chance of having this pointer in cache. (Yes something
+         * else gets pushed out). Doing this reduces the number of memory
+         * access to all nodepda variables to be one
+         */
+        struct nodepda_s *p_nodepda;            /* Pointer to Per node PDA */
+        struct subnodepda_s *p_subnodepda;      /* Pointer to CPU  subnode PDA */
+
+        /*
+         * Support for SN LEDs
+         */
+        volatile short  *led_address;
+        u8              led_state;
+        u8              hb_state;       /* supports blinking heartbeat leds */
+        unsigned int    hb_count;
+
+        unsigned int    idle_flag;
+        
+        volatile unsigned long *bedrock_rev_id;
+        volatile unsigned long *pio_write_status_addr;
+        unsigned long pio_write_status_val;
+        volatile unsigned long *pio_shub_war_cam_addr;
+
+        unsigned long   sn_soft_irr[4];
+        unsigned long   sn_in_service_ivecs[4];
+        short           cnodeid_to_nasid_table[MAX_NUMNODES];
+        int             sn_lb_int_war_ticks;
+        int             sn_last_irq;
+        int             sn_first_irq;
+} pda_t;
+
+
+#define CACHE_ALIGN(x)  (((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1))
+
+/*
+ * PDA
+ * Per-cpu private data area for each cpu. The PDA is located immediately after
+ * the IA64 cpu_data area. A full page is allocated for the cp_data area for each
+ * cpu but only a small amout of the page is actually used. We put the SNIA PDA
+ * in the same page as the cpu_data area. Note that there is a check in the setup
+ * code to verify that we don't overflow the page.
+ *
+ * Seems like we should should cache-line align the pda so that any changes in the
+ * size of the cpu_data area don't change cache layout. Should we align to 32, 64, 128
+ * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later.
+ */
+DECLARE_PER_CPU(struct pda_s, pda_percpu);
+
+#define pda             (&__ia64_per_cpu_var(pda_percpu))
+
+#define pdacpu(cpu)     (&per_cpu(pda_percpu, cpu))
+
+#endif /* _ASM_IA64_SN_PDA_H */
diff --git a/include/asm-ia64/sn/rw_mmr.h b/include/asm-ia64/sn/rw_mmr.h
new file mode 100644
index 000000000000..f40fd1a5510d
--- /dev/null
+++ b/include/asm-ia64/sn/rw_mmr.h
@@ -0,0 +1,74 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002-2004 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+#ifndef _ASM_IA64_SN_RW_MMR_H
+#define _ASM_IA64_SN_RW_MMR_H
+
+
+/*
+ * This file contains macros used to access MMR registers via
+ * uncached physical addresses.
+ *      pio_phys_read_mmr  - read an MMR
+ *      pio_phys_write_mmr - write an MMR
+ *      pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
+ *              Second MMR will be skipped if address is NULL
+ *
+ * Addresses passed to these routines should be uncached physical addresses
+ * ie., 0x80000....
+ */
+
+
+extern inline long
+pio_phys_read_mmr(volatile long *mmr) 
+{
+        long val;
+        asm volatile
+            ("mov r2=psr;;"
+             "rsm psr.i | psr.dt;;"
+             "srlz.i;;"
+             "ld8.acq %0=[%1];;"
+             "mov psr.l=r2;;"
+             "srlz.i;;"
+             : "=r"(val)
+             : "r"(mmr)
+             : "r2");
+        return val;
+}
+
+
+
+extern inline void
+pio_phys_write_mmr(volatile long *mmr, long val) 
+{
+        asm volatile
+            ("mov r2=psr;;"
+             "rsm psr.i | psr.dt;;"
+             "srlz.i;;"
+             "st8.rel [%0]=%1;;"
+             "mov psr.l=r2;;"
+             "srlz.i;;"
+             :: "r"(mmr), "r"(val)
+             : "r2", "memory");
+}            
+
+extern inline void
+pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2) 
+{
+        asm volatile
+            ("mov r2=psr;;"
+             "rsm psr.i | psr.dt | psr.ic;;"
+             "cmp.ne p9,p0=%2,r0;"
+             "srlz.i;;"
+             "st8.rel [%0]=%1;"
+             "(p9) st8.rel [%2]=%3;;"
+             "mov psr.l=r2;;"
+             "srlz.i;;"
+             :: "r"(mmr1), "r"(val1), "r"(mmr2), "r"(val2)
+             : "p9", "r2", "memory");
+}            
+
+#endif /* _ASM_IA64_SN_RW_MMR_H */
diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h
new file mode 100644
index 000000000000..5c2fcf13d5ce
--- /dev/null
+++ b/include/asm-ia64/sn/shub_mmr.h
@@ -0,0 +1,441 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001-2004 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SHUB_MMR_H
+#define _ASM_IA64_SN_SHUB_MMR_H
+
+/* ==================================================================== */
+/*                        Register "SH_IPI_INT"                         */
+/*               SHub Inter-Processor Interrupt Registers               */
+/* ==================================================================== */
+#define SH1_IPI_INT                               0x0000000110000380
+#define SH2_IPI_INT                               0x0000000010000380
+
+/*   SH_IPI_INT_TYPE                                                    */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_IPI_INT_TYPE_SHFT                     0
+#define SH_IPI_INT_TYPE_MASK                     0x0000000000000007
+
+/*   SH_IPI_INT_AGT                                                     */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_IPI_INT_AGT_SHFT                      3
+#define SH_IPI_INT_AGT_MASK                      0x0000000000000008
+
+/*   SH_IPI_INT_PID                                                     */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_IPI_INT_PID_SHFT                      4
+#define SH_IPI_INT_PID_MASK                      0x00000000000ffff0
+
+/*   SH_IPI_INT_BASE                                                    */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_IPI_INT_BASE_SHFT                     21
+#define SH_IPI_INT_BASE_MASK                     0x0003ffffffe00000
+
+/*   SH_IPI_INT_IDX                                                     */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_IPI_INT_IDX_SHFT                      52
+#define SH_IPI_INT_IDX_MASK                      0x0ff0000000000000
+
+/*   SH_IPI_INT_SEND                                                    */
+/*   Description:  Send Interrupt Message to PI, This generates a puls  */
+#define SH_IPI_INT_SEND_SHFT                     63
+#define SH_IPI_INT_SEND_MASK                     0x8000000000000000
+
+/* ==================================================================== */
+/*                     Register "SH_EVENT_OCCURRED"                     */
+/*                    SHub Interrupt Event Occurred                     */
+/* ==================================================================== */
+#define SH1_EVENT_OCCURRED                        0x0000000110010000
+#define SH1_EVENT_OCCURRED_ALIAS                  0x0000000110010008
+#define SH2_EVENT_OCCURRED                        0x0000000010010000
+#define SH2_EVENT_OCCURRED_ALIAS                  0x0000000010010008
+
+/* ==================================================================== */
+/*                     Register "SH_PI_CAM_CONTROL"                     */
+/*                      CRB CAM MMR Access Control                      */
+/* ==================================================================== */
+#define SH1_PI_CAM_CONTROL                        0x0000000120050300
+
+/* ==================================================================== */
+/*                        Register "SH_SHUB_ID"                         */
+/*                            SHub ID Number                            */
+/* ==================================================================== */
+#define SH1_SHUB_ID                               0x0000000110060580
+#define SH1_SHUB_ID_REVISION_SHFT                 28
+#define SH1_SHUB_ID_REVISION_MASK                 0x00000000f0000000
+
+/* ==================================================================== */
+/*                          Register "SH_RTC"                           */
+/*                           Real-time Clock                            */
+/* ==================================================================== */
+#define SH1_RTC                                   0x00000001101c0000
+#define SH2_RTC                                   0x00000002101c0000
+#define SH_RTC_MASK                               0x007fffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_PIO_WRITE_STATUS_0|1"                 */
+/*                      PIO Write Status for CPU 0 & 1                  */
+/* ==================================================================== */
+#define SH1_PIO_WRITE_STATUS_0                    0x0000000120070200
+#define SH1_PIO_WRITE_STATUS_1                    0x0000000120070280
+#define SH2_PIO_WRITE_STATUS_0                    0x0000000020070200
+#define SH2_PIO_WRITE_STATUS_1                    0x0000000020070280
+#define SH2_PIO_WRITE_STATUS_2                    0x0000000020070300
+#define SH2_PIO_WRITE_STATUS_3                    0x0000000020070380
+
+/*   SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK                               */
+/*   Description:  Deadlock response detected                           */
+#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1
+#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK 0x0000000000000002
+
+/*   SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT                          */
+/*   Description:  Count of currently pending PIO writes                */
+#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56
+#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                Register "SH_PIO_WRITE_STATUS_0_ALIAS"                */
+/* ==================================================================== */
+#define SH1_PIO_WRITE_STATUS_0_ALIAS              0x0000000120070208
+#define SH2_PIO_WRITE_STATUS_0_ALIAS              0x0000000020070208
+
+/* ==================================================================== */
+/*                     Register "SH_EVENT_OCCURRED"                     */
+/*                    SHub Interrupt Event Occurred                     */
+/* ==================================================================== */
+/*   SH_EVENT_OCCURRED_UART_INT                                         */
+/*   Description:  Pending Junk Bus UART Interrupt                      */
+#define SH_EVENT_OCCURRED_UART_INT_SHFT          20
+#define SH_EVENT_OCCURRED_UART_INT_MASK          0x0000000000100000
+
+/*   SH_EVENT_OCCURRED_IPI_INT                                          */
+/*   Description:  Pending IPI Interrupt                                */
+#define SH_EVENT_OCCURRED_IPI_INT_SHFT           28
+#define SH_EVENT_OCCURRED_IPI_INT_MASK           0x0000000010000000
+
+/*   SH_EVENT_OCCURRED_II_INT0                                          */
+/*   Description:  Pending II 0 Interrupt                               */
+#define SH_EVENT_OCCURRED_II_INT0_SHFT           29
+#define SH_EVENT_OCCURRED_II_INT0_MASK           0x0000000020000000
+
+/*   SH_EVENT_OCCURRED_II_INT1                                          */
+/*   Description:  Pending II 1 Interrupt                               */
+#define SH_EVENT_OCCURRED_II_INT1_SHFT           30
+#define SH_EVENT_OCCURRED_II_INT1_MASK           0x0000000040000000
+
+/* ==================================================================== */
+/*                         LEDS                                         */
+/* ==================================================================== */
+#define SH1_REAL_JUNK_BUS_LED0                   0x7fed00000UL
+#define SH1_REAL_JUNK_BUS_LED1                   0x7fed10000UL
+#define SH1_REAL_JUNK_BUS_LED2                   0x7fed20000UL
+#define SH1_REAL_JUNK_BUS_LED3                   0x7fed30000UL
+
+#define SH2_REAL_JUNK_BUS_LED0                   0xf0000000UL
+#define SH2_REAL_JUNK_BUS_LED1                   0xf0010000UL
+#define SH2_REAL_JUNK_BUS_LED2                   0xf0020000UL
+#define SH2_REAL_JUNK_BUS_LED3                   0xf0030000UL
+
+/* ==================================================================== */
+/*                         Register "SH1_PTC_0"                         */
+/*       Puge Translation Cache Message Configuration Information       */
+/* ==================================================================== */
+#define SH1_PTC_0                                 0x00000001101a0000
+
+/*   SH1_PTC_0_A                                                        */
+/*   Description:  Type                                                 */
+#define SH1_PTC_0_A_SHFT                          0
+
+/*   SH1_PTC_0_PS                                                       */
+/*   Description:  Page Size                                            */
+#define SH1_PTC_0_PS_SHFT                         2
+
+/*   SH1_PTC_0_RID                                                      */
+/*   Description:  Region ID                                            */
+#define SH1_PTC_0_RID_SHFT                        8
+
+/*   SH1_PTC_0_START                                                    */
+/*   Description:  Start                                                */
+#define SH1_PTC_0_START_SHFT                      63
+
+/* ==================================================================== */
+/*                         Register "SH1_PTC_1"                         */
+/*       Puge Translation Cache Message Configuration Information       */
+/* ==================================================================== */
+#define SH1_PTC_1                                 0x00000001101a0080
+
+/*   SH1_PTC_1_START                                                    */
+/*   Description:  PTC_1 Start                                          */
+#define SH1_PTC_1_START_SHFT                      63
+
+
+/* ==================================================================== */
+/*                         Register "SH2_PTC"                           */
+/*       Puge Translation Cache Message Configuration Information       */
+/* ==================================================================== */
+#define SH2_PTC                                   0x0000000170000000
+
+/*   SH2_PTC_A                                                          */
+/*   Description:  Type                                                 */
+#define SH2_PTC_A_SHFT                            0
+
+/*   SH2_PTC_PS                                                         */
+/*   Description:  Page Size                                            */
+#define SH2_PTC_PS_SHFT                           2
+
+/*   SH2_PTC_RID                                                      */
+/*   Description:  Region ID                                            */
+#define SH2_PTC_RID_SHFT                          4
+
+/*   SH2_PTC_START                                                      */
+/*   Description:  Start                                                */
+#define SH2_PTC_START_SHFT                        63
+
+/*   SH2_PTC_ADDR_RID                                                   */
+/*   Description:  Region ID                                            */
+#define SH2_PTC_ADDR_SHFT                         4
+#define SH2_PTC_ADDR_MASK                         0x1ffffffffffff000
+
+/* ==================================================================== */
+/*                    Register "SH_RTC1_INT_CONFIG"                     */
+/*                SHub RTC 1 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH1_RTC1_INT_CONFIG                      0x0000000110001480
+#define SH2_RTC1_INT_CONFIG                      0x0000000010001480
+#define SH_RTC1_INT_CONFIG_MASK                  0x0ff3ffffffefffff
+#define SH_RTC1_INT_CONFIG_INIT                  0x0000000000000000
+
+/*   SH_RTC1_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC1_INT_CONFIG_TYPE_SHFT             0
+#define SH_RTC1_INT_CONFIG_TYPE_MASK             0x0000000000000007
+
+/*   SH_RTC1_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC1_INT_CONFIG_AGT_SHFT              3
+#define SH_RTC1_INT_CONFIG_AGT_MASK              0x0000000000000008
+
+/*   SH_RTC1_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC1_INT_CONFIG_PID_SHFT              4
+#define SH_RTC1_INT_CONFIG_PID_MASK              0x00000000000ffff0
+
+/*   SH_RTC1_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC1_INT_CONFIG_BASE_SHFT             21
+#define SH_RTC1_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+
+/*   SH_RTC1_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC1_INT_CONFIG_IDX_SHFT              52
+#define SH_RTC1_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_RTC1_INT_ENABLE"                     */
+/*                SHub RTC 1 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH1_RTC1_INT_ENABLE                      0x0000000110001500
+#define SH2_RTC1_INT_ENABLE                      0x0000000010001500
+#define SH_RTC1_INT_ENABLE_MASK                  0x0000000000000001
+#define SH_RTC1_INT_ENABLE_INIT                  0x0000000000000000
+
+/*   SH_RTC1_INT_ENABLE_RTC1_ENABLE                                     */
+/*   Description:  Enable RTC 1 Interrupt                               */
+#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT      0
+#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                    Register "SH_RTC2_INT_CONFIG"                     */
+/*                SHub RTC 2 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH1_RTC2_INT_CONFIG                      0x0000000110001580
+#define SH2_RTC2_INT_CONFIG                      0x0000000010001580
+#define SH_RTC2_INT_CONFIG_MASK                  0x0ff3ffffffefffff
+#define SH_RTC2_INT_CONFIG_INIT                  0x0000000000000000
+
+/*   SH_RTC2_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC2_INT_CONFIG_TYPE_SHFT             0
+#define SH_RTC2_INT_CONFIG_TYPE_MASK             0x0000000000000007
+
+/*   SH_RTC2_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC2_INT_CONFIG_AGT_SHFT              3
+#define SH_RTC2_INT_CONFIG_AGT_MASK              0x0000000000000008
+
+/*   SH_RTC2_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC2_INT_CONFIG_PID_SHFT              4
+#define SH_RTC2_INT_CONFIG_PID_MASK              0x00000000000ffff0
+
+/*   SH_RTC2_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC2_INT_CONFIG_BASE_SHFT             21
+#define SH_RTC2_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+
+/*   SH_RTC2_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC2_INT_CONFIG_IDX_SHFT              52
+#define SH_RTC2_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_RTC2_INT_ENABLE"                     */
+/*                SHub RTC 2 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH1_RTC2_INT_ENABLE                      0x0000000110001600
+#define SH2_RTC2_INT_ENABLE                      0x0000000010001600
+#define SH_RTC2_INT_ENABLE_MASK                  0x0000000000000001
+#define SH_RTC2_INT_ENABLE_INIT                  0x0000000000000000
+
+/*   SH_RTC2_INT_ENABLE_RTC2_ENABLE                                     */
+/*   Description:  Enable RTC 2 Interrupt                               */
+#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT      0
+#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                    Register "SH_RTC3_INT_CONFIG"                     */
+/*                SHub RTC 3 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH1_RTC3_INT_CONFIG                      0x0000000110001680
+#define SH2_RTC3_INT_CONFIG                      0x0000000010001680
+#define SH_RTC3_INT_CONFIG_MASK                  0x0ff3ffffffefffff
+#define SH_RTC3_INT_CONFIG_INIT                  0x0000000000000000
+
+/*   SH_RTC3_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC3_INT_CONFIG_TYPE_SHFT             0
+#define SH_RTC3_INT_CONFIG_TYPE_MASK             0x0000000000000007
+
+/*   SH_RTC3_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC3_INT_CONFIG_AGT_SHFT              3
+#define SH_RTC3_INT_CONFIG_AGT_MASK              0x0000000000000008
+
+/*   SH_RTC3_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC3_INT_CONFIG_PID_SHFT              4
+#define SH_RTC3_INT_CONFIG_PID_MASK              0x00000000000ffff0
+
+/*   SH_RTC3_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC3_INT_CONFIG_BASE_SHFT             21
+#define SH_RTC3_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+
+/*   SH_RTC3_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC3_INT_CONFIG_IDX_SHFT              52
+#define SH_RTC3_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_RTC3_INT_ENABLE"                     */
+/*                SHub RTC 3 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH1_RTC3_INT_ENABLE                      0x0000000110001700
+#define SH2_RTC3_INT_ENABLE                      0x0000000010001700
+#define SH_RTC3_INT_ENABLE_MASK                  0x0000000000000001
+#define SH_RTC3_INT_ENABLE_INIT                  0x0000000000000000
+
+/*   SH_RTC3_INT_ENABLE_RTC3_ENABLE                                     */
+/*   Description:  Enable RTC 3 Interrupt                               */
+#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT      0
+#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK      0x0000000000000001
+
+/*   SH_EVENT_OCCURRED_RTC1_INT                                         */
+/*   Description:  Pending RTC 1 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC1_INT_SHFT          24
+#define SH_EVENT_OCCURRED_RTC1_INT_MASK          0x0000000001000000
+
+/*   SH_EVENT_OCCURRED_RTC2_INT                                         */
+/*   Description:  Pending RTC 2 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC2_INT_SHFT          25
+#define SH_EVENT_OCCURRED_RTC2_INT_MASK          0x0000000002000000
+
+/*   SH_EVENT_OCCURRED_RTC3_INT                                         */
+/*   Description:  Pending RTC 3 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC3_INT_SHFT          26
+#define SH_EVENT_OCCURRED_RTC3_INT_MASK          0x0000000004000000
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPB"                        */
+/*                  RTC Compare Value for Processor B                   */
+/* ==================================================================== */
+
+#define SH1_INT_CMPB                             0x00000001101b0080
+#define SH2_INT_CMPB                             0x00000000101b0080
+#define SH_INT_CMPB_MASK                         0x007fffffffffffff
+#define SH_INT_CMPB_INIT                         0x0000000000000000
+
+/*   SH_INT_CMPB_REAL_TIME_CMPB                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT          0
+#define SH_INT_CMPB_REAL_TIME_CMPB_MASK          0x007fffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPC"                        */
+/*                  RTC Compare Value for Processor C                   */
+/* ==================================================================== */
+
+#define SH1_INT_CMPC                             0x00000001101b0100
+#define SH2_INT_CMPC                             0x00000000101b0100
+#define SH_INT_CMPC_MASK                         0x007fffffffffffff
+#define SH_INT_CMPC_INIT                         0x0000000000000000
+
+/*   SH_INT_CMPC_REAL_TIME_CMPC                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT          0
+#define SH_INT_CMPC_REAL_TIME_CMPC_MASK          0x007fffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPD"                        */
+/*                  RTC Compare Value for Processor D                   */
+/* ==================================================================== */
+
+#define SH1_INT_CMPD                             0x00000001101b0180
+#define SH2_INT_CMPD                             0x00000000101b0180
+#define SH_INT_CMPD_MASK                         0x007fffffffffffff
+#define SH_INT_CMPD_INIT                         0x0000000000000000
+
+/*   SH_INT_CMPD_REAL_TIME_CMPD                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT          0
+#define SH_INT_CMPD_REAL_TIME_CMPD_MASK          0x007fffffffffffff
+
+
+/* ==================================================================== */
+/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
+/* and SHUB2 that it makes sense to define a geberic name for the MMR.  */
+/* It is acceptible to use (for example) SH_IPI_INT to reference the    */
+/* the IPI MMR. The value of SH_IPI_INT is determined at runtime based  */
+/* on the type of the SHUB. Do not use these #defines in performance    */
+/* critical code  or loops - there is a small performance penalty.      */
+/* ==================================================================== */
+#define shubmmr(a,b)            (is_shub2() ? a##2_##b : a##1_##b)
+
+#define SH_REAL_JUNK_BUS_LED0   shubmmr(SH, REAL_JUNK_BUS_LED0)
+#define SH_IPI_INT              shubmmr(SH, IPI_INT)
+#define SH_EVENT_OCCURRED       shubmmr(SH, EVENT_OCCURRED)
+#define SH_EVENT_OCCURRED_ALIAS shubmmr(SH, EVENT_OCCURRED_ALIAS)
+#define SH_RTC                  shubmmr(SH, RTC)
+#define SH_RTC1_INT_CONFIG      shubmmr(SH, RTC1_INT_CONFIG)
+#define SH_RTC1_INT_ENABLE      shubmmr(SH, RTC1_INT_ENABLE)
+#define SH_RTC2_INT_CONFIG      shubmmr(SH, RTC2_INT_CONFIG)
+#define SH_RTC2_INT_ENABLE      shubmmr(SH, RTC2_INT_ENABLE)
+#define SH_RTC3_INT_CONFIG      shubmmr(SH, RTC3_INT_CONFIG)
+#define SH_RTC3_INT_ENABLE      shubmmr(SH, RTC3_INT_ENABLE)
+#define SH_INT_CMPB             shubmmr(SH, INT_CMPB)
+#define SH_INT_CMPC             shubmmr(SH, INT_CMPC)
+#define SH_INT_CMPD             shubmmr(SH, INT_CMPD)
+
+#endif /* _ASM_IA64_SN_SHUB_MMR_H */
diff --git a/include/asm-ia64/sn/shubio.h b/include/asm-ia64/sn/shubio.h
new file mode 100644
index 000000000000..fbd880e6bb96
--- /dev/null
+++ b/include/asm-ia64/sn/shubio.h
@@ -0,0 +1,3476 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SHUBIO_H
+#define _ASM_IA64_SN_SHUBIO_H
+
+#define HUB_WIDGET_ID_MAX 0xf
+#define IIO_NUM_ITTES   7
+#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
+
+#define    IIO_WID                   0x00400000    /* Crosstalk Widget Identification */
+                                                   /* This register is also accessible from
+                                                    * Crosstalk at address 0x0.  */
+#define    IIO_WSTAT                 0x00400008    /* Crosstalk Widget Status */
+#define    IIO_WCR                   0x00400020    /* Crosstalk Widget Control Register */
+#define    IIO_ILAPR                 0x00400100    /* IO Local Access Protection Register */
+#define    IIO_ILAPO                 0x00400108    /* IO Local Access Protection Override */
+#define    IIO_IOWA                  0x00400110    /* IO Outbound Widget Access */
+#define    IIO_IIWA                  0x00400118    /* IO Inbound Widget Access */
+#define    IIO_IIDEM                 0x00400120    /* IO Inbound Device Error Mask */
+#define    IIO_ILCSR                 0x00400128    /* IO LLP Control and Status Register */
+#define    IIO_ILLR                  0x00400130    /* IO LLP Log Register    */
+#define    IIO_IIDSR                 0x00400138    /* IO Interrupt Destination */
+
+#define    IIO_IGFX0                 0x00400140    /* IO Graphics Node-Widget Map 0 */
+#define    IIO_IGFX1                 0x00400148    /* IO Graphics Node-Widget Map 1 */
+
+#define    IIO_ISCR0                 0x00400150    /* IO Scratch Register 0 */
+#define    IIO_ISCR1                 0x00400158    /* IO Scratch Register 1 */
+
+#define    IIO_ITTE1                 0x00400160    /* IO Translation Table Entry 1 */
+#define    IIO_ITTE2                 0x00400168    /* IO Translation Table Entry 2 */
+#define    IIO_ITTE3                 0x00400170    /* IO Translation Table Entry 3 */
+#define    IIO_ITTE4                 0x00400178    /* IO Translation Table Entry 4 */
+#define    IIO_ITTE5                 0x00400180    /* IO Translation Table Entry 5 */
+#define    IIO_ITTE6                 0x00400188    /* IO Translation Table Entry 6 */
+#define    IIO_ITTE7                 0x00400190    /* IO Translation Table Entry 7 */
+
+#define    IIO_IPRB0                 0x00400198    /* IO PRB Entry 0         */
+#define    IIO_IPRB8                 0x004001A0    /* IO PRB Entry 8         */
+#define    IIO_IPRB9                 0x004001A8    /* IO PRB Entry 9         */
+#define    IIO_IPRBA                 0x004001B0    /* IO PRB Entry A         */
+#define    IIO_IPRBB                 0x004001B8    /* IO PRB Entry B         */
+#define    IIO_IPRBC                 0x004001C0    /* IO PRB Entry C         */
+#define    IIO_IPRBD                 0x004001C8    /* IO PRB Entry D         */
+#define    IIO_IPRBE                 0x004001D0    /* IO PRB Entry E         */
+#define    IIO_IPRBF                 0x004001D8    /* IO PRB Entry F         */
+
+#define    IIO_IXCC                  0x004001E0    /* IO Crosstalk Credit Count Timeout */
+#define    IIO_IMEM                  0x004001E8    /* IO Miscellaneous Error Mask */
+#define    IIO_IXTT                  0x004001F0    /* IO Crosstalk Timeout Threshold */
+#define    IIO_IECLR                 0x004001F8    /* IO Error Clear Register */
+#define    IIO_IBCR                  0x00400200    /* IO BTE Control Register */
+
+#define    IIO_IXSM                  0x00400208    /* IO Crosstalk Spurious Message */
+#define    IIO_IXSS                  0x00400210    /* IO Crosstalk Spurious Sideband */
+
+#define    IIO_ILCT                  0x00400218    /* IO LLP Channel Test    */
+
+#define    IIO_IIEPH1                0x00400220    /* IO Incoming Error Packet Header, Part 1 */
+#define    IIO_IIEPH2                0x00400228    /* IO Incoming Error Packet Header, Part 2 */
+
+
+#define    IIO_ISLAPR                0x00400230    /* IO SXB Local Access Protection Regster */
+#define    IIO_ISLAPO                0x00400238    /* IO SXB Local Access Protection Override */
+
+#define    IIO_IWI                   0x00400240    /* IO Wrapper Interrupt Register */
+#define    IIO_IWEL                  0x00400248    /* IO Wrapper Error Log Register */
+#define    IIO_IWC                   0x00400250    /* IO Wrapper Control Register */
+#define    IIO_IWS                   0x00400258    /* IO Wrapper Status Register */
+#define    IIO_IWEIM                 0x00400260    /* IO Wrapper Error Interrupt Masking Register */
+
+#define    IIO_IPCA                  0x00400300    /* IO PRB Counter Adjust */
+
+#define    IIO_IPRTE0_A              0x00400308    /* IO PIO Read Address Table Entry 0, Part A */
+#define    IIO_IPRTE1_A              0x00400310    /* IO PIO Read Address Table Entry 1, Part A */
+#define    IIO_IPRTE2_A              0x00400318    /* IO PIO Read Address Table Entry 2, Part A */
+#define    IIO_IPRTE3_A               0x00400320    /* IO PIO Read Address Table Entry 3, Part A */
+#define    IIO_IPRTE4_A               0x00400328    /* IO PIO Read Address Table Entry 4, Part A */
+#define    IIO_IPRTE5_A               0x00400330    /* IO PIO Read Address Table Entry 5, Part A */
+#define    IIO_IPRTE6_A               0x00400338    /* IO PIO Read Address Table Entry 6, Part A */
+#define    IIO_IPRTE7_A               0x00400340    /* IO PIO Read Address Table Entry 7, Part A */
+
+#define    IIO_IPRTE0_B              0x00400348    /* IO PIO Read Address Table Entry 0, Part B */
+#define    IIO_IPRTE1_B              0x00400350    /* IO PIO Read Address Table Entry 1, Part B */
+#define    IIO_IPRTE2_B              0x00400358    /* IO PIO Read Address Table Entry 2, Part B */
+#define    IIO_IPRTE3_B               0x00400360    /* IO PIO Read Address Table Entry 3, Part B */
+#define    IIO_IPRTE4_B               0x00400368    /* IO PIO Read Address Table Entry 4, Part B */
+#define    IIO_IPRTE5_B               0x00400370    /* IO PIO Read Address Table Entry 5, Part B */
+#define    IIO_IPRTE6_B               0x00400378    /* IO PIO Read Address Table Entry 6, Part B */
+#define    IIO_IPRTE7_B               0x00400380    /* IO PIO Read Address Table Entry 7, Part B */
+
+#define    IIO_IPDR                  0x00400388    /* IO PIO Deallocation Register */
+#define    IIO_ICDR                  0x00400390    /* IO CRB Entry Deallocation Register */
+#define    IIO_IFDR                  0x00400398    /* IO IOQ FIFO Depth Register */
+#define    IIO_IIAP                  0x004003A0    /* IO IIQ Arbitration Parameters */
+#define    IIO_ICMR                  0x004003A8    /* IO CRB Management Register */
+#define    IIO_ICCR                  0x004003B0    /* IO CRB Control Register */
+#define    IIO_ICTO                  0x004003B8    /* IO CRB Timeout         */
+#define    IIO_ICTP                  0x004003C0    /* IO CRB Timeout Prescalar */
+
+#define    IIO_ICRB0_A               0x00400400    /* IO CRB Entry 0_A       */
+#define    IIO_ICRB0_B               0x00400408    /* IO CRB Entry 0_B       */
+#define    IIO_ICRB0_C               0x00400410    /* IO CRB Entry 0_C       */
+#define    IIO_ICRB0_D               0x00400418    /* IO CRB Entry 0_D       */
+#define    IIO_ICRB0_E               0x00400420    /* IO CRB Entry 0_E       */
+
+#define    IIO_ICRB1_A               0x00400430    /* IO CRB Entry 1_A       */
+#define    IIO_ICRB1_B               0x00400438    /* IO CRB Entry 1_B       */
+#define    IIO_ICRB1_C               0x00400440    /* IO CRB Entry 1_C       */
+#define    IIO_ICRB1_D               0x00400448    /* IO CRB Entry 1_D       */
+#define    IIO_ICRB1_E               0x00400450    /* IO CRB Entry 1_E       */
+
+#define    IIO_ICRB2_A               0x00400460    /* IO CRB Entry 2_A       */
+#define    IIO_ICRB2_B               0x00400468    /* IO CRB Entry 2_B       */
+#define    IIO_ICRB2_C               0x00400470    /* IO CRB Entry 2_C       */
+#define    IIO_ICRB2_D               0x00400478    /* IO CRB Entry 2_D       */
+#define    IIO_ICRB2_E               0x00400480    /* IO CRB Entry 2_E       */
+
+#define    IIO_ICRB3_A               0x00400490    /* IO CRB Entry 3_A       */
+#define    IIO_ICRB3_B               0x00400498    /* IO CRB Entry 3_B       */
+#define    IIO_ICRB3_C               0x004004a0    /* IO CRB Entry 3_C       */
+#define    IIO_ICRB3_D               0x004004a8    /* IO CRB Entry 3_D       */
+#define    IIO_ICRB3_E               0x004004b0    /* IO CRB Entry 3_E       */
+
+#define    IIO_ICRB4_A               0x004004c0    /* IO CRB Entry 4_A       */
+#define    IIO_ICRB4_B               0x004004c8    /* IO CRB Entry 4_B       */
+#define    IIO_ICRB4_C               0x004004d0    /* IO CRB Entry 4_C       */
+#define    IIO_ICRB4_D               0x004004d8    /* IO CRB Entry 4_D       */
+#define    IIO_ICRB4_E               0x004004e0    /* IO CRB Entry 4_E       */
+
+#define    IIO_ICRB5_A               0x004004f0    /* IO CRB Entry 5_A       */
+#define    IIO_ICRB5_B               0x004004f8    /* IO CRB Entry 5_B       */
+#define    IIO_ICRB5_C               0x00400500    /* IO CRB Entry 5_C       */
+#define    IIO_ICRB5_D               0x00400508    /* IO CRB Entry 5_D       */
+#define    IIO_ICRB5_E               0x00400510    /* IO CRB Entry 5_E       */
+
+#define    IIO_ICRB6_A               0x00400520    /* IO CRB Entry 6_A       */
+#define    IIO_ICRB6_B               0x00400528    /* IO CRB Entry 6_B       */
+#define    IIO_ICRB6_C               0x00400530    /* IO CRB Entry 6_C       */
+#define    IIO_ICRB6_D               0x00400538    /* IO CRB Entry 6_D       */
+#define    IIO_ICRB6_E               0x00400540    /* IO CRB Entry 6_E       */
+
+#define    IIO_ICRB7_A               0x00400550    /* IO CRB Entry 7_A       */
+#define    IIO_ICRB7_B               0x00400558    /* IO CRB Entry 7_B       */
+#define    IIO_ICRB7_C               0x00400560    /* IO CRB Entry 7_C       */
+#define    IIO_ICRB7_D               0x00400568    /* IO CRB Entry 7_D       */
+#define    IIO_ICRB7_E               0x00400570    /* IO CRB Entry 7_E       */
+
+#define    IIO_ICRB8_A               0x00400580    /* IO CRB Entry 8_A       */
+#define    IIO_ICRB8_B               0x00400588    /* IO CRB Entry 8_B       */
+#define    IIO_ICRB8_C               0x00400590    /* IO CRB Entry 8_C       */
+#define    IIO_ICRB8_D               0x00400598    /* IO CRB Entry 8_D       */
+#define    IIO_ICRB8_E               0x004005a0    /* IO CRB Entry 8_E       */
+
+#define    IIO_ICRB9_A               0x004005b0    /* IO CRB Entry 9_A       */
+#define    IIO_ICRB9_B               0x004005b8    /* IO CRB Entry 9_B       */
+#define    IIO_ICRB9_C               0x004005c0    /* IO CRB Entry 9_C       */
+#define    IIO_ICRB9_D               0x004005c8    /* IO CRB Entry 9_D       */
+#define    IIO_ICRB9_E               0x004005d0    /* IO CRB Entry 9_E       */
+
+#define    IIO_ICRBA_A               0x004005e0    /* IO CRB Entry A_A       */
+#define    IIO_ICRBA_B               0x004005e8    /* IO CRB Entry A_B       */
+#define    IIO_ICRBA_C               0x004005f0    /* IO CRB Entry A_C       */
+#define    IIO_ICRBA_D               0x004005f8    /* IO CRB Entry A_D       */
+#define    IIO_ICRBA_E               0x00400600    /* IO CRB Entry A_E       */
+
+#define    IIO_ICRBB_A               0x00400610    /* IO CRB Entry B_A       */
+#define    IIO_ICRBB_B               0x00400618    /* IO CRB Entry B_B       */
+#define    IIO_ICRBB_C               0x00400620    /* IO CRB Entry B_C       */
+#define    IIO_ICRBB_D               0x00400628    /* IO CRB Entry B_D       */
+#define    IIO_ICRBB_E               0x00400630    /* IO CRB Entry B_E       */
+
+#define    IIO_ICRBC_A               0x00400640    /* IO CRB Entry C_A       */
+#define    IIO_ICRBC_B               0x00400648    /* IO CRB Entry C_B       */
+#define    IIO_ICRBC_C               0x00400650    /* IO CRB Entry C_C       */
+#define    IIO_ICRBC_D               0x00400658    /* IO CRB Entry C_D       */
+#define    IIO_ICRBC_E               0x00400660    /* IO CRB Entry C_E       */
+
+#define    IIO_ICRBD_A               0x00400670    /* IO CRB Entry D_A       */
+#define    IIO_ICRBD_B               0x00400678    /* IO CRB Entry D_B       */
+#define    IIO_ICRBD_C               0x00400680    /* IO CRB Entry D_C       */
+#define    IIO_ICRBD_D               0x00400688    /* IO CRB Entry D_D       */
+#define    IIO_ICRBD_E               0x00400690    /* IO CRB Entry D_E       */
+
+#define    IIO_ICRBE_A               0x004006a0    /* IO CRB Entry E_A       */
+#define    IIO_ICRBE_B               0x004006a8    /* IO CRB Entry E_B       */
+#define    IIO_ICRBE_C               0x004006b0    /* IO CRB Entry E_C       */
+#define    IIO_ICRBE_D               0x004006b8    /* IO CRB Entry E_D       */
+#define    IIO_ICRBE_E               0x004006c0    /* IO CRB Entry E_E       */
+
+#define    IIO_ICSML                 0x00400700    /* IO CRB Spurious Message Low */
+#define    IIO_ICSMM                 0x00400708    /* IO CRB Spurious Message Middle */
+#define    IIO_ICSMH                 0x00400710    /* IO CRB Spurious Message High */
+
+#define    IIO_IDBSS                 0x00400718    /* IO Debug Submenu Select */
+
+#define    IIO_IBLS0                 0x00410000    /* IO BTE Length Status 0 */
+#define    IIO_IBSA0                 0x00410008    /* IO BTE Source Address 0 */
+#define    IIO_IBDA0                 0x00410010    /* IO BTE Destination Address 0 */
+#define    IIO_IBCT0                 0x00410018    /* IO BTE Control Terminate 0 */
+#define    IIO_IBNA0                 0x00410020    /* IO BTE Notification Address 0 */
+#define    IIO_IBIA0                 0x00410028    /* IO BTE Interrupt Address 0 */
+#define    IIO_IBLS1                 0x00420000    /* IO BTE Length Status 1 */
+#define    IIO_IBSA1                 0x00420008    /* IO BTE Source Address 1 */
+#define    IIO_IBDA1                 0x00420010    /* IO BTE Destination Address 1 */
+#define    IIO_IBCT1                 0x00420018    /* IO BTE Control Terminate 1 */
+#define    IIO_IBNA1                 0x00420020    /* IO BTE Notification Address 1 */
+#define    IIO_IBIA1                 0x00420028    /* IO BTE Interrupt Address 1 */
+
+#define    IIO_IPCR                  0x00430000    /* IO Performance Control */
+#define    IIO_IPPR                  0x00430008    /* IO Performance Profiling */
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register echoes some information from the         *
+ * LB_REV_ID register. It is available through Crosstalk as described   *
+ * above. The REV_NUM and MFG_NUM fields receive their values from      *
+ * the REVISION and MANUFACTURER fields in the LB_REV_ID register.      *
+ * The PART_NUM field's value is the Crosstalk device ID number that    *
+ * Steve Miller assigned to the SHub chip.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_wid_u {
+        uint64_t        ii_wid_regval;
+        struct  {
+                uint64_t        w_rsvd_1                  :      1;
+                uint64_t        w_mfg_num                 :     11;
+                uint64_t        w_part_num                :     16;
+                uint64_t        w_rev_num                 :      4;
+                uint64_t        w_rsvd                    :     32;
+        } ii_wid_fld_s;
+} ii_wid_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  The fields in this register are set upon detection of an error      *
+ * and cleared by various mechanisms, as explained in the               *
+ * description.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_wstat_u {
+        uint64_t        ii_wstat_regval;
+        struct  {
+                uint64_t        w_pending                 :      4;
+                uint64_t        w_xt_crd_to               :      1;
+                uint64_t        w_xt_tail_to              :      1;
+                uint64_t        w_rsvd_3                  :      3;
+                uint64_t       w_tx_mx_rty               :      1;
+                uint64_t        w_rsvd_2                  :      6;
+                uint64_t        w_llp_tx_cnt              :      8;
+                uint64_t        w_rsvd_1                  :      8;
+                uint64_t        w_crazy                   :      1;
+                uint64_t        w_rsvd                    :     31;
+        } ii_wstat_fld_s;
+} ii_wstat_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This is a read-write enabled register. It controls     *
+ * various aspects of the Crosstalk flow control.                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_wcr_u {
+        uint64_t        ii_wcr_regval;
+        struct  {
+                uint64_t        w_wid                     :      4;
+                uint64_t        w_tag                     :      1;
+                uint64_t        w_rsvd_1                  :      8;
+                uint64_t        w_dst_crd                 :      3;
+                uint64_t        w_f_bad_pkt               :      1;
+                uint64_t        w_dir_con                 :      1;
+                uint64_t        w_e_thresh                :      5;
+                uint64_t        w_rsvd                    :     41;
+        } ii_wcr_fld_s;
+} ii_wcr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register's value is a bit vector that guards      *
+ * access to local registers within the II as well as to external       *
+ * Crosstalk widgets. Each bit in the register corresponds to a         *
+ * particular region in the system; a region consists of one, two or    *
+ * four nodes (depending on the value of the REGION_SIZE field in the   *
+ * LB_REV_ID register, which is documented in Section 8.3.1.1). The     *
+ * protection provided by this register applies to PIO read             *
+ * operations as well as PIO write operations. The II will perform a    *
+ * PIO read or write request only if the bit for the requestor's        *
+ * region is set; otherwise, the II will not perform the requested      *
+ * operation and will return an error response. When a PIO read or      *
+ * write request targets an external Crosstalk widget, then not only    *
+ * must the bit for the requestor's region be set in the ILAPR, but     *
+ * also the target widget's bit in the IOWA register must be set in     *
+ * order for the II to perform the requested operation; otherwise,      *
+ * the II will return an error response. Hence, the protection          *
+ * provided by the IOWA register supplements the protection provided    *
+ * by the ILAPR for requests that target external Crosstalk widgets.    *
+ * This register itself can be accessed only by the nodes whose         *
+ * region ID bits are enabled in this same register. It can also be     *
+ * accessed through the IAlias space by the local processors.           *
+ * The reset value of this register allows access by all nodes.         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilapr_u {
+        uint64_t        ii_ilapr_regval;
+        struct  {
+                uint64_t        i_region                  :     64;
+        } ii_ilapr_fld_s;
+} ii_ilapr_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  A write to this register of the 64-bit value           *
+ * "SGIrules" in ASCII, will cause the bit in the ILAPR register        *
+ * corresponding to the region of the requestor to be set (allow        *
+ * access). A write of any other value will be ignored. Access          *
+ * protection for this register is "SGIrules".                          *
+ * This register can also be accessed through the IAlias space.         *
+ * However, this access will not change the access permissions in the   *
+ * ILAPR.                                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilapo_u {
+        uint64_t        ii_ilapo_regval;
+        struct  {
+                uint64_t        i_io_ovrride            :       64;
+        } ii_ilapo_fld_s;
+} ii_ilapo_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register qualifies all the PIO and Graphics writes launched    *
+ * from the SHUB towards a widget.                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iowa_u {
+        uint64_t        ii_iowa_regval;
+        struct  {
+                uint64_t        i_w0_oac                  :      1;
+                uint64_t        i_rsvd_1                  :      7;
+                uint64_t       i_wx_oac                  :      8;
+                uint64_t        i_rsvd                    :     48;
+        } ii_iowa_fld_s;
+} ii_iowa_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register qualifies all the requests launched      *
+ * from a widget towards the Shub. This register is intended to be      *
+ * used by software in case of misbehaving widgets.                     *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iiwa_u {
+        uint64_t        ii_iiwa_regval;
+        struct  {
+                uint64_t        i_w0_iac                  :      1;
+                uint64_t        i_rsvd_1                  :      7;
+                uint64_t        i_wx_iac                  :      8;
+                uint64_t        i_rsvd                    :     48;
+        } ii_iiwa_fld_s;
+} ii_iiwa_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register qualifies all the operations launched    *
+ * from a widget towards the SHub. It allows individual access          *
+ * control for up to 8 devices per widget. A device refers to           *
+ * individual DMA master hosted by a widget.                            *
+ * The bits in each field of this register are cleared by the Shub      *
+ * upon detection of an error which requires the device to be           *
+ * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric    *
+ * Crosstalk). Whether or not a device has access rights to this        *
+ * Shub is determined by an AND of the device enable bit in the         *
+ * appropriate field of this register and the corresponding bit in      *
+ * the Wx_IAC field (for the widget which this device belongs to).      *
+ * The bits in this field are set by writing a 1 to them. Incoming      *
+ * replies from Crosstalk are not subject to this access control        *
+ * mechanism.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iidem_u {
+        uint64_t        ii_iidem_regval;
+        struct  {
+                uint64_t        i_w8_dxs                  :      8;
+                uint64_t        i_w9_dxs                  :      8;
+                uint64_t        i_wa_dxs                  :      8;
+                uint64_t        i_wb_dxs                  :      8;
+                uint64_t        i_wc_dxs                  :      8;
+                uint64_t        i_wd_dxs                  :      8;
+                uint64_t        i_we_dxs                  :      8;
+                uint64_t        i_wf_dxs                  :      8;
+        } ii_iidem_fld_s;
+} ii_iidem_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the various programmable fields necessary    *
+ * for controlling and observing the LLP signals.                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilcsr_u {
+        uint64_t        ii_ilcsr_regval;
+        struct  {
+                uint64_t        i_nullto                  :      6;
+                uint64_t        i_rsvd_4                  :      2;
+                uint64_t        i_wrmrst                  :      1;
+                uint64_t        i_rsvd_3                  :      1;
+                uint64_t        i_llp_en                  :      1;
+                uint64_t        i_bm8                     :      1;
+                uint64_t        i_llp_stat                :      2;
+                uint64_t        i_remote_power            :      1;
+                uint64_t        i_rsvd_2                  :      1;
+                uint64_t        i_maxrtry                 :     10;
+                uint64_t        i_d_avail_sel             :      2;
+                uint64_t        i_rsvd_1                  :      4;
+                uint64_t        i_maxbrst                 :     10;
+                uint64_t       i_rsvd                    :     22;
+
+        } ii_ilcsr_fld_s;
+} ii_ilcsr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This is simply a status registers that monitors the LLP error       *
+ * rate.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_illr_u {
+        uint64_t        ii_illr_regval;
+        struct  {
+                uint64_t        i_sn_cnt                  :     16;
+                uint64_t        i_cb_cnt                  :     16;
+                uint64_t        i_rsvd                    :     32;
+        } ii_illr_fld_s;
+} ii_illr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  All II-detected non-BTE error interrupts are           *
+ * specified via this register.                                         *
+ * NOTE: The PI interrupt register address is hardcoded in the II. If   *
+ * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI      *
+ * packet) to address offset 0x0180_0090 within the local register      *
+ * address space of PI0 on the node specified by the NODE field. If     *
+ * PI_ID==1, then the II sends the interrupt request to address         *
+ * offset 0x01A0_0090 within the local register address space of PI1    *
+ * on the node specified by the NODE field.                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iidsr_u {
+        uint64_t        ii_iidsr_regval;
+        struct  {
+                uint64_t        i_level                   :      8;
+                uint64_t        i_pi_id                   :      1;
+                uint64_t        i_node                    :     11;
+                uint64_t       i_rsvd_3                  :      4;
+                uint64_t        i_enable                  :      1;
+                uint64_t        i_rsvd_2                  :      3;
+                uint64_t        i_int_sent                :      2;
+                uint64_t       i_rsvd_1                  :      2;
+                uint64_t        i_pi0_forward_int         :      1;
+                uint64_t        i_pi1_forward_int         :      1;
+                uint64_t        i_rsvd                    :     30;
+        } ii_iidsr_fld_s;
+} ii_iidsr_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this register. This register is used     *
+ * for matching up the incoming responses from the graphics widget to   *
+ * the processor that initiated the graphics operation. The             *
+ * write-responses are converted to graphics credits and returned to    *
+ * the processor so that the processor interface can manage the flow    *
+ * control.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_igfx0_u {
+        uint64_t        ii_igfx0_regval;
+        struct  {
+                uint64_t        i_w_num                   :      4;
+                uint64_t       i_pi_id                   :      1;
+                uint64_t        i_n_num                   :     12;
+                uint64_t       i_p_num                   :      1;
+                uint64_t       i_rsvd                    :     46;
+        } ii_igfx0_fld_s;
+} ii_igfx0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this register. This register is used     *
+ * for matching up the incoming responses from the graphics widget to   *
+ * the processor that initiated the graphics operation. The             *
+ * write-responses are converted to graphics credits and returned to    *
+ * the processor so that the processor interface can manage the flow    *
+ * control.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_igfx1_u {
+        uint64_t        ii_igfx1_regval;
+        struct  {
+                uint64_t        i_w_num                   :      4;
+                uint64_t       i_pi_id                   :      1;
+                uint64_t        i_n_num                   :     12;
+                uint64_t       i_p_num                   :      1;
+                uint64_t       i_rsvd                    :     46;
+        } ii_igfx1_fld_s;
+} ii_igfx1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this registers. These registers are      *
+ * used as scratch registers for software use.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iscr0_u {
+        uint64_t        ii_iscr0_regval;
+        struct  {
+                uint64_t        i_scratch                 :     64;
+        } ii_iscr0_fld_s;
+} ii_iscr0_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this registers. These registers are      *
+ * used as scratch registers for software use.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iscr1_u {
+        uint64_t        ii_iscr1_regval;
+        struct  {
+                uint64_t        i_scratch                 :     64;
+        } ii_iscr1_fld_s;
+} ii_iscr1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the SHub is thus the lower 16 GBytes per widget       * 
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte1_u {
+        uint64_t        ii_itte1_regval;
+        struct  {
+                uint64_t        i_offset                  :      5;
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_w_num                   :      4;
+                uint64_t        i_iosp                    :      1;
+                uint64_t        i_rsvd                    :     51;
+        } ii_itte1_fld_s;
+} ii_itte1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte2_u {
+        uint64_t        ii_itte2_regval;
+        struct  {
+                uint64_t        i_offset                  :      5;
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_w_num                   :      4;
+                uint64_t        i_iosp                    :      1;
+                uint64_t       i_rsvd                    :     51;
+        } ii_itte2_fld_s;
+} ii_itte2_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the SHub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte3_u {
+        uint64_t        ii_itte3_regval;
+        struct  {
+                uint64_t        i_offset                  :      5;
+                uint64_t       i_rsvd_1                  :      3;
+                uint64_t       i_w_num                   :      4;
+                uint64_t       i_iosp                    :      1;
+                uint64_t       i_rsvd                    :     51;
+        } ii_itte3_fld_s;
+} ii_itte3_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a SHub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the SHub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the SHub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte4_u {
+        uint64_t        ii_itte4_regval;
+        struct  {
+                uint64_t        i_offset                  :      5;
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t       i_w_num                   :      4;
+                uint64_t       i_iosp                    :      1;
+                uint64_t       i_rsvd                    :     51;
+        } ii_itte4_fld_s;
+} ii_itte4_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a SHub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte5_u {
+        uint64_t        ii_itte5_regval;
+        struct  {
+                uint64_t        i_offset                  :      5;
+                uint64_t       i_rsvd_1                  :      3;
+                uint64_t       i_w_num                   :      4;
+                uint64_t       i_iosp                    :      1;
+                uint64_t       i_rsvd                    :     51;
+        } ii_itte5_fld_s;
+} ii_itte5_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte6_u {
+        uint64_t        ii_itte6_regval;
+        struct  {
+                uint64_t        i_offset                  :      5;
+                uint64_t       i_rsvd_1                  :      3;
+                uint64_t       i_w_num                   :      4;
+                uint64_t       i_iosp                    :      1;
+                uint64_t       i_rsvd                    :     51;
+        } ii_itte6_fld_s;
+} ii_itte6_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the SHub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte7_u {
+        uint64_t        ii_itte7_regval;
+        struct  {
+                uint64_t        i_offset                  :      5;
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t       i_w_num                   :      4;
+                uint64_t       i_iosp                    :      1;
+                uint64_t       i_rsvd                    :     51;
+        } ii_itte7_fld_s;
+} ii_itte7_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprb0_u {
+        uint64_t        ii_iprb0_regval;
+        struct  {
+                uint64_t        i_c                       :      8;
+                uint64_t        i_na                      :     14;
+                uint64_t       i_rsvd_2                  :      2;
+                uint64_t        i_nb                      :     14;
+                uint64_t        i_rsvd_1                  :      2;
+                uint64_t        i_m                       :      2;
+                uint64_t        i_f                       :      1;
+                uint64_t        i_of_cnt                  :      5;
+                uint64_t        i_error                   :      1;
+                uint64_t        i_rd_to                   :      1;
+                uint64_t        i_spur_wr                 :      1;
+                uint64_t        i_spur_rd                 :      1;
+                uint64_t        i_rsvd                    :     11;
+                uint64_t        i_mult_err                :      1;
+        } ii_iprb0_fld_s;
+} ii_iprb0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprb8_u {
+        uint64_t        ii_iprb8_regval;
+        struct  {
+                uint64_t        i_c                       :      8;
+                uint64_t        i_na                      :     14;
+                uint64_t       i_rsvd_2                  :      2;
+                uint64_t        i_nb                      :     14;
+                uint64_t       i_rsvd_1                  :      2;
+                uint64_t       i_m                       :      2;
+                uint64_t       i_f                       :      1;
+                uint64_t       i_of_cnt                  :      5;
+                uint64_t       i_error                   :      1;
+                uint64_t       i_rd_to                   :      1;
+                uint64_t       i_spur_wr                 :      1;
+                uint64_t        i_spur_rd                 :      1;
+                uint64_t       i_rsvd                    :     11;
+                uint64_t        i_mult_err                :      1;
+        } ii_iprb8_fld_s;
+} ii_iprb8_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprb9_u {
+        uint64_t        ii_iprb9_regval;
+        struct  {
+                uint64_t        i_c                       :      8;
+                uint64_t        i_na                      :     14;
+                uint64_t        i_rsvd_2                  :      2;
+                uint64_t        i_nb                      :     14;
+                uint64_t        i_rsvd_1                  :      2;
+                uint64_t        i_m                       :      2;
+                uint64_t        i_f                       :      1;
+                uint64_t        i_of_cnt                  :      5;
+                uint64_t        i_error                   :      1;
+                uint64_t        i_rd_to                   :      1;
+                uint64_t        i_spur_wr                 :      1;
+                uint64_t        i_spur_rd                 :      1;
+                uint64_t        i_rsvd                    :     11;
+                uint64_t        i_mult_err                :      1;
+        } ii_iprb9_fld_s;
+} ii_iprb9_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.        *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprba_u {
+        uint64_t        ii_iprba_regval;
+        struct  {
+                uint64_t        i_c                       :      8;
+                uint64_t        i_na                      :     14;
+                uint64_t       i_rsvd_2                  :      2;
+                uint64_t        i_nb                      :     14;
+                uint64_t        i_rsvd_1                  :      2;
+                uint64_t        i_m                       :      2;
+                uint64_t        i_f                       :      1;
+                uint64_t        i_of_cnt                  :      5;
+                uint64_t        i_error                   :      1;
+                uint64_t        i_rd_to                   :      1;
+                uint64_t        i_spur_wr                 :      1;
+                uint64_t        i_spur_rd                 :      1;
+                uint64_t        i_rsvd                    :     11;
+                uint64_t        i_mult_err                :      1;
+        } ii_iprba_fld_s;
+} ii_iprba_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbb_u {
+        uint64_t        ii_iprbb_regval;
+        struct  {
+                uint64_t        i_c                       :      8;
+                uint64_t        i_na                      :     14;
+                uint64_t        i_rsvd_2                  :      2;
+                uint64_t        i_nb                      :     14;
+                uint64_t        i_rsvd_1                  :      2;
+                uint64_t        i_m                       :      2;
+                uint64_t        i_f                       :      1;
+                uint64_t        i_of_cnt                  :      5;
+                uint64_t        i_error                   :      1;
+                uint64_t        i_rd_to                   :      1;
+                uint64_t        i_spur_wr                 :      1;
+                uint64_t        i_spur_rd                 :      1;
+                uint64_t        i_rsvd                    :     11;
+                uint64_t        i_mult_err                :      1;
+        } ii_iprbb_fld_s;
+} ii_iprbb_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbc_u {
+        uint64_t        ii_iprbc_regval;
+        struct  {
+                uint64_t        i_c                       :      8;
+                uint64_t        i_na                      :     14;
+                uint64_t        i_rsvd_2                  :      2;
+                uint64_t        i_nb                      :     14;
+                uint64_t        i_rsvd_1                  :      2;
+                uint64_t        i_m                       :      2;
+                uint64_t        i_f                       :      1;
+                uint64_t        i_of_cnt                  :      5;
+                uint64_t        i_error                   :      1;
+                uint64_t        i_rd_to                   :      1;
+                uint64_t        i_spur_wr                 :      1;
+                uint64_t        i_spur_rd                 :      1;
+                uint64_t        i_rsvd                    :     11;
+                uint64_t        i_mult_err                :      1;
+        } ii_iprbc_fld_s;
+} ii_iprbc_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbd_u {
+        uint64_t        ii_iprbd_regval;
+        struct  {
+                uint64_t        i_c                       :      8;
+                uint64_t        i_na                      :     14;
+                uint64_t        i_rsvd_2                  :      2;
+                uint64_t        i_nb                      :     14;
+                uint64_t        i_rsvd_1                  :      2;
+                uint64_t        i_m                       :      2;
+                uint64_t        i_f                       :      1;
+                uint64_t        i_of_cnt                  :      5;
+                uint64_t        i_error                   :      1;
+                uint64_t        i_rd_to                   :      1;
+                uint64_t        i_spur_wr                 :      1;
+                uint64_t        i_spur_rd                 :      1;
+                uint64_t        i_rsvd                    :     11;
+                uint64_t        i_mult_err                :      1;
+        } ii_iprbd_fld_s;
+} ii_iprbd_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbe_u {
+        uint64_t        ii_iprbe_regval;
+        struct  {
+                uint64_t        i_c                       :      8;
+                uint64_t        i_na                      :     14;
+                uint64_t        i_rsvd_2                  :      2;
+                uint64_t        i_nb                      :     14;
+                uint64_t        i_rsvd_1                  :      2;
+                uint64_t        i_m                       :      2;
+                uint64_t        i_f                       :      1;
+                uint64_t        i_of_cnt                  :      5;
+                uint64_t        i_error                   :      1;
+                uint64_t        i_rd_to                   :      1;
+                uint64_t        i_spur_wr                 :      1;
+                uint64_t        i_spur_rd                 :      1;
+                uint64_t        i_rsvd                    :     11;
+                uint64_t        i_mult_err                :      1;
+        } ii_iprbe_fld_s;
+} ii_iprbe_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of Shub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbf_u {
+        uint64_t       ii_iprbf_regval;
+        struct  {
+                uint64_t       i_c                       :      8;
+                uint64_t       i_na                      :     14;
+                uint64_t       i_rsvd_2                  :      2;
+                uint64_t       i_nb                      :     14;
+                uint64_t       i_rsvd_1                  :      2;
+                uint64_t       i_m                       :      2;
+                uint64_t       i_f                       :      1;
+                uint64_t       i_of_cnt                  :      5;
+                uint64_t       i_error                   :      1;
+                uint64_t       i_rd_to                   :      1;
+                uint64_t       i_spur_wr                 :      1;
+                uint64_t       i_spur_rd                 :      1;
+                uint64_t       i_rsvd                    :     11;
+                uint64_t       i_mult_err                :      1;
+        } ii_iprbe_fld_s;
+} ii_iprbf_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register specifies the timeout value to use for monitoring     *
+ * Crosstalk credits which are used outbound to Crosstalk. An           *
+ * internal counter called the Crosstalk Credit Timeout Counter         *
+ * increments every 128 II clocks. The counter starts counting          *
+ * anytime the credit count drops below a threshold, and resets to      *
+ * zero (stops counting) anytime the credit count is at or above the    *
+ * threshold. The threshold is 1 credit in direct connect mode and 2    *
+ * in Crossbow connect mode. When the internal Crosstalk Credit         *
+ * Timeout Counter reaches the value programmed in this register, a     *
+ * Crosstalk Credit Timeout has occurred. The internal counter is not   *
+ * readable from software, and stops counting at its maximum value,     *
+ * so it cannot cause more than one interrupt.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixcc_u {
+        uint64_t        ii_ixcc_regval;
+        struct  {
+                uint64_t        i_time_out                :     26;
+                uint64_t        i_rsvd                    :     38;
+        } ii_ixcc_fld_s;
+} ii_ixcc_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register qualifies all the PIO and DMA            *
+ * operations launched from widget 0 towards the SHub. In               *
+ * addition, it also qualifies accesses by the BTE streams.             *
+ * The bits in each field of this register are cleared by the SHub      *
+ * upon detection of an error which requires widget 0 or the BTE        *
+ * streams to be terminated. Whether or not widget x has access         *
+ * rights to this SHub is determined by an AND of the device            *
+ * enable bit in the appropriate field of this register and bit 0 in    *
+ * the Wx_IAC field. The bits in this field are set by writing a 1 to   *
+ * them. Incoming replies from Crosstalk are not subject to this        *
+ * access control mechanism.                                            *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_imem_u {
+        uint64_t        ii_imem_regval;
+        struct  {
+                uint64_t        i_w0_esd                  :      1;
+                uint64_t        i_rsvd_3                  :      3;
+                uint64_t        i_b0_esd                  :      1;
+                uint64_t        i_rsvd_2                  :      3;
+                uint64_t        i_b1_esd                  :      1;
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_clr_precise             :      1;
+                uint64_t       i_rsvd                    :     51;
+        } ii_imem_fld_s;
+} ii_imem_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register specifies the timeout value to use for   *
+ * monitoring Crosstalk tail flits coming into the Shub in the          *
+ * TAIL_TO field. An internal counter associated with this register     *
+ * is incremented every 128 II internal clocks (7 bits). The counter    *
+ * starts counting anytime a header micropacket is received and stops   *
+ * counting (and resets to zero) any time a micropacket with a Tail     *
+ * bit is received. Once the counter reaches the threshold value        *
+ * programmed in this register, it generates an interrupt to the        *
+ * processor that is programmed into the IIDSR. The counter saturates   *
+ * (does not roll over) at its maximum value, so it cannot cause        *
+ * another interrupt until after it is cleared.                         *
+ * The register also contains the Read Response Timeout values. The     *
+ * Prescalar is 23 bits, and counts II clocks. An internal counter      *
+ * increments on every II clock and when it reaches the value in the    *
+ * Prescalar field, all IPRTE registers with their valid bits set       *
+ * have their Read Response timers bumped. Whenever any of them match   *
+ * the value in the RRSP_TO field, a Read Response Timeout has          *
+ * occurred, and error handling occurs as described in the Error        *
+ * Handling section of this document.                                   *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixtt_u {
+        uint64_t        ii_ixtt_regval;
+        struct  {
+                uint64_t        i_tail_to                 :     26;
+                uint64_t        i_rsvd_1                  :      6;
+                uint64_t        i_rrsp_ps                 :     23;
+                uint64_t        i_rrsp_to                 :      5;
+                uint64_t        i_rsvd                    :      4;
+        } ii_ixtt_fld_s;
+} ii_ixtt_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  Writing a 1 to the fields of this register clears the appropriate   *
+ * error bits in other areas of SHub. Note that when the                *
+ * E_PRB_x bits are used to clear error bits in PRB registers,          *
+ * SPUR_RD and SPUR_WR may persist, because they require additional     *
+ * action to clear them. See the IPRBx and IXSS Register                *
+ * specifications.                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ieclr_u {
+        uint64_t        ii_ieclr_regval;
+        struct  {
+                uint64_t        i_e_prb_0                 :      1;
+                uint64_t        i_rsvd                    :      7;
+                uint64_t        i_e_prb_8                 :      1;
+                uint64_t        i_e_prb_9                 :      1;
+                uint64_t        i_e_prb_a                 :      1;
+                uint64_t        i_e_prb_b                 :      1;
+                uint64_t        i_e_prb_c                 :      1;
+                uint64_t        i_e_prb_d                 :      1;
+                uint64_t        i_e_prb_e                 :      1;
+                uint64_t        i_e_prb_f                 :      1;
+                uint64_t        i_e_crazy                 :      1;
+                uint64_t        i_e_bte_0                 :      1;
+                uint64_t        i_e_bte_1                 :      1;
+                uint64_t        i_reserved_1              :     10;
+                uint64_t        i_spur_rd_hdr             :      1;
+                uint64_t        i_cam_intr_to             :      1;
+                uint64_t        i_cam_overflow            :      1;
+                uint64_t        i_cam_read_miss           :      1;
+                uint64_t        i_ioq_rep_underflow       :      1;
+                uint64_t        i_ioq_req_underflow       :      1;
+                uint64_t        i_ioq_rep_overflow        :      1;
+                uint64_t        i_ioq_req_overflow        :      1;
+                uint64_t        i_iiq_rep_overflow        :      1;
+                uint64_t        i_iiq_req_overflow        :      1;
+                uint64_t        i_ii_xn_rep_cred_overflow :      1;
+                uint64_t        i_ii_xn_req_cred_overflow :      1;
+                uint64_t        i_ii_xn_invalid_cmd       :      1;
+                uint64_t        i_xn_ii_invalid_cmd       :      1;
+                uint64_t        i_reserved_2              :     21;
+        } ii_ieclr_fld_s;
+} ii_ieclr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register controls both BTEs. SOFT_RESET is intended for        *
+ * recovery after an error. COUNT controls the total number of CRBs     *
+ * that both BTEs (combined) can use, which affects total BTE           *
+ * bandwidth.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibcr_u {
+        uint64_t        ii_ibcr_regval;
+        struct  {
+                uint64_t        i_count                   :      4;
+                uint64_t        i_rsvd_1                  :      4;
+                uint64_t        i_soft_reset              :      1;
+                uint64_t        i_rsvd                    :     55;
+        } ii_ibcr_fld_s;
+} ii_ibcr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the header of a spurious read response       *
+ * received from Crosstalk. A spurious read response is defined as a    *
+ * read response received by II from a widget for which (1) the SIDN    *
+ * has a value between 1 and 7, inclusive (II never sends requests to   *
+ * these widgets (2) there is no valid IPRTE register which             *
+ * corresponds to the TNUM, or (3) the widget indicated in SIDN is      *
+ * not the same as the widget recorded in the IPRTE register            *
+ * referenced by the TNUM. If this condition is true, and if the        *
+ * IXSS[VALID] bit is clear, then the header of the spurious read       *
+ * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The    *
+ * errant header is thereby captured, and no further spurious read      *
+ * respones are captured until IXSS[VALID] is cleared by setting the    *
+ * appropriate bit in IECLR.Everytime a spurious read response is       *
+ * detected, the SPUR_RD bit of the PRB corresponding to the incoming   *
+ * message's SIDN field is set. This always happens, regarless of       *
+ * whether a header is captured. The programmer should check            *
+ * IXSM[SIDN] to determine which widget sent the spurious response,     *
+ * because there may be more than one SPUR_RD bit set in the PRB        *
+ * registers. The widget indicated by IXSM[SIDN] was the first          *
+ * spurious read response to be received since the last time            *
+ * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB      *
+ * will be set. Any SPUR_RD bits in any other PRB registers indicate    *
+ * spurious messages from other widets which were detected after the    *
+ * header was captured..                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixsm_u {
+        uint64_t        ii_ixsm_regval;
+        struct  {
+                uint64_t        i_byte_en                 :     32;
+                uint64_t        i_reserved                :      1;
+                uint64_t        i_tag                     :      3;
+                uint64_t        i_alt_pactyp              :      4;
+                uint64_t        i_bo                      :      1;
+                uint64_t        i_error                   :      1;
+                uint64_t        i_vbpm                    :      1;
+                uint64_t        i_gbr                     :      1;
+                uint64_t        i_ds                      :      2;
+                uint64_t        i_ct                      :      1;
+                uint64_t        i_tnum                    :      5;
+                uint64_t        i_pactyp                  :      4;
+                uint64_t        i_sidn                    :      4;
+                uint64_t        i_didn                    :      4;
+        } ii_ixsm_fld_s;
+} ii_ixsm_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the sideband bits of a spurious read         *
+ * response received from Crosstalk.                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixss_u {
+        uint64_t        ii_ixss_regval;
+        struct  {
+                uint64_t        i_sideband                :      8;
+                uint64_t        i_rsvd                    :     55;
+                uint64_t        i_valid                   :      1;
+        } ii_ixss_fld_s;
+} ii_ixss_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register enables software to access the II LLP's test port.    *
+ * Refer to the LLP 2.5 documentation for an explanation of the test    *
+ * port. Software can write to this register to program the values      *
+ * for the control fields (TestErrCapture, TestClear, TestFlit,         *
+ * TestMask and TestSeed). Similarly, software can read from this       *
+ * register to obtain the values of the test port's status outputs      *
+ * (TestCBerr, TestValid and TestData).                                 *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilct_u {
+        uint64_t        ii_ilct_regval;
+        struct  {
+                uint64_t        i_test_seed               :     20;
+                uint64_t        i_test_mask               :      8;
+                uint64_t        i_test_data               :     20;
+                uint64_t        i_test_valid              :      1;
+                uint64_t        i_test_cberr              :      1;
+                uint64_t        i_test_flit               :      3;
+                uint64_t        i_test_clear              :      1;
+                uint64_t        i_test_err_capture        :      1;
+                uint64_t        i_rsvd                    :      9;
+        } ii_ilct_fld_s;
+} ii_ilct_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  If the II detects an illegal incoming Duplonet packet (request or   *
+ * reply) when VALID==0 in the IIEPH1 register, then it saves the       *
+ * contents of the packet's header flit in the IIEPH1 and IIEPH2        *
+ * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit,     *
+ * and assigns a value to the ERR_TYPE field which indicates the        *
+ * specific nature of the error. The II recognizes four different       *
+ * types of errors: short request packets (ERR_TYPE==2), short reply    *
+ * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long   *
+ * reply packets (ERR_TYPE==5). The encodings for these types of        *
+ * errors were chosen to be consistent with the same types of errors    *
+ * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in    *
+ * the LB unit). If the II detects an illegal incoming Duplonet         *
+ * packet when VALID==1 in the IIEPH1 register, then it merely sets     *
+ * the OVERRUN bit to indicate that a subsequent error has happened,    *
+ * and does nothing further.                                            *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iieph1_u {
+        uint64_t        ii_iieph1_regval;
+        struct  {
+                uint64_t        i_command                 :      7;
+                uint64_t        i_rsvd_5                  :      1;
+                uint64_t        i_suppl                   :     14;
+                uint64_t        i_rsvd_4                  :      1;
+                uint64_t        i_source                  :     14;
+                uint64_t        i_rsvd_3                  :      1;
+                uint64_t        i_err_type                :      4;
+                uint64_t        i_rsvd_2                  :      4;
+                uint64_t        i_overrun                 :      1;
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_valid                   :      1;
+                uint64_t        i_rsvd                    :     13;
+        } ii_iieph1_fld_s;
+} ii_iieph1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register holds the Address field from the header flit of an    *
+ * incoming erroneous Duplonet packet, along with the tail bit which    *
+ * accompanied this header flit. This register is essentially an        *
+ * extension of IIEPH1. Two registers were necessary because the 64     *
+ * bits available in only a single register were insufficient to        *
+ * capture the entire header flit of an erroneous packet.               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iieph2_u {
+        uint64_t        ii_iieph2_regval;
+        struct  {
+                uint64_t        i_rsvd_0                  :      3;
+                uint64_t        i_address                 :     47;
+                uint64_t        i_rsvd_1                  :     10;
+                uint64_t        i_tail                    :      1;
+                uint64_t        i_rsvd                    :      3;
+        } ii_iieph2_fld_s;
+} ii_iieph2_u_t;
+
+
+/******************************/
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register's value is a bit vector that guards access from SXBs  *
+ * to local registers within the II as well as to external Crosstalk    *
+ * widgets                                                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_islapr_u {
+        uint64_t        ii_islapr_regval;
+        struct  {
+                uint64_t        i_region                  :     64;
+        } ii_islapr_fld_s;
+} ii_islapr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register of the 56-bit value "Pup+Bun" will cause   *
+ * the bit in the ISLAPR register corresponding to the region of the    *
+ * requestor to be set (access allowed).                                (
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_islapo_u {
+        uint64_t        ii_islapo_regval;
+        struct  {
+                uint64_t        i_io_sbx_ovrride          :     56;
+                uint64_t        i_rsvd                    :      8;
+        } ii_islapo_fld_s;
+} ii_islapo_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Determines how long the wrapper will wait aftr an interrupt is      *
+ * initially issued from the II before it times out the outstanding     *
+ * interrupt and drops it from the interrupt queue.                     * 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iwi_u {
+        uint64_t        ii_iwi_regval;
+        struct  {
+                uint64_t        i_prescale                :     24;
+                uint64_t        i_rsvd                    :      8;
+                uint64_t        i_timeout                 :      8;
+                uint64_t        i_rsvd1                   :      8;
+                uint64_t        i_intrpt_retry_period     :      8;
+                uint64_t        i_rsvd2                   :      8;
+        } ii_iwi_fld_s;
+} ii_iwi_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Log errors which have occurred in the II wrapper. The errors are    *
+ * cleared by writing to the IECLR register.                            * 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iwel_u {
+        uint64_t        ii_iwel_regval;
+        struct  {
+                uint64_t        i_intr_timed_out          :      1;
+                uint64_t        i_rsvd                    :      7;
+                uint64_t        i_cam_overflow            :      1;
+                uint64_t        i_cam_read_miss           :      1;
+                uint64_t        i_rsvd1                   :      2;
+                uint64_t        i_ioq_rep_underflow       :      1;
+                uint64_t        i_ioq_req_underflow       :      1;
+                uint64_t        i_ioq_rep_overflow        :      1;
+                uint64_t        i_ioq_req_overflow        :      1;
+                uint64_t        i_iiq_rep_overflow        :      1;
+                uint64_t        i_iiq_req_overflow        :      1;
+                uint64_t        i_rsvd2                   :      6;
+                uint64_t        i_ii_xn_rep_cred_over_under:     1;
+                uint64_t        i_ii_xn_req_cred_over_under:     1;
+                uint64_t        i_rsvd3                   :      6;
+                uint64_t        i_ii_xn_invalid_cmd       :      1;
+                uint64_t        i_xn_ii_invalid_cmd       :      1;
+                uint64_t        i_rsvd4                   :     30;
+        } ii_iwel_fld_s;
+} ii_iwel_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Controls the II wrapper.                                            * 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iwc_u {
+        uint64_t        ii_iwc_regval;
+        struct  {
+                uint64_t        i_dma_byte_swap           :      1;
+                uint64_t        i_rsvd                    :      3;
+                uint64_t        i_cam_read_lines_reset    :      1;
+                uint64_t        i_rsvd1                   :      3;
+                uint64_t        i_ii_xn_cred_over_under_log:     1;
+                uint64_t        i_rsvd2                   :     19;
+                uint64_t        i_xn_rep_iq_depth         :      5;
+                uint64_t        i_rsvd3                   :      3;
+                uint64_t        i_xn_req_iq_depth         :      5;
+                uint64_t        i_rsvd4                   :      3;
+                uint64_t        i_iiq_depth               :      6;
+                uint64_t        i_rsvd5                   :     12;
+                uint64_t        i_force_rep_cred          :      1;
+                uint64_t        i_force_req_cred          :      1;
+        } ii_iwc_fld_s;
+} ii_iwc_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Status in the II wrapper.                                           * 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iws_u {
+        uint64_t        ii_iws_regval;
+        struct  {
+                uint64_t        i_xn_rep_iq_credits       :      5;
+                uint64_t        i_rsvd                    :      3;
+                uint64_t        i_xn_req_iq_credits       :      5;
+                uint64_t        i_rsvd1                   :     51;
+        } ii_iws_fld_s;
+} ii_iws_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Masks errors in the IWEL register.                                  *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iweim_u {
+        uint64_t        ii_iweim_regval;
+        struct  {
+                uint64_t        i_intr_timed_out          :      1;
+                uint64_t        i_rsvd                    :      7;
+                uint64_t        i_cam_overflow            :      1;
+                uint64_t        i_cam_read_miss           :      1;
+                uint64_t        i_rsvd1                   :      2;
+                uint64_t        i_ioq_rep_underflow       :      1;
+                uint64_t        i_ioq_req_underflow       :      1;
+                uint64_t        i_ioq_rep_overflow        :      1;
+                uint64_t        i_ioq_req_overflow        :      1;
+                uint64_t        i_iiq_rep_overflow        :      1;
+                uint64_t        i_iiq_req_overflow        :      1;
+                uint64_t        i_rsvd2                   :      6;
+                uint64_t        i_ii_xn_rep_cred_overflow :      1;
+                uint64_t        i_ii_xn_req_cred_overflow :      1;
+                uint64_t        i_rsvd3                   :      6;
+                uint64_t        i_ii_xn_invalid_cmd       :      1;
+                uint64_t        i_xn_ii_invalid_cmd       :      1;
+                uint64_t        i_rsvd4                   :     30;
+        } ii_iweim_fld_s;
+} ii_iweim_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register causes a particular field in the           *
+ * corresponding widget's PRB entry to be adjusted up or down by 1.     *
+ * This counter should be used when recovering from error and reset     *
+ * conditions. Note that software would be capable of causing           *
+ * inadvertent overflow or underflow of these counters.                 *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ipca_u {
+        uint64_t        ii_ipca_regval;
+        struct  {
+                uint64_t        i_wid                     :      4;
+                uint64_t        i_adjust                  :      1;
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_field                   :      2;
+                uint64_t        i_rsvd                    :     54;
+        } ii_ipca_fld_s;
+} ii_ipca_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+typedef union ii_iprte0a_u {
+        uint64_t        ii_iprte0a_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :     54;
+                uint64_t        i_widget                  :      4;
+                uint64_t        i_to_cnt                  :      5;
+                uint64_t       i_vld                     :      1;
+        } ii_iprte0a_fld_s;
+} ii_iprte0a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte1a_u {
+        uint64_t        ii_iprte1a_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :     54;
+                uint64_t        i_widget                  :      4;
+                uint64_t        i_to_cnt                  :      5;
+                uint64_t       i_vld                     :      1;
+        } ii_iprte1a_fld_s;
+} ii_iprte1a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte2a_u {
+        uint64_t        ii_iprte2a_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :     54;
+                uint64_t        i_widget                  :      4;
+                uint64_t        i_to_cnt                  :      5;
+                uint64_t       i_vld                     :      1;
+        } ii_iprte2a_fld_s;
+} ii_iprte2a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte3a_u {
+        uint64_t        ii_iprte3a_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :     54;
+                uint64_t        i_widget                  :      4;
+                uint64_t        i_to_cnt                  :      5;
+                uint64_t        i_vld                     :      1;
+        } ii_iprte3a_fld_s;
+} ii_iprte3a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte4a_u {
+        uint64_t        ii_iprte4a_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :     54;
+                uint64_t        i_widget                  :      4;
+                uint64_t        i_to_cnt                  :      5;
+                uint64_t        i_vld                     :      1;
+        } ii_iprte4a_fld_s;
+} ii_iprte4a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte5a_u {
+        uint64_t        ii_iprte5a_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :     54;
+                uint64_t        i_widget                  :      4;
+                uint64_t        i_to_cnt                  :      5;
+                uint64_t        i_vld                     :      1;
+        } ii_iprte5a_fld_s;
+} ii_iprte5a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte6a_u {
+        uint64_t        ii_iprte6a_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :     54;
+                uint64_t        i_widget                  :      4;
+                uint64_t        i_to_cnt                  :      5;
+                uint64_t        i_vld                     :      1;
+        } ii_iprte6a_fld_s;
+} ii_iprte6a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte7a_u {
+        uint64_t       ii_iprte7a_regval;
+        struct  {
+                uint64_t       i_rsvd_1                  :     54;
+                uint64_t       i_widget                  :      4;
+                uint64_t       i_to_cnt                  :      5;
+                uint64_t       i_vld                     :      1;
+        } ii_iprtea7_fld_s;
+} ii_iprte7a_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+typedef union ii_iprte0b_u {
+        uint64_t        ii_iprte0b_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_address                 :     47;
+                uint64_t        i_init                    :      3;
+                uint64_t       i_source                  :     11;
+        } ii_iprte0b_fld_s;
+} ii_iprte0b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte1b_u {
+        uint64_t        ii_iprte1b_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_address                 :     47;
+                uint64_t        i_init                    :      3;
+                uint64_t       i_source                  :     11;
+        } ii_iprte1b_fld_s;
+} ii_iprte1b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte2b_u {
+        uint64_t        ii_iprte2b_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_address                 :     47;
+                uint64_t        i_init                    :      3;
+                uint64_t       i_source                  :     11;
+        } ii_iprte2b_fld_s;
+} ii_iprte2b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte3b_u {
+        uint64_t        ii_iprte3b_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_address                 :     47;
+                uint64_t        i_init                    :      3;
+                uint64_t       i_source                  :     11;
+        } ii_iprte3b_fld_s;
+} ii_iprte3b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte4b_u {
+        uint64_t        ii_iprte4b_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_address                 :     47;
+                uint64_t        i_init                    :      3;
+                uint64_t       i_source                  :     11;
+        } ii_iprte4b_fld_s;
+} ii_iprte4b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte5b_u {
+        uint64_t        ii_iprte5b_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_address                 :     47;
+                uint64_t        i_init                    :      3;
+                uint64_t       i_source                  :     11;
+        } ii_iprte5b_fld_s;
+} ii_iprte5b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte6b_u {
+        uint64_t        ii_iprte6b_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_address                 :     47;
+                uint64_t        i_init                    :      3;
+                uint64_t       i_source                  :     11;
+
+        } ii_iprte6b_fld_s;
+} ii_iprte6b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte7b_u {
+        uint64_t       ii_iprte7b_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_address                 :     47;
+                uint64_t        i_init                    :      3;
+                uint64_t       i_source                  :     11;
+        } ii_iprte7b_fld_s;
+} ii_iprte7b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  SHub II contains a feature which did not exist in      *
+ * the Hub which automatically cleans up after a Read Response          *
+ * timeout, including deallocation of the IPRTE and recovery of IBuf    *
+ * space. The inclusion of this register in SHub is for backward        *
+ * compatibility                                                        *
+ * A write to this register causes an entry from the table of           *
+ * outstanding PIO Read Requests to be freed and returned to the        *
+ * stack of free entries. This register is used in handling the         *
+ * timeout errors that result in a PIO Reply never returning from       *
+ * Crosstalk.                                                           *
+ * Note that this register does not affect the contents of the IPRTE    *
+ * registers. The Valid bits in those registers have to be              *
+ * specifically turned off by software.                                 *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ipdr_u {
+        uint64_t        ii_ipdr_regval;
+        struct  {
+                uint64_t        i_te                      :      3;
+                uint64_t        i_rsvd_1                  :      1;
+                uint64_t        i_pnd                     :      1;
+                uint64_t        i_init_rpcnt              :      1;
+                uint64_t        i_rsvd                    :     58;
+        } ii_ipdr_fld_s;
+} ii_ipdr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register causes a CRB entry to be returned to the   *
+ * queue of free CRBs. The entry should have previously been cleared    *
+ * (mark bit) via backdoor access to the pertinent CRB entry. This      *
+ * register is used in the last step of handling the errors that are    *
+ * captured and marked in CRB entries.  Briefly: 1) first error for     *
+ * DMA write from a particular device, and first error for a            *
+ * particular BTE stream, lead to a marked CRB entry, and processor     *
+ * interrupt, 2) software reads the error information captured in the   *
+ * CRB entry, and presumably takes some corrective action, 3)           *
+ * software clears the mark bit, and finally 4) software writes to      *
+ * the ICDR register to return the CRB entry to the list of free CRB    *
+ * entries.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icdr_u {
+        uint64_t        ii_icdr_regval;
+        struct  {
+                uint64_t        i_crb_num                 :      4;
+                uint64_t        i_pnd                     :      1;
+                uint64_t       i_rsvd                    :     59;
+        } ii_icdr_fld_s;
+} ii_icdr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register provides debug access to two FIFOs inside of II.      *
+ * Both IOQ_MAX* fields of this register contain the instantaneous      *
+ * depth (in units of the number of available entries) of the           *
+ * associated IOQ FIFO.  A read of this register will return the        *
+ * number of free entries on each FIFO at the time of the read.  So     *
+ * when a FIFO is idle, the associated field contains the maximum       *
+ * depth of the FIFO.  This register is writable for debug reasons      *
+ * and is intended to be written with the maximum desired FIFO depth    *
+ * while the FIFO is idle. Software must assure that II is idle when    *
+ * this register is written. If there are any active entries in any     *
+ * of these FIFOs when this register is written, the results are        *
+ * undefined.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ifdr_u {
+        uint64_t        ii_ifdr_regval;
+        struct  {
+                uint64_t        i_ioq_max_rq              :      7;
+                uint64_t        i_set_ioq_rq              :      1;
+                uint64_t        i_ioq_max_rp              :      7;
+                uint64_t        i_set_ioq_rp              :      1;
+                uint64_t        i_rsvd                    :     48;
+        } ii_ifdr_fld_s;
+} ii_ifdr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows the II to become sluggish in removing          *
+ * messages from its inbound queue (IIQ). This will cause messages to   *
+ * back up in either virtual channel. Disabling the "molasses" mode     *
+ * subsequently allows the II to be tested under stress. In the         *
+ * sluggish ("Molasses") mode, the localized effects of congestion      *
+ * can be observed.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iiap_u {
+        uint64_t       ii_iiap_regval;
+        struct  {
+                uint64_t       i_rq_mls                  :      6;
+                uint64_t        i_rsvd_1                  :      2;
+                uint64_t        i_rp_mls                  :      6;
+                uint64_t       i_rsvd                    :     50;
+        } ii_iiap_fld_s;
+} ii_iiap_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows several parameters of CRB operation to be      *
+ * set. Note that writing to this register can have catastrophic side   *
+ * effects, if the CRB is not quiescent, i.e. if the CRB is             *
+ * processing protocol messages when the write occurs.                  *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icmr_u {
+        uint64_t        ii_icmr_regval;
+        struct  {
+                uint64_t        i_sp_msg                  :      1;
+                uint64_t        i_rd_hdr                  :      1;
+                uint64_t        i_rsvd_4                  :      2;
+                uint64_t        i_c_cnt                   :      4;
+                uint64_t        i_rsvd_3                  :      4;
+                uint64_t        i_clr_rqpd                :      1;
+                uint64_t        i_clr_rppd                :      1;
+                uint64_t        i_rsvd_2                  :      2;
+                uint64_t        i_fc_cnt                  :      4;
+                uint64_t        i_crb_vld                 :     15;
+                uint64_t        i_crb_mark                :     15;
+                uint64_t        i_rsvd_1                  :      2;
+                uint64_t        i_precise                 :      1;
+                uint64_t        i_rsvd                    :     11;
+        } ii_icmr_fld_s;
+} ii_icmr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows control of the table portion of the CRB        *
+ * logic via software. Control operations from this register have       *
+ * priority over all incoming Crosstalk or BTE requests.                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iccr_u {
+        uint64_t        ii_iccr_regval;
+        struct  {
+                uint64_t        i_crb_num                 :      4;
+                uint64_t        i_rsvd_1                  :      4;
+                uint64_t        i_cmd                     :      8;
+                uint64_t        i_pending                 :      1;
+                uint64_t        i_rsvd                    :     47;
+        } ii_iccr_fld_s;
+} ii_iccr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows the maximum timeout value to be programmed.    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icto_u {
+        uint64_t        ii_icto_regval;
+        struct  {
+                uint64_t        i_timeout                 :      8;
+                uint64_t        i_rsvd                    :     56;
+        } ii_icto_fld_s;
+} ii_icto_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows the timeout prescalar to be programmed. An     *
+ * internal counter is associated with this register. When the          *
+ * internal counter reaches the value of the PRESCALE field, the        *
+ * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT]   *
+ * field). The internal counter resets to zero, and then continues      *
+ * counting.                                                            *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ictp_u {
+        uint64_t        ii_ictp_regval;
+        struct  {
+                uint64_t        i_prescale                :     24;
+                uint64_t        i_rsvd                    :     40;
+        } ii_ictp_fld_s;
+} ii_ictp_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ * The CRB Entry registers can be conceptualized as rows and columns    *
+ * (illustrated in the table above). Each row contains the 4            *
+ * registers required for a single CRB Entry. The first doubleword      *
+ * (column) for each entry is labeled A, and the second doubleword      *
+ * (higher address) is labeled B, the third doubleword is labeled C,    *
+ * the fourth doubleword is labeled D and the fifth doubleword is       *
+ * labeled E. All CRB entries have their addresses on a quarter         *
+ * cacheline aligned boundary.                   *
+ * Upon reset, only the following fields are initialized: valid         *
+ * (VLD), priority count, timeout, timeout valid, and context valid.    *
+ * All other bits should be cleared by software before use (after       *
+ * recovering any potential error state from before the reset).         *
+ * The following four tables summarize the format for the four          *
+ * registers that are used for each ICRB# Entry.                        *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_a_u {
+        uint64_t        ii_icrb0_a_regval;
+        struct  {
+                uint64_t        ia_iow                    :      1;
+                uint64_t        ia_vld                    :      1;
+                uint64_t        ia_addr                   :     47;
+                uint64_t        ia_tnum                   :      5;
+                uint64_t        ia_sidn                   :      4;
+                uint64_t       ia_rsvd                   :      6;
+        } ii_icrb0_a_fld_s;
+} ii_icrb0_a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_b_u {
+        uint64_t        ii_icrb0_b_regval;
+        struct  {
+                uint64_t        ib_xt_err                 :      1;
+                uint64_t        ib_mark                   :      1;
+                uint64_t        ib_ln_uce                 :      1;
+                uint64_t        ib_errcode                :      3;
+                uint64_t        ib_error                  :      1;
+                uint64_t        ib_stall__bte_1           :      1;
+                uint64_t        ib_stall__bte_0           :      1;
+                uint64_t        ib_stall__intr            :      1;
+                uint64_t        ib_stall_ib               :      1;
+                uint64_t        ib_intvn                  :      1;
+                uint64_t        ib_wb                     :      1;
+                uint64_t        ib_hold                   :      1;
+                uint64_t        ib_ack                    :      1;
+                uint64_t        ib_resp                   :      1;
+                uint64_t        ib_ack_cnt                :     11;
+                uint64_t        ib_rsvd                   :      7;
+                uint64_t        ib_exc                    :      5;
+                uint64_t        ib_init                   :      3;
+                uint64_t        ib_imsg                   :      8;
+                uint64_t        ib_imsgtype               :      2;
+                uint64_t        ib_use_old                :      1;
+                uint64_t        ib_rsvd_1                 :     11;
+        } ii_icrb0_b_fld_s;
+} ii_icrb0_b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_c_u {
+        uint64_t        ii_icrb0_c_regval;
+        struct  {
+                uint64_t        ic_source                 :     15;
+                uint64_t        ic_size                   :      2;
+                uint64_t        ic_ct                     :      1;
+                uint64_t        ic_bte_num                :      1;
+                uint64_t        ic_gbr                    :      1;
+                uint64_t        ic_resprqd                :      1;
+                uint64_t        ic_bo                     :      1;
+                uint64_t        ic_suppl                  :     15;
+                uint64_t        ic_rsvd                   :     27;
+        } ii_icrb0_c_fld_s;
+} ii_icrb0_c_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_d_u {
+        uint64_t        ii_icrb0_d_regval;
+        struct  {
+                uint64_t        id_pa_be                  :     43;
+                uint64_t        id_bte_op                 :      1;
+                uint64_t        id_pr_psc                 :      4;
+                uint64_t        id_pr_cnt                 :      4;
+                uint64_t        id_sleep                  :      1;
+                uint64_t        id_rsvd                   :     11;
+        } ii_icrb0_d_fld_s;
+} ii_icrb0_d_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_e_u {
+        uint64_t        ii_icrb0_e_regval;
+        struct  {
+                uint64_t        ie_timeout                :      8;
+                uint64_t        ie_context                :     15;
+                uint64_t        ie_rsvd                   :      1;
+                uint64_t        ie_tvld                   :      1;
+                uint64_t        ie_cvld                   :      1;
+                uint64_t        ie_rsvd_0                 :     38;
+        } ii_icrb0_e_fld_s;
+} ii_icrb0_e_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the lower 64 bits of the header of the       *
+ * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
+ * register is set.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icsml_u {
+        uint64_t        ii_icsml_regval;
+        struct  {
+                uint64_t        i_tt_addr                 :     47;
+                uint64_t        i_newsuppl_ex             :     14;
+                uint64_t        i_reserved                :      2;
+                uint64_t       i_overflow                :      1;
+        } ii_icsml_fld_s;
+} ii_icsml_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the middle 64 bits of the header of the      *
+ * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
+ * register is set.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icsmm_u {
+        uint64_t        ii_icsmm_regval;
+        struct  {
+                uint64_t        i_tt_ack_cnt              :     11;
+                uint64_t        i_reserved                :     53;
+        } ii_icsmm_fld_s;
+} ii_icsmm_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the microscopic state, all the inputs to     *
+ * the protocol table, captured with the spurious message. Valid when   *
+ * the SP_MSG bit in the ICMR register is set.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icsmh_u {
+        uint64_t        ii_icsmh_regval;
+        struct  {
+                uint64_t        i_tt_vld                  :      1;
+                uint64_t        i_xerr                    :      1;
+                uint64_t        i_ft_cwact_o              :      1;
+                uint64_t        i_ft_wact_o               :      1;
+                uint64_t       i_ft_active_o             :      1;
+                uint64_t        i_sync                    :      1;
+                uint64_t        i_mnusg                   :      1;
+                uint64_t        i_mnusz                   :      1;
+                uint64_t        i_plusz                   :      1;
+                uint64_t        i_plusg                   :      1;
+                uint64_t        i_tt_exc                  :      5;
+                uint64_t        i_tt_wb                   :      1;
+                uint64_t        i_tt_hold                 :      1;
+                uint64_t        i_tt_ack                  :      1;
+                uint64_t        i_tt_resp                 :      1;
+                uint64_t        i_tt_intvn                :      1;
+                uint64_t        i_g_stall_bte1            :      1;
+                uint64_t        i_g_stall_bte0            :      1;
+                uint64_t        i_g_stall_il              :      1;
+                uint64_t        i_g_stall_ib              :      1;
+                uint64_t        i_tt_imsg                 :      8;
+                uint64_t        i_tt_imsgtype             :      2;
+                uint64_t        i_tt_use_old              :      1;
+                uint64_t        i_tt_respreqd             :      1;
+                uint64_t        i_tt_bte_num              :      1;
+                uint64_t        i_cbn                     :      1;
+                uint64_t        i_match                   :      1;
+                uint64_t        i_rpcnt_lt_34             :      1;
+                uint64_t        i_rpcnt_ge_34             :      1;
+                uint64_t        i_rpcnt_lt_18             :      1;
+                uint64_t        i_rpcnt_ge_18             :      1;
+                uint64_t       i_rpcnt_lt_2              :      1;
+                uint64_t        i_rpcnt_ge_2              :      1;
+                uint64_t        i_rqcnt_lt_18             :      1;
+                uint64_t        i_rqcnt_ge_18             :      1;
+                uint64_t        i_rqcnt_lt_2              :      1;
+                uint64_t        i_rqcnt_ge_2              :      1;
+                uint64_t        i_tt_device               :      7;
+                uint64_t        i_tt_init                 :      3;
+                uint64_t        i_reserved                :      5;
+        } ii_icsmh_fld_s;
+} ii_icsmh_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  The Shub DEBUG unit provides a 3-bit selection signal to the        *
+ * II core and a 3-bit selection signal to the fsbclk domain in the II  *
+ * wrapper.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_idbss_u {
+        uint64_t        ii_idbss_regval;
+        struct  {
+                uint64_t        i_iioclk_core_submenu     :      3;
+                uint64_t        i_rsvd                    :      5;
+                uint64_t        i_fsbclk_wrapper_submenu  :      3;
+                uint64_t        i_rsvd_1                  :      5;
+                uint64_t        i_iioclk_menu             :      5;
+                uint64_t        i_rsvd_2                  :     43;
+        } ii_idbss_fld_s;
+} ii_idbss_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register is used to set up the length for a       *
+ * transfer and then to monitor the progress of that transfer. This     *
+ * register needs to be initialized before a transfer is started. A     *
+ * legitimate write to this register will set the Busy bit, clear the   *
+ * Error bit, and initialize the length to the value desired.           *
+ * While the transfer is in progress, hardware will decrement the       *
+ * length field with each successful block that is copied. Once the     *
+ * transfer completes, hardware will clear the Busy bit. The length     *
+ * field will also contain the number of cache lines left to be         *
+ * transferred.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibls0_u {
+        uint64_t        ii_ibls0_regval;
+        struct  {
+                uint64_t        i_length                  :     16;
+                uint64_t        i_error                   :      1;
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_busy                    :      1;
+                uint64_t       i_rsvd                    :     43;
+        } ii_ibls0_fld_s;
+} ii_ibls0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibsa0_u {
+        uint64_t        ii_ibsa0_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :      7;
+                uint64_t        i_addr                    :     42;
+                uint64_t       i_rsvd                    :     15;
+        } ii_ibsa0_fld_s;
+} ii_ibsa0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibda0_u {
+        uint64_t        ii_ibda0_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :      7;
+                uint64_t        i_addr                    :     42;
+                uint64_t        i_rsvd                    :     15;
+        } ii_ibda0_fld_s;
+} ii_ibda0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  Writing to this register sets up the attributes of the transfer     *
+ * and initiates the transfer operation. Reading this register has      *
+ * the side effect of terminating any transfer in progress. Note:       *
+ * stopping a transfer midstream could have an adverse impact on the    *
+ * other BTE. If a BTE stream has to be stopped (due to error           *
+ * handling for example), both BTE streams should be stopped and        *
+ * their transfers discarded.                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibct0_u {
+        uint64_t        ii_ibct0_regval;
+        struct  {
+                uint64_t        i_zerofill                :      1;
+                uint64_t        i_rsvd_2                  :      3;
+                uint64_t        i_notify                  :      1;
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t       i_poison                  :      1;
+                uint64_t       i_rsvd                    :     55;
+        } ii_ibct0_fld_s;
+} ii_ibct0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the address to which the WINV is sent.       *
+ * This address has to be cache line aligned.                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibna0_u {
+        uint64_t        ii_ibna0_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :      7;
+                uint64_t        i_addr                    :     42;
+                uint64_t        i_rsvd                    :     15;
+        } ii_ibna0_fld_s;
+} ii_ibna0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the programmable level as well as the node   *
+ * ID and PI unit of the processor to which the interrupt will be       *
+ * sent.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibia0_u {
+        uint64_t        ii_ibia0_regval;
+        struct  {
+                uint64_t        i_rsvd_2                   :     1;
+                uint64_t        i_node_id                 :     11;
+                uint64_t        i_rsvd_1                  :      4;
+                uint64_t        i_level                   :      7;
+                uint64_t       i_rsvd                    :     41;
+        } ii_ibia0_fld_s;
+} ii_ibia0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register is used to set up the length for a       *
+ * transfer and then to monitor the progress of that transfer. This     *
+ * register needs to be initialized before a transfer is started. A     *
+ * legitimate write to this register will set the Busy bit, clear the   *
+ * Error bit, and initialize the length to the value desired.           *
+ * While the transfer is in progress, hardware will decrement the       *
+ * length field with each successful block that is copied. Once the     *
+ * transfer completes, hardware will clear the Busy bit. The length     *
+ * field will also contain the number of cache lines left to be         *
+ * transferred.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibls1_u {
+        uint64_t        ii_ibls1_regval;
+        struct  {
+                uint64_t        i_length                  :     16;
+                uint64_t        i_error                   :      1;
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_busy                    :      1;
+                uint64_t       i_rsvd                    :     43;
+        } ii_ibls1_fld_s;
+} ii_ibls1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibsa1_u {
+        uint64_t        ii_ibsa1_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :      7;
+                uint64_t        i_addr                    :     33;
+                uint64_t        i_rsvd                    :     24;
+        } ii_ibsa1_fld_s;
+} ii_ibsa1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibda1_u {
+        uint64_t        ii_ibda1_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :      7;
+                uint64_t        i_addr                    :     33;
+                uint64_t        i_rsvd                    :     24;
+        } ii_ibda1_fld_s;
+} ii_ibda1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  Writing to this register sets up the attributes of the transfer     *
+ * and initiates the transfer operation. Reading this register has      *
+ * the side effect of terminating any transfer in progress. Note:       *
+ * stopping a transfer midstream could have an adverse impact on the    *
+ * other BTE. If a BTE stream has to be stopped (due to error           *
+ * handling for example), both BTE streams should be stopped and        *
+ * their transfers discarded.                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibct1_u {
+        uint64_t        ii_ibct1_regval;
+        struct  {
+                uint64_t        i_zerofill                :      1;
+                uint64_t        i_rsvd_2                  :      3;
+                uint64_t        i_notify                  :      1;
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_poison                  :      1;
+                uint64_t        i_rsvd                    :     55;
+        } ii_ibct1_fld_s;
+} ii_ibct1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the address to which the WINV is sent.       *
+ * This address has to be cache line aligned.                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibna1_u {
+        uint64_t        ii_ibna1_regval;
+        struct  {
+                uint64_t        i_rsvd_1                  :      7;
+                uint64_t        i_addr                    :     33;
+                uint64_t       i_rsvd                    :     24;
+        } ii_ibna1_fld_s;
+} ii_ibna1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the programmable level as well as the node   *
+ * ID and PI unit of the processor to which the interrupt will be       *
+ * sent.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibia1_u {
+        uint64_t        ii_ibia1_regval;
+        struct  {
+                uint64_t        i_pi_id                   :      1;
+                uint64_t        i_node_id                 :      8;
+                uint64_t        i_rsvd_1                  :      7;
+                uint64_t        i_level                   :      7;
+                uint64_t        i_rsvd                    :     41;
+        } ii_ibia1_fld_s;
+} ii_ibia1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register defines the resources that feed information into      *
+ * the two performance counters located in the IO Performance           *
+ * Profiling Register. There are 17 different quantities that can be    *
+ * measured. Given these 17 different options, the two performance      *
+ * counters have 15 of them in common; menu selections 0 through 0xE    *
+ * are identical for each performance counter. As for the other two     *
+ * options, one is available from one performance counter and the       *
+ * other is available from the other performance counter. Hence, the    *
+ * II supports all 17*16=272 possible combinations of quantities to     *
+ * measure.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ipcr_u {
+        uint64_t        ii_ipcr_regval;
+        struct  {
+                uint64_t        i_ippr0_c                 :      4;
+                uint64_t        i_ippr1_c                 :      4;
+                uint64_t        i_icct                    :      8;
+                uint64_t       i_rsvd                    :     48;
+        } ii_ipcr_fld_s;
+} ii_ipcr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ippr_u {
+        uint64_t        ii_ippr_regval;
+        struct  {
+                uint64_t        i_ippr0                   :     32;
+                uint64_t        i_ippr1                   :     32;
+        } ii_ippr_fld_s;
+} ii_ippr_u_t;
+
+
+
+/**************************************************************************
+ *                                                                        *
+ * The following defines which were not formed into structures are        *
+ * probably indentical to another register, and the name of the           *
+ * register is provided against each of these registers. This             *
+ * information needs to be checked carefully                              *
+ *                                                                        *
+ *           IIO_ICRB1_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB1_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB1_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB1_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB1_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB2_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB2_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB2_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB2_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB2_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB3_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB3_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB3_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB3_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB3_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB4_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB4_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB4_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB4_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB4_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB5_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB5_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB5_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB5_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB5_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB6_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB6_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB6_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB6_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB6_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB7_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB7_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB7_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB7_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB7_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB8_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB8_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB8_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB8_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB8_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB9_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB9_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB9_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB9_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB9_E                IIO_ICRB0_E                       *
+ *           IIO_ICRBA_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBA_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBA_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBA_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBA_E                IIO_ICRB0_E                       *
+ *           IIO_ICRBB_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBB_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBB_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBB_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBB_E                IIO_ICRB0_E                       *
+ *           IIO_ICRBC_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBC_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBC_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBC_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBC_E                IIO_ICRB0_E                       *
+ *           IIO_ICRBD_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBD_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBD_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBD_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBD_E                IIO_ICRB0_E                       *
+ *           IIO_ICRBE_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBE_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBE_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBE_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBE_E                IIO_ICRB0_E                       *
+ *                                                                        *
+ **************************************************************************/
+
+
+/*
+ * Slightly friendlier names for some common registers.
+ */
+#define IIO_WIDGET              IIO_WID      /* Widget identification */
+#define IIO_WIDGET_STAT         IIO_WSTAT    /* Widget status register */
+#define IIO_WIDGET_CTRL         IIO_WCR      /* Widget control register */
+#define IIO_PROTECT             IIO_ILAPR    /* IO interface protection */
+#define IIO_PROTECT_OVRRD       IIO_ILAPO    /* IO protect override */
+#define IIO_OUTWIDGET_ACCESS    IIO_IOWA     /* Outbound widget access */
+#define IIO_INWIDGET_ACCESS     IIO_IIWA     /* Inbound widget access */
+#define IIO_INDEV_ERR_MASK      IIO_IIDEM    /* Inbound device error mask */
+#define IIO_LLP_CSR             IIO_ILCSR    /* LLP control and status */
+#define IIO_LLP_LOG             IIO_ILLR     /* LLP log */
+#define IIO_XTALKCC_TOUT        IIO_IXCC     /* Xtalk credit count timeout*/
+#define IIO_XTALKTT_TOUT        IIO_IXTT     /* Xtalk tail timeout */
+#define IIO_IO_ERR_CLR          IIO_IECLR    /* IO error clear */
+#define IIO_IGFX_0              IIO_IGFX0
+#define IIO_IGFX_1              IIO_IGFX1
+#define IIO_IBCT_0              IIO_IBCT0
+#define IIO_IBCT_1              IIO_IBCT1
+#define IIO_IBLS_0              IIO_IBLS0
+#define IIO_IBLS_1              IIO_IBLS1
+#define IIO_IBSA_0              IIO_IBSA0
+#define IIO_IBSA_1              IIO_IBSA1
+#define IIO_IBDA_0              IIO_IBDA0
+#define IIO_IBDA_1              IIO_IBDA1
+#define IIO_IBNA_0              IIO_IBNA0
+#define IIO_IBNA_1              IIO_IBNA1
+#define IIO_IBIA_0              IIO_IBIA0
+#define IIO_IBIA_1              IIO_IBIA1
+#define IIO_IOPRB_0             IIO_IPRB0
+
+#define IIO_PRTE_A(_x)          (IIO_IPRTE0_A + (8 * (_x)))
+#define IIO_PRTE_B(_x)          (IIO_IPRTE0_B + (8 * (_x)))
+#define IIO_NUM_PRTES           8       /* Total number of PRB table entries */
+#define IIO_WIDPRTE_A(x)        IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
+#define IIO_WIDPRTE_B(x)        IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */
+
+#define IIO_NUM_IPRBS           (9) 
+
+#define IIO_LLP_CSR_IS_UP               0x00002000
+#define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
+#define IIO_LLP_CSR_LLP_STAT_SHFT       12
+
+#define IIO_LLP_CB_MAX  0xffff  /* in ILLR CB_CNT, Max Check Bit errors */
+#define IIO_LLP_SN_MAX  0xffff  /* in ILLR SN_CNT, Max Sequence Number errors */
+
+/* key to IIO_PROTECT_OVRRD */
+#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
+
+/* BTE register names */
+#define IIO_BTE_STAT_0          IIO_IBLS_0   /* Also BTE length/status 0 */
+#define IIO_BTE_SRC_0           IIO_IBSA_0   /* Also BTE source address  0 */
+#define IIO_BTE_DEST_0          IIO_IBDA_0   /* Also BTE dest. address 0 */
+#define IIO_BTE_CTRL_0          IIO_IBCT_0   /* Also BTE control/terminate 0 */
+#define IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notification 0 */
+#define IIO_BTE_INT_0           IIO_IBIA_0   /* Also BTE interrupt 0 */
+#define IIO_BTE_OFF_0           0            /* Base offset from BTE 0 regs. */
+#define IIO_BTE_OFF_1           (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */
+
+/* BTE register offsets from base */
+#define BTEOFF_STAT             0
+#define BTEOFF_SRC              (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
+#define BTEOFF_DEST             (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
+#define BTEOFF_CTRL             (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
+#define BTEOFF_NOTIFY           (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
+#define BTEOFF_INT              (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
+
+
+/* names used in shub diags */
+#define IIO_BASE_BTE0   IIO_IBLS_0              
+#define IIO_BASE_BTE1   IIO_IBLS_1              
+
+/*
+ * Macro which takes the widget number, and returns the
+ * IO PRB address of that widget.
+ * value _x is expected to be a widget number in the range
+ * 0, 8 - 0xF
+ */
+#define IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
+                        (_x) : \
+                        (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
+
+
+/* GFX Flow Control Node/Widget Register */
+#define IIO_IGFX_W_NUM_BITS     4       /* size of widget num field */
+#define IIO_IGFX_W_NUM_MASK     ((1<<IIO_IGFX_W_NUM_BITS)-1)
+#define IIO_IGFX_W_NUM_SHIFT    0
+#define IIO_IGFX_PI_NUM_BITS    1       /* size of PI num field */
+#define IIO_IGFX_PI_NUM_MASK    ((1<<IIO_IGFX_PI_NUM_BITS)-1)
+#define IIO_IGFX_PI_NUM_SHIFT   4
+#define IIO_IGFX_N_NUM_BITS     8       /* size of node num field */
+#define IIO_IGFX_N_NUM_MASK     ((1<<IIO_IGFX_N_NUM_BITS)-1)
+#define IIO_IGFX_N_NUM_SHIFT    5
+#define IIO_IGFX_P_NUM_BITS     1       /* size of processor num field */
+#define IIO_IGFX_P_NUM_MASK     ((1<<IIO_IGFX_P_NUM_BITS)-1)
+#define IIO_IGFX_P_NUM_SHIFT    16
+#define IIO_IGFX_INIT(widget, pi, node, cpu)                            (\
+        (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |     \
+        (((pi)     & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)|     \
+        (((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |     \
+        (((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
+
+
+/* Scratch registers (all bits available) */
+#define IIO_SCRATCH_REG0        IIO_ISCR0
+#define IIO_SCRATCH_REG1        IIO_ISCR1
+#define IIO_SCRATCH_MASK        0xffffffffffffffffUL
+
+#define IIO_SCRATCH_BIT0_0      0x0000000000000001UL
+#define IIO_SCRATCH_BIT0_1      0x0000000000000002UL
+#define IIO_SCRATCH_BIT0_2      0x0000000000000004UL
+#define IIO_SCRATCH_BIT0_3      0x0000000000000008UL
+#define IIO_SCRATCH_BIT0_4      0x0000000000000010UL
+#define IIO_SCRATCH_BIT0_5      0x0000000000000020UL
+#define IIO_SCRATCH_BIT0_6      0x0000000000000040UL
+#define IIO_SCRATCH_BIT0_7      0x0000000000000080UL
+#define IIO_SCRATCH_BIT0_8      0x0000000000000100UL
+#define IIO_SCRATCH_BIT0_9      0x0000000000000200UL
+#define IIO_SCRATCH_BIT0_A      0x0000000000000400UL
+
+#define IIO_SCRATCH_BIT1_0      0x0000000000000001UL
+#define IIO_SCRATCH_BIT1_1      0x0000000000000002UL
+/* IO Translation Table Entries */
+#define IIO_NUM_ITTES   7               /* ITTEs numbered 0..6 */
+                                        /* Hw manuals number them 1..7! */
+/*
+ * IIO_IMEM Register fields.
+ */
+#define IIO_IMEM_W0ESD  0x1UL             /* Widget 0 shut down due to error */
+#define IIO_IMEM_B0ESD  (1UL << 4)        /* BTE 0 shut down due to error */
+#define IIO_IMEM_B1ESD  (1UL << 8)        /* BTE 1 Shut down due to error */
+
+/*
+ * As a permanent workaround for a bug in the PI side of the shub, we've
+ * redefined big window 7 as small window 0.
+ XXX does this still apply for SN1??
+ */
+#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
+
+/*
+ * Use the top big window as a surrogate for the first small window
+ */
+#define SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW
+
+#define ILCSR_WARM_RESET        0x100
+
+/*
+ * CRB manipulation macros
+ *      The CRB macros are slightly complicated, since there are up to
+ *      four registers associated with each CRB entry.
+ */
+#define IIO_NUM_CRBS            15      /* Number of CRBs */
+#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
+#define IIO_ICRB_OFFSET         8
+#define IIO_ICRB_0              IIO_ICRB0_A
+#define IIO_ICRB_ADDR_SHFT      2       /* Shift to get proper address */
+/* XXX - This is now tuneable:
+        #define IIO_FIRST_PC_ENTRY 12
+ */
+
+#define IIO_ICRB_A(_x)  ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))))
+#define IIO_ICRB_B(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET))
+#define IIO_ICRB_C(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET))
+#define IIO_ICRB_D(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET))
+#define IIO_ICRB_E(_x)  ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET))
+
+#define TNUM_TO_WIDGET_DEV(_tnum)       (_tnum & 0x7)
+
+/*
+ * values for "ecode" field
+ */
+#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
+#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
+#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
+                                         * e.g. WINV to a Read only line. */
+#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
+#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write       */
+#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read        */
+#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
+#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
+
+/*
+ * Values for field imsgtype
+ */
+#define IIO_ICRB_IMSGT_XTALK    0       /* Incoming Meessage from Xtalk */
+#define IIO_ICRB_IMSGT_BTE      1       /* Incoming message from BTE    */
+#define IIO_ICRB_IMSGT_SN1NET   2       /* Incoming message from SN1 net */
+#define IIO_ICRB_IMSGT_CRB      3       /* Incoming message from CRB ???  */
+
+/*
+ * values for field initiator.
+ */
+#define IIO_ICRB_INIT_XTALK     0       /* Message originated in xtalk  */
+#define IIO_ICRB_INIT_BTE0      0x1     /* Message originated in BTE 0  */
+#define IIO_ICRB_INIT_SN1NET    0x2     /* Message originated in SN1net */
+#define IIO_ICRB_INIT_CRB       0x3     /* Message originated in CRB ?  */
+#define IIO_ICRB_INIT_BTE1      0x5     /* MEssage originated in BTE 1  */
+
+/*
+ * Number of credits Hub widget has while sending req/response to
+ * xbow.
+ * Value of 3 is required by Xbow 1.1
+ * We may be able to increase this to 4 with Xbow 1.2.
+ */
+#define       HUBII_XBOW_CREDIT       3
+#define       HUBII_XBOW_REV2_CREDIT  4
+
+/*
+ * Number of credits that xtalk devices should use when communicating
+ * with a SHub (depth of SHub's queue).
+ */
+#define HUB_CREDIT 4
+
+/*
+ * Some IIO_PRB fields
+ */
+#define IIO_PRB_MULTI_ERR       (1LL << 63)
+#define IIO_PRB_SPUR_RD         (1LL << 51)
+#define IIO_PRB_SPUR_WR         (1LL << 50)
+#define IIO_PRB_RD_TO           (1LL << 49)
+#define IIO_PRB_ERROR           (1LL << 48)
+
+/*************************************************************************
+
+ Some of the IIO field masks and shifts are defined here.
+ This is in order to maintain compatibility in SN0 and SN1 code
+ 
+**************************************************************************/
+
+/*
+ * ICMR register fields
+ * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not
+ * present in SHub)
+ */
+
+#define IIO_ICMR_CRB_VLD_SHFT   20
+#define IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
+
+#define IIO_ICMR_FC_CNT_SHFT    16
+#define IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)
+
+#define IIO_ICMR_C_CNT_SHFT     4
+#define IIO_ICMR_C_CNT_MASK     (0xf << IIO_ICMR_C_CNT_SHFT)
+
+#define IIO_ICMR_PRECISE        (1UL << 52)
+#define IIO_ICMR_CLR_RPPD       (1UL << 13)
+#define IIO_ICMR_CLR_RQPD       (1UL << 12)
+
+/*
+ * IIO PIO Deallocation register field masks : (IIO_IPDR)
+ XXX present but not needed in bedrock?  See the manual.
+ */
+#define IIO_IPDR_PND    (1 << 4)
+
+/*
+ * IIO CRB deallocation register field masks: (IIO_ICDR)
+ */
+#define IIO_ICDR_PND    (1 << 4)
+
+/* 
+ * IO BTE Length/Status (IIO_IBLS) register bit field definitions
+ */
+#define IBLS_BUSY               (0x1UL << 20)
+#define IBLS_ERROR_SHFT         16
+#define IBLS_ERROR              (0x1UL << IBLS_ERROR_SHFT)
+#define IBLS_LENGTH_MASK        0xffff
+
+/*
+ * IO BTE Control/Terminate register (IBCT) register bit field definitions
+ */
+#define IBCT_POISON             (0x1UL << 8)
+#define IBCT_NOTIFY             (0x1UL << 4)
+#define IBCT_ZFIL_MODE          (0x1UL << 0)
+
+/*
+ * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2)
+ */
+#define IIEPH1_VALID            (1UL << 44)
+#define IIEPH1_OVERRUN          (1UL << 40)
+#define IIEPH1_ERR_TYPE_SHFT    32
+#define IIEPH1_ERR_TYPE_MASK    0xf
+#define IIEPH1_SOURCE_SHFT      20
+#define IIEPH1_SOURCE_MASK      11
+#define IIEPH1_SUPPL_SHFT       8
+#define IIEPH1_SUPPL_MASK       11
+#define IIEPH1_CMD_SHFT         0
+#define IIEPH1_CMD_MASK         7
+
+#define IIEPH2_TAIL             (1UL << 40)
+#define IIEPH2_ADDRESS_SHFT     0
+#define IIEPH2_ADDRESS_MASK     38
+
+#define IIEPH1_ERR_SHORT_REQ    2
+#define IIEPH1_ERR_SHORT_REPLY  3
+#define IIEPH1_ERR_LONG_REQ     4
+#define IIEPH1_ERR_LONG_REPLY   5
+
+/*
+ * IO Error Clear register bit field definitions
+ */
+#define IECLR_PI1_FWD_INT       (1UL << 31)  /* clear PI1_FORWARD_INT in iidsr */
+#define IECLR_PI0_FWD_INT       (1UL << 30)  /* clear PI0_FORWARD_INT in iidsr */
+#define IECLR_SPUR_RD_HDR       (1UL << 29)  /* clear valid bit in ixss reg */
+#define IECLR_BTE1              (1UL << 18)  /* clear bte error 1 */
+#define IECLR_BTE0              (1UL << 17)  /* clear bte error 0 */
+#define IECLR_CRAZY             (1UL << 16)  /* clear crazy bit in wstat reg */
+#define IECLR_PRB_F             (1UL << 15)  /* clear err bit in PRB_F reg */
+#define IECLR_PRB_E             (1UL << 14)  /* clear err bit in PRB_E reg */
+#define IECLR_PRB_D             (1UL << 13)  /* clear err bit in PRB_D reg */
+#define IECLR_PRB_C             (1UL << 12)  /* clear err bit in PRB_C reg */
+#define IECLR_PRB_B             (1UL << 11)  /* clear err bit in PRB_B reg */
+#define IECLR_PRB_A             (1UL << 10)  /* clear err bit in PRB_A reg */
+#define IECLR_PRB_9             (1UL << 9)   /* clear err bit in PRB_9 reg */
+#define IECLR_PRB_8             (1UL << 8)   /* clear err bit in PRB_8 reg */
+#define IECLR_PRB_0             (1UL << 0)   /* clear err bit in PRB_0 reg */
+
+/*
+ * IIO CRB control register Fields: IIO_ICCR 
+ */
+#define IIO_ICCR_PENDING        (0x10000)
+#define IIO_ICCR_CMD_MASK       (0xFF)
+#define IIO_ICCR_CMD_SHFT       (7)
+#define IIO_ICCR_CMD_NOP        (0x0)   /* No Op */
+#define IIO_ICCR_CMD_WAKE       (0x100) /* Reactivate CRB entry and process */
+#define IIO_ICCR_CMD_TIMEOUT    (0x200) /* Make CRB timeout & mark invalid */
+#define IIO_ICCR_CMD_EJECT      (0x400) /* Contents of entry written to memory 
+                                         * via a WB
+                                         */
+#define IIO_ICCR_CMD_FLUSH      (0x800)
+
+/*
+ *
+ * CRB Register description.
+ *
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ *
+ * Many of the fields in CRB are status bits used by hardware
+ * for implementation of the protocol. It's very dangerous to
+ * mess around with the CRB registers.
+ *
+ * It's OK to read the CRB registers and try to make sense out of the
+ * fields in CRB.
+ *
+ * Updating CRB requires all activities in Hub IIO to be quiesced.
+ * otherwise, a write to CRB could corrupt other CRB entries.
+ * CRBs are here only as a back door peek to shub IIO's status.
+ * Quiescing implies  no dmas no PIOs
+ * either directly from the cpu or from sn0net.
+ * this is not something that can be done easily. So, AVOID updating
+ * CRBs.
+ */
+
+/*
+ * Easy access macros for CRBs, all 5 registers (A-E)
+ */
+typedef ii_icrb0_a_u_t icrba_t;
+#define a_sidn          ii_icrb0_a_fld_s.ia_sidn
+#define a_tnum          ii_icrb0_a_fld_s.ia_tnum
+#define a_addr          ii_icrb0_a_fld_s.ia_addr
+#define a_valid         ii_icrb0_a_fld_s.ia_vld
+#define a_iow           ii_icrb0_a_fld_s.ia_iow
+#define a_regvalue      ii_icrb0_a_regval
+
+typedef ii_icrb0_b_u_t icrbb_t;
+#define b_use_old       ii_icrb0_b_fld_s.ib_use_old
+#define b_imsgtype      ii_icrb0_b_fld_s.ib_imsgtype
+#define b_imsg          ii_icrb0_b_fld_s.ib_imsg
+#define b_initiator     ii_icrb0_b_fld_s.ib_init
+#define b_exc           ii_icrb0_b_fld_s.ib_exc
+#define b_ackcnt        ii_icrb0_b_fld_s.ib_ack_cnt
+#define b_resp          ii_icrb0_b_fld_s.ib_resp
+#define b_ack           ii_icrb0_b_fld_s.ib_ack
+#define b_hold          ii_icrb0_b_fld_s.ib_hold
+#define b_wb            ii_icrb0_b_fld_s.ib_wb
+#define b_intvn         ii_icrb0_b_fld_s.ib_intvn
+#define b_stall_ib      ii_icrb0_b_fld_s.ib_stall_ib
+#define b_stall_int     ii_icrb0_b_fld_s.ib_stall__intr
+#define b_stall_bte_0   ii_icrb0_b_fld_s.ib_stall__bte_0
+#define b_stall_bte_1   ii_icrb0_b_fld_s.ib_stall__bte_1
+#define b_error         ii_icrb0_b_fld_s.ib_error
+#define b_ecode         ii_icrb0_b_fld_s.ib_errcode
+#define b_lnetuce       ii_icrb0_b_fld_s.ib_ln_uce
+#define b_mark          ii_icrb0_b_fld_s.ib_mark
+#define b_xerr          ii_icrb0_b_fld_s.ib_xt_err
+#define b_regvalue      ii_icrb0_b_regval
+
+typedef ii_icrb0_c_u_t icrbc_t;
+#define c_suppl         ii_icrb0_c_fld_s.ic_suppl
+#define c_barrop        ii_icrb0_c_fld_s.ic_bo
+#define c_doresp        ii_icrb0_c_fld_s.ic_resprqd
+#define c_gbr           ii_icrb0_c_fld_s.ic_gbr
+#define c_btenum        ii_icrb0_c_fld_s.ic_bte_num
+#define c_cohtrans      ii_icrb0_c_fld_s.ic_ct
+#define c_xtsize        ii_icrb0_c_fld_s.ic_size
+#define c_source        ii_icrb0_c_fld_s.ic_source
+#define c_regvalue      ii_icrb0_c_regval
+
+
+typedef ii_icrb0_d_u_t icrbd_t;
+#define d_sleep         ii_icrb0_d_fld_s.id_sleep
+#define d_pricnt        ii_icrb0_d_fld_s.id_pr_cnt
+#define d_pripsc        ii_icrb0_d_fld_s.id_pr_psc
+#define d_bteop         ii_icrb0_d_fld_s.id_bte_op
+#define d_bteaddr       ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/
+#define d_benable       ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/
+#define d_regvalue      ii_icrb0_d_regval
+
+typedef ii_icrb0_e_u_t icrbe_t;
+#define icrbe_ctxtvld   ii_icrb0_e_fld_s.ie_cvld
+#define icrbe_toutvld   ii_icrb0_e_fld_s.ie_tvld
+#define icrbe_context   ii_icrb0_e_fld_s.ie_context
+#define icrbe_timeout   ii_icrb0_e_fld_s.ie_timeout
+#define e_regvalue      ii_icrb0_e_regval
+
+
+/* Number of widgets supported by shub */
+#define HUB_NUM_WIDGET          9
+#define HUB_WIDGET_ID_MIN       0x8
+#define HUB_WIDGET_ID_MAX       0xf
+
+#define HUB_WIDGET_PART_NUM     0xc120
+#define MAX_HUBS_PER_XBOW       2
+
+/* A few more #defines for backwards compatibility */
+#define iprb_t          ii_iprb0_u_t
+#define iprb_regval     ii_iprb0_regval
+#define iprb_mult_err   ii_iprb0_fld_s.i_mult_err
+#define iprb_spur_rd    ii_iprb0_fld_s.i_spur_rd
+#define iprb_spur_wr    ii_iprb0_fld_s.i_spur_wr
+#define iprb_rd_to      ii_iprb0_fld_s.i_rd_to
+#define iprb_ovflow     ii_iprb0_fld_s.i_of_cnt
+#define iprb_error      ii_iprb0_fld_s.i_error
+#define iprb_ff         ii_iprb0_fld_s.i_f
+#define iprb_mode       ii_iprb0_fld_s.i_m
+#define iprb_bnakctr    ii_iprb0_fld_s.i_nb
+#define iprb_anakctr    ii_iprb0_fld_s.i_na
+#define iprb_xtalkctr   ii_iprb0_fld_s.i_c
+
+#define LNK_STAT_WORKING        0x2             /* LLP is working */
+
+#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
+#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
+#define IIO_WSTAT_TXRETRY_MASK  (0x7F)   /* should be 0xFF?? */
+#define IIO_WSTAT_TXRETRY_SHFT  (16)
+#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
+                                          IIO_WSTAT_TXRETRY_MASK)
+
+/* Number of II perf. counters we can multiplex at once */
+
+#define IO_PERF_SETS    32
+
+/* Bit for the widget in inbound access register */
+#define IIO_IIWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
+/* Bit for the widget in outbound access register */
+#define IIO_IOWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
+
+/* NOTE: The following define assumes that we are going to get
+ * widget numbers from 8 thru F and the device numbers within
+ * widget from 0 thru 7.
+ */
+#define IIO_IIDEM_WIDGETDEV_MASK(w, d)  ((uint64_t)(1ULL << (8 * ((w) - 8) + (d))))
+
+/* IO Interrupt Destination Register */
+#define IIO_IIDSR_SENT_SHIFT    28
+#define IIO_IIDSR_SENT_MASK     0x30000000
+#define IIO_IIDSR_ENB_SHIFT     24
+#define IIO_IIDSR_ENB_MASK      0x01000000
+#define IIO_IIDSR_NODE_SHIFT    9
+#define IIO_IIDSR_NODE_MASK     0x000ff700
+#define IIO_IIDSR_PI_ID_SHIFT   8
+#define IIO_IIDSR_PI_ID_MASK    0x00000100
+#define IIO_IIDSR_LVL_SHIFT     0
+#define IIO_IIDSR_LVL_MASK      0x000000ff
+
+/* Xtalk timeout threshhold register (IIO_IXTT) */
+#define IXTT_RRSP_TO_SHFT       55         /* read response timeout */
+#define IXTT_RRSP_TO_MASK       (0x1FULL << IXTT_RRSP_TO_SHFT)
+#define IXTT_RRSP_PS_SHFT       32         /* read responsed TO prescalar */
+#define IXTT_RRSP_PS_MASK       (0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
+#define IXTT_TAIL_TO_SHFT       0          /* tail timeout counter threshold */
+#define IXTT_TAIL_TO_MASK       (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
+
+/*
+ * The IO LLP control status register and widget control register
+ */
+
+typedef union hubii_wcr_u {
+        uint64_t      wcr_reg_value;
+        struct {
+          uint64_t      wcr_widget_id:   4,     /* LLP crossbar credit */
+                        wcr_tag_mode:    1,     /* Tag mode */
+                        wcr_rsvd1:       8,     /* Reserved */
+                        wcr_xbar_crd:    3,     /* LLP crossbar credit */
+                        wcr_f_bad_pkt:   1,     /* Force bad llp pkt enable */
+                        wcr_dir_con:     1,     /* widget direct connect */
+                        wcr_e_thresh:    5,     /* elasticity threshold */
+                        wcr_rsvd:       41;     /* unused */
+        } wcr_fields_s;
+} hubii_wcr_t;
+
+#define iwcr_dir_con    wcr_fields_s.wcr_dir_con
+
+/* The structures below are defined to extract and modify the ii
+performance registers */
+
+/* io_perf_sel allows the caller to specify what tests will be
+   performed */
+
+typedef union io_perf_sel {
+        uint64_t perf_sel_reg;
+        struct {
+               uint64_t perf_ippr0 :  4,
+                                perf_ippr1 :  4,
+                                perf_icct  :  8,
+                                perf_rsvd  : 48;
+        } perf_sel_bits;
+} io_perf_sel_t;
+
+/* io_perf_cnt is to extract the count from the shub registers. Due to
+   hardware problems there is only one counter, not two. */
+
+typedef union io_perf_cnt {
+        uint64_t      perf_cnt;
+        struct {
+               uint64_t perf_cnt   : 20,
+                                perf_rsvd2 : 12,
+                                perf_rsvd1 : 32;
+        } perf_cnt_bits;
+
+} io_perf_cnt_t;
+
+typedef union iprte_a {
+        uint64_t        entry;
+        struct {
+                uint64_t        i_rsvd_1                  :      3;
+                uint64_t        i_addr                    :     38;
+                uint64_t        i_init                    :      3;
+                uint64_t        i_source                  :      8;
+                uint64_t        i_rsvd                    :      2;
+                uint64_t        i_widget                  :      4;
+                uint64_t        i_to_cnt                  :      5;
+                uint64_t       i_vld                     :      1;
+        } iprte_fields;
+} iprte_a_t;
+
+#endif /* _ASM_IA64_SN_SHUBIO_H */
+
diff --git a/include/asm-ia64/sn/simulator.h b/include/asm-ia64/sn/simulator.h
new file mode 100644
index 000000000000..78eb4f869c8b
--- /dev/null
+++ b/include/asm-ia64/sn/simulator.h
@@ -0,0 +1,27 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SIMULATOR_H
+#define _ASM_IA64_SN_SIMULATOR_H
+
+#include <linux/config.h>
+
+#ifdef CONFIG_IA64_SGI_SN_SIM
+
+#define SNMAGIC 0xaeeeeeee8badbeefL
+#define IS_RUNNING_ON_SIMULATOR() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
+
+#define SIMULATOR_SLEEP()       asm("nop.i 0x8beef")
+
+#else
+
+#define IS_RUNNING_ON_SIMULATOR()       (0)
+#define SIMULATOR_SLEEP()
+
+#endif
+
+#endif /* _ASM_IA64_SN_SIMULATOR_H */
diff --git a/include/asm-ia64/sn/sn2/sn_hwperf.h b/include/asm-ia64/sn/sn2/sn_hwperf.h
new file mode 100644
index 000000000000..b0c4d6dd77ba
--- /dev/null
+++ b/include/asm-ia64/sn/sn2/sn_hwperf.h
@@ -0,0 +1,226 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
+ *
+ * Data types used by the SN_SAL_HWPERF_OP SAL call for monitoring
+ * SGI Altix node and router hardware
+ *
+ * Mark Goodwin <markgw@sgi.com> Mon Aug 30 12:23:46 EST 2004
+ */
+
+#ifndef SN_HWPERF_H
+#define SN_HWPERF_H
+
+/*
+ * object structure. SN_HWPERF_ENUM_OBJECTS and SN_HWPERF_GET_CPU_INFO
+ * return an array of these. Do not change this without also
+ * changing the corresponding SAL code.
+ */
+#define SN_HWPERF_MAXSTRING             128
+struct sn_hwperf_object_info {
+        u32 id;
+        union {
+                struct {
+                        u64 this_part:1;
+                        u64 is_shared:1;
+                } fields;
+                struct {
+                        u64 flags;
+                        u64 reserved;
+                } b;
+        } f;
+        char name[SN_HWPERF_MAXSTRING];
+        char location[SN_HWPERF_MAXSTRING];
+        u32 ports;
+};
+
+#define sn_hwp_this_part        f.fields.this_part
+#define sn_hwp_is_shared        f.fields.is_shared
+#define sn_hwp_flags            f.b.flags
+
+/* macros for object classification */
+#define SN_HWPERF_IS_NODE(x)            ((x) && strstr((x)->name, "SHub"))
+#define SN_HWPERF_IS_IONODE(x)          ((x) && strstr((x)->name, "TIO"))
+#define SN_HWPERF_IS_ROUTER(x)          ((x) && strstr((x)->name, "Router"))
+#define SN_HWPERF_IS_NL3ROUTER(x)       ((x) && strstr((x)->name, "NL3Router"))
+#define SN_HWPERF_FOREIGN(x)            ((x) && !(x)->sn_hwp_this_part && !(x)->sn_hwp_is_shared)
+#define SN_HWPERF_SAME_OBJTYPE(x,y)     ((SN_HWPERF_IS_NODE(x) && SN_HWPERF_IS_NODE(y)) ||\
+                                        (SN_HWPERF_IS_IONODE(x) && SN_HWPERF_IS_IONODE(y)) ||\
+                                        (SN_HWPERF_IS_ROUTER(x) && SN_HWPERF_IS_ROUTER(y)))
+
+/* numa port structure, SN_HWPERF_ENUM_PORTS returns an array of these */
+struct sn_hwperf_port_info {
+        u32 port;
+        u32 conn_id;
+        u32 conn_port;
+};
+
+/* for HWPERF_{GET,SET}_MMRS */
+struct sn_hwperf_data {
+        u64 addr;
+        u64 data;
+};
+
+/* user ioctl() argument, see below */
+struct sn_hwperf_ioctl_args {
+        u64 arg;                /* argument, usually an object id */
+        u64 sz;                 /* size of transfer */
+        void *ptr;              /* pointer to source/target */
+        u32 v0;                 /* second return value */
+};
+
+/*
+ * For SN_HWPERF_{GET,SET}_MMRS and SN_HWPERF_OBJECT_DISTANCE,
+ * sn_hwperf_ioctl_args.arg can be used to specify a CPU on which
+ * to call SAL, and whether to use an interprocessor interrupt
+ * or task migration in order to do so. If the CPU specified is
+ * SN_HWPERF_ARG_ANY_CPU, then the current CPU will be used.
+ */
+#define SN_HWPERF_ARG_ANY_CPU           0x7fffffffUL
+#define SN_HWPERF_ARG_CPU_MASK          0x7fffffff00000000ULL
+#define SN_HWPERF_ARG_USE_IPI_MASK      0x8000000000000000ULL
+#define SN_HWPERF_ARG_OBJID_MASK        0x00000000ffffffffULL
+
+/* 
+ * ioctl requests on the "sn_hwperf" misc device that call SAL.
+ */
+#define SN_HWPERF_OP_MEM_COPYIN         0x1000
+#define SN_HWPERF_OP_MEM_COPYOUT        0x2000
+#define SN_HWPERF_OP_MASK               0x0fff
+
+/*
+ * Determine mem requirement.
+ * arg  don't care
+ * sz   8
+ * p    pointer to u64 integer
+ */
+#define SN_HWPERF_GET_HEAPSIZE          1
+
+/*
+ * Install mem for SAL drvr
+ * arg  don't care
+ * sz   sizeof buffer pointed to by p
+ * p    pointer to buffer for scratch area
+ */
+#define SN_HWPERF_INSTALL_HEAP          2
+
+/*
+ * Determine number of objects
+ * arg  don't care
+ * sz   8
+ * p    pointer to u64 integer
+ */
+#define SN_HWPERF_OBJECT_COUNT          (10|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Determine object "distance", relative to a cpu. This operation can
+ * execute on a designated logical cpu number, using either an IPI or
+ * via task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
+ * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
+ *
+ * arg  bitmap of IPI flag, cpu number and object id
+ * sz   8
+ * p    pointer to u64 integer
+ */
+#define SN_HWPERF_OBJECT_DISTANCE       (11|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Enumerate objects. Special case if sz == 8, returns the required
+ * buffer size.
+ * arg  don't care
+ * sz   sizeof buffer pointed to by p
+ * p    pointer to array of struct sn_hwperf_object_info
+ */
+#define SN_HWPERF_ENUM_OBJECTS          (12|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Enumerate NumaLink ports for an object. Special case if sz == 8,
+ * returns the required buffer size.
+ * arg  object id
+ * sz   sizeof buffer pointed to by p
+ * p    pointer to array of struct sn_hwperf_port_info
+ */
+#define SN_HWPERF_ENUM_PORTS            (13|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * SET/GET memory mapped registers. These operations can execute
+ * on a designated logical cpu number, using either an IPI or via
+ * task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
+ * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
+ *
+ * arg  bitmap of ipi flag, cpu number and object id
+ * sz   sizeof buffer pointed to by p
+ * p    pointer to array of struct sn_hwperf_data
+ */
+#define SN_HWPERF_SET_MMRS              (14|SN_HWPERF_OP_MEM_COPYIN)
+#define SN_HWPERF_GET_MMRS              (15|SN_HWPERF_OP_MEM_COPYOUT| \
+                                            SN_HWPERF_OP_MEM_COPYIN)
+/*
+ * Lock a shared object
+ * arg  object id
+ * sz   don't care
+ * p    don't care
+ */
+#define SN_HWPERF_ACQUIRE               16
+
+/*
+ * Unlock a shared object
+ * arg  object id
+ * sz   don't care
+ * p    don't care
+ */
+#define SN_HWPERF_RELEASE               17
+
+/*
+ * Break a lock on a shared object
+ * arg  object id
+ * sz   don't care
+ * p    don't care
+ */
+#define SN_HWPERF_FORCE_RELEASE         18
+
+/*
+ * ioctl requests on "sn_hwperf" that do not call SAL
+ */
+
+/*
+ * get cpu info as an array of hwperf_object_info_t. 
+ * id is logical CPU number, name is description, location
+ * is geoid (e.g. 001c04#1c). Special case if sz == 8,
+ * returns the required buffer size.
+ *
+ * arg  don't care
+ * sz   sizeof buffer pointed to by p
+ * p    pointer to array of struct sn_hwperf_object_info
+ */
+#define SN_HWPERF_GET_CPU_INFO          (100|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Given an object id, return it's node number (aka cnode).
+ * arg  object id
+ * sz   8
+ * p    pointer to u64 integer
+ */
+#define SN_HWPERF_GET_OBJ_NODE          (101|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Given a node number (cnode), return it's nasid.
+ * arg  ordinal node number (aka cnodeid)
+ * sz   8
+ * p    pointer to u64 integer
+ */
+#define SN_HWPERF_GET_NODE_NASID        (102|SN_HWPERF_OP_MEM_COPYOUT)
+
+/* return codes */
+#define SN_HWPERF_OP_OK                 0
+#define SN_HWPERF_OP_NOMEM              1
+#define SN_HWPERF_OP_NO_PERM            2
+#define SN_HWPERF_OP_IO_ERROR           3
+#define SN_HWPERF_OP_BUSY               4
+#define SN_HWPERF_OP_RECONFIGURE        253
+#define SN_HWPERF_OP_INVAL              254
+
+#endif                          /* SN_HWPERF_H */
diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h
new file mode 100644
index 000000000000..685435af170d
--- /dev/null
+++ b/include/asm-ia64/sn/sn_cpuid.h
@@ -0,0 +1,144 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#ifndef _ASM_IA64_SN_SN_CPUID_H
+#define _ASM_IA64_SN_SN_CPUID_H
+
+#include <linux/config.h>
+#include <linux/smp.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/pda.h>
+#include <asm/intrinsics.h>
+
+
+/*
+ * Functions for converting between cpuids, nodeids and NASIDs.
+ * 
+ * These are for SGI platforms only.
+ *
+ */
+
+
+
+
+/*
+ *  Definitions of terms (these definitions are for IA64 ONLY. Other architectures
+ *  use cpuid/cpunum quite defferently):
+ *
+ *         CPUID - a number in range of 0..NR_CPUS-1 that uniquely identifies
+ *              the cpu. The value cpuid has no significance on IA64 other than
+ *              the boot cpu is 0.
+ *                      smp_processor_id() returns the cpuid of the current cpu.
+ *
+ *         CPU_PHYSICAL_ID (also known as HARD_PROCESSOR_ID)
+ *              This is the same as 31:24 of the processor LID register
+ *                      hard_smp_processor_id()- cpu_physical_id of current processor
+ *                      cpu_physical_id(cpuid) - convert a <cpuid> to a <physical_cpuid>
+ *                      cpu_logical_id(phy_id) - convert a <physical_cpuid> to a <cpuid> 
+ *                              * not real efficient - don't use in perf critical code
+ *
+ *         SLICE - a number in the range of 0 - 3 (typically) that represents the
+ *              cpu number on a brick.
+ *
+ *         SUBNODE - (almost obsolete) the number of the FSB that a cpu is
+ *              connected to. This is also the same as the PI number. Usually 0 or 1.
+ *
+ *      NOTE!!!: the value of the bits in the cpu physical id (SAPICid or LID) of a cpu has no 
+ *      significance. The SAPIC id (LID) is a 16-bit cookie that has meaning only to the PROM.
+ *
+ *
+ * The macros convert between cpu physical ids & slice/nasid/cnodeid.
+ * These terms are described below:
+ *
+ *
+ * Brick
+ *          -----   -----           -----   -----       CPU
+ *          | 0 |   | 1 |           | 0 |   | 1 |       SLICE
+ *          -----   -----           -----   -----
+ *            |       |               |       |
+ *            |       |               |       |
+ *          0 |       | 2           0 |       | 2       FSB SLOT
+ *             -------                 -------  
+ *                |                       |
+ *                |                       |
+ *                |                       |
+ *             ------------      -------------
+ *             |          |      |           |
+ *             |    SHUB  |      |   SHUB    |        NASID   (0..MAX_NASIDS)
+ *             |          |----- |           |        CNODEID (0..num_compact_nodes-1)
+ *             |          |      |           |
+ *             |          |      |           |
+ *             ------------      -------------
+ *                   |                 |
+ *                           
+ *
+ */
+
+#ifndef CONFIG_SMP
+#define cpu_physical_id(cpuid)                  ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff)
+#endif
+
+
+#define get_node_number(addr)                   NASID_GET(addr)
+
+/*
+ * NOTE: on non-MP systems, only cpuid 0 exists
+ */
+
+extern short physical_node_map[];                       /* indexed by nasid to get cnode */
+
+/*
+ * Macros for retrieving info about current cpu
+ */
+#define get_nasid()                     (nodepda->phys_cpuid[smp_processor_id()].nasid)
+#define get_subnode()                   (nodepda->phys_cpuid[smp_processor_id()].subnode)
+#define get_slice()                     (nodepda->phys_cpuid[smp_processor_id()].slice)
+#define get_cnode()                     (nodepda->phys_cpuid[smp_processor_id()].cnode)
+#define get_sapicid()                   ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff)
+
+/*
+ * Macros for retrieving info about an arbitrary cpu
+ *      cpuid - logical cpu id
+ */
+#define cpuid_to_nasid(cpuid)           (nodepda->phys_cpuid[cpuid].nasid)
+#define cpuid_to_subnode(cpuid)         (nodepda->phys_cpuid[cpuid].subnode)
+#define cpuid_to_slice(cpuid)           (nodepda->phys_cpuid[cpuid].slice)
+#define cpuid_to_cnodeid(cpuid)         (physical_node_map[cpuid_to_nasid(cpuid)])
+
+
+/*
+ * Dont use the following in performance critical code. They require scans
+ * of potentially large tables.
+ */
+extern int nasid_slice_to_cpuid(int, int);
+#define nasid_slice_to_cpu_physical_id(nasid, slice)                    \
+        cpu_physical_id(nasid_slice_to_cpuid(nasid, slice))
+
+/*
+ * cnodeid_to_nasid - convert a cnodeid to a NASID
+ *      Macro relies on pg_data for a node being on the node itself.
+ *      Just extract the NASID from the pointer.
+ *
+ */
+#define cnodeid_to_nasid(cnodeid)       pda->cnodeid_to_nasid_table[cnodeid]
+ 
+/*
+ * nasid_to_cnodeid - convert a NASID to a cnodeid
+ */
+#define nasid_to_cnodeid(nasid)         (physical_node_map[nasid])
+
+/*
+ * partition_coherence_id - get the coherence ID of the current partition
+ */
+extern u8 sn_coherency_id;
+#define partition_coherence_id()        (sn_coherency_id)
+
+#endif /* _ASM_IA64_SN_SN_CPUID_H */
+
diff --git a/include/asm-ia64/sn/sn_fru.h b/include/asm-ia64/sn/sn_fru.h
new file mode 100644
index 000000000000..8c21ac3f0156
--- /dev/null
+++ b/include/asm-ia64/sn/sn_fru.h
@@ -0,0 +1,44 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992-1997,1999-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN_FRU_H
+#define _ASM_IA64_SN_SN_FRU_H
+
+#define MAX_DIMMS                       8        /* max # of dimm banks */
+#define MAX_PCIDEV                      8        /* max # of pci devices on a pci bus */
+
+typedef unsigned char confidence_t;
+
+typedef struct kf_mem_s {
+        confidence_t km_confidence; /* confidence level that the memory is bad
+                                     * is this necessary ?
+                                     */
+        confidence_t km_dimm[MAX_DIMMS];
+                                    /* confidence level that dimm[i] is bad
+                                     *I think this is the right number
+                                     */
+
+} kf_mem_t;
+
+typedef struct kf_cpu_s {
+        confidence_t    kc_confidence; /* confidence level that cpu is bad */
+        confidence_t    kc_icache; /* confidence level that instr. cache is bad */
+        confidence_t    kc_dcache; /* confidence level that data   cache is bad */
+        confidence_t    kc_scache; /* confidence level that sec.   cache is bad */
+        confidence_t    kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
+} kf_cpu_t;
+
+
+typedef struct kf_pci_bus_s {
+        confidence_t    kpb_belief;     /* confidence level  that the  pci bus is bad */
+        confidence_t    kpb_pcidev_belief[MAX_PCIDEV];
+                                        /* confidence level that the pci dev is bad */
+} kf_pci_bus_t;
+
+
+#endif /* _ASM_IA64_SN_SN_FRU_H */
+
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
new file mode 100644
index 000000000000..88c31b53dc09
--- /dev/null
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -0,0 +1,1015 @@
+#ifndef _ASM_IA64_SN_SN_SAL_H
+#define _ASM_IA64_SN_SN_SAL_H
+
+/*
+ * System Abstraction Layer definitions for IA64
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2000-2004 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+#include <linux/config.h>
+#include <asm/sal.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/geo.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/shub_mmr.h>
+
+// SGI Specific Calls
+#define  SN_SAL_POD_MODE                           0x02000001
+#define  SN_SAL_SYSTEM_RESET                       0x02000002
+#define  SN_SAL_PROBE                              0x02000003
+#define  SN_SAL_GET_MASTER_NASID                   0x02000004
+#define  SN_SAL_GET_KLCONFIG_ADDR                  0x02000005
+#define  SN_SAL_LOG_CE                             0x02000006
+#define  SN_SAL_REGISTER_CE                        0x02000007
+#define  SN_SAL_GET_PARTITION_ADDR                 0x02000009
+#define  SN_SAL_XP_ADDR_REGION                     0x0200000f
+#define  SN_SAL_NO_FAULT_ZONE_VIRTUAL              0x02000010
+#define  SN_SAL_NO_FAULT_ZONE_PHYSICAL             0x02000011
+#define  SN_SAL_PRINT_ERROR                        0x02000012
+#define  SN_SAL_SET_ERROR_HANDLING_FEATURES        0x0200001a   // reentrant
+#define  SN_SAL_GET_FIT_COMPT                      0x0200001b   // reentrant
+#define  SN_SAL_GET_SN_INFO                        0x0200001c
+#define  SN_SAL_GET_SAPIC_INFO                     0x0200001d
+#define  SN_SAL_CONSOLE_PUTC                       0x02000021
+#define  SN_SAL_CONSOLE_GETC                       0x02000022
+#define  SN_SAL_CONSOLE_PUTS                       0x02000023
+#define  SN_SAL_CONSOLE_GETS                       0x02000024
+#define  SN_SAL_CONSOLE_GETS_TIMEOUT               0x02000025
+#define  SN_SAL_CONSOLE_POLL                       0x02000026
+#define  SN_SAL_CONSOLE_INTR                       0x02000027
+#define  SN_SAL_CONSOLE_PUTB                       0x02000028
+#define  SN_SAL_CONSOLE_XMIT_CHARS                 0x0200002a
+#define  SN_SAL_CONSOLE_READC                      0x0200002b
+#define  SN_SAL_SYSCTL_MODID_GET                   0x02000031
+#define  SN_SAL_SYSCTL_GET                         0x02000032
+#define  SN_SAL_SYSCTL_IOBRICK_MODULE_GET          0x02000033
+#define  SN_SAL_SYSCTL_IO_PORTSPEED_GET            0x02000035
+#define  SN_SAL_SYSCTL_SLAB_GET                    0x02000036
+#define  SN_SAL_BUS_CONFIG                         0x02000037
+#define  SN_SAL_SYS_SERIAL_GET                     0x02000038
+#define  SN_SAL_PARTITION_SERIAL_GET               0x02000039
+#define  SN_SAL_SYSCTL_PARTITION_GET               0x0200003a
+#define  SN_SAL_SYSTEM_POWER_DOWN                  0x0200003b
+#define  SN_SAL_GET_MASTER_BASEIO_NASID            0x0200003c
+#define  SN_SAL_COHERENCE                          0x0200003d
+#define  SN_SAL_MEMPROTECT                         0x0200003e
+#define  SN_SAL_SYSCTL_FRU_CAPTURE                 0x0200003f
+
+#define  SN_SAL_SYSCTL_IOBRICK_PCI_OP              0x02000042   // reentrant
+#define  SN_SAL_IROUTER_OP                         0x02000043
+#define  SN_SAL_IOIF_INTERRUPT                     0x0200004a
+#define  SN_SAL_HWPERF_OP                          0x02000050   // lock
+#define  SN_SAL_IOIF_ERROR_INTERRUPT               0x02000051
+
+#define  SN_SAL_IOIF_SLOT_ENABLE                   0x02000053
+#define  SN_SAL_IOIF_SLOT_DISABLE                  0x02000054
+#define  SN_SAL_IOIF_GET_HUBDEV_INFO               0x02000055
+#define  SN_SAL_IOIF_GET_PCIBUS_INFO               0x02000056
+#define  SN_SAL_IOIF_GET_PCIDEV_INFO               0x02000057
+#define  SN_SAL_IOIF_GET_WIDGET_DMAFLUSH_LIST      0x02000058
+
+#define SN_SAL_HUB_ERROR_INTERRUPT                 0x02000060
+
+
+/*
+ * Service-specific constants
+ */
+
+/* Console interrupt manipulation */
+        /* action codes */
+#define SAL_CONSOLE_INTR_OFF    0       /* turn the interrupt off */
+#define SAL_CONSOLE_INTR_ON     1       /* turn the interrupt on */
+#define SAL_CONSOLE_INTR_STATUS 2       /* retrieve the interrupt status */
+        /* interrupt specification & status return codes */
+#define SAL_CONSOLE_INTR_XMIT   1       /* output interrupt */
+#define SAL_CONSOLE_INTR_RECV   2       /* input interrupt */
+
+/* interrupt handling */
+#define SAL_INTR_ALLOC          1
+#define SAL_INTR_FREE           2
+
+/*
+ * IRouter (i.e. generalized system controller) operations
+ */
+#define SAL_IROUTER_OPEN        0       /* open a subchannel */
+#define SAL_IROUTER_CLOSE       1       /* close a subchannel */
+#define SAL_IROUTER_SEND        2       /* send part of an IRouter packet */
+#define SAL_IROUTER_RECV        3       /* receive part of an IRouter packet */
+#define SAL_IROUTER_INTR_STATUS 4       /* check the interrupt status for
+                                         * an open subchannel
+                                         */
+#define SAL_IROUTER_INTR_ON     5       /* enable an interrupt */
+#define SAL_IROUTER_INTR_OFF    6       /* disable an interrupt */
+#define SAL_IROUTER_INIT        7       /* initialize IRouter driver */
+
+/* IRouter interrupt mask bits */
+#define SAL_IROUTER_INTR_XMIT   SAL_CONSOLE_INTR_XMIT
+#define SAL_IROUTER_INTR_RECV   SAL_CONSOLE_INTR_RECV
+
+
+/*
+ * SAL Error Codes
+ */
+#define SALRET_MORE_PASSES      1
+#define SALRET_OK               0
+#define SALRET_NOT_IMPLEMENTED  (-1)
+#define SALRET_INVALID_ARG      (-2)
+#define SALRET_ERROR            (-3)
+
+
+/**
+ * sn_sal_rev_major - get the major SGI SAL revision number
+ *
+ * The SGI PROM stores its version in sal_[ab]_rev_(major|minor).
+ * This routine simply extracts the major value from the
+ * @ia64_sal_systab structure constructed by ia64_sal_init().
+ */
+static inline int
+sn_sal_rev_major(void)
+{
+        struct ia64_sal_systab *systab = efi.sal_systab;
+
+        return (int)systab->sal_b_rev_major;
+}
+
+/**
+ * sn_sal_rev_minor - get the minor SGI SAL revision number
+ *
+ * The SGI PROM stores its version in sal_[ab]_rev_(major|minor).
+ * This routine simply extracts the minor value from the
+ * @ia64_sal_systab structure constructed by ia64_sal_init().
+ */
+static inline int
+sn_sal_rev_minor(void)
+{
+        struct ia64_sal_systab *systab = efi.sal_systab;
+        
+        return (int)systab->sal_b_rev_minor;
+}
+
+/*
+ * Specify the minimum PROM revsion required for this kernel.
+ * Note that they're stored in hex format...
+ */
+#define SN_SAL_MIN_MAJOR        0x4  /* SN2 kernels need at least PROM 4.0 */
+#define SN_SAL_MIN_MINOR        0x0
+
+/*
+ * Returns the master console nasid, if the call fails, return an illegal
+ * value.
+ */
+static inline u64
+ia64_sn_get_console_nasid(void)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_NASID, 0, 0, 0, 0, 0, 0, 0);
+
+        if (ret_stuff.status < 0)
+                return ret_stuff.status;
+
+        /* Master console nasid is in 'v0' */
+        return ret_stuff.v0;
+}
+
+/*
+ * Returns the master baseio nasid, if the call fails, return an illegal
+ * value.
+ */
+static inline u64
+ia64_sn_get_master_baseio_nasid(void)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_BASEIO_NASID, 0, 0, 0, 0, 0, 0, 0);
+
+        if (ret_stuff.status < 0)
+                return ret_stuff.status;
+
+        /* Master baseio nasid is in 'v0' */
+        return ret_stuff.v0;
+}
+
+static inline char *
+ia64_sn_get_klconfig_addr(nasid_t nasid)
+{
+        struct ia64_sal_retval ret_stuff;
+        int cnodeid;
+
+        cnodeid = nasid_to_cnodeid(nasid);
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL(ret_stuff, SN_SAL_GET_KLCONFIG_ADDR, (u64)nasid, 0, 0, 0, 0, 0, 0);
+
+        /*
+         * We should panic if a valid cnode nasid does not produce
+         * a klconfig address.
+         */
+        if (ret_stuff.status != 0) {
+                panic("ia64_sn_get_klconfig_addr: Returned error %lx\n", ret_stuff.status);
+        }
+        return ret_stuff.v0 ? __va(ret_stuff.v0) : NULL;
+}
+
+/*
+ * Returns the next console character.
+ */
+static inline u64
+ia64_sn_console_getc(int *ch)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_GETC, 0, 0, 0, 0, 0, 0, 0);
+
+        /* character is in 'v0' */
+        *ch = (int)ret_stuff.v0;
+
+        return ret_stuff.status;
+}
+
+/*
+ * Read a character from the SAL console device, after a previous interrupt
+ * or poll operation has given us to know that a character is available
+ * to be read.
+ */
+static inline u64
+ia64_sn_console_readc(void)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_READC, 0, 0, 0, 0, 0, 0, 0);
+
+        /* character is in 'v0' */
+        return ret_stuff.v0;
+}
+
+/*
+ * Sends the given character to the console.
+ */
+static inline u64
+ia64_sn_console_putc(char ch)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (uint64_t)ch, 0, 0, 0, 0, 0, 0);
+
+        return ret_stuff.status;
+}
+
+/*
+ * Sends the given buffer to the console.
+ */
+static inline u64
+ia64_sn_console_putb(const char *buf, int len)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0; 
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (uint64_t)buf, (uint64_t)len, 0, 0, 0, 0, 0);
+
+        if ( ret_stuff.status == 0 ) {
+                return ret_stuff.v0;
+        }
+        return (u64)0;
+}
+
+/*
+ * Print a platform error record
+ */
+static inline u64
+ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (uint64_t)hook, (uint64_t)rec, 0, 0, 0, 0, 0);
+
+        return ret_stuff.status;
+}
+
+/*
+ * Check for Platform errors
+ */
+static inline u64
+ia64_sn_plat_cpei_handler(void)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_LOG_CE, 0, 0, 0, 0, 0, 0, 0);
+
+        return ret_stuff.status;
+}
+
+/*
+ * Checks for console input.
+ */
+static inline u64
+ia64_sn_console_check(int *result)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_POLL, 0, 0, 0, 0, 0, 0, 0);
+
+        /* result is in 'v0' */
+        *result = (int)ret_stuff.v0;
+
+        return ret_stuff.status;
+}
+
+/*
+ * Checks console interrupt status
+ */
+static inline u64
+ia64_sn_console_intr_status(void)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR, 
+                 0, SAL_CONSOLE_INTR_STATUS,
+                 0, 0, 0, 0, 0);
+
+        if (ret_stuff.status == 0) {
+            return ret_stuff.v0;
+        }
+        
+        return 0;
+}
+
+/*
+ * Enable an interrupt on the SAL console device.
+ */
+static inline void
+ia64_sn_console_intr_enable(uint64_t intr)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR, 
+                 intr, SAL_CONSOLE_INTR_ON,
+                 0, 0, 0, 0, 0);
+}
+
+/*
+ * Disable an interrupt on the SAL console device.
+ */
+static inline void
+ia64_sn_console_intr_disable(uint64_t intr)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR, 
+                 intr, SAL_CONSOLE_INTR_OFF,
+                 0, 0, 0, 0, 0);
+}
+
+/*
+ * Sends a character buffer to the console asynchronously.
+ */
+static inline u64
+ia64_sn_console_xmit_chars(char *buf, int len)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_XMIT_CHARS,
+                 (uint64_t)buf, (uint64_t)len,
+                 0, 0, 0, 0, 0);
+
+        if (ret_stuff.status == 0) {
+            return ret_stuff.v0;
+        }
+
+        return 0;
+}
+
+/*
+ * Returns the iobrick module Id
+ */
+static inline u64
+ia64_sn_sysctl_iobrick_module_get(nasid_t nasid, int *result)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYSCTL_IOBRICK_MODULE_GET, nasid, 0, 0, 0, 0, 0, 0);
+
+        /* result is in 'v0' */
+        *result = (int)ret_stuff.v0;
+
+        return ret_stuff.status;
+}
+
+/**
+ * ia64_sn_pod_mode - call the SN_SAL_POD_MODE function
+ *
+ * SN_SAL_POD_MODE actually takes an argument, but it's always
+ * 0 when we call it from the kernel, so we don't have to expose
+ * it to the caller.
+ */
+static inline u64
+ia64_sn_pod_mode(void)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL(isrv, SN_SAL_POD_MODE, 0, 0, 0, 0, 0, 0, 0);
+        if (isrv.status)
+                return 0;
+        return isrv.v0;
+}
+
+/**
+ * ia64_sn_probe_mem - read from memory safely
+ * @addr: address to probe
+ * @size: number bytes to read (1,2,4,8)
+ * @data_ptr: address to store value read by probe (-1 returned if probe fails)
+ *
+ * Call into the SAL to do a memory read.  If the read generates a machine
+ * check, this routine will recover gracefully and return -1 to the caller.
+ * @addr is usually a kernel virtual address in uncached space (i.e. the
+ * address starts with 0xc), but if called in physical mode, @addr should
+ * be a physical address.
+ *
+ * Return values:
+ *  0 - probe successful
+ *  1 - probe failed (generated MCA)
+ *  2 - Bad arg
+ * <0 - PAL error
+ */
+static inline u64
+ia64_sn_probe_mem(long addr, long size, void *data_ptr)
+{
+        struct ia64_sal_retval isrv;
+
+        SAL_CALL(isrv, SN_SAL_PROBE, addr, size, 0, 0, 0, 0, 0);
+
+        if (data_ptr) {
+                switch (size) {
+                case 1:
+                        *((u8*)data_ptr) = (u8)isrv.v0;
+                        break;
+                case 2:
+                        *((u16*)data_ptr) = (u16)isrv.v0;
+                        break;
+                case 4:
+                        *((u32*)data_ptr) = (u32)isrv.v0;
+                        break;
+                case 8:
+                        *((u64*)data_ptr) = (u64)isrv.v0;
+                        break;
+                default:
+                        isrv.status = 2;
+                }
+        }
+        return isrv.status;
+}
+
+/*
+ * Retrieve the system serial number as an ASCII string.
+ */
+static inline u64
+ia64_sn_sys_serial_get(char *buf)
+{
+        struct ia64_sal_retval ret_stuff;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYS_SERIAL_GET, buf, 0, 0, 0, 0, 0, 0);
+        return ret_stuff.status;
+}
+
+extern char sn_system_serial_number_string[];
+extern u64 sn_partition_serial_number;
+
+static inline char *
+sn_system_serial_number(void) {
+        if (sn_system_serial_number_string[0]) {
+                return(sn_system_serial_number_string);
+        } else {
+                ia64_sn_sys_serial_get(sn_system_serial_number_string);
+                return(sn_system_serial_number_string);
+        }
+}
+        
+
+/*
+ * Returns a unique id number for this system and partition (suitable for
+ * use with license managers), based in part on the system serial number.
+ */
+static inline u64
+ia64_sn_partition_serial_get(void)
+{
+        struct ia64_sal_retval ret_stuff;
+        SAL_CALL(ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0, 0, 0, 0, 0, 0, 0);
+        if (ret_stuff.status != 0)
+            return 0;
+        return ret_stuff.v0;
+}
+
+static inline u64
+sn_partition_serial_number_val(void) {
+        if (sn_partition_serial_number) {
+                return(sn_partition_serial_number);
+        } else {
+                return(sn_partition_serial_number = ia64_sn_partition_serial_get());
+        }
+}
+
+/*
+ * Returns the partition id of the nasid passed in as an argument,
+ * or INVALID_PARTID if the partition id cannot be retrieved.
+ */
+static inline partid_t
+ia64_sn_sysctl_partition_get(nasid_t nasid)
+{
+        struct ia64_sal_retval ret_stuff;
+        SAL_CALL(ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid,
+                 0, 0, 0, 0, 0, 0);
+        if (ret_stuff.status != 0)
+            return INVALID_PARTID;
+        return ((partid_t)ret_stuff.v0);
+}
+
+/*
+ * Returns the partition id of the current processor.
+ */
+
+extern partid_t sn_partid;
+
+static inline partid_t
+sn_local_partid(void) {
+        if (sn_partid < 0) {
+                return (sn_partid = ia64_sn_sysctl_partition_get(cpuid_to_nasid(smp_processor_id())));
+        } else {
+                return sn_partid;
+        }
+}
+
+/*
+ * Register or unregister a physical address range being referenced across
+ * a partition boundary for which certain SAL errors should be scanned for,
+ * cleaned up and ignored.  This is of value for kernel partitioning code only.
+ * Values for the operation argument:
+ *      1 = register this address range with SAL
+ *      0 = unregister this address range with SAL
+ * 
+ * SAL maintains a reference count on an address range in case it is registered
+ * multiple times.
+ * 
+ * On success, returns the reference count of the address range after the SAL
+ * call has performed the current registration/unregistration.  Returns a
+ * negative value if an error occurred.
+ */
+static inline int
+sn_register_xp_addr_region(u64 paddr, u64 len, int operation)
+{
+        struct ia64_sal_retval ret_stuff;
+        SAL_CALL(ret_stuff, SN_SAL_XP_ADDR_REGION, paddr, len, (u64)operation,
+                 0, 0, 0, 0);
+        return ret_stuff.status;
+}
+
+/*
+ * Register or unregister an instruction range for which SAL errors should
+ * be ignored.  If an error occurs while in the registered range, SAL jumps
+ * to return_addr after ignoring the error.  Values for the operation argument:
+ *      1 = register this instruction range with SAL
+ *      0 = unregister this instruction range with SAL
+ *
+ * Returns 0 on success, or a negative value if an error occurred.
+ */
+static inline int
+sn_register_nofault_code(u64 start_addr, u64 end_addr, u64 return_addr,
+                         int virtual, int operation)
+{
+        struct ia64_sal_retval ret_stuff;
+        u64 call;
+        if (virtual) {
+                call = SN_SAL_NO_FAULT_ZONE_VIRTUAL;
+        } else {
+                call = SN_SAL_NO_FAULT_ZONE_PHYSICAL;
+        }
+        SAL_CALL(ret_stuff, call, start_addr, end_addr, return_addr, (u64)1,
+                 0, 0, 0);
+        return ret_stuff.status;
+}
+
+/*
+ * Change or query the coherence domain for this partition. Each cpu-based
+ * nasid is represented by a bit in an array of 64-bit words:
+ *      0 = not in this partition's coherency domain
+ *      1 = in this partition's coherency domain
+ *
+ * It is not possible for the local system's nasids to be removed from
+ * the coherency domain.  Purpose of the domain arguments:
+ *      new_domain = set the coherence domain to the given nasids
+ *      old_domain = return the current coherence domain
+ *
+ * Returns 0 on success, or a negative value if an error occurred.
+ */
+static inline int
+sn_change_coherence(u64 *new_domain, u64 *old_domain)
+{
+        struct ia64_sal_retval ret_stuff;
+        SAL_CALL(ret_stuff, SN_SAL_COHERENCE, new_domain, old_domain, 0, 0,
+                 0, 0, 0);
+        return ret_stuff.status;
+}
+
+/*
+ * Change memory access protections for a physical address range.
+ * nasid_array is not used on Altix, but may be in future architectures.
+ * Available memory protection access classes are defined after the function.
+ */
+static inline int
+sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array)
+{
+        struct ia64_sal_retval ret_stuff;
+        int cnodeid;
+        unsigned long irq_flags;
+
+        cnodeid = nasid_to_cnodeid(get_node_number(paddr));
+        // spin_lock(&NODEPDA(cnodeid)->bist_lock);
+        local_irq_save(irq_flags);
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_MEMPROTECT, paddr, len, nasid_array,
+                 perms, 0, 0, 0);
+        local_irq_restore(irq_flags);
+        // spin_unlock(&NODEPDA(cnodeid)->bist_lock);
+        return ret_stuff.status;
+}
+#define SN_MEMPROT_ACCESS_CLASS_0               0x14a080
+#define SN_MEMPROT_ACCESS_CLASS_1               0x2520c2
+#define SN_MEMPROT_ACCESS_CLASS_2               0x14a1ca
+#define SN_MEMPROT_ACCESS_CLASS_3               0x14a290
+#define SN_MEMPROT_ACCESS_CLASS_6               0x084080
+#define SN_MEMPROT_ACCESS_CLASS_7               0x021080
+
+/*
+ * Turns off system power.
+ */
+static inline void
+ia64_sn_power_down(void)
+{
+        struct ia64_sal_retval ret_stuff;
+        SAL_CALL(ret_stuff, SN_SAL_SYSTEM_POWER_DOWN, 0, 0, 0, 0, 0, 0, 0);
+        while(1);
+        /* never returns */
+}
+
+/**
+ * ia64_sn_fru_capture - tell the system controller to capture hw state
+ *
+ * This routine will call the SAL which will tell the system controller(s)
+ * to capture hw mmr information from each SHub in the system.
+ */
+static inline u64
+ia64_sn_fru_capture(void)
+{
+        struct ia64_sal_retval isrv;
+        SAL_CALL(isrv, SN_SAL_SYSCTL_FRU_CAPTURE, 0, 0, 0, 0, 0, 0, 0);
+        if (isrv.status)
+                return 0;
+        return isrv.v0;
+}
+
+/*
+ * Performs an operation on a PCI bus or slot -- power up, power down
+ * or reset.
+ */
+static inline u64
+ia64_sn_sysctl_iobrick_pci_op(nasid_t n, u64 connection_type, 
+                              u64 bus, char slot, 
+                              u64 action)
+{
+        struct ia64_sal_retval rv = {0, 0, 0, 0};
+
+        SAL_CALL_NOLOCK(rv, SN_SAL_SYSCTL_IOBRICK_PCI_OP, connection_type, n, action,
+                 bus, (u64) slot, 0, 0);
+        if (rv.status)
+                return rv.v0;
+        return 0;
+}
+
+
+/*
+ * Open a subchannel for sending arbitrary data to the system
+ * controller network via the system controller device associated with
+ * 'nasid'.  Return the subchannel number or a negative error code.
+ */
+static inline int
+ia64_sn_irtr_open(nasid_t nasid)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_OPEN, nasid,
+                           0, 0, 0, 0, 0);
+        return (int) rv.v0;
+}
+
+/*
+ * Close system controller subchannel 'subch' previously opened on 'nasid'.
+ */
+static inline int
+ia64_sn_irtr_close(nasid_t nasid, int subch)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_CLOSE,
+                           (u64) nasid, (u64) subch, 0, 0, 0, 0);
+        return (int) rv.status;
+}
+
+/*
+ * Read data from system controller associated with 'nasid' on
+ * subchannel 'subch'.  The buffer to be filled is pointed to by
+ * 'buf', and its capacity is in the integer pointed to by 'len'.  The
+ * referent of 'len' is set to the number of bytes read by the SAL
+ * call.  The return value is either SALRET_OK (for bytes read) or
+ * SALRET_ERROR (for error or "no data available").
+ */
+static inline int
+ia64_sn_irtr_recv(nasid_t nasid, int subch, char *buf, int *len)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_RECV,
+                           (u64) nasid, (u64) subch, (u64) buf, (u64) len,
+                           0, 0);
+        return (int) rv.status;
+}
+
+/*
+ * Write data to the system controller network via the system
+ * controller associated with 'nasid' on suchannel 'subch'.  The
+ * buffer to be written out is pointed to by 'buf', and 'len' is the
+ * number of bytes to be written.  The return value is either the
+ * number of bytes written (which could be zero) or a negative error
+ * code.
+ */
+static inline int
+ia64_sn_irtr_send(nasid_t nasid, int subch, char *buf, int len)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_SEND,
+                           (u64) nasid, (u64) subch, (u64) buf, (u64) len,
+                           0, 0);
+        return (int) rv.v0;
+}
+
+/*
+ * Check whether any interrupts are pending for the system controller
+ * associated with 'nasid' and its subchannel 'subch'.  The return
+ * value is a mask of pending interrupts (SAL_IROUTER_INTR_XMIT and/or
+ * SAL_IROUTER_INTR_RECV).
+ */
+static inline int
+ia64_sn_irtr_intr(nasid_t nasid, int subch)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_STATUS,
+                           (u64) nasid, (u64) subch, 0, 0, 0, 0);
+        return (int) rv.v0;
+}
+
+/*
+ * Enable the interrupt indicated by the intr parameter (either
+ * SAL_IROUTER_INTR_XMIT or SAL_IROUTER_INTR_RECV).
+ */
+static inline int
+ia64_sn_irtr_intr_enable(nasid_t nasid, int subch, u64 intr)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_ON,
+                           (u64) nasid, (u64) subch, intr, 0, 0, 0);
+        return (int) rv.v0;
+}
+
+/*
+ * Disable the interrupt indicated by the intr parameter (either
+ * SAL_IROUTER_INTR_XMIT or SAL_IROUTER_INTR_RECV).
+ */
+static inline int
+ia64_sn_irtr_intr_disable(nasid_t nasid, int subch, u64 intr)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_OFF,
+                           (u64) nasid, (u64) subch, intr, 0, 0, 0);
+        return (int) rv.v0;
+}
+
+/**
+ * ia64_sn_get_fit_compt - read a FIT entry from the PROM header
+ * @nasid: NASID of node to read
+ * @index: FIT entry index to be retrieved (0..n)
+ * @fitentry: 16 byte buffer where FIT entry will be stored.
+ * @banbuf: optional buffer for retrieving banner
+ * @banlen: length of banner buffer
+ *
+ * Access to the physical PROM chips needs to be serialized since reads and
+ * writes can't occur at the same time, so we need to call into the SAL when
+ * we want to look at the FIT entries on the chips.
+ *
+ * Returns:
+ *      %SALRET_OK if ok
+ *      %SALRET_INVALID_ARG if index too big
+ *      %SALRET_NOT_IMPLEMENTED if running on older PROM
+ *      ??? if nasid invalid OR banner buffer not large enough
+ */
+static inline int
+ia64_sn_get_fit_compt(u64 nasid, u64 index, void *fitentry, void *banbuf,
+                      u64 banlen)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_NOLOCK(rv, SN_SAL_GET_FIT_COMPT, nasid, index, fitentry,
+                        banbuf, banlen, 0, 0);
+        return (int) rv.status;
+}
+
+/*
+ * Initialize the SAL components of the system controller
+ * communication driver; specifically pass in a sizable buffer that
+ * can be used for allocation of subchannel queues as new subchannels
+ * are opened.  "buf" points to the buffer, and "len" specifies its
+ * length.
+ */
+static inline int
+ia64_sn_irtr_init(nasid_t nasid, void *buf, int len)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INIT,
+                           (u64) nasid, (u64) buf, (u64) len, 0, 0, 0);
+        return (int) rv.status;
+}
+
+/*
+ * Returns the nasid, subnode & slice corresponding to a SAPIC ID
+ *
+ *  In:
+ *      arg0 - SN_SAL_GET_SAPIC_INFO
+ *      arg1 - sapicid (lid >> 16) 
+ *  Out:
+ *      v0 - nasid
+ *      v1 - subnode
+ *      v2 - slice
+ */
+static inline u64
+ia64_sn_get_sapic_info(int sapicid, int *nasid, int *subnode, int *slice)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SAPIC_INFO, sapicid, 0, 0, 0, 0, 0, 0);
+
+/***** BEGIN HACK - temp til old proms no longer supported ********/
+        if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
+                if (nasid) *nasid = sapicid & 0xfff;
+                if (subnode) *subnode = (sapicid >> 13) & 1;
+                if (slice) *slice = (sapicid >> 12) & 3;
+                return 0;
+        }
+/***** END HACK *******/
+
+        if (ret_stuff.status < 0)
+                return ret_stuff.status;
+
+        if (nasid) *nasid = (int) ret_stuff.v0;
+        if (subnode) *subnode = (int) ret_stuff.v1;
+        if (slice) *slice = (int) ret_stuff.v2;
+        return 0;
+}
+ 
+/*
+ * Returns information about the HUB/SHUB.
+ *  In:
+ *      arg0 - SN_SAL_GET_SN_INFO
+ *      arg1 - 0 (other values reserved for future use)
+ *  Out:
+ *      v0 
+ *              [7:0]   - shub type (0=shub1, 1=shub2)
+ *              [15:8]  - Log2 max number of nodes in entire system (includes
+ *                        C-bricks, I-bricks, etc)
+ *              [23:16] - Log2 of nodes per sharing domain                       
+ *              [31:24] - partition ID
+ *              [39:32] - coherency_id
+ *              [47:40] - regionsize
+ *      v1 
+ *              [15:0]  - nasid mask (ex., 0x7ff for 11 bit nasid)
+ *              [23:15] - bit position of low nasid bit
+ */
+static inline u64
+ia64_sn_get_sn_info(int fc, u8 *shubtype, u16 *nasid_bitmask, u8 *nasid_shift, 
+                u8 *systemsize, u8 *sharing_domain_size, u8 *partid, u8 *coher, u8 *reg)
+{
+        struct ia64_sal_retval ret_stuff;
+
+        ret_stuff.status = 0;
+        ret_stuff.v0 = 0;
+        ret_stuff.v1 = 0;
+        ret_stuff.v2 = 0;
+        SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SN_INFO, fc, 0, 0, 0, 0, 0, 0);
+
+/***** BEGIN HACK - temp til old proms no longer supported ********/
+        if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
+                int nasid = get_sapicid() & 0xfff;;
+#define SH_SHUB_ID_NODES_PER_BIT_MASK 0x001f000000000000UL                                               
+#define SH_SHUB_ID_NODES_PER_BIT_SHFT 48                                                               
+                if (shubtype) *shubtype = 0;
+                if (nasid_bitmask) *nasid_bitmask = 0x7ff;
+                if (nasid_shift) *nasid_shift = 38;
+                if (systemsize) *systemsize = 11;
+                if (sharing_domain_size) *sharing_domain_size = 9;
+                if (partid) *partid = ia64_sn_sysctl_partition_get(nasid);
+                if (coher) *coher = nasid >> 9;
+                if (reg) *reg = (HUB_L((u64 *) LOCAL_MMR_ADDR(SH1_SHUB_ID)) & SH_SHUB_ID_NODES_PER_BIT_MASK) >>
+                        SH_SHUB_ID_NODES_PER_BIT_SHFT;
+                return 0;
+        }
+/***** END HACK *******/
+
+        if (ret_stuff.status < 0)
+                return ret_stuff.status;
+
+        if (shubtype) *shubtype = ret_stuff.v0 & 0xff;
+        if (systemsize) *systemsize = (ret_stuff.v0 >> 8) & 0xff;
+        if (sharing_domain_size) *sharing_domain_size = (ret_stuff.v0 >> 16) & 0xff;
+        if (partid) *partid = (ret_stuff.v0 >> 24) & 0xff;
+        if (coher) *coher = (ret_stuff.v0 >> 32) & 0xff;
+        if (reg) *reg = (ret_stuff.v0 >> 40) & 0xff;
+        if (nasid_bitmask) *nasid_bitmask = (ret_stuff.v1 & 0xffff);
+        if (nasid_shift) *nasid_shift = (ret_stuff.v1 >> 16) & 0xff;
+        return 0;
+}
+ 
+/*
+ * This is the access point to the Altix PROM hardware performance
+ * and status monitoring interface. For info on using this, see
+ * include/asm-ia64/sn/sn2/sn_hwperf.h
+ */
+static inline int
+ia64_sn_hwperf_op(nasid_t nasid, u64 opcode, u64 a0, u64 a1, u64 a2,
+                  u64 a3, u64 a4, int *v0)
+{
+        struct ia64_sal_retval rv;
+        SAL_CALL_NOLOCK(rv, SN_SAL_HWPERF_OP, (u64)nasid,
+                opcode, a0, a1, a2, a3, a4);
+        if (v0)
+                *v0 = (int) rv.v0;
+        return (int) rv.status;
+}
+
+#endif /* _ASM_IA64_SN_SN_SAL_H */
diff --git a/include/asm-ia64/sn/sndrv.h b/include/asm-ia64/sn/sndrv.h
new file mode 100644
index 000000000000..aa00d42cde32
--- /dev/null
+++ b/include/asm-ia64/sn/sndrv.h
@@ -0,0 +1,47 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2002-2004 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SNDRV_H
+#define _ASM_IA64_SN_SNDRV_H
+
+/* ioctl commands */
+#define SNDRV_GET_ROUTERINFO            1
+#define SNDRV_GET_INFOSIZE              2
+#define SNDRV_GET_HUBINFO               3
+#define SNDRV_GET_FLASHLOGSIZE          4
+#define SNDRV_SET_FLASHSYNC             5
+#define SNDRV_GET_FLASHLOGDATA          6
+#define SNDRV_GET_FLASHLOGALL           7
+
+#define SNDRV_SET_HISTOGRAM_TYPE        14
+
+#define SNDRV_ELSC_COMMAND              19
+#define SNDRV_CLEAR_LOG                 20
+#define SNDRV_INIT_LOG                  21
+#define SNDRV_GET_PIMM_PSC              22
+#define SNDRV_SET_PARTITION             23
+#define SNDRV_GET_PARTITION             24
+
+/* see synergy_perf_ioctl() */
+#define SNDRV_GET_SYNERGY_VERSION       30
+#define SNDRV_GET_SYNERGY_STATUS        31
+#define SNDRV_GET_SYNERGYINFO           32
+#define SNDRV_SYNERGY_APPEND            33
+#define SNDRV_SYNERGY_ENABLE            34
+#define SNDRV_SYNERGY_FREQ              35
+
+/* Devices */
+#define SNDRV_UKNOWN_DEVICE             -1
+#define SNDRV_ROUTER_DEVICE             1
+#define SNDRV_HUB_DEVICE                2
+#define SNDRV_ELSC_NVRAM_DEVICE         3
+#define SNDRV_ELSC_CONTROLLER_DEVICE    4
+#define SNDRV_SYSCTL_SUBCH              5
+#define SNDRV_SYNERGY_DEVICE            6
+
+#endif /* _ASM_IA64_SN_SNDRV_H */
diff --git a/include/asm-ia64/sn/types.h b/include/asm-ia64/sn/types.h
new file mode 100644
index 000000000000..586ed47cae9c
--- /dev/null
+++ b/include/asm-ia64/sn/types.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999,2001-2003 Silicon Graphics, Inc.  All Rights Reserved.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_IA64_SN_TYPES_H
+#define _ASM_IA64_SN_TYPES_H
+
+#include <linux/types.h>
+
+typedef unsigned long   cpuid_t;
+typedef signed short    nasid_t;        /* node id in numa-as-id space */
+typedef signed char     partid_t;       /* partition ID type */
+typedef unsigned int    moduleid_t;     /* user-visible module number type */
+typedef unsigned int    cmoduleid_t;    /* kernel compact module id type */
+typedef signed char     slabid_t;
+typedef u64 nic_t;
+typedef unsigned long iopaddr_t;
+typedef unsigned long paddr_t;
+typedef short cnodeid_t;
+
+#endif /* _ASM_IA64_SN_TYPES_H */