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-rw-r--r--include/asm-ia64/sn/acpi.h17
-rw-r--r--include/asm-ia64/sn/addrs.h299
-rw-r--r--include/asm-ia64/sn/arch.h86
-rw-r--r--include/asm-ia64/sn/bte.h233
-rw-r--r--include/asm-ia64/sn/clksupport.h28
-rw-r--r--include/asm-ia64/sn/geo.h132
-rw-r--r--include/asm-ia64/sn/intr.h68
-rw-r--r--include/asm-ia64/sn/io.h274
-rw-r--r--include/asm-ia64/sn/ioc3.h241
-rw-r--r--include/asm-ia64/sn/klconfig.h246
-rw-r--r--include/asm-ia64/sn/l1.h51
-rw-r--r--include/asm-ia64/sn/leds.h33
-rw-r--r--include/asm-ia64/sn/module.h127
-rw-r--r--include/asm-ia64/sn/mspec.h59
-rw-r--r--include/asm-ia64/sn/nodepda.h82
-rw-r--r--include/asm-ia64/sn/pcibr_provider.h150
-rw-r--r--include/asm-ia64/sn/pcibus_provider_defs.h68
-rw-r--r--include/asm-ia64/sn/pcidev.h85
-rw-r--r--include/asm-ia64/sn/pda.h69
-rw-r--r--include/asm-ia64/sn/pic.h261
-rw-r--r--include/asm-ia64/sn/rw_mmr.h28
-rw-r--r--include/asm-ia64/sn/shub_mmr.h502
-rw-r--r--include/asm-ia64/sn/shubio.h3358
-rw-r--r--include/asm-ia64/sn/simulator.h25
-rw-r--r--include/asm-ia64/sn/sn2/sn_hwperf.h242
-rw-r--r--include/asm-ia64/sn/sn_cpuid.h132
-rw-r--r--include/asm-ia64/sn/sn_feature_sets.h58
-rw-r--r--include/asm-ia64/sn/sn_sal.h1188
-rw-r--r--include/asm-ia64/sn/tioca.h596
-rw-r--r--include/asm-ia64/sn/tioca_provider.h207
-rw-r--r--include/asm-ia64/sn/tioce.h760
-rw-r--r--include/asm-ia64/sn/tioce_provider.h63
-rw-r--r--include/asm-ia64/sn/tiocp.h257
-rw-r--r--include/asm-ia64/sn/tiocx.h72
-rw-r--r--include/asm-ia64/sn/types.h26
35 files changed, 0 insertions, 10123 deletions
diff --git a/include/asm-ia64/sn/acpi.h b/include/asm-ia64/sn/acpi.h
deleted file mode 100644
index 9ce2801cbd57..000000000000
--- a/include/asm-ia64/sn/acpi.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_ACPI_H
10#define _ASM_IA64_SN_ACPI_H
11
12#include "acpi/acglobal.h"
13
14extern int sn_acpi_rev;
15#define SN_ACPI_BASE_SUPPORT() (sn_acpi_rev >= 0x20101)
16
17#endif /* _ASM_IA64_SN_ACPI_H */
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
deleted file mode 100644
index e715c794b186..000000000000
--- a/include/asm-ia64/sn/addrs.h
+++ /dev/null
@@ -1,299 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_ADDRS_H
10#define _ASM_IA64_SN_ADDRS_H
11
12#include <asm/percpu.h>
13#include <asm/sn/types.h>
14#include <asm/sn/arch.h>
15#include <asm/sn/pda.h>
16
17/*
18 * Memory/SHUB Address Format:
19 * +-+---------+--+--------------+
20 * |0| NASID |AS| NodeOffset |
21 * +-+---------+--+--------------+
22 *
23 * NASID: (low NASID bit is 0) Memory and SHUB MMRs
24 * AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
25 * 00: Local Resources and MMR space
26 * Top bit of NodeOffset
27 * 0: Local resources space
28 * node id:
29 * 0: IA64/NT compatibility space
30 * 2: Local MMR Space
31 * 4: Local memory, regardless of local node id
32 * 1: Global MMR space
33 * 01: GET space.
34 * 10: AMO space.
35 * 11: Cacheable memory space.
36 *
37 * NodeOffset: byte offset
38 *
39 *
40 * TIO address format:
41 * +-+----------+--+--------------+
42 * |0| NASID |AS| Nodeoffset |
43 * +-+----------+--+--------------+
44 *
45 * NASID: (low NASID bit is 1) TIO
46 * AS: 2-bit Chiplet Identifier
47 * 00: TIO LB (Indicates TIO MMR access.)
48 * 01: TIO ICE (indicates coretalk space access.)
49 *
50 * NodeOffset: top bit must be set.
51 *
52 *
53 * Note that in both of the above address formats, the low
54 * NASID bit indicates if the reference is to the SHUB or TIO MMRs.
55 */
56
57
58/*
59 * Define basic shift & mask constants for manipulating NASIDs and AS values.
60 */
61#define NASID_BITMASK (sn_hub_info->nasid_bitmask)
62#define NASID_SHIFT (sn_hub_info->nasid_shift)
63#define AS_SHIFT (sn_hub_info->as_shift)
64#define AS_BITMASK 0x3UL
65
66#define NASID_MASK ((u64)NASID_BITMASK << NASID_SHIFT)
67#define AS_MASK ((u64)AS_BITMASK << AS_SHIFT)
68
69
70/*
71 * AS values. These are the same on both SHUB1 & SHUB2.
72 */
73#define AS_GET_VAL 1UL
74#define AS_AMO_VAL 2UL
75#define AS_CAC_VAL 3UL
76#define AS_GET_SPACE (AS_GET_VAL << AS_SHIFT)
77#define AS_AMO_SPACE (AS_AMO_VAL << AS_SHIFT)
78#define AS_CAC_SPACE (AS_CAC_VAL << AS_SHIFT)
79
80
81/*
82 * Virtual Mode Local & Global MMR space.
83 */
84#define SH1_LOCAL_MMR_OFFSET 0x8000000000UL
85#define SH2_LOCAL_MMR_OFFSET 0x0200000000UL
86#define LOCAL_MMR_OFFSET (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
87#define LOCAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET)
88#define LOCAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET)
89
90#define SH1_GLOBAL_MMR_OFFSET 0x0800000000UL
91#define SH2_GLOBAL_MMR_OFFSET 0x0300000000UL
92#define GLOBAL_MMR_OFFSET (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
93#define GLOBAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET)
94
95/*
96 * Physical mode addresses
97 */
98#define GLOBAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET)
99
100
101/*
102 * Clear region & AS bits.
103 */
104#define TO_PHYS_MASK (~(RGN_BITS | AS_MASK))
105
106
107/*
108 * Misc NASID manipulation.
109 */
110#define NASID_SPACE(n) ((u64)(n) << NASID_SHIFT)
111#define REMOTE_ADDR(n,a) (NASID_SPACE(n) | (a))
112#define NODE_OFFSET(x) ((x) & (NODE_ADDRSPACE_SIZE - 1))
113#define NODE_ADDRSPACE_SIZE (1UL << AS_SHIFT)
114#define NASID_GET(x) (int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
115#define LOCAL_MMR_ADDR(a) (LOCAL_MMR_SPACE | (a))
116#define GLOBAL_MMR_ADDR(n,a) (GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
117#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
118#define GLOBAL_CAC_ADDR(n,a) (CAC_BASE | REMOTE_ADDR(n,a))
119#define CHANGE_NASID(n,x) ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
120#define IS_TIO_NASID(n) ((n) & 1)
121
122
123/* non-II mmr's start at top of big window space (4G) */
124#define BWIN_TOP 0x0000000100000000UL
125
126/*
127 * general address defines
128 */
129#define CAC_BASE (PAGE_OFFSET | AS_CAC_SPACE)
130#define AMO_BASE (__IA64_UNCACHED_OFFSET | AS_AMO_SPACE)
131#define AMO_PHYS_BASE (RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE)
132#define GET_BASE (PAGE_OFFSET | AS_GET_SPACE)
133
134/*
135 * Convert Memory addresses between various addressing modes.
136 */
137#define TO_PHYS(x) (TO_PHYS_MASK & (x))
138#define TO_CAC(x) (CAC_BASE | TO_PHYS(x))
139#ifdef CONFIG_SGI_SN
140#define TO_AMO(x) (AMO_BASE | TO_PHYS(x))
141#define TO_GET(x) (GET_BASE | TO_PHYS(x))
142#else
143#define TO_AMO(x) ({ BUG(); x; })
144#define TO_GET(x) ({ BUG(); x; })
145#endif
146
147/*
148 * Covert from processor physical address to II/TIO physical address:
149 * II - squeeze out the AS bits
150 * TIO- requires a chiplet id in bits 38-39. For DMA to memory,
151 * the chiplet id is zero. If we implement TIO-TIO dma, we might need
152 * to insert a chiplet id into this macro. However, it is our belief
153 * right now that this chiplet id will be ICE, which is also zero.
154 */
155#define SH1_TIO_PHYS_TO_DMA(x) \
156 ((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
157
158#define SH2_NETWORK_BANK_OFFSET(x) \
159 ((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
160
161#define SH2_NETWORK_BANK_SELECT(x) \
162 ((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4))) \
163 >> (sn_hub_info->nasid_shift - 4)) << 36)
164
165#define SH2_NETWORK_ADDRESS(x) \
166 (SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
167
168#define SH2_TIO_PHYS_TO_DMA(x) \
169 (((u64)(NASID_GET(x)) << 40) | SH2_NETWORK_ADDRESS(x))
170
171#define PHYS_TO_TIODMA(x) \
172 (is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
173
174#define PHYS_TO_DMA(x) \
175 ((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
176
177
178/*
179 * Macros to test for address type.
180 */
181#define IS_AMO_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE)
182#define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE)
183
184
185/*
186 * The following definitions pertain to the IO special address
187 * space. They define the location of the big and little windows
188 * of any given node.
189 */
190#define BWIN_SIZE_BITS 29 /* big window size: 512M */
191#define TIO_BWIN_SIZE_BITS 30 /* big window size: 1G */
192#define NODE_SWIN_BASE(n, w) ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
193 : RAW_NODE_SWIN_BASE(n, w))
194#define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \
195 ((u64) (w) << TIO_SWIN_SIZE_BITS))
196#define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n))
197#define TIO_IO_BASE(n) (__IA64_UNCACHED_OFFSET | NASID_SPACE(n))
198#define BWIN_SIZE (1UL << BWIN_SIZE_BITS)
199#define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE)
200#define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
201#define RAW_NODE_SWIN_BASE(n, w) (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
202#define BWIN_WIDGET_MASK 0x7
203#define BWIN_WINDOWNUM(x) (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
204#define SH1_IS_BIG_WINDOW_ADDR(x) ((x) & BWIN_TOP)
205
206#define TIO_BWIN_WINDOW_SELECT_MASK 0x7
207#define TIO_BWIN_WINDOWNUM(x) (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
208
209#define TIO_HWIN_SHIFT_BITS 33
210#define TIO_HWIN(x) (NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)
211
212/*
213 * The following definitions pertain to the IO special address
214 * space. They define the location of the big and little windows
215 * of any given node.
216 */
217
218#define SWIN_SIZE_BITS 24
219#define SWIN_WIDGET_MASK 0xF
220
221#define TIO_SWIN_SIZE_BITS 28
222#define TIO_SWIN_SIZE (1UL << TIO_SWIN_SIZE_BITS)
223#define TIO_SWIN_WIDGET_MASK 0x3
224
225/*
226 * Convert smallwindow address to xtalk address.
227 *
228 * 'addr' can be physical or virtual address, but will be converted
229 * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
230 */
231#define SWIN_WIDGETNUM(x) (((x) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
232#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
233
234
235/*
236 * The following macros produce the correct base virtual address for
237 * the hub registers. The REMOTE_HUB_* macro produce
238 * the address for the specified hub's registers. The intent is
239 * that the appropriate PI, MD, NI, or II register would be substituted
240 * for x.
241 *
242 * WARNING:
243 * When certain Hub chip workaround are defined, it's not sufficient
244 * to dereference the *_HUB_ADDR() macros. You should instead use
245 * HUB_L() and HUB_S() if you must deal with pointers to hub registers.
246 * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
247 * They're always safe.
248 */
249/* Shub1 TIO & MMR addressing macros */
250#define SH1_TIO_IOSPACE_ADDR(n,x) \
251 GLOBAL_MMR_ADDR(n,x)
252
253#define SH1_REMOTE_BWIN_MMR(n,x) \
254 GLOBAL_MMR_ADDR(n,x)
255
256#define SH1_REMOTE_SWIN_MMR(n,x) \
257 (NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
258
259#define SH1_REMOTE_MMR(n,x) \
260 (SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) : \
261 SH1_REMOTE_SWIN_MMR(n,x))
262
263/* Shub1 TIO & MMR addressing macros */
264#define SH2_TIO_IOSPACE_ADDR(n,x) \
265 ((__IA64_UNCACHED_OFFSET | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
266
267#define SH2_REMOTE_MMR(n,x) \
268 GLOBAL_MMR_ADDR(n,x)
269
270
271/* TIO & MMR addressing macros that work on both shub1 & shub2 */
272#define TIO_IOSPACE_ADDR(n,x) \
273 ((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) : \
274 SH2_TIO_IOSPACE_ADDR(n,x)))
275
276#define SH_REMOTE_MMR(n,x) \
277 (is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
278
279#define REMOTE_HUB_ADDR(n,x) \
280 (IS_TIO_NASID(n) ? ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) : \
281 ((volatile u64*)SH_REMOTE_MMR(n,x)))
282
283
284#define HUB_L(x) (*((volatile typeof(*x) *)x))
285#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d))
286
287#define REMOTE_HUB_L(n, a) HUB_L(REMOTE_HUB_ADDR((n), (a)))
288#define REMOTE_HUB_S(n, a, d) HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
289
290/*
291 * Coretalk address breakdown
292 */
293#define CTALK_NASID_SHFT 40
294#define CTALK_NASID_MASK (0x3FFFULL << CTALK_NASID_SHFT)
295#define CTALK_CID_SHFT 38
296#define CTALK_CID_MASK (0x3ULL << CTALK_CID_SHFT)
297#define CTALK_NODE_OFFSET 0x3FFFFFFFFF
298
299#endif /* _ASM_IA64_SN_ADDRS_H */
diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h
deleted file mode 100644
index 7caa1f44cd95..000000000000
--- a/include/asm-ia64/sn/arch.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI specific setup.
7 *
8 * Copyright (C) 1995-1997,1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
9 * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
10 */
11#ifndef _ASM_IA64_SN_ARCH_H
12#define _ASM_IA64_SN_ARCH_H
13
14#include <linux/numa.h>
15#include <asm/types.h>
16#include <asm/percpu.h>
17#include <asm/sn/types.h>
18#include <asm/sn/sn_cpuid.h>
19
20/*
21 * This is the maximum number of NUMALINK nodes that can be part of a single
22 * SSI kernel. This number includes C-brick, M-bricks, and TIOs. Nodes in
23 * remote partitions are NOT included in this number.
24 * The number of compact nodes cannot exceed size of a coherency domain.
25 * The purpose of this define is to specify a node count that includes
26 * all C/M/TIO nodes in an SSI system.
27 *
28 * SGI system can currently support up to 256 C/M nodes plus additional TIO nodes.
29 *
30 * Note: ACPI20 has an architectural limit of 256 nodes. When we upgrade
31 * to ACPI3.0, this limit will be removed. The notion of "compact nodes"
32 * should be deleted and TIOs should be included in MAX_NUMNODES.
33 */
34#define MAX_TIO_NODES MAX_NUMNODES
35#define MAX_COMPACT_NODES (MAX_NUMNODES + MAX_TIO_NODES)
36
37/*
38 * Maximum number of nodes in all partitions and in all coherency domains.
39 * This is the total number of nodes accessible in the numalink fabric. It
40 * includes all C & M bricks, plus all TIOs.
41 *
42 * This value is also the value of the maximum number of NASIDs in the numalink
43 * fabric.
44 */
45#define MAX_NUMALINK_NODES 16384
46
47/*
48 * The following defines attributes of the HUB chip. These attributes are
49 * frequently referenced. They are kept in the per-cpu data areas of each cpu.
50 * They are kept together in a struct to minimize cache misses.
51 */
52struct sn_hub_info_s {
53 u8 shub2;
54 u8 nasid_shift;
55 u8 as_shift;
56 u8 shub_1_1_found;
57 u16 nasid_bitmask;
58};
59DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
60#define sn_hub_info (&__get_cpu_var(__sn_hub_info))
61#define is_shub2() (sn_hub_info->shub2)
62#define is_shub1() (sn_hub_info->shub2 == 0)
63
64/*
65 * Use this macro to test if shub 1.1 wars should be enabled
66 */
67#define enable_shub_wars_1_1() (sn_hub_info->shub_1_1_found)
68
69
70/*
71 * Compact node ID to nasid mappings kept in the per-cpu data areas of each
72 * cpu.
73 */
74DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]);
75#define sn_cnodeid_to_nasid (&__get_cpu_var(__sn_cnodeid_to_nasid[0]))
76
77
78extern u8 sn_partition_id;
79extern u8 sn_system_size;
80extern u8 sn_sharing_domain_size;
81extern u8 sn_region_size;
82
83extern void sn_flush_all_caches(long addr, long bytes);
84extern bool sn_cpu_disable_allowed(int cpu);
85
86#endif /* _ASM_IA64_SN_ARCH_H */
diff --git a/include/asm-ia64/sn/bte.h b/include/asm-ia64/sn/bte.h
deleted file mode 100644
index a0d214f43115..000000000000
--- a/include/asm-ia64/sn/bte.h
+++ /dev/null
@@ -1,233 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2000-2007 Silicon Graphics, Inc. All Rights Reserved.
7 */
8
9
10#ifndef _ASM_IA64_SN_BTE_H
11#define _ASM_IA64_SN_BTE_H
12
13#include <linux/timer.h>
14#include <linux/spinlock.h>
15#include <linux/cache.h>
16#include <asm/sn/pda.h>
17#include <asm/sn/types.h>
18#include <asm/sn/shub_mmr.h>
19
20#define IBCT_NOTIFY (0x1UL << 4)
21#define IBCT_ZFIL_MODE (0x1UL << 0)
22
23/* #define BTE_DEBUG */
24/* #define BTE_DEBUG_VERBOSE */
25
26#ifdef BTE_DEBUG
27# define BTE_PRINTK(x) printk x /* Terse */
28# ifdef BTE_DEBUG_VERBOSE
29# define BTE_PRINTKV(x) printk x /* Verbose */
30# else
31# define BTE_PRINTKV(x)
32# endif /* BTE_DEBUG_VERBOSE */
33#else
34# define BTE_PRINTK(x)
35# define BTE_PRINTKV(x)
36#endif /* BTE_DEBUG */
37
38
39/* BTE status register only supports 16 bits for length field */
40#define BTE_LEN_BITS (16)
41#define BTE_LEN_MASK ((1 << BTE_LEN_BITS) - 1)
42#define BTE_MAX_XFER ((1 << BTE_LEN_BITS) * L1_CACHE_BYTES)
43
44
45/* Define hardware */
46#define BTES_PER_NODE (is_shub2() ? 4 : 2)
47#define MAX_BTES_PER_NODE 4
48
49#define BTE2OFF_CTRL 0
50#define BTE2OFF_SRC (SH2_BT_ENG_SRC_ADDR_0 - SH2_BT_ENG_CSR_0)
51#define BTE2OFF_DEST (SH2_BT_ENG_DEST_ADDR_0 - SH2_BT_ENG_CSR_0)
52#define BTE2OFF_NOTIFY (SH2_BT_ENG_NOTIF_ADDR_0 - SH2_BT_ENG_CSR_0)
53
54#define BTE_BASE_ADDR(interface) \
55 (is_shub2() ? (interface == 0) ? SH2_BT_ENG_CSR_0 : \
56 (interface == 1) ? SH2_BT_ENG_CSR_1 : \
57 (interface == 2) ? SH2_BT_ENG_CSR_2 : \
58 SH2_BT_ENG_CSR_3 \
59 : (interface == 0) ? IIO_IBLS0 : IIO_IBLS1)
60
61#define BTE_SOURCE_ADDR(base) \
62 (is_shub2() ? base + (BTE2OFF_SRC/8) \
63 : base + (BTEOFF_SRC/8))
64
65#define BTE_DEST_ADDR(base) \
66 (is_shub2() ? base + (BTE2OFF_DEST/8) \
67 : base + (BTEOFF_DEST/8))
68
69#define BTE_CTRL_ADDR(base) \
70 (is_shub2() ? base + (BTE2OFF_CTRL/8) \
71 : base + (BTEOFF_CTRL/8))
72
73#define BTE_NOTIF_ADDR(base) \
74 (is_shub2() ? base + (BTE2OFF_NOTIFY/8) \
75 : base + (BTEOFF_NOTIFY/8))
76
77/* Define hardware modes */
78#define BTE_NOTIFY IBCT_NOTIFY
79#define BTE_NORMAL BTE_NOTIFY
80#define BTE_ZERO_FILL (BTE_NOTIFY | IBCT_ZFIL_MODE)
81/* Use a reserved bit to let the caller specify a wait for any BTE */
82#define BTE_WACQUIRE 0x4000
83/* Use the BTE on the node with the destination memory */
84#define BTE_USE_DEST (BTE_WACQUIRE << 1)
85/* Use any available BTE interface on any node for the transfer */
86#define BTE_USE_ANY (BTE_USE_DEST << 1)
87/* macro to force the IBCT0 value valid */
88#define BTE_VALID_MODE(x) ((x) & (IBCT_NOTIFY | IBCT_ZFIL_MODE))
89
90#define BTE_ACTIVE (IBLS_BUSY | IBLS_ERROR)
91#define BTE_WORD_AVAILABLE (IBLS_BUSY << 1)
92#define BTE_WORD_BUSY (~BTE_WORD_AVAILABLE)
93
94/*
95 * Some macros to simplify reading.
96 * Start with macros to locate the BTE control registers.
97 */
98#define BTE_LNSTAT_LOAD(_bte) \
99 HUB_L(_bte->bte_base_addr)
100#define BTE_LNSTAT_STORE(_bte, _x) \
101 HUB_S(_bte->bte_base_addr, (_x))
102#define BTE_SRC_STORE(_bte, _x) \
103({ \
104 u64 __addr = ((_x) & ~AS_MASK); \
105 if (is_shub2()) \
106 __addr = SH2_TIO_PHYS_TO_DMA(__addr); \
107 HUB_S(_bte->bte_source_addr, __addr); \
108})
109#define BTE_DEST_STORE(_bte, _x) \
110({ \
111 u64 __addr = ((_x) & ~AS_MASK); \
112 if (is_shub2()) \
113 __addr = SH2_TIO_PHYS_TO_DMA(__addr); \
114 HUB_S(_bte->bte_destination_addr, __addr); \
115})
116#define BTE_CTRL_STORE(_bte, _x) \
117 HUB_S(_bte->bte_control_addr, (_x))
118#define BTE_NOTIF_STORE(_bte, _x) \
119({ \
120 u64 __addr = ia64_tpa((_x) & ~AS_MASK); \
121 if (is_shub2()) \
122 __addr = SH2_TIO_PHYS_TO_DMA(__addr); \
123 HUB_S(_bte->bte_notify_addr, __addr); \
124})
125
126#define BTE_START_TRANSFER(_bte, _len, _mode) \
127 is_shub2() ? BTE_CTRL_STORE(_bte, IBLS_BUSY | (_mode << 24) | _len) \
128 : BTE_LNSTAT_STORE(_bte, _len); \
129 BTE_CTRL_STORE(_bte, _mode)
130
131/* Possible results from bte_copy and bte_unaligned_copy */
132/* The following error codes map into the BTE hardware codes
133 * IIO_ICRB_ECODE_* (in shubio.h). The hardware uses
134 * an error code of 0 (IIO_ICRB_ECODE_DERR), but we want zero
135 * to mean BTE_SUCCESS, so add one (BTEFAIL_OFFSET) to the error
136 * codes to give the following error codes.
137 */
138#define BTEFAIL_OFFSET 1
139
140typedef enum {
141 BTE_SUCCESS, /* 0 is success */
142 BTEFAIL_DIR, /* Directory error due to IIO access*/
143 BTEFAIL_POISON, /* poison error on IO access (write to poison page) */
144 BTEFAIL_WERR, /* Write error (ie WINV to a Read only line) */
145 BTEFAIL_ACCESS, /* access error (protection violation) */
146 BTEFAIL_PWERR, /* Partial Write Error */
147 BTEFAIL_PRERR, /* Partial Read Error */
148 BTEFAIL_TOUT, /* CRB Time out */
149 BTEFAIL_XTERR, /* Incoming xtalk pkt had error bit */
150 BTEFAIL_NOTAVAIL, /* BTE not available */
151} bte_result_t;
152
153#define BTEFAIL_SH2_RESP_SHORT 0x1 /* bit 000001 */
154#define BTEFAIL_SH2_RESP_LONG 0x2 /* bit 000010 */
155#define BTEFAIL_SH2_RESP_DSP 0x4 /* bit 000100 */
156#define BTEFAIL_SH2_RESP_ACCESS 0x8 /* bit 001000 */
157#define BTEFAIL_SH2_CRB_TO 0x10 /* bit 010000 */
158#define BTEFAIL_SH2_NACK_LIMIT 0x20 /* bit 100000 */
159#define BTEFAIL_SH2_ALL 0x3F /* bit 111111 */
160
161#define BTE_ERR_BITS 0x3FUL
162#define BTE_ERR_SHIFT 36
163#define BTE_ERR_MASK (BTE_ERR_BITS << BTE_ERR_SHIFT)
164
165#define BTE_ERROR_RETRY(value) \
166 (is_shub2() ? (value != BTEFAIL_SH2_CRB_TO) \
167 : (value != BTEFAIL_TOUT))
168
169/*
170 * On shub1 BTE_ERR_MASK will always be false, so no need for is_shub2()
171 */
172#define BTE_SHUB2_ERROR(_status) \
173 ((_status & BTE_ERR_MASK) \
174 ? (((_status >> BTE_ERR_SHIFT) & BTE_ERR_BITS) | IBLS_ERROR) \
175 : _status)
176
177#define BTE_GET_ERROR_STATUS(_status) \
178 (BTE_SHUB2_ERROR(_status) & ~IBLS_ERROR)
179
180#define BTE_VALID_SH2_ERROR(value) \
181 ((value >= BTEFAIL_SH2_RESP_SHORT) && (value <= BTEFAIL_SH2_ALL))
182
183/*
184 * Structure defining a bte. An instance of this
185 * structure is created in the nodepda for each
186 * bte on that node (as defined by BTES_PER_NODE)
187 * This structure contains everything necessary
188 * to work with a BTE.
189 */
190struct bteinfo_s {
191 volatile u64 notify ____cacheline_aligned;
192 u64 *bte_base_addr ____cacheline_aligned;
193 u64 *bte_source_addr;
194 u64 *bte_destination_addr;
195 u64 *bte_control_addr;
196 u64 *bte_notify_addr;
197 spinlock_t spinlock;
198 cnodeid_t bte_cnode; /* cnode */
199 int bte_error_count; /* Number of errors encountered */
200 int bte_num; /* 0 --> BTE0, 1 --> BTE1 */
201 int cleanup_active; /* Interface is locked for cleanup */
202 volatile bte_result_t bh_error; /* error while processing */
203 volatile u64 *most_rcnt_na;
204 struct bteinfo_s *btes_to_try[MAX_BTES_PER_NODE];
205};
206
207
208/*
209 * Function prototypes (functions defined in bte.c, used elsewhere)
210 */
211extern bte_result_t bte_copy(u64, u64, u64, u64, void *);
212extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64);
213extern void bte_error_handler(unsigned long);
214
215#define bte_zero(dest, len, mode, notification) \
216 bte_copy(0, dest, len, ((mode) | BTE_ZERO_FILL), notification)
217
218/*
219 * The following is the prefered way of calling bte_unaligned_copy
220 * If the copy is fully cache line aligned, then bte_copy is
221 * used instead. Since bte_copy is inlined, this saves a call
222 * stack. NOTE: bte_copy is called synchronously and does block
223 * until the transfer is complete. In order to get the asynch
224 * version of bte_copy, you must perform this check yourself.
225 */
226#define BTE_UNALIGNED_COPY(src, dest, len, mode) \
227 (((len & L1_CACHE_MASK) || (src & L1_CACHE_MASK) || \
228 (dest & L1_CACHE_MASK)) ? \
229 bte_unaligned_copy(src, dest, len, mode) : \
230 bte_copy(src, dest, len, mode, NULL))
231
232
233#endif /* _ASM_IA64_SN_BTE_H */
diff --git a/include/asm-ia64/sn/clksupport.h b/include/asm-ia64/sn/clksupport.h
deleted file mode 100644
index d340c365a824..000000000000
--- a/include/asm-ia64/sn/clksupport.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8
9/*
10 * This file contains definitions for accessing a platform supported high resolution
11 * clock. The clock is monitonically increasing and can be accessed from any node
12 * in the system. The clock is synchronized across nodes - all nodes see the
13 * same value.
14 *
15 * RTC_COUNTER_ADDR - contains the address of the counter
16 *
17 */
18
19#ifndef _ASM_IA64_SN_CLKSUPPORT_H
20#define _ASM_IA64_SN_CLKSUPPORT_H
21
22extern unsigned long sn_rtc_cycles_per_second;
23
24#define RTC_COUNTER_ADDR ((long *)LOCAL_MMR_ADDR(SH_RTC))
25
26#define rtc_time() (*RTC_COUNTER_ADDR)
27
28#endif /* _ASM_IA64_SN_CLKSUPPORT_H */
diff --git a/include/asm-ia64/sn/geo.h b/include/asm-ia64/sn/geo.h
deleted file mode 100644
index f083c9434066..000000000000
--- a/include/asm-ia64/sn/geo.h
+++ /dev/null
@@ -1,132 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_GEO_H
10#define _ASM_IA64_SN_GEO_H
11
12/* The geoid_t implementation below is based loosely on the pcfg_t
13 implementation in sys/SN/promcfg.h. */
14
15/* Type declaractions */
16
17/* Size of a geoid_t structure (must be before decl. of geoid_u) */
18#define GEOID_SIZE 8 /* Would 16 be better? The size can
19 be different on different platforms. */
20
21#define MAX_SLOTS 0xf /* slots per module */
22#define MAX_SLABS 0xf /* slabs per slot */
23
24typedef unsigned char geo_type_t;
25
26/* Fields common to all substructures */
27typedef struct geo_common_s {
28 moduleid_t module; /* The module (box) this h/w lives in */
29 geo_type_t type; /* What type of h/w is named by this geoid_t */
30 slabid_t slab:4; /* slab (ASIC), 0 .. 15 within slot */
31 slotid_t slot:4; /* slot (Blade), 0 .. 15 within module */
32} geo_common_t;
33
34/* Additional fields for particular types of hardware */
35typedef struct geo_node_s {
36 geo_common_t common; /* No additional fields needed */
37} geo_node_t;
38
39typedef struct geo_rtr_s {
40 geo_common_t common; /* No additional fields needed */
41} geo_rtr_t;
42
43typedef struct geo_iocntl_s {
44 geo_common_t common; /* No additional fields needed */
45} geo_iocntl_t;
46
47typedef struct geo_pcicard_s {
48 geo_iocntl_t common;
49 char bus; /* Bus/widget number */
50 char slot; /* PCI slot number */
51} geo_pcicard_t;
52
53/* Subcomponents of a node */
54typedef struct geo_cpu_s {
55 geo_node_t node;
56 char slice; /* Which CPU on the node */
57} geo_cpu_t;
58
59typedef struct geo_mem_s {
60 geo_node_t node;
61 char membus; /* The memory bus on the node */
62 char memslot; /* The memory slot on the bus */
63} geo_mem_t;
64
65
66typedef union geoid_u {
67 geo_common_t common;
68 geo_node_t node;
69 geo_iocntl_t iocntl;
70 geo_pcicard_t pcicard;
71 geo_rtr_t rtr;
72 geo_cpu_t cpu;
73 geo_mem_t mem;
74 char padsize[GEOID_SIZE];
75} geoid_t;
76
77
78/* Preprocessor macros */
79
80#define GEO_MAX_LEN 48 /* max. formatted length, plus some pad:
81 module/001c07/slab/5/node/memory/2/slot/4 */
82
83/* Values for geo_type_t */
84#define GEO_TYPE_INVALID 0
85#define GEO_TYPE_MODULE 1
86#define GEO_TYPE_NODE 2
87#define GEO_TYPE_RTR 3
88#define GEO_TYPE_IOCNTL 4
89#define GEO_TYPE_IOCARD 5
90#define GEO_TYPE_CPU 6
91#define GEO_TYPE_MEM 7
92#define GEO_TYPE_MAX (GEO_TYPE_MEM+1)
93
94/* Parameter for hwcfg_format_geoid_compt() */
95#define GEO_COMPT_MODULE 1
96#define GEO_COMPT_SLAB 2
97#define GEO_COMPT_IOBUS 3
98#define GEO_COMPT_IOSLOT 4
99#define GEO_COMPT_CPU 5
100#define GEO_COMPT_MEMBUS 6
101#define GEO_COMPT_MEMSLOT 7
102
103#define GEO_INVALID_STR "<invalid>"
104
105#define INVALID_NASID ((nasid_t)-1)
106#define INVALID_CNODEID ((cnodeid_t)-1)
107#define INVALID_PNODEID ((pnodeid_t)-1)
108#define INVALID_SLAB (slabid_t)-1
109#define INVALID_SLOT (slotid_t)-1
110#define INVALID_MODULE ((moduleid_t)-1)
111
112static inline slabid_t geo_slab(geoid_t g)
113{
114 return (g.common.type == GEO_TYPE_INVALID) ?
115 INVALID_SLAB : g.common.slab;
116}
117
118static inline slotid_t geo_slot(geoid_t g)
119{
120 return (g.common.type == GEO_TYPE_INVALID) ?
121 INVALID_SLOT : g.common.slot;
122}
123
124static inline moduleid_t geo_module(geoid_t g)
125{
126 return (g.common.type == GEO_TYPE_INVALID) ?
127 INVALID_MODULE : g.common.module;
128}
129
130extern geoid_t cnodeid_get_geoid(cnodeid_t cnode);
131
132#endif /* _ASM_IA64_SN_GEO_H */
diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h
deleted file mode 100644
index e0487aa97418..000000000000
--- a/include/asm-ia64/sn/intr.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_INTR_H
10#define _ASM_IA64_SN_INTR_H
11
12#include <linux/rcupdate.h>
13#include <asm/sn/types.h>
14
15#define SGI_UART_VECTOR 0xe9
16
17/* Reserved IRQs : Note, not to exceed IA64_SN2_FIRST_DEVICE_VECTOR */
18#define SGI_XPC_ACTIVATE 0x30
19#define SGI_II_ERROR 0x31
20#define SGI_XBOW_ERROR 0x32
21#define SGI_PCIASIC_ERROR 0x33
22#define SGI_ACPI_SCI_INT 0x34
23#define SGI_TIOCA_ERROR 0x35
24#define SGI_TIO_ERROR 0x36
25#define SGI_TIOCX_ERROR 0x37
26#define SGI_MMTIMER_VECTOR 0x38
27#define SGI_XPC_NOTIFY 0xe7
28
29#define IA64_SN2_FIRST_DEVICE_VECTOR 0x3c
30#define IA64_SN2_LAST_DEVICE_VECTOR 0xe6
31
32#define SN2_IRQ_RESERVED 0x1
33#define SN2_IRQ_CONNECTED 0x2
34#define SN2_IRQ_SHARED 0x4
35
36// The SN PROM irq struct
37struct sn_irq_info {
38 struct sn_irq_info *irq_next; /* deprecated DO NOT USE */
39 short irq_nasid; /* Nasid IRQ is assigned to */
40 int irq_slice; /* slice IRQ is assigned to */
41 int irq_cpuid; /* kernel logical cpuid */
42 int irq_irq; /* the IRQ number */
43 int irq_int_bit; /* Bridge interrupt pin */
44 /* <0 means MSI */
45 u64 irq_xtalkaddr; /* xtalkaddr IRQ is sent to */
46 int irq_bridge_type;/* pciio asic type (pciio.h) */
47 void *irq_bridge; /* bridge generating irq */
48 void *irq_pciioinfo; /* associated pciio_info_t */
49 int irq_last_intr; /* For Shub lb lost intr WAR */
50 int irq_cookie; /* unique cookie */
51 int irq_flags; /* flags */
52 int irq_share_cnt; /* num devices sharing IRQ */
53 struct list_head list; /* list of sn_irq_info structs */
54 struct rcu_head rcu; /* rcu callback list */
55};
56
57extern void sn_send_IPI_phys(int, long, int, int);
58extern u64 sn_intr_alloc(nasid_t, int,
59 struct sn_irq_info *,
60 int, nasid_t, int);
61extern void sn_intr_free(nasid_t, int, struct sn_irq_info *);
62extern struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *, nasid_t, int);
63extern void sn_set_err_irq_affinity(unsigned int);
64extern struct list_head **sn_irq_lh;
65
66#define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector)
67
68#endif /* _ASM_IA64_SN_INTR_H */
diff --git a/include/asm-ia64/sn/io.h b/include/asm-ia64/sn/io.h
deleted file mode 100644
index 41c73a735628..000000000000
--- a/include/asm-ia64/sn/io.h
+++ /dev/null
@@ -1,274 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_SN_IO_H
10#define _ASM_SN_IO_H
11#include <linux/compiler.h>
12#include <asm/intrinsics.h>
13
14extern void * sn_io_addr(unsigned long port) __attribute_const__; /* Forward definition */
15extern void __sn_mmiowb(void); /* Forward definition */
16
17extern int num_cnodes;
18
19#define __sn_mf_a() ia64_mfa()
20
21extern void sn_dma_flush(unsigned long);
22
23#define __sn_inb ___sn_inb
24#define __sn_inw ___sn_inw
25#define __sn_inl ___sn_inl
26#define __sn_outb ___sn_outb
27#define __sn_outw ___sn_outw
28#define __sn_outl ___sn_outl
29#define __sn_readb ___sn_readb
30#define __sn_readw ___sn_readw
31#define __sn_readl ___sn_readl
32#define __sn_readq ___sn_readq
33#define __sn_readb_relaxed ___sn_readb_relaxed
34#define __sn_readw_relaxed ___sn_readw_relaxed
35#define __sn_readl_relaxed ___sn_readl_relaxed
36#define __sn_readq_relaxed ___sn_readq_relaxed
37
38/*
39 * Convenience macros for setting/clearing bits using the above accessors
40 */
41
42#define __sn_setq_relaxed(addr, val) \
43 writeq((__sn_readq_relaxed(addr) | (val)), (addr))
44#define __sn_clrq_relaxed(addr, val) \
45 writeq((__sn_readq_relaxed(addr) & ~(val)), (addr))
46
47/*
48 * The following routines are SN Platform specific, called when
49 * a reference is made to inX/outX set macros. SN Platform
50 * inX set of macros ensures that Posted DMA writes on the
51 * Bridge is flushed.
52 *
53 * The routines should be self explainatory.
54 */
55
56static inline unsigned int
57___sn_inb (unsigned long port)
58{
59 volatile unsigned char *addr;
60 unsigned char ret = -1;
61
62 if ((addr = sn_io_addr(port))) {
63 ret = *addr;
64 __sn_mf_a();
65 sn_dma_flush((unsigned long)addr);
66 }
67 return ret;
68}
69
70static inline unsigned int
71___sn_inw (unsigned long port)
72{
73 volatile unsigned short *addr;
74 unsigned short ret = -1;
75
76 if ((addr = sn_io_addr(port))) {
77 ret = *addr;
78 __sn_mf_a();
79 sn_dma_flush((unsigned long)addr);
80 }
81 return ret;
82}
83
84static inline unsigned int
85___sn_inl (unsigned long port)
86{
87 volatile unsigned int *addr;
88 unsigned int ret = -1;
89
90 if ((addr = sn_io_addr(port))) {
91 ret = *addr;
92 __sn_mf_a();
93 sn_dma_flush((unsigned long)addr);
94 }
95 return ret;
96}
97
98static inline void
99___sn_outb (unsigned char val, unsigned long port)
100{
101 volatile unsigned char *addr;
102
103 if ((addr = sn_io_addr(port))) {
104 *addr = val;
105 __sn_mmiowb();
106 }
107}
108
109static inline void
110___sn_outw (unsigned short val, unsigned long port)
111{
112 volatile unsigned short *addr;
113
114 if ((addr = sn_io_addr(port))) {
115 *addr = val;
116 __sn_mmiowb();
117 }
118}
119
120static inline void
121___sn_outl (unsigned int val, unsigned long port)
122{
123 volatile unsigned int *addr;
124
125 if ((addr = sn_io_addr(port))) {
126 *addr = val;
127 __sn_mmiowb();
128 }
129}
130
131/*
132 * The following routines are SN Platform specific, called when
133 * a reference is made to readX/writeX set macros. SN Platform
134 * readX set of macros ensures that Posted DMA writes on the
135 * Bridge is flushed.
136 *
137 * The routines should be self explainatory.
138 */
139
140static inline unsigned char
141___sn_readb (const volatile void __iomem *addr)
142{
143 unsigned char val;
144
145 val = *(volatile unsigned char __force *)addr;
146 __sn_mf_a();
147 sn_dma_flush((unsigned long)addr);
148 return val;
149}
150
151static inline unsigned short
152___sn_readw (const volatile void __iomem *addr)
153{
154 unsigned short val;
155
156 val = *(volatile unsigned short __force *)addr;
157 __sn_mf_a();
158 sn_dma_flush((unsigned long)addr);
159 return val;
160}
161
162static inline unsigned int
163___sn_readl (const volatile void __iomem *addr)
164{
165 unsigned int val;
166
167 val = *(volatile unsigned int __force *)addr;
168 __sn_mf_a();
169 sn_dma_flush((unsigned long)addr);
170 return val;
171}
172
173static inline unsigned long
174___sn_readq (const volatile void __iomem *addr)
175{
176 unsigned long val;
177
178 val = *(volatile unsigned long __force *)addr;
179 __sn_mf_a();
180 sn_dma_flush((unsigned long)addr);
181 return val;
182}
183
184/*
185 * For generic and SN2 kernels, we have a set of fast access
186 * PIO macros. These macros are provided on SN Platform
187 * because the normal inX and readX macros perform an
188 * additional task of flushing Post DMA request on the Bridge.
189 *
190 * These routines should be self explainatory.
191 */
192
193static inline unsigned int
194sn_inb_fast (unsigned long port)
195{
196 volatile unsigned char *addr = (unsigned char *)port;
197 unsigned char ret;
198
199 ret = *addr;
200 __sn_mf_a();
201 return ret;
202}
203
204static inline unsigned int
205sn_inw_fast (unsigned long port)
206{
207 volatile unsigned short *addr = (unsigned short *)port;
208 unsigned short ret;
209
210 ret = *addr;
211 __sn_mf_a();
212 return ret;
213}
214
215static inline unsigned int
216sn_inl_fast (unsigned long port)
217{
218 volatile unsigned int *addr = (unsigned int *)port;
219 unsigned int ret;
220
221 ret = *addr;
222 __sn_mf_a();
223 return ret;
224}
225
226static inline unsigned char
227___sn_readb_relaxed (const volatile void __iomem *addr)
228{
229 return *(volatile unsigned char __force *)addr;
230}
231
232static inline unsigned short
233___sn_readw_relaxed (const volatile void __iomem *addr)
234{
235 return *(volatile unsigned short __force *)addr;
236}
237
238static inline unsigned int
239___sn_readl_relaxed (const volatile void __iomem *addr)
240{
241 return *(volatile unsigned int __force *) addr;
242}
243
244static inline unsigned long
245___sn_readq_relaxed (const volatile void __iomem *addr)
246{
247 return *(volatile unsigned long __force *) addr;
248}
249
250struct pci_dev;
251
252static inline int
253sn_pci_set_vchan(struct pci_dev *pci_dev, unsigned long *addr, int vchan)
254{
255
256 if (vchan > 1) {
257 return -1;
258 }
259
260 if (!(*addr >> 32)) /* Using a mask here would be cleaner */
261 return 0; /* but this generates better code */
262
263 if (vchan == 1) {
264 /* Set Bit 57 */
265 *addr |= (1UL << 57);
266 } else {
267 /* Clear Bit 57 */
268 *addr &= ~(1UL << 57);
269 }
270
271 return 0;
272}
273
274#endif /* _ASM_SN_IO_H */
diff --git a/include/asm-ia64/sn/ioc3.h b/include/asm-ia64/sn/ioc3.h
deleted file mode 100644
index 95ed6cc83cf1..000000000000
--- a/include/asm-ia64/sn/ioc3.h
+++ /dev/null
@@ -1,241 +0,0 @@
1/*
2 * Copyright (C) 2005 Silicon Graphics, Inc.
3 */
4#ifndef IA64_SN_IOC3_H
5#define IA64_SN_IOC3_H
6
7/* serial port register map */
8struct ioc3_serialregs {
9 uint32_t sscr;
10 uint32_t stpir;
11 uint32_t stcir;
12 uint32_t srpir;
13 uint32_t srcir;
14 uint32_t srtr;
15 uint32_t shadow;
16};
17
18/* SUPERIO uart register map */
19struct ioc3_uartregs {
20 char iu_lcr;
21 union {
22 char iir; /* read only */
23 char fcr; /* write only */
24 } u3;
25 union {
26 char ier; /* DLAB == 0 */
27 char dlm; /* DLAB == 1 */
28 } u2;
29 union {
30 char rbr; /* read only, DLAB == 0 */
31 char thr; /* write only, DLAB == 0 */
32 char dll; /* DLAB == 1 */
33 } u1;
34 char iu_scr;
35 char iu_msr;
36 char iu_lsr;
37 char iu_mcr;
38};
39
40#define iu_rbr u1.rbr
41#define iu_thr u1.thr
42#define iu_dll u1.dll
43#define iu_ier u2.ier
44#define iu_dlm u2.dlm
45#define iu_iir u3.iir
46#define iu_fcr u3.fcr
47
48struct ioc3_sioregs {
49 char fill[0x170];
50 struct ioc3_uartregs uartb;
51 struct ioc3_uartregs uarta;
52};
53
54/* PCI IO/mem space register map */
55struct ioc3 {
56 uint32_t pci_id;
57 uint32_t pci_scr;
58 uint32_t pci_rev;
59 uint32_t pci_lat;
60 uint32_t pci_addr;
61 uint32_t pci_err_addr_l;
62 uint32_t pci_err_addr_h;
63
64 uint32_t sio_ir;
65 /* these registers are read-only for general kernel code. To
66 * modify them use the functions in ioc3.c
67 */
68 uint32_t sio_ies;
69 uint32_t sio_iec;
70 uint32_t sio_cr;
71 uint32_t int_out;
72 uint32_t mcr;
73 uint32_t gpcr_s;
74 uint32_t gpcr_c;
75 uint32_t gpdr;
76 uint32_t gppr[9];
77 char fill[0x4c];
78
79 /* serial port registers */
80 uint32_t sbbr_h;
81 uint32_t sbbr_l;
82
83 struct ioc3_serialregs port_a;
84 struct ioc3_serialregs port_b;
85 char fill1[0x1ff10];
86 /* superio registers */
87 struct ioc3_sioregs sregs;
88};
89
90/* These don't exist on the ioc3 serial card... */
91#define eier fill1[8]
92#define eisr fill1[4]
93
94#define PCI_LAT 0xc /* Latency Timer */
95#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */
96#define UARTA_BASE 0x178
97#define UARTB_BASE 0x170
98
99
100/* bitmasks for serial RX status byte */
101#define RXSB_OVERRUN 0x01 /* char(s) lost */
102#define RXSB_PAR_ERR 0x02 /* parity error */
103#define RXSB_FRAME_ERR 0x04 /* framing error */
104#define RXSB_BREAK 0x08 /* break character */
105#define RXSB_CTS 0x10 /* state of CTS */
106#define RXSB_DCD 0x20 /* state of DCD */
107#define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */
108#define RXSB_DATA_VALID 0x80 /* FRAME_ERR PAR_ERR & BREAK valid */
109
110/* bitmasks for serial TX control byte */
111#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
112#define TXCB_INVALID 0x00 /* byte is invalid */
113#define TXCB_VALID 0x40 /* byte is valid */
114#define TXCB_MCR 0x80 /* data<7:0> to modem cntrl register */
115#define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */
116
117/* bitmasks for SBBR_L */
118#define SBBR_L_SIZE 0x00000001 /* 0 1KB rings, 1 4KB rings */
119
120/* bitmasks for SSCR_<A:B> */
121#define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */
122#define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
123#define SSCR_HFC_EN 0x00020000 /* h/w flow cntrl enabled */
124#define SSCR_RX_RING_DCD 0x00040000 /* postRX record on delta-DCD */
125#define SSCR_RX_RING_CTS 0x00080000 /* postRX record on delta-CTS */
126#define SSCR_HIGH_SPD 0x00100000 /* 4X speed */
127#define SSCR_DIAG 0x00200000 /* bypass clock divider */
128#define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */
129#define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */
130#define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */
131#define SSCR_PAUSE_STATE 0x40000000 /* set when PAUSE takes effect*/
132#define SSCR_RESET 0x80000000 /* reset DMA channels */
133
134/* all producer/comsumer pointers are the same bitfield */
135#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */
136#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */
137#define PROD_CONS_PTR_OFF 3
138
139/* bitmasks for SRCIR_<A:B> */
140#define SRCIR_ARM 0x80000000 /* arm RX timer */
141
142/* bitmasks for SHADOW_<A:B> */
143#define SHADOW_DR 0x00000001 /* data ready */
144#define SHADOW_OE 0x00000002 /* overrun error */
145#define SHADOW_PE 0x00000004 /* parity error */
146#define SHADOW_FE 0x00000008 /* framing error */
147#define SHADOW_BI 0x00000010 /* break interrupt */
148#define SHADOW_THRE 0x00000020 /* transmit holding reg empty */
149#define SHADOW_TEMT 0x00000040 /* transmit shift reg empty */
150#define SHADOW_RFCE 0x00000080 /* char in RX fifo has error */
151#define SHADOW_DCTS 0x00010000 /* delta clear to send */
152#define SHADOW_DDCD 0x00080000 /* delta data carrier detect */
153#define SHADOW_CTS 0x00100000 /* clear to send */
154#define SHADOW_DCD 0x00800000 /* data carrier detect */
155#define SHADOW_DTR 0x01000000 /* data terminal ready */
156#define SHADOW_RTS 0x02000000 /* request to send */
157#define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
158#define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
159#define SHADOW_LOOP 0x10000000 /* loopback enabled */
160
161/* bitmasks for SRTR_<A:B> */
162#define SRTR_CNT 0x00000fff /* reload value for RX timer */
163#define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */
164#define SRTR_CNT_VAL_SHIFT 16
165#define SRTR_HZ 16000 /* SRTR clock frequency */
166
167/* bitmasks for SIO_IR, SIO_IEC and SIO_IES */
168#define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */
169#define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */
170#define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */
171#define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */
172#define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */
173#define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */
174#define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */
175#define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */
176#define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */
177#define SIO_IR_SB_TX_MT 0x00000200
178#define SIO_IR_SB_RX_FULL 0x00000400
179#define SIO_IR_SB_RX_HIGH 0x00000800
180#define SIO_IR_SB_RX_TIMER 0x00001000
181#define SIO_IR_SB_DELTA_DCD 0x00002000
182#define SIO_IR_SB_DELTA_CTS 0x00004000
183#define SIO_IR_SB_INT 0x00008000
184#define SIO_IR_SB_TX_EXPLICIT 0x00010000
185#define SIO_IR_SB_MEMERR 0x00020000
186#define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */
187#define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */
188#define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */
189#define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */
190#define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */
191#define SIO_IR_RT_INT 0x08000000 /* RT output pulse */
192#define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */
193#define SIO_IR_GEN_INT_SHIFT 28
194
195/* per device interrupt masks */
196#define SIO_IR_SA (SIO_IR_SA_TX_MT | \
197 SIO_IR_SA_RX_FULL | \
198 SIO_IR_SA_RX_HIGH | \
199 SIO_IR_SA_RX_TIMER | \
200 SIO_IR_SA_DELTA_DCD | \
201 SIO_IR_SA_DELTA_CTS | \
202 SIO_IR_SA_INT | \
203 SIO_IR_SA_TX_EXPLICIT | \
204 SIO_IR_SA_MEMERR)
205
206#define SIO_IR_SB (SIO_IR_SB_TX_MT | \
207 SIO_IR_SB_RX_FULL | \
208 SIO_IR_SB_RX_HIGH | \
209 SIO_IR_SB_RX_TIMER | \
210 SIO_IR_SB_DELTA_DCD | \
211 SIO_IR_SB_DELTA_CTS | \
212 SIO_IR_SB_INT | \
213 SIO_IR_SB_TX_EXPLICIT | \
214 SIO_IR_SB_MEMERR)
215
216#define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
217 SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
218#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
219
220/* bitmasks for SIO_CR */
221#define SIO_CR_CMD_PULSE_SHIFT 15
222#define SIO_CR_SER_A_BASE_SHIFT 1
223#define SIO_CR_SER_B_BASE_SHIFT 8
224#define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */
225#define SIO_CR_ARB_DIAG_TXA 0x00000000
226#define SIO_CR_ARB_DIAG_RXA 0x00080000
227#define SIO_CR_ARB_DIAG_TXB 0x00100000
228#define SIO_CR_ARB_DIAG_RXB 0x00180000
229#define SIO_CR_ARB_DIAG_PP 0x00200000
230#define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */
231
232/* defs for some of the generic I/O pins */
233#define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */
234#define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */
235#define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */
236
237#define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */
238#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin cntrling uartb modeselect */
239#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin cntrling uarta modeselect */
240
241#endif /* IA64_SN_IOC3_H */
diff --git a/include/asm-ia64/sn/klconfig.h b/include/asm-ia64/sn/klconfig.h
deleted file mode 100644
index bcbf209d63be..000000000000
--- a/include/asm-ia64/sn/klconfig.h
+++ /dev/null
@@ -1,246 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/klconfig.h>.
7 *
8 * Copyright (C) 1992-1997,1999,2001-2004 Silicon Graphics, Inc. All Rights Reserved.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11#ifndef _ASM_IA64_SN_KLCONFIG_H
12#define _ASM_IA64_SN_KLCONFIG_H
13
14/*
15 * The KLCONFIG structures store info about the various BOARDs found
16 * during Hardware Discovery. In addition, it stores info about the
17 * components found on the BOARDs.
18 */
19
20typedef s32 klconf_off_t;
21
22
23/* Functions/macros needed to use this structure */
24
25typedef struct kl_config_hdr {
26 char pad[20];
27 klconf_off_t ch_board_info; /* the link list of boards */
28 char pad0[88];
29} kl_config_hdr_t;
30
31
32#define NODE_OFFSET_TO_LBOARD(nasid,off) (lboard_t*)(GLOBAL_CAC_ADDR((nasid), (off)))
33
34/*
35 * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
36 * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to
37 * the LOCAL/current NODE. REMOTE means it is attached to a different
38 * node.(TBD - Need a way to treat ROUTER boards.)
39 *
40 * There are 2 different structures to represent these boards -
41 * lboard - Local board, rboard - remote board. These 2 structures
42 * can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer
43 * Figure below). The first byte of the rboard or lboard structure
44 * is used to find out its type - no unions are used.
45 * If it is a lboard, then the config info of this board will be found
46 * on the local node. (LOCAL NODE BASE + offset value gives pointer to
47 * the structure.
48 * If it is a rboard, the local structure contains the node number
49 * and the offset of the beginning of the LINKED LIST on the remote node.
50 * The details of the hardware on a remote node can be built locally,
51 * if required, by reading the LINKED LIST on the remote node and
52 * ignoring all the rboards on that node.
53 *
54 * The local node uses the REMOTE NODE NUMBER + OFFSET to point to the
55 * First board info on the remote node. The remote node list is
56 * traversed as the local list, using the REMOTE BASE ADDRESS and not
57 * the local base address and ignoring all rboard values.
58 *
59 *
60 KLCONFIG
61
62 +------------+ +------------+ +------------+ +------------+
63 | lboard | +-->| lboard | +-->| rboard | +-->| lboard |
64 +------------+ | +------------+ | +------------+ | +------------+
65 | board info | | | board info | | |errinfo,bptr| | | board info |
66 +------------+ | +------------+ | +------------+ | +------------+
67 | offset |--+ | offset |--+ | offset |--+ |offset=NULL |
68 +------------+ +------------+ +------------+ +------------+
69
70
71 +------------+
72 | board info |
73 +------------+ +--------------------------------+
74 | compt 1 |------>| type, rev, diaginfo, size ... | (CPU)
75 +------------+ +--------------------------------+
76 | compt 2 |--+
77 +------------+ | +--------------------------------+
78 | ... | +--->| type, rev, diaginfo, size ... | (MEM_BANK)
79 +------------+ +--------------------------------+
80 | errinfo |--+
81 +------------+ | +--------------------------------+
82 +--->|r/l brd errinfo,compt err flags |
83 +--------------------------------+
84
85 *
86 * Each BOARD consists of COMPONENTs and the BOARD structure has
87 * pointers (offsets) to its COMPONENT structure.
88 * The COMPONENT structure has version info, size and speed info, revision,
89 * error info and the NIC info. This structure can accommodate any
90 * BOARD with arbitrary COMPONENT composition.
91 *
92 * The ERRORINFO part of each BOARD has error information
93 * that describes errors about the BOARD itself. It also has flags to
94 * indicate the COMPONENT(s) on the board that have errors. The error
95 * information specific to the COMPONENT is present in the respective
96 * COMPONENT structure.
97 *
98 * The ERRORINFO structure is also treated like a COMPONENT, ie. the
99 * BOARD has pointers(offset) to the ERRORINFO structure. The rboard
100 * structure also has a pointer to the ERRORINFO structure. This is
101 * the place to store ERRORINFO about a REMOTE NODE, if the HUB on
102 * that NODE is not working or if the REMOTE MEMORY is BAD. In cases where
103 * only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can
104 * be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info
105 * which is present on the REMOTE NODE.(TBD)
106 * REMOTE ERRINFO can be stored on any of the nearest nodes
107 * or on all the nearest nodes.(TBD)
108 * Like BOARD structures, REMOTE ERRINFO structures can be built locally
109 * using the rboard errinfo pointer.
110 *
111 * In order to get useful information from this Data organization, a set of
112 * interface routines are provided (TBD). The important thing to remember while
113 * manipulating the structures, is that, the NODE number information should
114 * be used. If the NODE is non-zero (remote) then each offset should
115 * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR.
116 * This includes offsets for BOARDS, COMPONENTS and ERRORINFO.
117 *
118 * Note that these structures do not provide much info about connectivity.
119 * That info will be part of HWGRAPH, which is an extension of the cfg_t
120 * data structure. (ref IP27prom/cfg.h) It has to be extended to include
121 * the IO part of the Network(TBD).
122 *
123 * The data structures below define the above concepts.
124 */
125
126
127/*
128 * BOARD classes
129 */
130
131#define KLCLASS_MASK 0xf0
132#define KLCLASS_NONE 0x00
133#define KLCLASS_NODE 0x10 /* CPU, Memory and HUB board */
134#define KLCLASS_CPU KLCLASS_NODE
135#define KLCLASS_IO 0x20 /* BaseIO, 4 ch SCSI, ethernet, FDDI
136 and the non-graphics widget boards */
137#define KLCLASS_ROUTER 0x30 /* Router board */
138#define KLCLASS_MIDPLANE 0x40 /* We need to treat this as a board
139 so that we can record error info */
140#define KLCLASS_IOBRICK 0x70 /* IP35 iobrick */
141#define KLCLASS_MAX 8 /* Bump this if a new CLASS is added */
142
143#define KLCLASS(_x) ((_x) & KLCLASS_MASK)
144
145
146/*
147 * board types
148 */
149
150#define KLTYPE_MASK 0x0f
151#define KLTYPE(_x) ((_x) & KLTYPE_MASK)
152
153#define KLTYPE_SNIA (KLCLASS_CPU | 0x1)
154#define KLTYPE_TIO (KLCLASS_CPU | 0x2)
155
156#define KLTYPE_ROUTER (KLCLASS_ROUTER | 0x1)
157#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
158#define KLTYPE_REPEATER_ROUTER (KLCLASS_ROUTER | 0x4)
159
160#define KLTYPE_IOBRICK_XBOW (KLCLASS_MIDPLANE | 0x2)
161
162#define KLTYPE_IOBRICK (KLCLASS_IOBRICK | 0x0)
163#define KLTYPE_NBRICK (KLCLASS_IOBRICK | 0x4)
164#define KLTYPE_PXBRICK (KLCLASS_IOBRICK | 0x6)
165#define KLTYPE_IXBRICK (KLCLASS_IOBRICK | 0x7)
166#define KLTYPE_CGBRICK (KLCLASS_IOBRICK | 0x8)
167#define KLTYPE_OPUSBRICK (KLCLASS_IOBRICK | 0x9)
168#define KLTYPE_SABRICK (KLCLASS_IOBRICK | 0xa)
169#define KLTYPE_IABRICK (KLCLASS_IOBRICK | 0xb)
170#define KLTYPE_PABRICK (KLCLASS_IOBRICK | 0xc)
171#define KLTYPE_GABRICK (KLCLASS_IOBRICK | 0xd)
172
173
174/*
175 * board structures
176 */
177
178#define MAX_COMPTS_PER_BRD 24
179
180typedef struct lboard_s {
181 klconf_off_t brd_next_any; /* Next BOARD */
182 unsigned char struct_type; /* type of structure, local or remote */
183 unsigned char brd_type; /* type+class */
184 unsigned char brd_sversion; /* version of this structure */
185 unsigned char brd_brevision; /* board revision */
186 unsigned char brd_promver; /* board prom version, if any */
187 unsigned char brd_flags; /* Enabled, Disabled etc */
188 unsigned char brd_slot; /* slot number */
189 unsigned short brd_debugsw; /* Debug switches */
190 geoid_t brd_geoid; /* geo id */
191 partid_t brd_partition; /* Partition number */
192 unsigned short brd_diagval; /* diagnostic value */
193 unsigned short brd_diagparm; /* diagnostic parameter */
194 unsigned char brd_inventory; /* inventory history */
195 unsigned char brd_numcompts; /* Number of components */
196 nic_t brd_nic; /* Number in CAN */
197 nasid_t brd_nasid; /* passed parameter */
198 klconf_off_t brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
199 klconf_off_t brd_errinfo; /* Board's error information */
200 struct lboard_s *brd_parent; /* Logical parent for this brd */
201 char pad0[4];
202 unsigned char brd_confidence; /* confidence that the board is bad */
203 nasid_t brd_owner; /* who owns this board */
204 unsigned char brd_nic_flags; /* To handle 8 more NICs */
205 char pad1[24]; /* future expansion */
206 char brd_name[32];
207 nasid_t brd_next_same_host; /* host of next brd w/same nasid */
208 klconf_off_t brd_next_same; /* Next BOARD with same nasid */
209} lboard_t;
210
211/*
212 * Generic info structure. This stores common info about a
213 * component.
214 */
215
216typedef struct klinfo_s { /* Generic info */
217 unsigned char struct_type; /* type of this structure */
218 unsigned char struct_version; /* version of this structure */
219 unsigned char flags; /* Enabled, disabled etc */
220 unsigned char revision; /* component revision */
221 unsigned short diagval; /* result of diagnostics */
222 unsigned short diagparm; /* diagnostic parameter */
223 unsigned char inventory; /* previous inventory status */
224 unsigned short partid; /* widget part number */
225 nic_t nic; /* MUst be aligned properly */
226 unsigned char physid; /* physical id of component */
227 unsigned int virtid; /* virtual id as seen by system */
228 unsigned char widid; /* Widget id - if applicable */
229 nasid_t nasid; /* node number - from parent */
230 char pad1; /* pad out structure. */
231 char pad2; /* pad out structure. */
232 void *data;
233 klconf_off_t errinfo; /* component specific errors */
234 unsigned short pad3; /* pci fields have moved over to */
235 unsigned short pad4; /* klbri_t */
236} klinfo_t ;
237
238
239static inline lboard_t *find_lboard_next(lboard_t * brd)
240{
241 if (brd && brd->brd_next_any)
242 return NODE_OFFSET_TO_LBOARD(NASID_GET(brd), brd->brd_next_any);
243 return NULL;
244}
245
246#endif /* _ASM_IA64_SN_KLCONFIG_H */
diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h
deleted file mode 100644
index 344bf44bb356..000000000000
--- a/include/asm-ia64/sn/l1.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All Rights Reserved.
7 */
8
9#ifndef _ASM_IA64_SN_L1_H
10#define _ASM_IA64_SN_L1_H
11
12/* brick type response codes */
13#define L1_BRICKTYPE_PX 0x23 /* # */
14#define L1_BRICKTYPE_PE 0x25 /* % */
15#define L1_BRICKTYPE_N_p0 0x26 /* & */
16#define L1_BRICKTYPE_IP45 0x34 /* 4 */
17#define L1_BRICKTYPE_IP41 0x35 /* 5 */
18#define L1_BRICKTYPE_TWISTER 0x36 /* 6 */ /* IP53 & ROUTER */
19#define L1_BRICKTYPE_IX 0x3d /* = */
20#define L1_BRICKTYPE_IP34 0x61 /* a */
21#define L1_BRICKTYPE_GA 0x62 /* b */
22#define L1_BRICKTYPE_C 0x63 /* c */
23#define L1_BRICKTYPE_OPUS_TIO 0x66 /* f */
24#define L1_BRICKTYPE_I 0x69 /* i */
25#define L1_BRICKTYPE_N 0x6e /* n */
26#define L1_BRICKTYPE_OPUS 0x6f /* o */
27#define L1_BRICKTYPE_P 0x70 /* p */
28#define L1_BRICKTYPE_R 0x72 /* r */
29#define L1_BRICKTYPE_CHI_CG 0x76 /* v */
30#define L1_BRICKTYPE_X 0x78 /* x */
31#define L1_BRICKTYPE_X2 0x79 /* y */
32#define L1_BRICKTYPE_SA 0x5e /* ^ */
33#define L1_BRICKTYPE_PA 0x6a /* j */
34#define L1_BRICKTYPE_IA 0x6b /* k */
35#define L1_BRICKTYPE_ATHENA 0x2b /* + */
36#define L1_BRICKTYPE_DAYTONA 0x7a /* z */
37#define L1_BRICKTYPE_1932 0x2c /* . */
38#define L1_BRICKTYPE_191010 0x2e /* , */
39
40/* board type response codes */
41#define L1_BOARDTYPE_IP69 0x0100 /* CA */
42#define L1_BOARDTYPE_IP63 0x0200 /* CB */
43#define L1_BOARDTYPE_BASEIO 0x0300 /* IB */
44#define L1_BOARDTYPE_PCIE2SLOT 0x0400 /* IC */
45#define L1_BOARDTYPE_PCIX3SLOT 0x0500 /* ID */
46#define L1_BOARDTYPE_PCIXPCIE4SLOT 0x0600 /* IE */
47#define L1_BOARDTYPE_ABACUS 0x0700 /* AB */
48#define L1_BOARDTYPE_DAYTONA 0x0800 /* AD */
49#define L1_BOARDTYPE_INVAL (-1) /* invalid brick type */
50
51#endif /* _ASM_IA64_SN_L1_H */
diff --git a/include/asm-ia64/sn/leds.h b/include/asm-ia64/sn/leds.h
deleted file mode 100644
index 66cf8c4d92c9..000000000000
--- a/include/asm-ia64/sn/leds.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
6 */
7#ifndef _ASM_IA64_SN_LEDS_H
8#define _ASM_IA64_SN_LEDS_H
9
10#include <asm/sn/addrs.h>
11#include <asm/sn/pda.h>
12#include <asm/sn/shub_mmr.h>
13
14#define LED0 (LOCAL_MMR_ADDR(SH_REAL_JUNK_BUS_LED0))
15#define LED_CPU_SHIFT 16
16
17#define LED_CPU_HEARTBEAT 0x01
18#define LED_CPU_ACTIVITY 0x02
19#define LED_ALWAYS_SET 0x00
20
21/*
22 * Basic macros for flashing the LEDS on an SGI SN.
23 */
24
25static __inline__ void
26set_led_bits(u8 value, u8 mask)
27{
28 pda->led_state = (pda->led_state & ~mask) | (value & mask);
29 *pda->led_address = (short) pda->led_state;
30}
31
32#endif /* _ASM_IA64_SN_LEDS_H */
33
diff --git a/include/asm-ia64/sn/module.h b/include/asm-ia64/sn/module.h
deleted file mode 100644
index 734e980ece2f..000000000000
--- a/include/asm-ia64/sn/module.h
+++ /dev/null
@@ -1,127 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_MODULE_H
9#define _ASM_IA64_SN_MODULE_H
10
11/* parameter for format_module_id() */
12#define MODULE_FORMAT_BRIEF 1
13#define MODULE_FORMAT_LONG 2
14#define MODULE_FORMAT_LCD 3
15
16/*
17 * Module id format
18 *
19 * 31-16 Rack ID (encoded class, group, number - 16-bit unsigned int)
20 * 15-8 Brick type (8-bit ascii character)
21 * 7-0 Bay (brick position in rack (0-63) - 8-bit unsigned int)
22 *
23 */
24
25/*
26 * Macros for getting the brick type
27 */
28#define MODULE_BTYPE_MASK 0xff00
29#define MODULE_BTYPE_SHFT 8
30#define MODULE_GET_BTYPE(_m) (((_m) & MODULE_BTYPE_MASK) >> MODULE_BTYPE_SHFT)
31#define MODULE_BT_TO_CHAR(_b) ((char)(_b))
32#define MODULE_GET_BTCHAR(_m) (MODULE_BT_TO_CHAR(MODULE_GET_BTYPE(_m)))
33
34/*
35 * Macros for getting the rack ID.
36 */
37#define MODULE_RACK_MASK 0xffff0000
38#define MODULE_RACK_SHFT 16
39#define MODULE_GET_RACK(_m) (((_m) & MODULE_RACK_MASK) >> MODULE_RACK_SHFT)
40
41/*
42 * Macros for getting the brick position
43 */
44#define MODULE_BPOS_MASK 0x00ff
45#define MODULE_BPOS_SHFT 0
46#define MODULE_GET_BPOS(_m) (((_m) & MODULE_BPOS_MASK) >> MODULE_BPOS_SHFT)
47
48/*
49 * Macros for encoding and decoding rack IDs
50 * A rack number consists of three parts:
51 * class (0==CPU/mixed, 1==I/O), group, number
52 *
53 * Rack number is stored just as it is displayed on the screen:
54 * a 3-decimal-digit number.
55 */
56#define RACK_CLASS_DVDR 100
57#define RACK_GROUP_DVDR 10
58#define RACK_NUM_DVDR 1
59
60#define RACK_CREATE_RACKID(_c, _g, _n) ((_c) * RACK_CLASS_DVDR + \
61 (_g) * RACK_GROUP_DVDR + (_n) * RACK_NUM_DVDR)
62
63#define RACK_GET_CLASS(_r) ((_r) / RACK_CLASS_DVDR)
64#define RACK_GET_GROUP(_r) (((_r) - RACK_GET_CLASS(_r) * \
65 RACK_CLASS_DVDR) / RACK_GROUP_DVDR)
66#define RACK_GET_NUM(_r) (((_r) - RACK_GET_CLASS(_r) * \
67 RACK_CLASS_DVDR - RACK_GET_GROUP(_r) * \
68 RACK_GROUP_DVDR) / RACK_NUM_DVDR)
69
70/*
71 * Macros for encoding and decoding rack IDs
72 * A rack number consists of three parts:
73 * class 1 bit, 0==CPU/mixed, 1==I/O
74 * group 2 bits for CPU/mixed, 3 bits for I/O
75 * number 3 bits for CPU/mixed, 2 bits for I/O (1 based)
76 */
77#define RACK_GROUP_BITS(_r) (RACK_GET_CLASS(_r) ? 3 : 2)
78#define RACK_NUM_BITS(_r) (RACK_GET_CLASS(_r) ? 2 : 3)
79
80#define RACK_CLASS_MASK(_r) 0x20
81#define RACK_CLASS_SHFT(_r) 5
82#define RACK_ADD_CLASS(_r, _c) \
83 ((_r) |= (_c) << RACK_CLASS_SHFT(_r) & RACK_CLASS_MASK(_r))
84
85#define RACK_GROUP_SHFT(_r) RACK_NUM_BITS(_r)
86#define RACK_GROUP_MASK(_r) \
87 ( (((unsigned)1<<RACK_GROUP_BITS(_r)) - 1) << RACK_GROUP_SHFT(_r) )
88#define RACK_ADD_GROUP(_r, _g) \
89 ((_r) |= (_g) << RACK_GROUP_SHFT(_r) & RACK_GROUP_MASK(_r))
90
91#define RACK_NUM_SHFT(_r) 0
92#define RACK_NUM_MASK(_r) \
93 ( (((unsigned)1<<RACK_NUM_BITS(_r)) - 1) << RACK_NUM_SHFT(_r) )
94#define RACK_ADD_NUM(_r, _n) \
95 ((_r) |= ((_n) - 1) << RACK_NUM_SHFT(_r) & RACK_NUM_MASK(_r))
96
97
98/*
99 * Brick type definitions
100 */
101#define MAX_BRICK_TYPES 256 /* brick type is stored as uchar */
102
103extern char brick_types[];
104
105#define MODULE_CBRICK 0
106#define MODULE_RBRICK 1
107#define MODULE_IBRICK 2
108#define MODULE_KBRICK 3
109#define MODULE_XBRICK 4
110#define MODULE_DBRICK 5
111#define MODULE_PBRICK 6
112#define MODULE_NBRICK 7
113#define MODULE_PEBRICK 8
114#define MODULE_PXBRICK 9
115#define MODULE_IXBRICK 10
116#define MODULE_CGBRICK 11
117#define MODULE_OPUSBRICK 12
118#define MODULE_SABRICK 13 /* TIO BringUp Brick */
119#define MODULE_IABRICK 14
120#define MODULE_PABRICK 15
121#define MODULE_GABRICK 16
122#define MODULE_OPUS_TIO 17 /* OPUS TIO Riser */
123
124extern char brick_types[];
125extern void format_module_id(char *, moduleid_t, int);
126
127#endif /* _ASM_IA64_SN_MODULE_H */
diff --git a/include/asm-ia64/sn/mspec.h b/include/asm-ia64/sn/mspec.h
deleted file mode 100644
index c1d3c50c3223..000000000000
--- a/include/asm-ia64/sn/mspec.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (c) 2001-2008 Silicon Graphics, Inc. All rights reserved.
8 */
9
10#ifndef _ASM_IA64_SN_MSPEC_H
11#define _ASM_IA64_SN_MSPEC_H
12
13#define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */
14
15#define FETCHOP_LOAD 0
16#define FETCHOP_INCREMENT 8
17#define FETCHOP_DECREMENT 16
18#define FETCHOP_CLEAR 24
19
20#define FETCHOP_STORE 0
21#define FETCHOP_AND 24
22#define FETCHOP_OR 32
23
24#define FETCHOP_CLEAR_CACHE 56
25
26#define FETCHOP_LOAD_OP(addr, op) ( \
27 *(volatile long *)((char*) (addr) + (op)))
28
29#define FETCHOP_STORE_OP(addr, op, x) ( \
30 *(volatile long *)((char*) (addr) + (op)) = (long) (x))
31
32#ifdef __KERNEL__
33
34/*
35 * Each Atomic Memory Operation (amo, formerly known as fetchop)
36 * variable is 64 bytes long. The first 8 bytes are used. The
37 * remaining 56 bytes are unaddressable due to the operation taking
38 * that portion of the address.
39 *
40 * NOTE: The amo structure _MUST_ be placed in either the first or second
41 * half of the cache line. The cache line _MUST NOT_ be used for anything
42 * other than additional amo entries. This is because there are two
43 * addresses which reference the same physical cache line. One will
44 * be a cached entry with the memory type bits all set. This address
45 * may be loaded into processor cache. The amo will be referenced
46 * uncached via the memory special memory type. If any portion of the
47 * cached cache-line is modified, when that line is flushed, it will
48 * overwrite the uncached value in physical memory and lead to
49 * inconsistency.
50 */
51struct amo {
52 u64 variable;
53 u64 unused[7];
54};
55
56
57#endif /* __KERNEL__ */
58
59#endif /* _ASM_IA64_SN_MSPEC_H */
diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h
deleted file mode 100644
index ee118b901de4..000000000000
--- a/include/asm-ia64/sn/nodepda.h
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_NODEPDA_H
9#define _ASM_IA64_SN_NODEPDA_H
10
11
12#include <asm/irq.h>
13#include <asm/sn/arch.h>
14#include <asm/sn/intr.h>
15#include <asm/sn/bte.h>
16
17/*
18 * NUMA Node-Specific Data structures are defined in this file.
19 * In particular, this is the location of the node PDA.
20 * A pointer to the right node PDA is saved in each CPU PDA.
21 */
22
23/*
24 * Node-specific data structure.
25 *
26 * One of these structures is allocated on each node of a NUMA system.
27 *
28 * This structure provides a convenient way of keeping together
29 * all per-node data structures.
30 */
31struct phys_cpuid {
32 short nasid;
33 char subnode;
34 char slice;
35};
36
37struct nodepda_s {
38 void *pdinfo; /* Platform-dependent per-node info */
39
40 /*
41 * The BTEs on this node are shared by the local cpus
42 */
43 struct bteinfo_s bte_if[MAX_BTES_PER_NODE]; /* Virtual Interface */
44 struct timer_list bte_recovery_timer;
45 spinlock_t bte_recovery_lock;
46
47 /*
48 * Array of pointers to the nodepdas for each node.
49 */
50 struct nodepda_s *pernode_pdaindr[MAX_COMPACT_NODES];
51
52 /*
53 * Array of physical cpu identifiers. Indexed by cpuid.
54 */
55 struct phys_cpuid phys_cpuid[NR_CPUS];
56 spinlock_t ptc_lock ____cacheline_aligned_in_smp;
57};
58
59typedef struct nodepda_s nodepda_t;
60
61/*
62 * Access Functions for node PDA.
63 * Since there is one nodepda for each node, we need a convenient mechanism
64 * to access these nodepdas without cluttering code with #ifdefs.
65 * The next set of definitions provides this.
66 * Routines are expected to use
67 *
68 * sn_nodepda - to access node PDA for the node on which code is running
69 * NODEPDA(cnodeid) - to access node PDA for cnodeid
70 */
71
72DECLARE_PER_CPU(struct nodepda_s *, __sn_nodepda);
73#define sn_nodepda (__get_cpu_var(__sn_nodepda))
74#define NODEPDA(cnodeid) (sn_nodepda->pernode_pdaindr[cnodeid])
75
76/*
77 * Check if given a compact node id the corresponding node has all the
78 * cpus disabled.
79 */
80#define is_headless_node(cnodeid) (nr_cpus_node(cnodeid) == 0)
81
82#endif /* _ASM_IA64_SN_NODEPDA_H */
diff --git a/include/asm-ia64/sn/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h
deleted file mode 100644
index da205b7cdaac..000000000000
--- a/include/asm-ia64/sn/pcibr_provider.h
+++ /dev/null
@@ -1,150 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992-1997,2000-2006 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
9#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
10
11#include <asm/sn/intr.h>
12#include <asm/sn/pcibus_provider_defs.h>
13
14/* Workarounds */
15#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
16
17#define BUSTYPE_MASK 0x1
18
19/* Macros given a pcibus structure */
20#define IS_PCIX(ps) ((ps)->pbi_bridge_mode & BUSTYPE_MASK)
21#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
22 asic == PCIIO_ASIC_TYPE_TIOCP)
23#define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
24#define IS_TIOCP_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_TIOCP)
25
26
27/*
28 * The different PCI Bridge types supported on the SGI Altix platforms
29 */
30#define PCIBR_BRIDGETYPE_UNKNOWN -1
31#define PCIBR_BRIDGETYPE_PIC 2
32#define PCIBR_BRIDGETYPE_TIOCP 3
33
34/*
35 * Bridge 64bit Direct Map Attributes
36 */
37#define PCI64_ATTR_PREF (1ull << 59)
38#define PCI64_ATTR_PREC (1ull << 58)
39#define PCI64_ATTR_VIRTUAL (1ull << 57)
40#define PCI64_ATTR_BAR (1ull << 56)
41#define PCI64_ATTR_SWAP (1ull << 55)
42#define PCI64_ATTR_VIRTUAL1 (1ull << 54)
43
44#define PCI32_LOCAL_BASE 0
45#define PCI32_MAPPED_BASE 0x40000000
46#define PCI32_DIRECT_BASE 0x80000000
47
48#define IS_PCI32_MAPPED(x) ((u64)(x) < PCI32_DIRECT_BASE && \
49 (u64)(x) >= PCI32_MAPPED_BASE)
50#define IS_PCI32_DIRECT(x) ((u64)(x) >= PCI32_MAPPED_BASE)
51
52
53/*
54 * Bridge PMU Address Transaltion Entry Attibutes
55 */
56#define PCI32_ATE_V (0x1 << 0)
57#define PCI32_ATE_CO (0x1 << 1) /* PIC ASIC ONLY */
58#define PCI32_ATE_PIO (0x1 << 1) /* TIOCP ASIC ONLY */
59#define PCI32_ATE_MSI (0x1 << 2)
60#define PCI32_ATE_PREF (0x1 << 3)
61#define PCI32_ATE_BAR (0x1 << 4)
62#define PCI32_ATE_ADDR_SHFT 12
63
64#define MINIMAL_ATES_REQUIRED(addr, size) \
65 (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
66
67#define MINIMAL_ATE_FLAG(addr, size) \
68 (MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0)
69
70/* bit 29 of the pci address is the SWAP bit */
71#define ATE_SWAPSHIFT 29
72#define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT))
73#define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT))
74
75/*
76 * I/O page size
77 */
78#if PAGE_SIZE < 16384
79#define IOPFNSHIFT 12 /* 4K per mapped page */
80#else
81#define IOPFNSHIFT 14 /* 16K per mapped page */
82#endif
83
84#define IOPGSIZE (1 << IOPFNSHIFT)
85#define IOPG(x) ((x) >> IOPFNSHIFT)
86#define IOPGOFF(x) ((x) & (IOPGSIZE-1))
87
88#define PCIBR_DEV_SWAP_DIR (1ull << 19)
89#define PCIBR_CTRL_PAGE_SIZE (0x1 << 21)
90
91/*
92 * PMU resources.
93 */
94struct ate_resource{
95 u64 *ate;
96 u64 num_ate;
97 u64 lowest_free_index;
98};
99
100struct pcibus_info {
101 struct pcibus_bussoft pbi_buscommon; /* common header */
102 u32 pbi_moduleid;
103 short pbi_bridge_type;
104 short pbi_bridge_mode;
105
106 struct ate_resource pbi_int_ate_resource;
107 u64 pbi_int_ate_size;
108
109 u64 pbi_dir_xbase;
110 char pbi_hub_xid;
111
112 u64 pbi_devreg[8];
113
114 u32 pbi_valid_devices;
115 u32 pbi_enabled_devices;
116
117 spinlock_t pbi_lock;
118};
119
120extern int pcibr_init_provider(void);
121extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *);
122extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t, int type);
123extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t, int type);
124extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
125
126/*
127 * prototypes for the bridge asic register access routines in pcibr_reg.c
128 */
129extern void pcireg_control_bit_clr(struct pcibus_info *, u64);
130extern void pcireg_control_bit_set(struct pcibus_info *, u64);
131extern u64 pcireg_tflush_get(struct pcibus_info *);
132extern u64 pcireg_intr_status_get(struct pcibus_info *);
133extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, u64);
134extern void pcireg_intr_enable_bit_set(struct pcibus_info *, u64);
135extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64);
136extern void pcireg_force_intr_set(struct pcibus_info *, int);
137extern u64 pcireg_wrb_flush_get(struct pcibus_info *, int);
138extern void pcireg_int_ate_set(struct pcibus_info *, int, u64);
139extern u64 __iomem * pcireg_int_ate_addr(struct pcibus_info *, int);
140extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
141extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
142extern int pcibr_ate_alloc(struct pcibus_info *, int);
143extern void pcibr_ate_free(struct pcibus_info *, int);
144extern void ate_write(struct pcibus_info *, int, int, u64);
145extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
146 void *resp, char **ssdt);
147extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
148 int action, void *resp);
149extern u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus);
150#endif
diff --git a/include/asm-ia64/sn/pcibus_provider_defs.h b/include/asm-ia64/sn/pcibus_provider_defs.h
deleted file mode 100644
index 8f7c83d0f6d3..000000000000
--- a/include/asm-ia64/sn/pcibus_provider_defs.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
9#define _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
10
11/*
12 * SN pci asic types. Do not ever renumber these or reuse values. The
13 * values must agree with what prom thinks they are.
14 */
15
16#define PCIIO_ASIC_TYPE_UNKNOWN 0
17#define PCIIO_ASIC_TYPE_PPB 1
18#define PCIIO_ASIC_TYPE_PIC 2
19#define PCIIO_ASIC_TYPE_TIOCP 3
20#define PCIIO_ASIC_TYPE_TIOCA 4
21#define PCIIO_ASIC_TYPE_TIOCE 5
22
23#define PCIIO_ASIC_MAX_TYPES 6
24
25/*
26 * Common pciio bus provider data. There should be one of these as the
27 * first field in any pciio based provider soft structure (e.g. pcibr_soft
28 * tioca_soft, etc).
29 */
30
31struct pcibus_bussoft {
32 u32 bs_asic_type; /* chipset type */
33 u32 bs_xid; /* xwidget id */
34 u32 bs_persist_busnum; /* Persistent Bus Number */
35 u32 bs_persist_segment; /* Segment Number */
36 u64 bs_legacy_io; /* legacy io pio addr */
37 u64 bs_legacy_mem; /* legacy mem pio addr */
38 u64 bs_base; /* widget base */
39 struct xwidget_info *bs_xwidget_info;
40};
41
42struct pci_controller;
43/*
44 * SN pci bus indirection
45 */
46
47struct sn_pcibus_provider {
48 dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t, int flags);
49 dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t, int flags);
50 void (*dma_unmap)(struct pci_dev *, dma_addr_t, int);
51 void * (*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *);
52 void (*force_interrupt)(struct sn_irq_info *);
53 void (*target_interrupt)(struct sn_irq_info *);
54};
55
56/*
57 * Flags used by the map interfaces
58 * bits 3:0 specifies format of passed in address
59 * bit 4 specifies that address is to be used for MSI
60 */
61
62#define SN_DMA_ADDRTYPE(x) ((x) & 0xf)
63#define SN_DMA_ADDR_PHYS 1 /* address is an xio address. */
64#define SN_DMA_ADDR_XIO 2 /* address is phys memory */
65#define SN_DMA_MSI 0x10 /* Bus address is to be used for MSI */
66
67extern struct sn_pcibus_provider *sn_pci_provider[];
68#endif /* _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H */
diff --git a/include/asm-ia64/sn/pcidev.h b/include/asm-ia64/sn/pcidev.h
deleted file mode 100644
index 1c2382cea807..000000000000
--- a/include/asm-ia64/sn/pcidev.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PCIDEV_H
9#define _ASM_IA64_SN_PCI_PCIDEV_H
10
11#include <linux/pci.h>
12
13/*
14 * In ia64, pci_dev->sysdata must be a *pci_controller. To provide access to
15 * the pcidev_info structs for all devices under a controller, we keep a
16 * list of pcidev_info under pci_controller->platform_data.
17 */
18struct sn_platform_data {
19 void *provider_soft;
20 struct list_head pcidev_info;
21};
22
23#define SN_PLATFORM_DATA(busdev) \
24 ((struct sn_platform_data *)(PCI_CONTROLLER(busdev)->platform_data))
25
26#define SN_PCIDEV_INFO(dev) sn_pcidev_info_get(dev)
27
28/*
29 * Given a pci_bus, return the sn pcibus_bussoft struct. Note that
30 * this only works for root busses, not for busses represented by PPB's.
31 */
32
33#define SN_PCIBUS_BUSSOFT(pci_bus) \
34 ((struct pcibus_bussoft *)(SN_PLATFORM_DATA(pci_bus)->provider_soft))
35
36#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \
37 ((struct pcibus_info *)(SN_PLATFORM_DATA(pci_bus)->provider_soft))
38/*
39 * Given a struct pci_dev, return the sn pcibus_bussoft struct. Note
40 * that this is not equivalent to SN_PCIBUS_BUSSOFT(pci_dev->bus) due
41 * due to possible PPB's in the path.
42 */
43
44#define SN_PCIDEV_BUSSOFT(pci_dev) \
45 (SN_PCIDEV_INFO(pci_dev)->pdi_host_pcidev_info->pdi_pcibus_info)
46
47#define SN_PCIDEV_BUSPROVIDER(pci_dev) \
48 (SN_PCIDEV_INFO(pci_dev)->pdi_provider)
49
50#define PCIIO_BUS_NONE 255 /* bus 255 reserved */
51#define PCIIO_SLOT_NONE 255
52#define PCIIO_FUNC_NONE 255
53#define PCIIO_VENDOR_ID_NONE (-1)
54
55struct pcidev_info {
56 u64 pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
57 u64 pdi_slot_host_handle; /* Bus and devfn Host pci_dev */
58
59 struct pcibus_bussoft *pdi_pcibus_info; /* Kernel common bus soft */
60 struct pcidev_info *pdi_host_pcidev_info; /* Kernel Host pci_dev */
61 struct pci_dev *pdi_linux_pcidev; /* Kernel pci_dev */
62
63 struct sn_irq_info *pdi_sn_irq_info;
64 struct sn_pcibus_provider *pdi_provider; /* sn pci ops */
65 struct pci_dev *host_pci_dev; /* host bus link */
66 struct list_head pdi_list; /* List of pcidev_info */
67};
68
69extern void sn_irq_fixup(struct pci_dev *pci_dev,
70 struct sn_irq_info *sn_irq_info);
71extern void sn_irq_unfixup(struct pci_dev *pci_dev);
72extern struct pcidev_info * sn_pcidev_info_get(struct pci_dev *);
73extern void sn_bus_fixup(struct pci_bus *);
74extern void sn_acpi_bus_fixup(struct pci_bus *);
75extern void sn_common_bus_fixup(struct pci_bus *, struct pcibus_bussoft *);
76extern void sn_bus_store_sysdata(struct pci_dev *dev);
77extern void sn_bus_free_sysdata(void);
78extern void sn_generate_path(struct pci_bus *pci_bus, char *address);
79extern void sn_io_slot_fixup(struct pci_dev *);
80extern void sn_acpi_slot_fixup(struct pci_dev *);
81extern void sn_pci_fixup_slot(struct pci_dev *dev, struct pcidev_info *,
82 struct sn_irq_info *);
83extern void sn_pci_unfixup_slot(struct pci_dev *dev);
84extern void sn_irq_lh_init(void);
85#endif /* _ASM_IA64_SN_PCI_PCIDEV_H */
diff --git a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h
deleted file mode 100644
index 1c5108d44d8b..000000000000
--- a/include/asm-ia64/sn/pda.h
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PDA_H
9#define _ASM_IA64_SN_PDA_H
10
11#include <linux/cache.h>
12#include <asm/percpu.h>
13#include <asm/system.h>
14
15
16/*
17 * CPU-specific data structure.
18 *
19 * One of these structures is allocated for each cpu of a NUMA system.
20 *
21 * This structure provides a convenient way of keeping together
22 * all SN per-cpu data structures.
23 */
24
25typedef struct pda_s {
26
27 /*
28 * Support for SN LEDs
29 */
30 volatile short *led_address;
31 u8 led_state;
32 u8 hb_state; /* supports blinking heartbeat leds */
33 unsigned int hb_count;
34
35 unsigned int idle_flag;
36
37 volatile unsigned long *bedrock_rev_id;
38 volatile unsigned long *pio_write_status_addr;
39 unsigned long pio_write_status_val;
40 volatile unsigned long *pio_shub_war_cam_addr;
41
42 unsigned long sn_in_service_ivecs[4];
43 int sn_lb_int_war_ticks;
44 int sn_last_irq;
45 int sn_first_irq;
46} pda_t;
47
48
49#define CACHE_ALIGN(x) (((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1))
50
51/*
52 * PDA
53 * Per-cpu private data area for each cpu. The PDA is located immediately after
54 * the IA64 cpu_data area. A full page is allocated for the cp_data area for each
55 * cpu but only a small amout of the page is actually used. We put the SNIA PDA
56 * in the same page as the cpu_data area. Note that there is a check in the setup
57 * code to verify that we don't overflow the page.
58 *
59 * Seems like we should should cache-line align the pda so that any changes in the
60 * size of the cpu_data area don't change cache layout. Should we align to 32, 64, 128
61 * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later.
62 */
63DECLARE_PER_CPU(struct pda_s, pda_percpu);
64
65#define pda (&__ia64_per_cpu_var(pda_percpu))
66
67#define pdacpu(cpu) (&per_cpu(pda_percpu, cpu))
68
69#endif /* _ASM_IA64_SN_PDA_H */
diff --git a/include/asm-ia64/sn/pic.h b/include/asm-ia64/sn/pic.h
deleted file mode 100644
index 5f9da5fd6e56..000000000000
--- a/include/asm-ia64/sn/pic.h
+++ /dev/null
@@ -1,261 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PIC_H
9#define _ASM_IA64_SN_PCI_PIC_H
10
11/*
12 * PIC AS DEVICE ZERO
13 * ------------------
14 *
15 * PIC handles PCI/X busses. PCI/X requires that the 'bridge' (i.e. PIC)
16 * be designated as 'device 0'. That is a departure from earlier SGI
17 * PCI bridges. Because of that we use config space 1 to access the
18 * config space of the first actual PCI device on the bus.
19 * Here's what the PIC manual says:
20 *
21 * The current PCI-X bus specification now defines that the parent
22 * hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC
23 * reduced the total number of devices from 8 to 4 and removed the
24 * device registers and windows, now only supporting devices 0,1,2, and
25 * 3. PIC did leave all 8 configuration space windows. The reason was
26 * there was nothing to gain by removing them. Here in lies the problem.
27 * The device numbering we do using 0 through 3 is unrelated to the device
28 * numbering which PCI-X requires in configuration space. In the past we
29 * correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
30 * PCI-X requires we start a 1, not 0 and currently the PX brick
31 * does associate our:
32 *
33 * device 0 with configuration space window 1,
34 * device 1 with configuration space window 2,
35 * device 2 with configuration space window 3,
36 * device 3 with configuration space window 4.
37 *
38 * The net effect is that all config space access are off-by-one with
39 * relation to other per-slot accesses on the PIC.
40 * Here is a table that shows some of that:
41 *
42 * Internal Slot#
43 * |
44 * | 0 1 2 3
45 * ----------|---------------------------------------
46 * config | 0x21000 0x22000 0x23000 0x24000
47 * |
48 * even rrb | 0[0] n/a 1[0] n/a [] == implied even/odd
49 * |
50 * odd rrb | n/a 0[1] n/a 1[1]
51 * |
52 * int dev | 00 01 10 11
53 * |
54 * ext slot# | 1 2 3 4
55 * ----------|---------------------------------------
56 */
57
58#define PIC_ATE_TARGETID_SHFT 8
59#define PIC_HOST_INTR_ADDR 0x0000FFFFFFFFFFFFUL
60#define PIC_PCI64_ATTR_TARG_SHFT 60
61
62
63/*****************************************************************************
64 *********************** PIC MMR structure mapping ***************************
65 *****************************************************************************/
66
67/* NOTE: PIC WAR. PV#854697. PIC does not allow writes just to [31:0]
68 * of a 64-bit register. When writing PIC registers, always write the
69 * entire 64 bits.
70 */
71
72struct pic {
73
74 /* 0x000000-0x00FFFF -- Local Registers */
75
76 /* 0x000000-0x000057 -- Standard Widget Configuration */
77 u64 p_wid_id; /* 0x000000 */
78 u64 p_wid_stat; /* 0x000008 */
79 u64 p_wid_err_upper; /* 0x000010 */
80 u64 p_wid_err_lower; /* 0x000018 */
81 #define p_wid_err p_wid_err_lower
82 u64 p_wid_control; /* 0x000020 */
83 u64 p_wid_req_timeout; /* 0x000028 */
84 u64 p_wid_int_upper; /* 0x000030 */
85 u64 p_wid_int_lower; /* 0x000038 */
86 #define p_wid_int p_wid_int_lower
87 u64 p_wid_err_cmdword; /* 0x000040 */
88 u64 p_wid_llp; /* 0x000048 */
89 u64 p_wid_tflush; /* 0x000050 */
90
91 /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
92 u64 p_wid_aux_err; /* 0x000058 */
93 u64 p_wid_resp_upper; /* 0x000060 */
94 u64 p_wid_resp_lower; /* 0x000068 */
95 #define p_wid_resp p_wid_resp_lower
96 u64 p_wid_tst_pin_ctrl; /* 0x000070 */
97 u64 p_wid_addr_lkerr; /* 0x000078 */
98
99 /* 0x000080-0x00008F -- PMU & MAP */
100 u64 p_dir_map; /* 0x000080 */
101 u64 _pad_000088; /* 0x000088 */
102
103 /* 0x000090-0x00009F -- SSRAM */
104 u64 p_map_fault; /* 0x000090 */
105 u64 _pad_000098; /* 0x000098 */
106
107 /* 0x0000A0-0x0000AF -- Arbitration */
108 u64 p_arb; /* 0x0000A0 */
109 u64 _pad_0000A8; /* 0x0000A8 */
110
111 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
112 u64 p_ate_parity_err; /* 0x0000B0 */
113 u64 _pad_0000B8; /* 0x0000B8 */
114
115 /* 0x0000C0-0x0000FF -- PCI/GIO */
116 u64 p_bus_timeout; /* 0x0000C0 */
117 u64 p_pci_cfg; /* 0x0000C8 */
118 u64 p_pci_err_upper; /* 0x0000D0 */
119 u64 p_pci_err_lower; /* 0x0000D8 */
120 #define p_pci_err p_pci_err_lower
121 u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
122
123 /* 0x000100-0x0001FF -- Interrupt */
124 u64 p_int_status; /* 0x000100 */
125 u64 p_int_enable; /* 0x000108 */
126 u64 p_int_rst_stat; /* 0x000110 */
127 u64 p_int_mode; /* 0x000118 */
128 u64 p_int_device; /* 0x000120 */
129 u64 p_int_host_err; /* 0x000128 */
130 u64 p_int_addr[8]; /* 0x0001{30,,,68} */
131 u64 p_err_int_view; /* 0x000170 */
132 u64 p_mult_int; /* 0x000178 */
133 u64 p_force_always[8]; /* 0x0001{80,,,B8} */
134 u64 p_force_pin[8]; /* 0x0001{C0,,,F8} */
135
136 /* 0x000200-0x000298 -- Device */
137 u64 p_device[4]; /* 0x0002{00,,,18} */
138 u64 _pad_000220[4]; /* 0x0002{20,,,38} */
139 u64 p_wr_req_buf[4]; /* 0x0002{40,,,58} */
140 u64 _pad_000260[4]; /* 0x0002{60,,,78} */
141 u64 p_rrb_map[2]; /* 0x0002{80,,,88} */
142 #define p_even_resp p_rrb_map[0] /* 0x000280 */
143 #define p_odd_resp p_rrb_map[1] /* 0x000288 */
144 u64 p_resp_status; /* 0x000290 */
145 u64 p_resp_clear; /* 0x000298 */
146
147 u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
148
149 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
150 struct {
151 u64 upper; /* 0x0003{00,,,F0} */
152 u64 lower; /* 0x0003{08,,,F8} */
153 } p_buf_addr_match[16];
154
155 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
156 struct {
157 u64 flush_w_touch; /* 0x000{400,,,5C0} */
158 u64 flush_wo_touch; /* 0x000{408,,,5C8} */
159 u64 inflight; /* 0x000{410,,,5D0} */
160 u64 prefetch; /* 0x000{418,,,5D8} */
161 u64 total_pci_retry; /* 0x000{420,,,5E0} */
162 u64 max_pci_retry; /* 0x000{428,,,5E8} */
163 u64 max_latency; /* 0x000{430,,,5F0} */
164 u64 clear_all; /* 0x000{438,,,5F8} */
165 } p_buf_count[8];
166
167
168 /* 0x000600-0x0009FF -- PCI/X registers */
169 u64 p_pcix_bus_err_addr; /* 0x000600 */
170 u64 p_pcix_bus_err_attr; /* 0x000608 */
171 u64 p_pcix_bus_err_data; /* 0x000610 */
172 u64 p_pcix_pio_split_addr; /* 0x000618 */
173 u64 p_pcix_pio_split_attr; /* 0x000620 */
174 u64 p_pcix_dma_req_err_attr; /* 0x000628 */
175 u64 p_pcix_dma_req_err_addr; /* 0x000630 */
176 u64 p_pcix_timeout; /* 0x000638 */
177
178 u64 _pad_000640[120]; /* 0x000{640,,,9F8} */
179
180 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
181 struct {
182 u64 p_buf_addr; /* 0x000{A00,,,AF0} */
183 u64 p_buf_attr; /* 0X000{A08,,,AF8} */
184 } p_pcix_read_buf_64[16];
185
186 struct {
187 u64 p_buf_addr; /* 0x000{B00,,,BE0} */
188 u64 p_buf_attr; /* 0x000{B08,,,BE8} */
189 u64 p_buf_valid; /* 0x000{B10,,,BF0} */
190 u64 __pad1; /* 0x000{B18,,,BF8} */
191 } p_pcix_write_buf_64[8];
192
193 /* End of Local Registers -- Start of Address Map space */
194
195 char _pad_000c00[0x010000 - 0x000c00];
196
197 /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
198 u64 p_int_ate_ram[1024]; /* 0x010000-0x011fff */
199
200 /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
201 u64 p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */
202
203 char _pad_014000[0x18000 - 0x014000];
204
205 /* 0x18000-0x197F8 -- PIC Write Request Ram */
206 u64 p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
207 u64 p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
208 u64 p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
209
210 char _pad_019800[0x20000 - 0x019800];
211
212 /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
213 union {
214 u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
215 u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
216 u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
217 u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
218 union {
219 u8 c[0x100 / 1];
220 u16 s[0x100 / 2];
221 u32 l[0x100 / 4];
222 u64 d[0x100 / 8];
223 } f[8];
224 } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */
225
226 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
227 union {
228 u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
229 u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
230 u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
231 u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
232 union {
233 u8 c[0x100 / 1];
234 u16 s[0x100 / 2];
235 u32 l[0x100 / 4];
236 u64 d[0x100 / 8];
237 } f[8];
238 } p_type1_cfg; /* 0x028000-0x029000 */
239
240 char _pad_029000[0x030000-0x029000];
241
242 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
243 union {
244 u8 c[8 / 1];
245 u16 s[8 / 2];
246 u32 l[8 / 4];
247 u64 d[8 / 8];
248 } p_pci_iack; /* 0x030000-0x030007 */
249
250 char _pad_030007[0x040000-0x030008];
251
252 /* 0x040000-0x030007 -- PCIX Special Cycle */
253 union {
254 u8 c[8 / 1];
255 u16 s[8 / 2];
256 u32 l[8 / 4];
257 u64 d[8 / 8];
258 } p_pcix_cycle; /* 0x040000-0x040007 */
259};
260
261#endif /* _ASM_IA64_SN_PCI_PIC_H */
diff --git a/include/asm-ia64/sn/rw_mmr.h b/include/asm-ia64/sn/rw_mmr.h
deleted file mode 100644
index 2d78f4c5a45e..000000000000
--- a/include/asm-ia64/sn/rw_mmr.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002-2006 Silicon Graphics, Inc. All Rights Reserved.
7 */
8#ifndef _ASM_IA64_SN_RW_MMR_H
9#define _ASM_IA64_SN_RW_MMR_H
10
11
12/*
13 * This file that access MMRs via uncached physical addresses.
14 * pio_phys_read_mmr - read an MMR
15 * pio_phys_write_mmr - write an MMR
16 * pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
17 * Second MMR will be skipped if address is NULL
18 *
19 * Addresses passed to these routines should be uncached physical addresses
20 * ie., 0x80000....
21 */
22
23
24extern long pio_phys_read_mmr(volatile long *mmr);
25extern void pio_phys_write_mmr(volatile long *mmr, long val);
26extern void pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2);
27
28#endif /* _ASM_IA64_SN_RW_MMR_H */
diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h
deleted file mode 100644
index 7de1d1d4b71a..000000000000
--- a/include/asm-ia64/sn/shub_mmr.h
+++ /dev/null
@@ -1,502 +0,0 @@
1/*
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (c) 2001-2005 Silicon Graphics, Inc. All rights reserved.
8 */
9
10#ifndef _ASM_IA64_SN_SHUB_MMR_H
11#define _ASM_IA64_SN_SHUB_MMR_H
12
13/* ==================================================================== */
14/* Register "SH_IPI_INT" */
15/* SHub Inter-Processor Interrupt Registers */
16/* ==================================================================== */
17#define SH1_IPI_INT __IA64_UL_CONST(0x0000000110000380)
18#define SH2_IPI_INT __IA64_UL_CONST(0x0000000010000380)
19
20/* SH_IPI_INT_TYPE */
21/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
22#define SH_IPI_INT_TYPE_SHFT 0
23#define SH_IPI_INT_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
24
25/* SH_IPI_INT_AGT */
26/* Description: Agent, must be 0 for SHub */
27#define SH_IPI_INT_AGT_SHFT 3
28#define SH_IPI_INT_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
29
30/* SH_IPI_INT_PID */
31/* Description: Processor ID, same setting as on targeted McKinley */
32#define SH_IPI_INT_PID_SHFT 4
33#define SH_IPI_INT_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
34
35/* SH_IPI_INT_BASE */
36/* Description: Optional interrupt vector area, 2MB aligned */
37#define SH_IPI_INT_BASE_SHFT 21
38#define SH_IPI_INT_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
39
40/* SH_IPI_INT_IDX */
41/* Description: Targeted McKinley interrupt vector */
42#define SH_IPI_INT_IDX_SHFT 52
43#define SH_IPI_INT_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
44
45/* SH_IPI_INT_SEND */
46/* Description: Send Interrupt Message to PI, This generates a puls */
47#define SH_IPI_INT_SEND_SHFT 63
48#define SH_IPI_INT_SEND_MASK __IA64_UL_CONST(0x8000000000000000)
49
50/* ==================================================================== */
51/* Register "SH_EVENT_OCCURRED" */
52/* SHub Interrupt Event Occurred */
53/* ==================================================================== */
54#define SH1_EVENT_OCCURRED __IA64_UL_CONST(0x0000000110010000)
55#define SH1_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000110010008)
56#define SH2_EVENT_OCCURRED __IA64_UL_CONST(0x0000000010010000)
57#define SH2_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000010010008)
58
59/* ==================================================================== */
60/* Register "SH_PI_CAM_CONTROL" */
61/* CRB CAM MMR Access Control */
62/* ==================================================================== */
63#define SH1_PI_CAM_CONTROL __IA64_UL_CONST(0x0000000120050300)
64
65/* ==================================================================== */
66/* Register "SH_SHUB_ID" */
67/* SHub ID Number */
68/* ==================================================================== */
69#define SH1_SHUB_ID __IA64_UL_CONST(0x0000000110060580)
70#define SH1_SHUB_ID_REVISION_SHFT 28
71#define SH1_SHUB_ID_REVISION_MASK __IA64_UL_CONST(0x00000000f0000000)
72
73/* ==================================================================== */
74/* Register "SH_RTC" */
75/* Real-time Clock */
76/* ==================================================================== */
77#define SH1_RTC __IA64_UL_CONST(0x00000001101c0000)
78#define SH2_RTC __IA64_UL_CONST(0x00000002101c0000)
79#define SH_RTC_MASK __IA64_UL_CONST(0x007fffffffffffff)
80
81/* ==================================================================== */
82/* Register "SH_PIO_WRITE_STATUS_0|1" */
83/* PIO Write Status for CPU 0 & 1 */
84/* ==================================================================== */
85#define SH1_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000120070200)
86#define SH1_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000120070280)
87#define SH2_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000020070200)
88#define SH2_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000020070280)
89#define SH2_PIO_WRITE_STATUS_2 __IA64_UL_CONST(0x0000000020070300)
90#define SH2_PIO_WRITE_STATUS_3 __IA64_UL_CONST(0x0000000020070380)
91
92/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */
93/* Description: Deadlock response detected */
94#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1
95#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK \
96 __IA64_UL_CONST(0x0000000000000002)
97
98/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */
99/* Description: Count of currently pending PIO writes */
100#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56
101#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK \
102 __IA64_UL_CONST(0x3f00000000000000)
103
104/* ==================================================================== */
105/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */
106/* ==================================================================== */
107#define SH1_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000120070208)
108#define SH2_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000020070208)
109
110/* ==================================================================== */
111/* Register "SH_EVENT_OCCURRED" */
112/* SHub Interrupt Event Occurred */
113/* ==================================================================== */
114/* SH_EVENT_OCCURRED_UART_INT */
115/* Description: Pending Junk Bus UART Interrupt */
116#define SH_EVENT_OCCURRED_UART_INT_SHFT 20
117#define SH_EVENT_OCCURRED_UART_INT_MASK __IA64_UL_CONST(0x0000000000100000)
118
119/* SH_EVENT_OCCURRED_IPI_INT */
120/* Description: Pending IPI Interrupt */
121#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28
122#define SH_EVENT_OCCURRED_IPI_INT_MASK __IA64_UL_CONST(0x0000000010000000)
123
124/* SH_EVENT_OCCURRED_II_INT0 */
125/* Description: Pending II 0 Interrupt */
126#define SH_EVENT_OCCURRED_II_INT0_SHFT 29
127#define SH_EVENT_OCCURRED_II_INT0_MASK __IA64_UL_CONST(0x0000000020000000)
128
129/* SH_EVENT_OCCURRED_II_INT1 */
130/* Description: Pending II 1 Interrupt */
131#define SH_EVENT_OCCURRED_II_INT1_SHFT 30
132#define SH_EVENT_OCCURRED_II_INT1_MASK __IA64_UL_CONST(0x0000000040000000)
133
134/* SH2_EVENT_OCCURRED_EXTIO_INT2 */
135/* Description: Pending SHUB 2 EXT IO INT2 */
136#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33
137#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK __IA64_UL_CONST(0x0000000200000000)
138
139/* SH2_EVENT_OCCURRED_EXTIO_INT3 */
140/* Description: Pending SHUB 2 EXT IO INT3 */
141#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34
142#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK __IA64_UL_CONST(0x0000000400000000)
143
144#define SH_ALL_INT_MASK \
145 (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
146 SH_EVENT_OCCURRED_II_INT0_MASK | SH_EVENT_OCCURRED_II_INT1_MASK | \
147 SH_EVENT_OCCURRED_II_INT1_MASK | SH2_EVENT_OCCURRED_EXTIO_INT2_MASK | \
148 SH2_EVENT_OCCURRED_EXTIO_INT3_MASK)
149
150
151/* ==================================================================== */
152/* LEDS */
153/* ==================================================================== */
154#define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL
155#define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL
156#define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL
157#define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL
158
159#define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL
160#define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL
161#define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL
162#define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL
163
164/* ==================================================================== */
165/* Register "SH1_PTC_0" */
166/* Puge Translation Cache Message Configuration Information */
167/* ==================================================================== */
168#define SH1_PTC_0 __IA64_UL_CONST(0x00000001101a0000)
169
170/* SH1_PTC_0_A */
171/* Description: Type */
172#define SH1_PTC_0_A_SHFT 0
173
174/* SH1_PTC_0_PS */
175/* Description: Page Size */
176#define SH1_PTC_0_PS_SHFT 2
177
178/* SH1_PTC_0_RID */
179/* Description: Region ID */
180#define SH1_PTC_0_RID_SHFT 8
181
182/* SH1_PTC_0_START */
183/* Description: Start */
184#define SH1_PTC_0_START_SHFT 63
185
186/* ==================================================================== */
187/* Register "SH1_PTC_1" */
188/* Puge Translation Cache Message Configuration Information */
189/* ==================================================================== */
190#define SH1_PTC_1 __IA64_UL_CONST(0x00000001101a0080)
191
192/* SH1_PTC_1_START */
193/* Description: PTC_1 Start */
194#define SH1_PTC_1_START_SHFT 63
195
196/* ==================================================================== */
197/* Register "SH2_PTC" */
198/* Puge Translation Cache Message Configuration Information */
199/* ==================================================================== */
200#define SH2_PTC __IA64_UL_CONST(0x0000000170000000)
201
202/* SH2_PTC_A */
203/* Description: Type */
204#define SH2_PTC_A_SHFT 0
205
206/* SH2_PTC_PS */
207/* Description: Page Size */
208#define SH2_PTC_PS_SHFT 2
209
210/* SH2_PTC_RID */
211/* Description: Region ID */
212#define SH2_PTC_RID_SHFT 4
213
214/* SH2_PTC_START */
215/* Description: Start */
216#define SH2_PTC_START_SHFT 63
217
218/* SH2_PTC_ADDR_RID */
219/* Description: Region ID */
220#define SH2_PTC_ADDR_SHFT 4
221#define SH2_PTC_ADDR_MASK __IA64_UL_CONST(0x1ffffffffffff000)
222
223/* ==================================================================== */
224/* Register "SH_RTC1_INT_CONFIG" */
225/* SHub RTC 1 Interrupt Config Registers */
226/* ==================================================================== */
227
228#define SH1_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000110001480)
229#define SH2_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000010001480)
230#define SH_RTC1_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
231#define SH_RTC1_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
232
233/* SH_RTC1_INT_CONFIG_TYPE */
234/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
235#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0
236#define SH_RTC1_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
237
238/* SH_RTC1_INT_CONFIG_AGT */
239/* Description: Agent, must be 0 for SHub */
240#define SH_RTC1_INT_CONFIG_AGT_SHFT 3
241#define SH_RTC1_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
242
243/* SH_RTC1_INT_CONFIG_PID */
244/* Description: Processor ID, same setting as on targeted McKinley */
245#define SH_RTC1_INT_CONFIG_PID_SHFT 4
246#define SH_RTC1_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
247
248/* SH_RTC1_INT_CONFIG_BASE */
249/* Description: Optional interrupt vector area, 2MB aligned */
250#define SH_RTC1_INT_CONFIG_BASE_SHFT 21
251#define SH_RTC1_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
252
253/* SH_RTC1_INT_CONFIG_IDX */
254/* Description: Targeted McKinley interrupt vector */
255#define SH_RTC1_INT_CONFIG_IDX_SHFT 52
256#define SH_RTC1_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
257
258/* ==================================================================== */
259/* Register "SH_RTC1_INT_ENABLE" */
260/* SHub RTC 1 Interrupt Enable Registers */
261/* ==================================================================== */
262
263#define SH1_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000110001500)
264#define SH2_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000010001500)
265#define SH_RTC1_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
266#define SH_RTC1_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
267
268/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */
269/* Description: Enable RTC 1 Interrupt */
270#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0
271#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK \
272 __IA64_UL_CONST(0x0000000000000001)
273
274/* ==================================================================== */
275/* Register "SH_RTC2_INT_CONFIG" */
276/* SHub RTC 2 Interrupt Config Registers */
277/* ==================================================================== */
278
279#define SH1_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000110001580)
280#define SH2_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000010001580)
281#define SH_RTC2_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
282#define SH_RTC2_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
283
284/* SH_RTC2_INT_CONFIG_TYPE */
285/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
286#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0
287#define SH_RTC2_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
288
289/* SH_RTC2_INT_CONFIG_AGT */
290/* Description: Agent, must be 0 for SHub */
291#define SH_RTC2_INT_CONFIG_AGT_SHFT 3
292#define SH_RTC2_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
293
294/* SH_RTC2_INT_CONFIG_PID */
295/* Description: Processor ID, same setting as on targeted McKinley */
296#define SH_RTC2_INT_CONFIG_PID_SHFT 4
297#define SH_RTC2_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
298
299/* SH_RTC2_INT_CONFIG_BASE */
300/* Description: Optional interrupt vector area, 2MB aligned */
301#define SH_RTC2_INT_CONFIG_BASE_SHFT 21
302#define SH_RTC2_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
303
304/* SH_RTC2_INT_CONFIG_IDX */
305/* Description: Targeted McKinley interrupt vector */
306#define SH_RTC2_INT_CONFIG_IDX_SHFT 52
307#define SH_RTC2_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
308
309/* ==================================================================== */
310/* Register "SH_RTC2_INT_ENABLE" */
311/* SHub RTC 2 Interrupt Enable Registers */
312/* ==================================================================== */
313
314#define SH1_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000110001600)
315#define SH2_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000010001600)
316#define SH_RTC2_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
317#define SH_RTC2_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
318
319/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */
320/* Description: Enable RTC 2 Interrupt */
321#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0
322#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK \
323 __IA64_UL_CONST(0x0000000000000001)
324
325/* ==================================================================== */
326/* Register "SH_RTC3_INT_CONFIG" */
327/* SHub RTC 3 Interrupt Config Registers */
328/* ==================================================================== */
329
330#define SH1_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000110001680)
331#define SH2_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000010001680)
332#define SH_RTC3_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
333#define SH_RTC3_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
334
335/* SH_RTC3_INT_CONFIG_TYPE */
336/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
337#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0
338#define SH_RTC3_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
339
340/* SH_RTC3_INT_CONFIG_AGT */
341/* Description: Agent, must be 0 for SHub */
342#define SH_RTC3_INT_CONFIG_AGT_SHFT 3
343#define SH_RTC3_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
344
345/* SH_RTC3_INT_CONFIG_PID */
346/* Description: Processor ID, same setting as on targeted McKinley */
347#define SH_RTC3_INT_CONFIG_PID_SHFT 4
348#define SH_RTC3_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
349
350/* SH_RTC3_INT_CONFIG_BASE */
351/* Description: Optional interrupt vector area, 2MB aligned */
352#define SH_RTC3_INT_CONFIG_BASE_SHFT 21
353#define SH_RTC3_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
354
355/* SH_RTC3_INT_CONFIG_IDX */
356/* Description: Targeted McKinley interrupt vector */
357#define SH_RTC3_INT_CONFIG_IDX_SHFT 52
358#define SH_RTC3_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
359
360/* ==================================================================== */
361/* Register "SH_RTC3_INT_ENABLE" */
362/* SHub RTC 3 Interrupt Enable Registers */
363/* ==================================================================== */
364
365#define SH1_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000110001700)
366#define SH2_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000010001700)
367#define SH_RTC3_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
368#define SH_RTC3_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
369
370/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */
371/* Description: Enable RTC 3 Interrupt */
372#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0
373#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK \
374 __IA64_UL_CONST(0x0000000000000001)
375
376/* SH_EVENT_OCCURRED_RTC1_INT */
377/* Description: Pending RTC 1 Interrupt */
378#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24
379#define SH_EVENT_OCCURRED_RTC1_INT_MASK __IA64_UL_CONST(0x0000000001000000)
380
381/* SH_EVENT_OCCURRED_RTC2_INT */
382/* Description: Pending RTC 2 Interrupt */
383#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25
384#define SH_EVENT_OCCURRED_RTC2_INT_MASK __IA64_UL_CONST(0x0000000002000000)
385
386/* SH_EVENT_OCCURRED_RTC3_INT */
387/* Description: Pending RTC 3 Interrupt */
388#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26
389#define SH_EVENT_OCCURRED_RTC3_INT_MASK __IA64_UL_CONST(0x0000000004000000)
390
391/* ==================================================================== */
392/* Register "SH_IPI_ACCESS" */
393/* CPU interrupt Access Permission Bits */
394/* ==================================================================== */
395
396#define SH1_IPI_ACCESS __IA64_UL_CONST(0x0000000110060480)
397#define SH2_IPI_ACCESS0 __IA64_UL_CONST(0x0000000010060c00)
398#define SH2_IPI_ACCESS1 __IA64_UL_CONST(0x0000000010060c80)
399#define SH2_IPI_ACCESS2 __IA64_UL_CONST(0x0000000010060d00)
400#define SH2_IPI_ACCESS3 __IA64_UL_CONST(0x0000000010060d80)
401
402/* ==================================================================== */
403/* Register "SH_INT_CMPB" */
404/* RTC Compare Value for Processor B */
405/* ==================================================================== */
406
407#define SH1_INT_CMPB __IA64_UL_CONST(0x00000001101b0080)
408#define SH2_INT_CMPB __IA64_UL_CONST(0x00000000101b0080)
409#define SH_INT_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
410#define SH_INT_CMPB_INIT __IA64_UL_CONST(0x0000000000000000)
411
412/* SH_INT_CMPB_REAL_TIME_CMPB */
413/* Description: Real Time Clock Compare */
414#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
415#define SH_INT_CMPB_REAL_TIME_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
416
417/* ==================================================================== */
418/* Register "SH_INT_CMPC" */
419/* RTC Compare Value for Processor C */
420/* ==================================================================== */
421
422#define SH1_INT_CMPC __IA64_UL_CONST(0x00000001101b0100)
423#define SH2_INT_CMPC __IA64_UL_CONST(0x00000000101b0100)
424#define SH_INT_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
425#define SH_INT_CMPC_INIT __IA64_UL_CONST(0x0000000000000000)
426
427/* SH_INT_CMPC_REAL_TIME_CMPC */
428/* Description: Real Time Clock Compare */
429#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
430#define SH_INT_CMPC_REAL_TIME_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
431
432/* ==================================================================== */
433/* Register "SH_INT_CMPD" */
434/* RTC Compare Value for Processor D */
435/* ==================================================================== */
436
437#define SH1_INT_CMPD __IA64_UL_CONST(0x00000001101b0180)
438#define SH2_INT_CMPD __IA64_UL_CONST(0x00000000101b0180)
439#define SH_INT_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
440#define SH_INT_CMPD_INIT __IA64_UL_CONST(0x0000000000000000)
441
442/* SH_INT_CMPD_REAL_TIME_CMPD */
443/* Description: Real Time Clock Compare */
444#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
445#define SH_INT_CMPD_REAL_TIME_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
446
447/* ==================================================================== */
448/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */
449/* privilege vector for acc=0 */
450/* ==================================================================== */
451#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100030300)
452
453/* ==================================================================== */
454/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */
455/* privilege vector for acc=0 */
456/* ==================================================================== */
457#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100050300)
458
459/* ==================================================================== */
460/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
461/* and SHUB2 that it makes sense to define a geberic name for the MMR. */
462/* It is acceptible to use (for example) SH_IPI_INT to reference the */
463/* the IPI MMR. The value of SH_IPI_INT is determined at runtime based */
464/* on the type of the SHUB. Do not use these #defines in performance */
465/* critical code or loops - there is a small performance penalty. */
466/* ==================================================================== */
467#define shubmmr(a,b) (is_shub2() ? a##2_##b : a##1_##b)
468
469#define SH_REAL_JUNK_BUS_LED0 shubmmr(SH, REAL_JUNK_BUS_LED0)
470#define SH_IPI_INT shubmmr(SH, IPI_INT)
471#define SH_EVENT_OCCURRED shubmmr(SH, EVENT_OCCURRED)
472#define SH_EVENT_OCCURRED_ALIAS shubmmr(SH, EVENT_OCCURRED_ALIAS)
473#define SH_RTC shubmmr(SH, RTC)
474#define SH_RTC1_INT_CONFIG shubmmr(SH, RTC1_INT_CONFIG)
475#define SH_RTC1_INT_ENABLE shubmmr(SH, RTC1_INT_ENABLE)
476#define SH_RTC2_INT_CONFIG shubmmr(SH, RTC2_INT_CONFIG)
477#define SH_RTC2_INT_ENABLE shubmmr(SH, RTC2_INT_ENABLE)
478#define SH_RTC3_INT_CONFIG shubmmr(SH, RTC3_INT_CONFIG)
479#define SH_RTC3_INT_ENABLE shubmmr(SH, RTC3_INT_ENABLE)
480#define SH_INT_CMPB shubmmr(SH, INT_CMPB)
481#define SH_INT_CMPC shubmmr(SH, INT_CMPC)
482#define SH_INT_CMPD shubmmr(SH, INT_CMPD)
483
484/* ========================================================================== */
485/* Register "SH2_BT_ENG_CSR_0" */
486/* Engine 0 Control and Status Register */
487/* ========================================================================== */
488
489#define SH2_BT_ENG_CSR_0 __IA64_UL_CONST(0x0000000030040000)
490#define SH2_BT_ENG_SRC_ADDR_0 __IA64_UL_CONST(0x0000000030040080)
491#define SH2_BT_ENG_DEST_ADDR_0 __IA64_UL_CONST(0x0000000030040100)
492#define SH2_BT_ENG_NOTIF_ADDR_0 __IA64_UL_CONST(0x0000000030040180)
493
494/* ========================================================================== */
495/* BTE interfaces 1-3 */
496/* ========================================================================== */
497
498#define SH2_BT_ENG_CSR_1 __IA64_UL_CONST(0x0000000030050000)
499#define SH2_BT_ENG_CSR_2 __IA64_UL_CONST(0x0000000030060000)
500#define SH2_BT_ENG_CSR_3 __IA64_UL_CONST(0x0000000030070000)
501
502#endif /* _ASM_IA64_SN_SHUB_MMR_H */
diff --git a/include/asm-ia64/sn/shubio.h b/include/asm-ia64/sn/shubio.h
deleted file mode 100644
index 22a6f18a5313..000000000000
--- a/include/asm-ia64/sn/shubio.h
+++ /dev/null
@@ -1,3358 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_SHUBIO_H
10#define _ASM_IA64_SN_SHUBIO_H
11
12#define HUB_WIDGET_ID_MAX 0xf
13#define IIO_NUM_ITTES 7
14#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
15
16#define IIO_WID 0x00400000 /* Crosstalk Widget Identification */
17 /* This register is also accessible from
18 * Crosstalk at address 0x0. */
19#define IIO_WSTAT 0x00400008 /* Crosstalk Widget Status */
20#define IIO_WCR 0x00400020 /* Crosstalk Widget Control Register */
21#define IIO_ILAPR 0x00400100 /* IO Local Access Protection Register */
22#define IIO_ILAPO 0x00400108 /* IO Local Access Protection Override */
23#define IIO_IOWA 0x00400110 /* IO Outbound Widget Access */
24#define IIO_IIWA 0x00400118 /* IO Inbound Widget Access */
25#define IIO_IIDEM 0x00400120 /* IO Inbound Device Error Mask */
26#define IIO_ILCSR 0x00400128 /* IO LLP Control and Status Register */
27#define IIO_ILLR 0x00400130 /* IO LLP Log Register */
28#define IIO_IIDSR 0x00400138 /* IO Interrupt Destination */
29
30#define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */
31#define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */
32
33#define IIO_ISCR0 0x00400150 /* IO Scratch Register 0 */
34#define IIO_ISCR1 0x00400158 /* IO Scratch Register 1 */
35
36#define IIO_ITTE1 0x00400160 /* IO Translation Table Entry 1 */
37#define IIO_ITTE2 0x00400168 /* IO Translation Table Entry 2 */
38#define IIO_ITTE3 0x00400170 /* IO Translation Table Entry 3 */
39#define IIO_ITTE4 0x00400178 /* IO Translation Table Entry 4 */
40#define IIO_ITTE5 0x00400180 /* IO Translation Table Entry 5 */
41#define IIO_ITTE6 0x00400188 /* IO Translation Table Entry 6 */
42#define IIO_ITTE7 0x00400190 /* IO Translation Table Entry 7 */
43
44#define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */
45#define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */
46#define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */
47#define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */
48#define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */
49#define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */
50#define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */
51#define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */
52#define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */
53
54#define IIO_IXCC 0x004001E0 /* IO Crosstalk Credit Count Timeout */
55#define IIO_IMEM 0x004001E8 /* IO Miscellaneous Error Mask */
56#define IIO_IXTT 0x004001F0 /* IO Crosstalk Timeout Threshold */
57#define IIO_IECLR 0x004001F8 /* IO Error Clear Register */
58#define IIO_IBCR 0x00400200 /* IO BTE Control Register */
59
60#define IIO_IXSM 0x00400208 /* IO Crosstalk Spurious Message */
61#define IIO_IXSS 0x00400210 /* IO Crosstalk Spurious Sideband */
62
63#define IIO_ILCT 0x00400218 /* IO LLP Channel Test */
64
65#define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */
66#define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */
67
68#define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */
69#define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */
70
71#define IIO_IWI 0x00400240 /* IO Wrapper Interrupt Register */
72#define IIO_IWEL 0x00400248 /* IO Wrapper Error Log Register */
73#define IIO_IWC 0x00400250 /* IO Wrapper Control Register */
74#define IIO_IWS 0x00400258 /* IO Wrapper Status Register */
75#define IIO_IWEIM 0x00400260 /* IO Wrapper Error Interrupt Masking Register */
76
77#define IIO_IPCA 0x00400300 /* IO PRB Counter Adjust */
78
79#define IIO_IPRTE0_A 0x00400308 /* IO PIO Read Address Table Entry 0, Part A */
80#define IIO_IPRTE1_A 0x00400310 /* IO PIO Read Address Table Entry 1, Part A */
81#define IIO_IPRTE2_A 0x00400318 /* IO PIO Read Address Table Entry 2, Part A */
82#define IIO_IPRTE3_A 0x00400320 /* IO PIO Read Address Table Entry 3, Part A */
83#define IIO_IPRTE4_A 0x00400328 /* IO PIO Read Address Table Entry 4, Part A */
84#define IIO_IPRTE5_A 0x00400330 /* IO PIO Read Address Table Entry 5, Part A */
85#define IIO_IPRTE6_A 0x00400338 /* IO PIO Read Address Table Entry 6, Part A */
86#define IIO_IPRTE7_A 0x00400340 /* IO PIO Read Address Table Entry 7, Part A */
87
88#define IIO_IPRTE0_B 0x00400348 /* IO PIO Read Address Table Entry 0, Part B */
89#define IIO_IPRTE1_B 0x00400350 /* IO PIO Read Address Table Entry 1, Part B */
90#define IIO_IPRTE2_B 0x00400358 /* IO PIO Read Address Table Entry 2, Part B */
91#define IIO_IPRTE3_B 0x00400360 /* IO PIO Read Address Table Entry 3, Part B */
92#define IIO_IPRTE4_B 0x00400368 /* IO PIO Read Address Table Entry 4, Part B */
93#define IIO_IPRTE5_B 0x00400370 /* IO PIO Read Address Table Entry 5, Part B */
94#define IIO_IPRTE6_B 0x00400378 /* IO PIO Read Address Table Entry 6, Part B */
95#define IIO_IPRTE7_B 0x00400380 /* IO PIO Read Address Table Entry 7, Part B */
96
97#define IIO_IPDR 0x00400388 /* IO PIO Deallocation Register */
98#define IIO_ICDR 0x00400390 /* IO CRB Entry Deallocation Register */
99#define IIO_IFDR 0x00400398 /* IO IOQ FIFO Depth Register */
100#define IIO_IIAP 0x004003A0 /* IO IIQ Arbitration Parameters */
101#define IIO_ICMR 0x004003A8 /* IO CRB Management Register */
102#define IIO_ICCR 0x004003B0 /* IO CRB Control Register */
103#define IIO_ICTO 0x004003B8 /* IO CRB Timeout */
104#define IIO_ICTP 0x004003C0 /* IO CRB Timeout Prescalar */
105
106#define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */
107#define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */
108#define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */
109#define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */
110#define IIO_ICRB0_E 0x00400420 /* IO CRB Entry 0_E */
111
112#define IIO_ICRB1_A 0x00400430 /* IO CRB Entry 1_A */
113#define IIO_ICRB1_B 0x00400438 /* IO CRB Entry 1_B */
114#define IIO_ICRB1_C 0x00400440 /* IO CRB Entry 1_C */
115#define IIO_ICRB1_D 0x00400448 /* IO CRB Entry 1_D */
116#define IIO_ICRB1_E 0x00400450 /* IO CRB Entry 1_E */
117
118#define IIO_ICRB2_A 0x00400460 /* IO CRB Entry 2_A */
119#define IIO_ICRB2_B 0x00400468 /* IO CRB Entry 2_B */
120#define IIO_ICRB2_C 0x00400470 /* IO CRB Entry 2_C */
121#define IIO_ICRB2_D 0x00400478 /* IO CRB Entry 2_D */
122#define IIO_ICRB2_E 0x00400480 /* IO CRB Entry 2_E */
123
124#define IIO_ICRB3_A 0x00400490 /* IO CRB Entry 3_A */
125#define IIO_ICRB3_B 0x00400498 /* IO CRB Entry 3_B */
126#define IIO_ICRB3_C 0x004004a0 /* IO CRB Entry 3_C */
127#define IIO_ICRB3_D 0x004004a8 /* IO CRB Entry 3_D */
128#define IIO_ICRB3_E 0x004004b0 /* IO CRB Entry 3_E */
129
130#define IIO_ICRB4_A 0x004004c0 /* IO CRB Entry 4_A */
131#define IIO_ICRB4_B 0x004004c8 /* IO CRB Entry 4_B */
132#define IIO_ICRB4_C 0x004004d0 /* IO CRB Entry 4_C */
133#define IIO_ICRB4_D 0x004004d8 /* IO CRB Entry 4_D */
134#define IIO_ICRB4_E 0x004004e0 /* IO CRB Entry 4_E */
135
136#define IIO_ICRB5_A 0x004004f0 /* IO CRB Entry 5_A */
137#define IIO_ICRB5_B 0x004004f8 /* IO CRB Entry 5_B */
138#define IIO_ICRB5_C 0x00400500 /* IO CRB Entry 5_C */
139#define IIO_ICRB5_D 0x00400508 /* IO CRB Entry 5_D */
140#define IIO_ICRB5_E 0x00400510 /* IO CRB Entry 5_E */
141
142#define IIO_ICRB6_A 0x00400520 /* IO CRB Entry 6_A */
143#define IIO_ICRB6_B 0x00400528 /* IO CRB Entry 6_B */
144#define IIO_ICRB6_C 0x00400530 /* IO CRB Entry 6_C */
145#define IIO_ICRB6_D 0x00400538 /* IO CRB Entry 6_D */
146#define IIO_ICRB6_E 0x00400540 /* IO CRB Entry 6_E */
147
148#define IIO_ICRB7_A 0x00400550 /* IO CRB Entry 7_A */
149#define IIO_ICRB7_B 0x00400558 /* IO CRB Entry 7_B */
150#define IIO_ICRB7_C 0x00400560 /* IO CRB Entry 7_C */
151#define IIO_ICRB7_D 0x00400568 /* IO CRB Entry 7_D */
152#define IIO_ICRB7_E 0x00400570 /* IO CRB Entry 7_E */
153
154#define IIO_ICRB8_A 0x00400580 /* IO CRB Entry 8_A */
155#define IIO_ICRB8_B 0x00400588 /* IO CRB Entry 8_B */
156#define IIO_ICRB8_C 0x00400590 /* IO CRB Entry 8_C */
157#define IIO_ICRB8_D 0x00400598 /* IO CRB Entry 8_D */
158#define IIO_ICRB8_E 0x004005a0 /* IO CRB Entry 8_E */
159
160#define IIO_ICRB9_A 0x004005b0 /* IO CRB Entry 9_A */
161#define IIO_ICRB9_B 0x004005b8 /* IO CRB Entry 9_B */
162#define IIO_ICRB9_C 0x004005c0 /* IO CRB Entry 9_C */
163#define IIO_ICRB9_D 0x004005c8 /* IO CRB Entry 9_D */
164#define IIO_ICRB9_E 0x004005d0 /* IO CRB Entry 9_E */
165
166#define IIO_ICRBA_A 0x004005e0 /* IO CRB Entry A_A */
167#define IIO_ICRBA_B 0x004005e8 /* IO CRB Entry A_B */
168#define IIO_ICRBA_C 0x004005f0 /* IO CRB Entry A_C */
169#define IIO_ICRBA_D 0x004005f8 /* IO CRB Entry A_D */
170#define IIO_ICRBA_E 0x00400600 /* IO CRB Entry A_E */
171
172#define IIO_ICRBB_A 0x00400610 /* IO CRB Entry B_A */
173#define IIO_ICRBB_B 0x00400618 /* IO CRB Entry B_B */
174#define IIO_ICRBB_C 0x00400620 /* IO CRB Entry B_C */
175#define IIO_ICRBB_D 0x00400628 /* IO CRB Entry B_D */
176#define IIO_ICRBB_E 0x00400630 /* IO CRB Entry B_E */
177
178#define IIO_ICRBC_A 0x00400640 /* IO CRB Entry C_A */
179#define IIO_ICRBC_B 0x00400648 /* IO CRB Entry C_B */
180#define IIO_ICRBC_C 0x00400650 /* IO CRB Entry C_C */
181#define IIO_ICRBC_D 0x00400658 /* IO CRB Entry C_D */
182#define IIO_ICRBC_E 0x00400660 /* IO CRB Entry C_E */
183
184#define IIO_ICRBD_A 0x00400670 /* IO CRB Entry D_A */
185#define IIO_ICRBD_B 0x00400678 /* IO CRB Entry D_B */
186#define IIO_ICRBD_C 0x00400680 /* IO CRB Entry D_C */
187#define IIO_ICRBD_D 0x00400688 /* IO CRB Entry D_D */
188#define IIO_ICRBD_E 0x00400690 /* IO CRB Entry D_E */
189
190#define IIO_ICRBE_A 0x004006a0 /* IO CRB Entry E_A */
191#define IIO_ICRBE_B 0x004006a8 /* IO CRB Entry E_B */
192#define IIO_ICRBE_C 0x004006b0 /* IO CRB Entry E_C */
193#define IIO_ICRBE_D 0x004006b8 /* IO CRB Entry E_D */
194#define IIO_ICRBE_E 0x004006c0 /* IO CRB Entry E_E */
195
196#define IIO_ICSML 0x00400700 /* IO CRB Spurious Message Low */
197#define IIO_ICSMM 0x00400708 /* IO CRB Spurious Message Middle */
198#define IIO_ICSMH 0x00400710 /* IO CRB Spurious Message High */
199
200#define IIO_IDBSS 0x00400718 /* IO Debug Submenu Select */
201
202#define IIO_IBLS0 0x00410000 /* IO BTE Length Status 0 */
203#define IIO_IBSA0 0x00410008 /* IO BTE Source Address 0 */
204#define IIO_IBDA0 0x00410010 /* IO BTE Destination Address 0 */
205#define IIO_IBCT0 0x00410018 /* IO BTE Control Terminate 0 */
206#define IIO_IBNA0 0x00410020 /* IO BTE Notification Address 0 */
207#define IIO_IBIA0 0x00410028 /* IO BTE Interrupt Address 0 */
208#define IIO_IBLS1 0x00420000 /* IO BTE Length Status 1 */
209#define IIO_IBSA1 0x00420008 /* IO BTE Source Address 1 */
210#define IIO_IBDA1 0x00420010 /* IO BTE Destination Address 1 */
211#define IIO_IBCT1 0x00420018 /* IO BTE Control Terminate 1 */
212#define IIO_IBNA1 0x00420020 /* IO BTE Notification Address 1 */
213#define IIO_IBIA1 0x00420028 /* IO BTE Interrupt Address 1 */
214
215#define IIO_IPCR 0x00430000 /* IO Performance Control */
216#define IIO_IPPR 0x00430008 /* IO Performance Profiling */
217
218/************************************************************************
219 * *
220 * Description: This register echoes some information from the *
221 * LB_REV_ID register. It is available through Crosstalk as described *
222 * above. The REV_NUM and MFG_NUM fields receive their values from *
223 * the REVISION and MANUFACTURER fields in the LB_REV_ID register. *
224 * The PART_NUM field's value is the Crosstalk device ID number that *
225 * Steve Miller assigned to the SHub chip. *
226 * *
227 ************************************************************************/
228
229typedef union ii_wid_u {
230 u64 ii_wid_regval;
231 struct {
232 u64 w_rsvd_1:1;
233 u64 w_mfg_num:11;
234 u64 w_part_num:16;
235 u64 w_rev_num:4;
236 u64 w_rsvd:32;
237 } ii_wid_fld_s;
238} ii_wid_u_t;
239
240/************************************************************************
241 * *
242 * The fields in this register are set upon detection of an error *
243 * and cleared by various mechanisms, as explained in the *
244 * description. *
245 * *
246 ************************************************************************/
247
248typedef union ii_wstat_u {
249 u64 ii_wstat_regval;
250 struct {
251 u64 w_pending:4;
252 u64 w_xt_crd_to:1;
253 u64 w_xt_tail_to:1;
254 u64 w_rsvd_3:3;
255 u64 w_tx_mx_rty:1;
256 u64 w_rsvd_2:6;
257 u64 w_llp_tx_cnt:8;
258 u64 w_rsvd_1:8;
259 u64 w_crazy:1;
260 u64 w_rsvd:31;
261 } ii_wstat_fld_s;
262} ii_wstat_u_t;
263
264/************************************************************************
265 * *
266 * Description: This is a read-write enabled register. It controls *
267 * various aspects of the Crosstalk flow control. *
268 * *
269 ************************************************************************/
270
271typedef union ii_wcr_u {
272 u64 ii_wcr_regval;
273 struct {
274 u64 w_wid:4;
275 u64 w_tag:1;
276 u64 w_rsvd_1:8;
277 u64 w_dst_crd:3;
278 u64 w_f_bad_pkt:1;
279 u64 w_dir_con:1;
280 u64 w_e_thresh:5;
281 u64 w_rsvd:41;
282 } ii_wcr_fld_s;
283} ii_wcr_u_t;
284
285/************************************************************************
286 * *
287 * Description: This register's value is a bit vector that guards *
288 * access to local registers within the II as well as to external *
289 * Crosstalk widgets. Each bit in the register corresponds to a *
290 * particular region in the system; a region consists of one, two or *
291 * four nodes (depending on the value of the REGION_SIZE field in the *
292 * LB_REV_ID register, which is documented in Section 8.3.1.1). The *
293 * protection provided by this register applies to PIO read *
294 * operations as well as PIO write operations. The II will perform a *
295 * PIO read or write request only if the bit for the requestor's *
296 * region is set; otherwise, the II will not perform the requested *
297 * operation and will return an error response. When a PIO read or *
298 * write request targets an external Crosstalk widget, then not only *
299 * must the bit for the requestor's region be set in the ILAPR, but *
300 * also the target widget's bit in the IOWA register must be set in *
301 * order for the II to perform the requested operation; otherwise, *
302 * the II will return an error response. Hence, the protection *
303 * provided by the IOWA register supplements the protection provided *
304 * by the ILAPR for requests that target external Crosstalk widgets. *
305 * This register itself can be accessed only by the nodes whose *
306 * region ID bits are enabled in this same register. It can also be *
307 * accessed through the IAlias space by the local processors. *
308 * The reset value of this register allows access by all nodes. *
309 * *
310 ************************************************************************/
311
312typedef union ii_ilapr_u {
313 u64 ii_ilapr_regval;
314 struct {
315 u64 i_region:64;
316 } ii_ilapr_fld_s;
317} ii_ilapr_u_t;
318
319/************************************************************************
320 * *
321 * Description: A write to this register of the 64-bit value *
322 * "SGIrules" in ASCII, will cause the bit in the ILAPR register *
323 * corresponding to the region of the requestor to be set (allow *
324 * access). A write of any other value will be ignored. Access *
325 * protection for this register is "SGIrules". *
326 * This register can also be accessed through the IAlias space. *
327 * However, this access will not change the access permissions in the *
328 * ILAPR. *
329 * *
330 ************************************************************************/
331
332typedef union ii_ilapo_u {
333 u64 ii_ilapo_regval;
334 struct {
335 u64 i_io_ovrride:64;
336 } ii_ilapo_fld_s;
337} ii_ilapo_u_t;
338
339/************************************************************************
340 * *
341 * This register qualifies all the PIO and Graphics writes launched *
342 * from the SHUB towards a widget. *
343 * *
344 ************************************************************************/
345
346typedef union ii_iowa_u {
347 u64 ii_iowa_regval;
348 struct {
349 u64 i_w0_oac:1;
350 u64 i_rsvd_1:7;
351 u64 i_wx_oac:8;
352 u64 i_rsvd:48;
353 } ii_iowa_fld_s;
354} ii_iowa_u_t;
355
356/************************************************************************
357 * *
358 * Description: This register qualifies all the requests launched *
359 * from a widget towards the Shub. This register is intended to be *
360 * used by software in case of misbehaving widgets. *
361 * *
362 * *
363 ************************************************************************/
364
365typedef union ii_iiwa_u {
366 u64 ii_iiwa_regval;
367 struct {
368 u64 i_w0_iac:1;
369 u64 i_rsvd_1:7;
370 u64 i_wx_iac:8;
371 u64 i_rsvd:48;
372 } ii_iiwa_fld_s;
373} ii_iiwa_u_t;
374
375/************************************************************************
376 * *
377 * Description: This register qualifies all the operations launched *
378 * from a widget towards the SHub. It allows individual access *
379 * control for up to 8 devices per widget. A device refers to *
380 * individual DMA master hosted by a widget. *
381 * The bits in each field of this register are cleared by the Shub *
382 * upon detection of an error which requires the device to be *
383 * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric *
384 * Crosstalk). Whether or not a device has access rights to this *
385 * Shub is determined by an AND of the device enable bit in the *
386 * appropriate field of this register and the corresponding bit in *
387 * the Wx_IAC field (for the widget which this device belongs to). *
388 * The bits in this field are set by writing a 1 to them. Incoming *
389 * replies from Crosstalk are not subject to this access control *
390 * mechanism. *
391 * *
392 ************************************************************************/
393
394typedef union ii_iidem_u {
395 u64 ii_iidem_regval;
396 struct {
397 u64 i_w8_dxs:8;
398 u64 i_w9_dxs:8;
399 u64 i_wa_dxs:8;
400 u64 i_wb_dxs:8;
401 u64 i_wc_dxs:8;
402 u64 i_wd_dxs:8;
403 u64 i_we_dxs:8;
404 u64 i_wf_dxs:8;
405 } ii_iidem_fld_s;
406} ii_iidem_u_t;
407
408/************************************************************************
409 * *
410 * This register contains the various programmable fields necessary *
411 * for controlling and observing the LLP signals. *
412 * *
413 ************************************************************************/
414
415typedef union ii_ilcsr_u {
416 u64 ii_ilcsr_regval;
417 struct {
418 u64 i_nullto:6;
419 u64 i_rsvd_4:2;
420 u64 i_wrmrst:1;
421 u64 i_rsvd_3:1;
422 u64 i_llp_en:1;
423 u64 i_bm8:1;
424 u64 i_llp_stat:2;
425 u64 i_remote_power:1;
426 u64 i_rsvd_2:1;
427 u64 i_maxrtry:10;
428 u64 i_d_avail_sel:2;
429 u64 i_rsvd_1:4;
430 u64 i_maxbrst:10;
431 u64 i_rsvd:22;
432
433 } ii_ilcsr_fld_s;
434} ii_ilcsr_u_t;
435
436/************************************************************************
437 * *
438 * This is simply a status registers that monitors the LLP error *
439 * rate. *
440 * *
441 ************************************************************************/
442
443typedef union ii_illr_u {
444 u64 ii_illr_regval;
445 struct {
446 u64 i_sn_cnt:16;
447 u64 i_cb_cnt:16;
448 u64 i_rsvd:32;
449 } ii_illr_fld_s;
450} ii_illr_u_t;
451
452/************************************************************************
453 * *
454 * Description: All II-detected non-BTE error interrupts are *
455 * specified via this register. *
456 * NOTE: The PI interrupt register address is hardcoded in the II. If *
457 * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI *
458 * packet) to address offset 0x0180_0090 within the local register *
459 * address space of PI0 on the node specified by the NODE field. If *
460 * PI_ID==1, then the II sends the interrupt request to address *
461 * offset 0x01A0_0090 within the local register address space of PI1 *
462 * on the node specified by the NODE field. *
463 * *
464 ************************************************************************/
465
466typedef union ii_iidsr_u {
467 u64 ii_iidsr_regval;
468 struct {
469 u64 i_level:8;
470 u64 i_pi_id:1;
471 u64 i_node:11;
472 u64 i_rsvd_3:4;
473 u64 i_enable:1;
474 u64 i_rsvd_2:3;
475 u64 i_int_sent:2;
476 u64 i_rsvd_1:2;
477 u64 i_pi0_forward_int:1;
478 u64 i_pi1_forward_int:1;
479 u64 i_rsvd:30;
480 } ii_iidsr_fld_s;
481} ii_iidsr_u_t;
482
483/************************************************************************
484 * *
485 * There are two instances of this register. This register is used *
486 * for matching up the incoming responses from the graphics widget to *
487 * the processor that initiated the graphics operation. The *
488 * write-responses are converted to graphics credits and returned to *
489 * the processor so that the processor interface can manage the flow *
490 * control. *
491 * *
492 ************************************************************************/
493
494typedef union ii_igfx0_u {
495 u64 ii_igfx0_regval;
496 struct {
497 u64 i_w_num:4;
498 u64 i_pi_id:1;
499 u64 i_n_num:12;
500 u64 i_p_num:1;
501 u64 i_rsvd:46;
502 } ii_igfx0_fld_s;
503} ii_igfx0_u_t;
504
505/************************************************************************
506 * *
507 * There are two instances of this register. This register is used *
508 * for matching up the incoming responses from the graphics widget to *
509 * the processor that initiated the graphics operation. The *
510 * write-responses are converted to graphics credits and returned to *
511 * the processor so that the processor interface can manage the flow *
512 * control. *
513 * *
514 ************************************************************************/
515
516typedef union ii_igfx1_u {
517 u64 ii_igfx1_regval;
518 struct {
519 u64 i_w_num:4;
520 u64 i_pi_id:1;
521 u64 i_n_num:12;
522 u64 i_p_num:1;
523 u64 i_rsvd:46;
524 } ii_igfx1_fld_s;
525} ii_igfx1_u_t;
526
527/************************************************************************
528 * *
529 * There are two instances of this registers. These registers are *
530 * used as scratch registers for software use. *
531 * *
532 ************************************************************************/
533
534typedef union ii_iscr0_u {
535 u64 ii_iscr0_regval;
536 struct {
537 u64 i_scratch:64;
538 } ii_iscr0_fld_s;
539} ii_iscr0_u_t;
540
541/************************************************************************
542 * *
543 * There are two instances of this registers. These registers are *
544 * used as scratch registers for software use. *
545 * *
546 ************************************************************************/
547
548typedef union ii_iscr1_u {
549 u64 ii_iscr1_regval;
550 struct {
551 u64 i_scratch:64;
552 } ii_iscr1_fld_s;
553} ii_iscr1_u_t;
554
555/************************************************************************
556 * *
557 * Description: There are seven instances of translation table entry *
558 * registers. Each register maps a Shub Big Window to a 48-bit *
559 * address on Crosstalk. *
560 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
561 * number) are used to select one of these 7 registers. The Widget *
562 * number field is then derived from the W_NUM field for synthesizing *
563 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
564 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
565 * are padded with zeros. Although the maximum Crosstalk space *
566 * addressable by the SHub is thus the lower 16 GBytes per widget *
567 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
568 * space can be accessed. *
569 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
570 * Window number) are used to select one of these 7 registers. The *
571 * Widget number field is then derived from the W_NUM field for *
572 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
573 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
574 * field is used as Crosstalk[47], and remainder of the Crosstalk *
575 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
576 * Crosstalk space addressable by the Shub is thus the lower *
577 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
578 * of this space can be accessed. *
579 * *
580 ************************************************************************/
581
582typedef union ii_itte1_u {
583 u64 ii_itte1_regval;
584 struct {
585 u64 i_offset:5;
586 u64 i_rsvd_1:3;
587 u64 i_w_num:4;
588 u64 i_iosp:1;
589 u64 i_rsvd:51;
590 } ii_itte1_fld_s;
591} ii_itte1_u_t;
592
593/************************************************************************
594 * *
595 * Description: There are seven instances of translation table entry *
596 * registers. Each register maps a Shub Big Window to a 48-bit *
597 * address on Crosstalk. *
598 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
599 * number) are used to select one of these 7 registers. The Widget *
600 * number field is then derived from the W_NUM field for synthesizing *
601 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
602 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
603 * are padded with zeros. Although the maximum Crosstalk space *
604 * addressable by the Shub is thus the lower 16 GBytes per widget *
605 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
606 * space can be accessed. *
607 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
608 * Window number) are used to select one of these 7 registers. The *
609 * Widget number field is then derived from the W_NUM field for *
610 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
611 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
612 * field is used as Crosstalk[47], and remainder of the Crosstalk *
613 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
614 * Crosstalk space addressable by the Shub is thus the lower *
615 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
616 * of this space can be accessed. *
617 * *
618 ************************************************************************/
619
620typedef union ii_itte2_u {
621 u64 ii_itte2_regval;
622 struct {
623 u64 i_offset:5;
624 u64 i_rsvd_1:3;
625 u64 i_w_num:4;
626 u64 i_iosp:1;
627 u64 i_rsvd:51;
628 } ii_itte2_fld_s;
629} ii_itte2_u_t;
630
631/************************************************************************
632 * *
633 * Description: There are seven instances of translation table entry *
634 * registers. Each register maps a Shub Big Window to a 48-bit *
635 * address on Crosstalk. *
636 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
637 * number) are used to select one of these 7 registers. The Widget *
638 * number field is then derived from the W_NUM field for synthesizing *
639 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
640 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
641 * are padded with zeros. Although the maximum Crosstalk space *
642 * addressable by the Shub is thus the lower 16 GBytes per widget *
643 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
644 * space can be accessed. *
645 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
646 * Window number) are used to select one of these 7 registers. The *
647 * Widget number field is then derived from the W_NUM field for *
648 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
649 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
650 * field is used as Crosstalk[47], and remainder of the Crosstalk *
651 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
652 * Crosstalk space addressable by the SHub is thus the lower *
653 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
654 * of this space can be accessed. *
655 * *
656 ************************************************************************/
657
658typedef union ii_itte3_u {
659 u64 ii_itte3_regval;
660 struct {
661 u64 i_offset:5;
662 u64 i_rsvd_1:3;
663 u64 i_w_num:4;
664 u64 i_iosp:1;
665 u64 i_rsvd:51;
666 } ii_itte3_fld_s;
667} ii_itte3_u_t;
668
669/************************************************************************
670 * *
671 * Description: There are seven instances of translation table entry *
672 * registers. Each register maps a SHub Big Window to a 48-bit *
673 * address on Crosstalk. *
674 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
675 * number) are used to select one of these 7 registers. The Widget *
676 * number field is then derived from the W_NUM field for synthesizing *
677 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
678 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
679 * are padded with zeros. Although the maximum Crosstalk space *
680 * addressable by the SHub is thus the lower 16 GBytes per widget *
681 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
682 * space can be accessed. *
683 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
684 * Window number) are used to select one of these 7 registers. The *
685 * Widget number field is then derived from the W_NUM field for *
686 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
687 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
688 * field is used as Crosstalk[47], and remainder of the Crosstalk *
689 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
690 * Crosstalk space addressable by the SHub is thus the lower *
691 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
692 * of this space can be accessed. *
693 * *
694 ************************************************************************/
695
696typedef union ii_itte4_u {
697 u64 ii_itte4_regval;
698 struct {
699 u64 i_offset:5;
700 u64 i_rsvd_1:3;
701 u64 i_w_num:4;
702 u64 i_iosp:1;
703 u64 i_rsvd:51;
704 } ii_itte4_fld_s;
705} ii_itte4_u_t;
706
707/************************************************************************
708 * *
709 * Description: There are seven instances of translation table entry *
710 * registers. Each register maps a SHub Big Window to a 48-bit *
711 * address on Crosstalk. *
712 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
713 * number) are used to select one of these 7 registers. The Widget *
714 * number field is then derived from the W_NUM field for synthesizing *
715 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
716 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
717 * are padded with zeros. Although the maximum Crosstalk space *
718 * addressable by the Shub is thus the lower 16 GBytes per widget *
719 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
720 * space can be accessed. *
721 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
722 * Window number) are used to select one of these 7 registers. The *
723 * Widget number field is then derived from the W_NUM field for *
724 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
725 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
726 * field is used as Crosstalk[47], and remainder of the Crosstalk *
727 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
728 * Crosstalk space addressable by the Shub is thus the lower *
729 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
730 * of this space can be accessed. *
731 * *
732 ************************************************************************/
733
734typedef union ii_itte5_u {
735 u64 ii_itte5_regval;
736 struct {
737 u64 i_offset:5;
738 u64 i_rsvd_1:3;
739 u64 i_w_num:4;
740 u64 i_iosp:1;
741 u64 i_rsvd:51;
742 } ii_itte5_fld_s;
743} ii_itte5_u_t;
744
745/************************************************************************
746 * *
747 * Description: There are seven instances of translation table entry *
748 * registers. Each register maps a Shub Big Window to a 48-bit *
749 * address on Crosstalk. *
750 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
751 * number) are used to select one of these 7 registers. The Widget *
752 * number field is then derived from the W_NUM field for synthesizing *
753 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
754 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
755 * are padded with zeros. Although the maximum Crosstalk space *
756 * addressable by the Shub is thus the lower 16 GBytes per widget *
757 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
758 * space can be accessed. *
759 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
760 * Window number) are used to select one of these 7 registers. The *
761 * Widget number field is then derived from the W_NUM field for *
762 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
763 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
764 * field is used as Crosstalk[47], and remainder of the Crosstalk *
765 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
766 * Crosstalk space addressable by the Shub is thus the lower *
767 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
768 * of this space can be accessed. *
769 * *
770 ************************************************************************/
771
772typedef union ii_itte6_u {
773 u64 ii_itte6_regval;
774 struct {
775 u64 i_offset:5;
776 u64 i_rsvd_1:3;
777 u64 i_w_num:4;
778 u64 i_iosp:1;
779 u64 i_rsvd:51;
780 } ii_itte6_fld_s;
781} ii_itte6_u_t;
782
783/************************************************************************
784 * *
785 * Description: There are seven instances of translation table entry *
786 * registers. Each register maps a Shub Big Window to a 48-bit *
787 * address on Crosstalk. *
788 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
789 * number) are used to select one of these 7 registers. The Widget *
790 * number field is then derived from the W_NUM field for synthesizing *
791 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
792 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
793 * are padded with zeros. Although the maximum Crosstalk space *
794 * addressable by the Shub is thus the lower 16 GBytes per widget *
795 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
796 * space can be accessed. *
797 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
798 * Window number) are used to select one of these 7 registers. The *
799 * Widget number field is then derived from the W_NUM field for *
800 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
801 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
802 * field is used as Crosstalk[47], and remainder of the Crosstalk *
803 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
804 * Crosstalk space addressable by the SHub is thus the lower *
805 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
806 * of this space can be accessed. *
807 * *
808 ************************************************************************/
809
810typedef union ii_itte7_u {
811 u64 ii_itte7_regval;
812 struct {
813 u64 i_offset:5;
814 u64 i_rsvd_1:3;
815 u64 i_w_num:4;
816 u64 i_iosp:1;
817 u64 i_rsvd:51;
818 } ii_itte7_fld_s;
819} ii_itte7_u_t;
820
821/************************************************************************
822 * *
823 * Description: There are 9 instances of this register, one per *
824 * actual widget in this implementation of SHub and Crossbow. *
825 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
826 * refers to Crossbow's internal space. *
827 * This register contains the state elements per widget that are *
828 * necessary to manage the PIO flow control on Crosstalk and on the *
829 * Router Network. See the PIO Flow Control chapter for a complete *
830 * description of this register *
831 * The SPUR_WR bit requires some explanation. When this register is *
832 * written, the new value of the C field is captured in an internal *
833 * register so the hardware can remember what the programmer wrote *
834 * into the credit counter. The SPUR_WR bit sets whenever the C field *
835 * increments above this stored value, which indicates that there *
836 * have been more responses received than requests sent. The SPUR_WR *
837 * bit cannot be cleared until a value is written to the IPRBx *
838 * register; the write will correct the C field and capture its new *
839 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
840 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
841 * . *
842 * *
843 ************************************************************************/
844
845typedef union ii_iprb0_u {
846 u64 ii_iprb0_regval;
847 struct {
848 u64 i_c:8;
849 u64 i_na:14;
850 u64 i_rsvd_2:2;
851 u64 i_nb:14;
852 u64 i_rsvd_1:2;
853 u64 i_m:2;
854 u64 i_f:1;
855 u64 i_of_cnt:5;
856 u64 i_error:1;
857 u64 i_rd_to:1;
858 u64 i_spur_wr:1;
859 u64 i_spur_rd:1;
860 u64 i_rsvd:11;
861 u64 i_mult_err:1;
862 } ii_iprb0_fld_s;
863} ii_iprb0_u_t;
864
865/************************************************************************
866 * *
867 * Description: There are 9 instances of this register, one per *
868 * actual widget in this implementation of SHub and Crossbow. *
869 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
870 * refers to Crossbow's internal space. *
871 * This register contains the state elements per widget that are *
872 * necessary to manage the PIO flow control on Crosstalk and on the *
873 * Router Network. See the PIO Flow Control chapter for a complete *
874 * description of this register *
875 * The SPUR_WR bit requires some explanation. When this register is *
876 * written, the new value of the C field is captured in an internal *
877 * register so the hardware can remember what the programmer wrote *
878 * into the credit counter. The SPUR_WR bit sets whenever the C field *
879 * increments above this stored value, which indicates that there *
880 * have been more responses received than requests sent. The SPUR_WR *
881 * bit cannot be cleared until a value is written to the IPRBx *
882 * register; the write will correct the C field and capture its new *
883 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
884 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
885 * . *
886 * *
887 ************************************************************************/
888
889typedef union ii_iprb8_u {
890 u64 ii_iprb8_regval;
891 struct {
892 u64 i_c:8;
893 u64 i_na:14;
894 u64 i_rsvd_2:2;
895 u64 i_nb:14;
896 u64 i_rsvd_1:2;
897 u64 i_m:2;
898 u64 i_f:1;
899 u64 i_of_cnt:5;
900 u64 i_error:1;
901 u64 i_rd_to:1;
902 u64 i_spur_wr:1;
903 u64 i_spur_rd:1;
904 u64 i_rsvd:11;
905 u64 i_mult_err:1;
906 } ii_iprb8_fld_s;
907} ii_iprb8_u_t;
908
909/************************************************************************
910 * *
911 * Description: There are 9 instances of this register, one per *
912 * actual widget in this implementation of SHub and Crossbow. *
913 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
914 * refers to Crossbow's internal space. *
915 * This register contains the state elements per widget that are *
916 * necessary to manage the PIO flow control on Crosstalk and on the *
917 * Router Network. See the PIO Flow Control chapter for a complete *
918 * description of this register *
919 * The SPUR_WR bit requires some explanation. When this register is *
920 * written, the new value of the C field is captured in an internal *
921 * register so the hardware can remember what the programmer wrote *
922 * into the credit counter. The SPUR_WR bit sets whenever the C field *
923 * increments above this stored value, which indicates that there *
924 * have been more responses received than requests sent. The SPUR_WR *
925 * bit cannot be cleared until a value is written to the IPRBx *
926 * register; the write will correct the C field and capture its new *
927 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
928 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
929 * . *
930 * *
931 ************************************************************************/
932
933typedef union ii_iprb9_u {
934 u64 ii_iprb9_regval;
935 struct {
936 u64 i_c:8;
937 u64 i_na:14;
938 u64 i_rsvd_2:2;
939 u64 i_nb:14;
940 u64 i_rsvd_1:2;
941 u64 i_m:2;
942 u64 i_f:1;
943 u64 i_of_cnt:5;
944 u64 i_error:1;
945 u64 i_rd_to:1;
946 u64 i_spur_wr:1;
947 u64 i_spur_rd:1;
948 u64 i_rsvd:11;
949 u64 i_mult_err:1;
950 } ii_iprb9_fld_s;
951} ii_iprb9_u_t;
952
953/************************************************************************
954 * *
955 * Description: There are 9 instances of this register, one per *
956 * actual widget in this implementation of SHub and Crossbow. *
957 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
958 * refers to Crossbow's internal space. *
959 * This register contains the state elements per widget that are *
960 * necessary to manage the PIO flow control on Crosstalk and on the *
961 * Router Network. See the PIO Flow Control chapter for a complete *
962 * description of this register *
963 * The SPUR_WR bit requires some explanation. When this register is *
964 * written, the new value of the C field is captured in an internal *
965 * register so the hardware can remember what the programmer wrote *
966 * into the credit counter. The SPUR_WR bit sets whenever the C field *
967 * increments above this stored value, which indicates that there *
968 * have been more responses received than requests sent. The SPUR_WR *
969 * bit cannot be cleared until a value is written to the IPRBx *
970 * register; the write will correct the C field and capture its new *
971 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
972 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
973 * *
974 * *
975 ************************************************************************/
976
977typedef union ii_iprba_u {
978 u64 ii_iprba_regval;
979 struct {
980 u64 i_c:8;
981 u64 i_na:14;
982 u64 i_rsvd_2:2;
983 u64 i_nb:14;
984 u64 i_rsvd_1:2;
985 u64 i_m:2;
986 u64 i_f:1;
987 u64 i_of_cnt:5;
988 u64 i_error:1;
989 u64 i_rd_to:1;
990 u64 i_spur_wr:1;
991 u64 i_spur_rd:1;
992 u64 i_rsvd:11;
993 u64 i_mult_err:1;
994 } ii_iprba_fld_s;
995} ii_iprba_u_t;
996
997/************************************************************************
998 * *
999 * Description: There are 9 instances of this register, one per *
1000 * actual widget in this implementation of SHub and Crossbow. *
1001 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1002 * refers to Crossbow's internal space. *
1003 * This register contains the state elements per widget that are *
1004 * necessary to manage the PIO flow control on Crosstalk and on the *
1005 * Router Network. See the PIO Flow Control chapter for a complete *
1006 * description of this register *
1007 * The SPUR_WR bit requires some explanation. When this register is *
1008 * written, the new value of the C field is captured in an internal *
1009 * register so the hardware can remember what the programmer wrote *
1010 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1011 * increments above this stored value, which indicates that there *
1012 * have been more responses received than requests sent. The SPUR_WR *
1013 * bit cannot be cleared until a value is written to the IPRBx *
1014 * register; the write will correct the C field and capture its new *
1015 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1016 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1017 * . *
1018 * *
1019 ************************************************************************/
1020
1021typedef union ii_iprbb_u {
1022 u64 ii_iprbb_regval;
1023 struct {
1024 u64 i_c:8;
1025 u64 i_na:14;
1026 u64 i_rsvd_2:2;
1027 u64 i_nb:14;
1028 u64 i_rsvd_1:2;
1029 u64 i_m:2;
1030 u64 i_f:1;
1031 u64 i_of_cnt:5;
1032 u64 i_error:1;
1033 u64 i_rd_to:1;
1034 u64 i_spur_wr:1;
1035 u64 i_spur_rd:1;
1036 u64 i_rsvd:11;
1037 u64 i_mult_err:1;
1038 } ii_iprbb_fld_s;
1039} ii_iprbb_u_t;
1040
1041/************************************************************************
1042 * *
1043 * Description: There are 9 instances of this register, one per *
1044 * actual widget in this implementation of SHub and Crossbow. *
1045 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1046 * refers to Crossbow's internal space. *
1047 * This register contains the state elements per widget that are *
1048 * necessary to manage the PIO flow control on Crosstalk and on the *
1049 * Router Network. See the PIO Flow Control chapter for a complete *
1050 * description of this register *
1051 * The SPUR_WR bit requires some explanation. When this register is *
1052 * written, the new value of the C field is captured in an internal *
1053 * register so the hardware can remember what the programmer wrote *
1054 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1055 * increments above this stored value, which indicates that there *
1056 * have been more responses received than requests sent. The SPUR_WR *
1057 * bit cannot be cleared until a value is written to the IPRBx *
1058 * register; the write will correct the C field and capture its new *
1059 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1060 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1061 * . *
1062 * *
1063 ************************************************************************/
1064
1065typedef union ii_iprbc_u {
1066 u64 ii_iprbc_regval;
1067 struct {
1068 u64 i_c:8;
1069 u64 i_na:14;
1070 u64 i_rsvd_2:2;
1071 u64 i_nb:14;
1072 u64 i_rsvd_1:2;
1073 u64 i_m:2;
1074 u64 i_f:1;
1075 u64 i_of_cnt:5;
1076 u64 i_error:1;
1077 u64 i_rd_to:1;
1078 u64 i_spur_wr:1;
1079 u64 i_spur_rd:1;
1080 u64 i_rsvd:11;
1081 u64 i_mult_err:1;
1082 } ii_iprbc_fld_s;
1083} ii_iprbc_u_t;
1084
1085/************************************************************************
1086 * *
1087 * Description: There are 9 instances of this register, one per *
1088 * actual widget in this implementation of SHub and Crossbow. *
1089 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1090 * refers to Crossbow's internal space. *
1091 * This register contains the state elements per widget that are *
1092 * necessary to manage the PIO flow control on Crosstalk and on the *
1093 * Router Network. See the PIO Flow Control chapter for a complete *
1094 * description of this register *
1095 * The SPUR_WR bit requires some explanation. When this register is *
1096 * written, the new value of the C field is captured in an internal *
1097 * register so the hardware can remember what the programmer wrote *
1098 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1099 * increments above this stored value, which indicates that there *
1100 * have been more responses received than requests sent. The SPUR_WR *
1101 * bit cannot be cleared until a value is written to the IPRBx *
1102 * register; the write will correct the C field and capture its new *
1103 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1104 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1105 * . *
1106 * *
1107 ************************************************************************/
1108
1109typedef union ii_iprbd_u {
1110 u64 ii_iprbd_regval;
1111 struct {
1112 u64 i_c:8;
1113 u64 i_na:14;
1114 u64 i_rsvd_2:2;
1115 u64 i_nb:14;
1116 u64 i_rsvd_1:2;
1117 u64 i_m:2;
1118 u64 i_f:1;
1119 u64 i_of_cnt:5;
1120 u64 i_error:1;
1121 u64 i_rd_to:1;
1122 u64 i_spur_wr:1;
1123 u64 i_spur_rd:1;
1124 u64 i_rsvd:11;
1125 u64 i_mult_err:1;
1126 } ii_iprbd_fld_s;
1127} ii_iprbd_u_t;
1128
1129/************************************************************************
1130 * *
1131 * Description: There are 9 instances of this register, one per *
1132 * actual widget in this implementation of SHub and Crossbow. *
1133 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1134 * refers to Crossbow's internal space. *
1135 * This register contains the state elements per widget that are *
1136 * necessary to manage the PIO flow control on Crosstalk and on the *
1137 * Router Network. See the PIO Flow Control chapter for a complete *
1138 * description of this register *
1139 * The SPUR_WR bit requires some explanation. When this register is *
1140 * written, the new value of the C field is captured in an internal *
1141 * register so the hardware can remember what the programmer wrote *
1142 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1143 * increments above this stored value, which indicates that there *
1144 * have been more responses received than requests sent. The SPUR_WR *
1145 * bit cannot be cleared until a value is written to the IPRBx *
1146 * register; the write will correct the C field and capture its new *
1147 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1148 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1149 * . *
1150 * *
1151 ************************************************************************/
1152
1153typedef union ii_iprbe_u {
1154 u64 ii_iprbe_regval;
1155 struct {
1156 u64 i_c:8;
1157 u64 i_na:14;
1158 u64 i_rsvd_2:2;
1159 u64 i_nb:14;
1160 u64 i_rsvd_1:2;
1161 u64 i_m:2;
1162 u64 i_f:1;
1163 u64 i_of_cnt:5;
1164 u64 i_error:1;
1165 u64 i_rd_to:1;
1166 u64 i_spur_wr:1;
1167 u64 i_spur_rd:1;
1168 u64 i_rsvd:11;
1169 u64 i_mult_err:1;
1170 } ii_iprbe_fld_s;
1171} ii_iprbe_u_t;
1172
1173/************************************************************************
1174 * *
1175 * Description: There are 9 instances of this register, one per *
1176 * actual widget in this implementation of Shub and Crossbow. *
1177 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1178 * refers to Crossbow's internal space. *
1179 * This register contains the state elements per widget that are *
1180 * necessary to manage the PIO flow control on Crosstalk and on the *
1181 * Router Network. See the PIO Flow Control chapter for a complete *
1182 * description of this register *
1183 * The SPUR_WR bit requires some explanation. When this register is *
1184 * written, the new value of the C field is captured in an internal *
1185 * register so the hardware can remember what the programmer wrote *
1186 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1187 * increments above this stored value, which indicates that there *
1188 * have been more responses received than requests sent. The SPUR_WR *
1189 * bit cannot be cleared until a value is written to the IPRBx *
1190 * register; the write will correct the C field and capture its new *
1191 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1192 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1193 * . *
1194 * *
1195 ************************************************************************/
1196
1197typedef union ii_iprbf_u {
1198 u64 ii_iprbf_regval;
1199 struct {
1200 u64 i_c:8;
1201 u64 i_na:14;
1202 u64 i_rsvd_2:2;
1203 u64 i_nb:14;
1204 u64 i_rsvd_1:2;
1205 u64 i_m:2;
1206 u64 i_f:1;
1207 u64 i_of_cnt:5;
1208 u64 i_error:1;
1209 u64 i_rd_to:1;
1210 u64 i_spur_wr:1;
1211 u64 i_spur_rd:1;
1212 u64 i_rsvd:11;
1213 u64 i_mult_err:1;
1214 } ii_iprbe_fld_s;
1215} ii_iprbf_u_t;
1216
1217/************************************************************************
1218 * *
1219 * This register specifies the timeout value to use for monitoring *
1220 * Crosstalk credits which are used outbound to Crosstalk. An *
1221 * internal counter called the Crosstalk Credit Timeout Counter *
1222 * increments every 128 II clocks. The counter starts counting *
1223 * anytime the credit count drops below a threshold, and resets to *
1224 * zero (stops counting) anytime the credit count is at or above the *
1225 * threshold. The threshold is 1 credit in direct connect mode and 2 *
1226 * in Crossbow connect mode. When the internal Crosstalk Credit *
1227 * Timeout Counter reaches the value programmed in this register, a *
1228 * Crosstalk Credit Timeout has occurred. The internal counter is not *
1229 * readable from software, and stops counting at its maximum value, *
1230 * so it cannot cause more than one interrupt. *
1231 * *
1232 ************************************************************************/
1233
1234typedef union ii_ixcc_u {
1235 u64 ii_ixcc_regval;
1236 struct {
1237 u64 i_time_out:26;
1238 u64 i_rsvd:38;
1239 } ii_ixcc_fld_s;
1240} ii_ixcc_u_t;
1241
1242/************************************************************************
1243 * *
1244 * Description: This register qualifies all the PIO and DMA *
1245 * operations launched from widget 0 towards the SHub. In *
1246 * addition, it also qualifies accesses by the BTE streams. *
1247 * The bits in each field of this register are cleared by the SHub *
1248 * upon detection of an error which requires widget 0 or the BTE *
1249 * streams to be terminated. Whether or not widget x has access *
1250 * rights to this SHub is determined by an AND of the device *
1251 * enable bit in the appropriate field of this register and bit 0 in *
1252 * the Wx_IAC field. The bits in this field are set by writing a 1 to *
1253 * them. Incoming replies from Crosstalk are not subject to this *
1254 * access control mechanism. *
1255 * *
1256 ************************************************************************/
1257
1258typedef union ii_imem_u {
1259 u64 ii_imem_regval;
1260 struct {
1261 u64 i_w0_esd:1;
1262 u64 i_rsvd_3:3;
1263 u64 i_b0_esd:1;
1264 u64 i_rsvd_2:3;
1265 u64 i_b1_esd:1;
1266 u64 i_rsvd_1:3;
1267 u64 i_clr_precise:1;
1268 u64 i_rsvd:51;
1269 } ii_imem_fld_s;
1270} ii_imem_u_t;
1271
1272/************************************************************************
1273 * *
1274 * Description: This register specifies the timeout value to use for *
1275 * monitoring Crosstalk tail flits coming into the Shub in the *
1276 * TAIL_TO field. An internal counter associated with this register *
1277 * is incremented every 128 II internal clocks (7 bits). The counter *
1278 * starts counting anytime a header micropacket is received and stops *
1279 * counting (and resets to zero) any time a micropacket with a Tail *
1280 * bit is received. Once the counter reaches the threshold value *
1281 * programmed in this register, it generates an interrupt to the *
1282 * processor that is programmed into the IIDSR. The counter saturates *
1283 * (does not roll over) at its maximum value, so it cannot cause *
1284 * another interrupt until after it is cleared. *
1285 * The register also contains the Read Response Timeout values. The *
1286 * Prescalar is 23 bits, and counts II clocks. An internal counter *
1287 * increments on every II clock and when it reaches the value in the *
1288 * Prescalar field, all IPRTE registers with their valid bits set *
1289 * have their Read Response timers bumped. Whenever any of them match *
1290 * the value in the RRSP_TO field, a Read Response Timeout has *
1291 * occurred, and error handling occurs as described in the Error *
1292 * Handling section of this document. *
1293 * *
1294 ************************************************************************/
1295
1296typedef union ii_ixtt_u {
1297 u64 ii_ixtt_regval;
1298 struct {
1299 u64 i_tail_to:26;
1300 u64 i_rsvd_1:6;
1301 u64 i_rrsp_ps:23;
1302 u64 i_rrsp_to:5;
1303 u64 i_rsvd:4;
1304 } ii_ixtt_fld_s;
1305} ii_ixtt_u_t;
1306
1307/************************************************************************
1308 * *
1309 * Writing a 1 to the fields of this register clears the appropriate *
1310 * error bits in other areas of SHub. Note that when the *
1311 * E_PRB_x bits are used to clear error bits in PRB registers, *
1312 * SPUR_RD and SPUR_WR may persist, because they require additional *
1313 * action to clear them. See the IPRBx and IXSS Register *
1314 * specifications. *
1315 * *
1316 ************************************************************************/
1317
1318typedef union ii_ieclr_u {
1319 u64 ii_ieclr_regval;
1320 struct {
1321 u64 i_e_prb_0:1;
1322 u64 i_rsvd:7;
1323 u64 i_e_prb_8:1;
1324 u64 i_e_prb_9:1;
1325 u64 i_e_prb_a:1;
1326 u64 i_e_prb_b:1;
1327 u64 i_e_prb_c:1;
1328 u64 i_e_prb_d:1;
1329 u64 i_e_prb_e:1;
1330 u64 i_e_prb_f:1;
1331 u64 i_e_crazy:1;
1332 u64 i_e_bte_0:1;
1333 u64 i_e_bte_1:1;
1334 u64 i_reserved_1:10;
1335 u64 i_spur_rd_hdr:1;
1336 u64 i_cam_intr_to:1;
1337 u64 i_cam_overflow:1;
1338 u64 i_cam_read_miss:1;
1339 u64 i_ioq_rep_underflow:1;
1340 u64 i_ioq_req_underflow:1;
1341 u64 i_ioq_rep_overflow:1;
1342 u64 i_ioq_req_overflow:1;
1343 u64 i_iiq_rep_overflow:1;
1344 u64 i_iiq_req_overflow:1;
1345 u64 i_ii_xn_rep_cred_overflow:1;
1346 u64 i_ii_xn_req_cred_overflow:1;
1347 u64 i_ii_xn_invalid_cmd:1;
1348 u64 i_xn_ii_invalid_cmd:1;
1349 u64 i_reserved_2:21;
1350 } ii_ieclr_fld_s;
1351} ii_ieclr_u_t;
1352
1353/************************************************************************
1354 * *
1355 * This register controls both BTEs. SOFT_RESET is intended for *
1356 * recovery after an error. COUNT controls the total number of CRBs *
1357 * that both BTEs (combined) can use, which affects total BTE *
1358 * bandwidth. *
1359 * *
1360 ************************************************************************/
1361
1362typedef union ii_ibcr_u {
1363 u64 ii_ibcr_regval;
1364 struct {
1365 u64 i_count:4;
1366 u64 i_rsvd_1:4;
1367 u64 i_soft_reset:1;
1368 u64 i_rsvd:55;
1369 } ii_ibcr_fld_s;
1370} ii_ibcr_u_t;
1371
1372/************************************************************************
1373 * *
1374 * This register contains the header of a spurious read response *
1375 * received from Crosstalk. A spurious read response is defined as a *
1376 * read response received by II from a widget for which (1) the SIDN *
1377 * has a value between 1 and 7, inclusive (II never sends requests to *
1378 * these widgets (2) there is no valid IPRTE register which *
1379 * corresponds to the TNUM, or (3) the widget indicated in SIDN is *
1380 * not the same as the widget recorded in the IPRTE register *
1381 * referenced by the TNUM. If this condition is true, and if the *
1382 * IXSS[VALID] bit is clear, then the header of the spurious read *
1383 * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The *
1384 * errant header is thereby captured, and no further spurious read *
1385 * respones are captured until IXSS[VALID] is cleared by setting the *
1386 * appropriate bit in IECLR.Everytime a spurious read response is *
1387 * detected, the SPUR_RD bit of the PRB corresponding to the incoming *
1388 * message's SIDN field is set. This always happens, regarless of *
1389 * whether a header is captured. The programmer should check *
1390 * IXSM[SIDN] to determine which widget sent the spurious response, *
1391 * because there may be more than one SPUR_RD bit set in the PRB *
1392 * registers. The widget indicated by IXSM[SIDN] was the first *
1393 * spurious read response to be received since the last time *
1394 * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB *
1395 * will be set. Any SPUR_RD bits in any other PRB registers indicate *
1396 * spurious messages from other widets which were detected after the *
1397 * header was captured.. *
1398 * *
1399 ************************************************************************/
1400
1401typedef union ii_ixsm_u {
1402 u64 ii_ixsm_regval;
1403 struct {
1404 u64 i_byte_en:32;
1405 u64 i_reserved:1;
1406 u64 i_tag:3;
1407 u64 i_alt_pactyp:4;
1408 u64 i_bo:1;
1409 u64 i_error:1;
1410 u64 i_vbpm:1;
1411 u64 i_gbr:1;
1412 u64 i_ds:2;
1413 u64 i_ct:1;
1414 u64 i_tnum:5;
1415 u64 i_pactyp:4;
1416 u64 i_sidn:4;
1417 u64 i_didn:4;
1418 } ii_ixsm_fld_s;
1419} ii_ixsm_u_t;
1420
1421/************************************************************************
1422 * *
1423 * This register contains the sideband bits of a spurious read *
1424 * response received from Crosstalk. *
1425 * *
1426 ************************************************************************/
1427
1428typedef union ii_ixss_u {
1429 u64 ii_ixss_regval;
1430 struct {
1431 u64 i_sideband:8;
1432 u64 i_rsvd:55;
1433 u64 i_valid:1;
1434 } ii_ixss_fld_s;
1435} ii_ixss_u_t;
1436
1437/************************************************************************
1438 * *
1439 * This register enables software to access the II LLP's test port. *
1440 * Refer to the LLP 2.5 documentation for an explanation of the test *
1441 * port. Software can write to this register to program the values *
1442 * for the control fields (TestErrCapture, TestClear, TestFlit, *
1443 * TestMask and TestSeed). Similarly, software can read from this *
1444 * register to obtain the values of the test port's status outputs *
1445 * (TestCBerr, TestValid and TestData). *
1446 * *
1447 ************************************************************************/
1448
1449typedef union ii_ilct_u {
1450 u64 ii_ilct_regval;
1451 struct {
1452 u64 i_test_seed:20;
1453 u64 i_test_mask:8;
1454 u64 i_test_data:20;
1455 u64 i_test_valid:1;
1456 u64 i_test_cberr:1;
1457 u64 i_test_flit:3;
1458 u64 i_test_clear:1;
1459 u64 i_test_err_capture:1;
1460 u64 i_rsvd:9;
1461 } ii_ilct_fld_s;
1462} ii_ilct_u_t;
1463
1464/************************************************************************
1465 * *
1466 * If the II detects an illegal incoming Duplonet packet (request or *
1467 * reply) when VALID==0 in the IIEPH1 register, then it saves the *
1468 * contents of the packet's header flit in the IIEPH1 and IIEPH2 *
1469 * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit, *
1470 * and assigns a value to the ERR_TYPE field which indicates the *
1471 * specific nature of the error. The II recognizes four different *
1472 * types of errors: short request packets (ERR_TYPE==2), short reply *
1473 * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long *
1474 * reply packets (ERR_TYPE==5). The encodings for these types of *
1475 * errors were chosen to be consistent with the same types of errors *
1476 * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in *
1477 * the LB unit). If the II detects an illegal incoming Duplonet *
1478 * packet when VALID==1 in the IIEPH1 register, then it merely sets *
1479 * the OVERRUN bit to indicate that a subsequent error has happened, *
1480 * and does nothing further. *
1481 * *
1482 ************************************************************************/
1483
1484typedef union ii_iieph1_u {
1485 u64 ii_iieph1_regval;
1486 struct {
1487 u64 i_command:7;
1488 u64 i_rsvd_5:1;
1489 u64 i_suppl:14;
1490 u64 i_rsvd_4:1;
1491 u64 i_source:14;
1492 u64 i_rsvd_3:1;
1493 u64 i_err_type:4;
1494 u64 i_rsvd_2:4;
1495 u64 i_overrun:1;
1496 u64 i_rsvd_1:3;
1497 u64 i_valid:1;
1498 u64 i_rsvd:13;
1499 } ii_iieph1_fld_s;
1500} ii_iieph1_u_t;
1501
1502/************************************************************************
1503 * *
1504 * This register holds the Address field from the header flit of an *
1505 * incoming erroneous Duplonet packet, along with the tail bit which *
1506 * accompanied this header flit. This register is essentially an *
1507 * extension of IIEPH1. Two registers were necessary because the 64 *
1508 * bits available in only a single register were insufficient to *
1509 * capture the entire header flit of an erroneous packet. *
1510 * *
1511 ************************************************************************/
1512
1513typedef union ii_iieph2_u {
1514 u64 ii_iieph2_regval;
1515 struct {
1516 u64 i_rsvd_0:3;
1517 u64 i_address:47;
1518 u64 i_rsvd_1:10;
1519 u64 i_tail:1;
1520 u64 i_rsvd:3;
1521 } ii_iieph2_fld_s;
1522} ii_iieph2_u_t;
1523
1524/******************************/
1525
1526/************************************************************************
1527 * *
1528 * This register's value is a bit vector that guards access from SXBs *
1529 * to local registers within the II as well as to external Crosstalk *
1530 * widgets *
1531 * *
1532 ************************************************************************/
1533
1534typedef union ii_islapr_u {
1535 u64 ii_islapr_regval;
1536 struct {
1537 u64 i_region:64;
1538 } ii_islapr_fld_s;
1539} ii_islapr_u_t;
1540
1541/************************************************************************
1542 * *
1543 * A write to this register of the 56-bit value "Pup+Bun" will cause *
1544 * the bit in the ISLAPR register corresponding to the region of the *
1545 * requestor to be set (access allowed). (
1546 * *
1547 ************************************************************************/
1548
1549typedef union ii_islapo_u {
1550 u64 ii_islapo_regval;
1551 struct {
1552 u64 i_io_sbx_ovrride:56;
1553 u64 i_rsvd:8;
1554 } ii_islapo_fld_s;
1555} ii_islapo_u_t;
1556
1557/************************************************************************
1558 * *
1559 * Determines how long the wrapper will wait aftr an interrupt is *
1560 * initially issued from the II before it times out the outstanding *
1561 * interrupt and drops it from the interrupt queue. *
1562 * *
1563 ************************************************************************/
1564
1565typedef union ii_iwi_u {
1566 u64 ii_iwi_regval;
1567 struct {
1568 u64 i_prescale:24;
1569 u64 i_rsvd:8;
1570 u64 i_timeout:8;
1571 u64 i_rsvd1:8;
1572 u64 i_intrpt_retry_period:8;
1573 u64 i_rsvd2:8;
1574 } ii_iwi_fld_s;
1575} ii_iwi_u_t;
1576
1577/************************************************************************
1578 * *
1579 * Log errors which have occurred in the II wrapper. The errors are *
1580 * cleared by writing to the IECLR register. *
1581 * *
1582 ************************************************************************/
1583
1584typedef union ii_iwel_u {
1585 u64 ii_iwel_regval;
1586 struct {
1587 u64 i_intr_timed_out:1;
1588 u64 i_rsvd:7;
1589 u64 i_cam_overflow:1;
1590 u64 i_cam_read_miss:1;
1591 u64 i_rsvd1:2;
1592 u64 i_ioq_rep_underflow:1;
1593 u64 i_ioq_req_underflow:1;
1594 u64 i_ioq_rep_overflow:1;
1595 u64 i_ioq_req_overflow:1;
1596 u64 i_iiq_rep_overflow:1;
1597 u64 i_iiq_req_overflow:1;
1598 u64 i_rsvd2:6;
1599 u64 i_ii_xn_rep_cred_over_under:1;
1600 u64 i_ii_xn_req_cred_over_under:1;
1601 u64 i_rsvd3:6;
1602 u64 i_ii_xn_invalid_cmd:1;
1603 u64 i_xn_ii_invalid_cmd:1;
1604 u64 i_rsvd4:30;
1605 } ii_iwel_fld_s;
1606} ii_iwel_u_t;
1607
1608/************************************************************************
1609 * *
1610 * Controls the II wrapper. *
1611 * *
1612 ************************************************************************/
1613
1614typedef union ii_iwc_u {
1615 u64 ii_iwc_regval;
1616 struct {
1617 u64 i_dma_byte_swap:1;
1618 u64 i_rsvd:3;
1619 u64 i_cam_read_lines_reset:1;
1620 u64 i_rsvd1:3;
1621 u64 i_ii_xn_cred_over_under_log:1;
1622 u64 i_rsvd2:19;
1623 u64 i_xn_rep_iq_depth:5;
1624 u64 i_rsvd3:3;
1625 u64 i_xn_req_iq_depth:5;
1626 u64 i_rsvd4:3;
1627 u64 i_iiq_depth:6;
1628 u64 i_rsvd5:12;
1629 u64 i_force_rep_cred:1;
1630 u64 i_force_req_cred:1;
1631 } ii_iwc_fld_s;
1632} ii_iwc_u_t;
1633
1634/************************************************************************
1635 * *
1636 * Status in the II wrapper. *
1637 * *
1638 ************************************************************************/
1639
1640typedef union ii_iws_u {
1641 u64 ii_iws_regval;
1642 struct {
1643 u64 i_xn_rep_iq_credits:5;
1644 u64 i_rsvd:3;
1645 u64 i_xn_req_iq_credits:5;
1646 u64 i_rsvd1:51;
1647 } ii_iws_fld_s;
1648} ii_iws_u_t;
1649
1650/************************************************************************
1651 * *
1652 * Masks errors in the IWEL register. *
1653 * *
1654 ************************************************************************/
1655
1656typedef union ii_iweim_u {
1657 u64 ii_iweim_regval;
1658 struct {
1659 u64 i_intr_timed_out:1;
1660 u64 i_rsvd:7;
1661 u64 i_cam_overflow:1;
1662 u64 i_cam_read_miss:1;
1663 u64 i_rsvd1:2;
1664 u64 i_ioq_rep_underflow:1;
1665 u64 i_ioq_req_underflow:1;
1666 u64 i_ioq_rep_overflow:1;
1667 u64 i_ioq_req_overflow:1;
1668 u64 i_iiq_rep_overflow:1;
1669 u64 i_iiq_req_overflow:1;
1670 u64 i_rsvd2:6;
1671 u64 i_ii_xn_rep_cred_overflow:1;
1672 u64 i_ii_xn_req_cred_overflow:1;
1673 u64 i_rsvd3:6;
1674 u64 i_ii_xn_invalid_cmd:1;
1675 u64 i_xn_ii_invalid_cmd:1;
1676 u64 i_rsvd4:30;
1677 } ii_iweim_fld_s;
1678} ii_iweim_u_t;
1679
1680/************************************************************************
1681 * *
1682 * A write to this register causes a particular field in the *
1683 * corresponding widget's PRB entry to be adjusted up or down by 1. *
1684 * This counter should be used when recovering from error and reset *
1685 * conditions. Note that software would be capable of causing *
1686 * inadvertent overflow or underflow of these counters. *
1687 * *
1688 ************************************************************************/
1689
1690typedef union ii_ipca_u {
1691 u64 ii_ipca_regval;
1692 struct {
1693 u64 i_wid:4;
1694 u64 i_adjust:1;
1695 u64 i_rsvd_1:3;
1696 u64 i_field:2;
1697 u64 i_rsvd:54;
1698 } ii_ipca_fld_s;
1699} ii_ipca_u_t;
1700
1701/************************************************************************
1702 * *
1703 * There are 8 instances of this register. This register contains *
1704 * the information that the II has to remember once it has launched a *
1705 * PIO Read operation. The contents are used to form the correct *
1706 * Router Network packet and direct the Crosstalk reply to the *
1707 * appropriate processor. *
1708 * *
1709 ************************************************************************/
1710
1711typedef union ii_iprte0a_u {
1712 u64 ii_iprte0a_regval;
1713 struct {
1714 u64 i_rsvd_1:54;
1715 u64 i_widget:4;
1716 u64 i_to_cnt:5;
1717 u64 i_vld:1;
1718 } ii_iprte0a_fld_s;
1719} ii_iprte0a_u_t;
1720
1721/************************************************************************
1722 * *
1723 * There are 8 instances of this register. This register contains *
1724 * the information that the II has to remember once it has launched a *
1725 * PIO Read operation. The contents are used to form the correct *
1726 * Router Network packet and direct the Crosstalk reply to the *
1727 * appropriate processor. *
1728 * *
1729 ************************************************************************/
1730
1731typedef union ii_iprte1a_u {
1732 u64 ii_iprte1a_regval;
1733 struct {
1734 u64 i_rsvd_1:54;
1735 u64 i_widget:4;
1736 u64 i_to_cnt:5;
1737 u64 i_vld:1;
1738 } ii_iprte1a_fld_s;
1739} ii_iprte1a_u_t;
1740
1741/************************************************************************
1742 * *
1743 * There are 8 instances of this register. This register contains *
1744 * the information that the II has to remember once it has launched a *
1745 * PIO Read operation. The contents are used to form the correct *
1746 * Router Network packet and direct the Crosstalk reply to the *
1747 * appropriate processor. *
1748 * *
1749 ************************************************************************/
1750
1751typedef union ii_iprte2a_u {
1752 u64 ii_iprte2a_regval;
1753 struct {
1754 u64 i_rsvd_1:54;
1755 u64 i_widget:4;
1756 u64 i_to_cnt:5;
1757 u64 i_vld:1;
1758 } ii_iprte2a_fld_s;
1759} ii_iprte2a_u_t;
1760
1761/************************************************************************
1762 * *
1763 * There are 8 instances of this register. This register contains *
1764 * the information that the II has to remember once it has launched a *
1765 * PIO Read operation. The contents are used to form the correct *
1766 * Router Network packet and direct the Crosstalk reply to the *
1767 * appropriate processor. *
1768 * *
1769 ************************************************************************/
1770
1771typedef union ii_iprte3a_u {
1772 u64 ii_iprte3a_regval;
1773 struct {
1774 u64 i_rsvd_1:54;
1775 u64 i_widget:4;
1776 u64 i_to_cnt:5;
1777 u64 i_vld:1;
1778 } ii_iprte3a_fld_s;
1779} ii_iprte3a_u_t;
1780
1781/************************************************************************
1782 * *
1783 * There are 8 instances of this register. This register contains *
1784 * the information that the II has to remember once it has launched a *
1785 * PIO Read operation. The contents are used to form the correct *
1786 * Router Network packet and direct the Crosstalk reply to the *
1787 * appropriate processor. *
1788 * *
1789 ************************************************************************/
1790
1791typedef union ii_iprte4a_u {
1792 u64 ii_iprte4a_regval;
1793 struct {
1794 u64 i_rsvd_1:54;
1795 u64 i_widget:4;
1796 u64 i_to_cnt:5;
1797 u64 i_vld:1;
1798 } ii_iprte4a_fld_s;
1799} ii_iprte4a_u_t;
1800
1801/************************************************************************
1802 * *
1803 * There are 8 instances of this register. This register contains *
1804 * the information that the II has to remember once it has launched a *
1805 * PIO Read operation. The contents are used to form the correct *
1806 * Router Network packet and direct the Crosstalk reply to the *
1807 * appropriate processor. *
1808 * *
1809 ************************************************************************/
1810
1811typedef union ii_iprte5a_u {
1812 u64 ii_iprte5a_regval;
1813 struct {
1814 u64 i_rsvd_1:54;
1815 u64 i_widget:4;
1816 u64 i_to_cnt:5;
1817 u64 i_vld:1;
1818 } ii_iprte5a_fld_s;
1819} ii_iprte5a_u_t;
1820
1821/************************************************************************
1822 * *
1823 * There are 8 instances of this register. This register contains *
1824 * the information that the II has to remember once it has launched a *
1825 * PIO Read operation. The contents are used to form the correct *
1826 * Router Network packet and direct the Crosstalk reply to the *
1827 * appropriate processor. *
1828 * *
1829 ************************************************************************/
1830
1831typedef union ii_iprte6a_u {
1832 u64 ii_iprte6a_regval;
1833 struct {
1834 u64 i_rsvd_1:54;
1835 u64 i_widget:4;
1836 u64 i_to_cnt:5;
1837 u64 i_vld:1;
1838 } ii_iprte6a_fld_s;
1839} ii_iprte6a_u_t;
1840
1841/************************************************************************
1842 * *
1843 * There are 8 instances of this register. This register contains *
1844 * the information that the II has to remember once it has launched a *
1845 * PIO Read operation. The contents are used to form the correct *
1846 * Router Network packet and direct the Crosstalk reply to the *
1847 * appropriate processor. *
1848 * *
1849 ************************************************************************/
1850
1851typedef union ii_iprte7a_u {
1852 u64 ii_iprte7a_regval;
1853 struct {
1854 u64 i_rsvd_1:54;
1855 u64 i_widget:4;
1856 u64 i_to_cnt:5;
1857 u64 i_vld:1;
1858 } ii_iprtea7_fld_s;
1859} ii_iprte7a_u_t;
1860
1861/************************************************************************
1862 * *
1863 * There are 8 instances of this register. This register contains *
1864 * the information that the II has to remember once it has launched a *
1865 * PIO Read operation. The contents are used to form the correct *
1866 * Router Network packet and direct the Crosstalk reply to the *
1867 * appropriate processor. *
1868 * *
1869 ************************************************************************/
1870
1871typedef union ii_iprte0b_u {
1872 u64 ii_iprte0b_regval;
1873 struct {
1874 u64 i_rsvd_1:3;
1875 u64 i_address:47;
1876 u64 i_init:3;
1877 u64 i_source:11;
1878 } ii_iprte0b_fld_s;
1879} ii_iprte0b_u_t;
1880
1881/************************************************************************
1882 * *
1883 * There are 8 instances of this register. This register contains *
1884 * the information that the II has to remember once it has launched a *
1885 * PIO Read operation. The contents are used to form the correct *
1886 * Router Network packet and direct the Crosstalk reply to the *
1887 * appropriate processor. *
1888 * *
1889 ************************************************************************/
1890
1891typedef union ii_iprte1b_u {
1892 u64 ii_iprte1b_regval;
1893 struct {
1894 u64 i_rsvd_1:3;
1895 u64 i_address:47;
1896 u64 i_init:3;
1897 u64 i_source:11;
1898 } ii_iprte1b_fld_s;
1899} ii_iprte1b_u_t;
1900
1901/************************************************************************
1902 * *
1903 * There are 8 instances of this register. This register contains *
1904 * the information that the II has to remember once it has launched a *
1905 * PIO Read operation. The contents are used to form the correct *
1906 * Router Network packet and direct the Crosstalk reply to the *
1907 * appropriate processor. *
1908 * *
1909 ************************************************************************/
1910
1911typedef union ii_iprte2b_u {
1912 u64 ii_iprte2b_regval;
1913 struct {
1914 u64 i_rsvd_1:3;
1915 u64 i_address:47;
1916 u64 i_init:3;
1917 u64 i_source:11;
1918 } ii_iprte2b_fld_s;
1919} ii_iprte2b_u_t;
1920
1921/************************************************************************
1922 * *
1923 * There are 8 instances of this register. This register contains *
1924 * the information that the II has to remember once it has launched a *
1925 * PIO Read operation. The contents are used to form the correct *
1926 * Router Network packet and direct the Crosstalk reply to the *
1927 * appropriate processor. *
1928 * *
1929 ************************************************************************/
1930
1931typedef union ii_iprte3b_u {
1932 u64 ii_iprte3b_regval;
1933 struct {
1934 u64 i_rsvd_1:3;
1935 u64 i_address:47;
1936 u64 i_init:3;
1937 u64 i_source:11;
1938 } ii_iprte3b_fld_s;
1939} ii_iprte3b_u_t;
1940
1941/************************************************************************
1942 * *
1943 * There are 8 instances of this register. This register contains *
1944 * the information that the II has to remember once it has launched a *
1945 * PIO Read operation. The contents are used to form the correct *
1946 * Router Network packet and direct the Crosstalk reply to the *
1947 * appropriate processor. *
1948 * *
1949 ************************************************************************/
1950
1951typedef union ii_iprte4b_u {
1952 u64 ii_iprte4b_regval;
1953 struct {
1954 u64 i_rsvd_1:3;
1955 u64 i_address:47;
1956 u64 i_init:3;
1957 u64 i_source:11;
1958 } ii_iprte4b_fld_s;
1959} ii_iprte4b_u_t;
1960
1961/************************************************************************
1962 * *
1963 * There are 8 instances of this register. This register contains *
1964 * the information that the II has to remember once it has launched a *
1965 * PIO Read operation. The contents are used to form the correct *
1966 * Router Network packet and direct the Crosstalk reply to the *
1967 * appropriate processor. *
1968 * *
1969 ************************************************************************/
1970
1971typedef union ii_iprte5b_u {
1972 u64 ii_iprte5b_regval;
1973 struct {
1974 u64 i_rsvd_1:3;
1975 u64 i_address:47;
1976 u64 i_init:3;
1977 u64 i_source:11;
1978 } ii_iprte5b_fld_s;
1979} ii_iprte5b_u_t;
1980
1981/************************************************************************
1982 * *
1983 * There are 8 instances of this register. This register contains *
1984 * the information that the II has to remember once it has launched a *
1985 * PIO Read operation. The contents are used to form the correct *
1986 * Router Network packet and direct the Crosstalk reply to the *
1987 * appropriate processor. *
1988 * *
1989 ************************************************************************/
1990
1991typedef union ii_iprte6b_u {
1992 u64 ii_iprte6b_regval;
1993 struct {
1994 u64 i_rsvd_1:3;
1995 u64 i_address:47;
1996 u64 i_init:3;
1997 u64 i_source:11;
1998
1999 } ii_iprte6b_fld_s;
2000} ii_iprte6b_u_t;
2001
2002/************************************************************************
2003 * *
2004 * There are 8 instances of this register. This register contains *
2005 * the information that the II has to remember once it has launched a *
2006 * PIO Read operation. The contents are used to form the correct *
2007 * Router Network packet and direct the Crosstalk reply to the *
2008 * appropriate processor. *
2009 * *
2010 ************************************************************************/
2011
2012typedef union ii_iprte7b_u {
2013 u64 ii_iprte7b_regval;
2014 struct {
2015 u64 i_rsvd_1:3;
2016 u64 i_address:47;
2017 u64 i_init:3;
2018 u64 i_source:11;
2019 } ii_iprte7b_fld_s;
2020} ii_iprte7b_u_t;
2021
2022/************************************************************************
2023 * *
2024 * Description: SHub II contains a feature which did not exist in *
2025 * the Hub which automatically cleans up after a Read Response *
2026 * timeout, including deallocation of the IPRTE and recovery of IBuf *
2027 * space. The inclusion of this register in SHub is for backward *
2028 * compatibility *
2029 * A write to this register causes an entry from the table of *
2030 * outstanding PIO Read Requests to be freed and returned to the *
2031 * stack of free entries. This register is used in handling the *
2032 * timeout errors that result in a PIO Reply never returning from *
2033 * Crosstalk. *
2034 * Note that this register does not affect the contents of the IPRTE *
2035 * registers. The Valid bits in those registers have to be *
2036 * specifically turned off by software. *
2037 * *
2038 ************************************************************************/
2039
2040typedef union ii_ipdr_u {
2041 u64 ii_ipdr_regval;
2042 struct {
2043 u64 i_te:3;
2044 u64 i_rsvd_1:1;
2045 u64 i_pnd:1;
2046 u64 i_init_rpcnt:1;
2047 u64 i_rsvd:58;
2048 } ii_ipdr_fld_s;
2049} ii_ipdr_u_t;
2050
2051/************************************************************************
2052 * *
2053 * A write to this register causes a CRB entry to be returned to the *
2054 * queue of free CRBs. The entry should have previously been cleared *
2055 * (mark bit) via backdoor access to the pertinent CRB entry. This *
2056 * register is used in the last step of handling the errors that are *
2057 * captured and marked in CRB entries. Briefly: 1) first error for *
2058 * DMA write from a particular device, and first error for a *
2059 * particular BTE stream, lead to a marked CRB entry, and processor *
2060 * interrupt, 2) software reads the error information captured in the *
2061 * CRB entry, and presumably takes some corrective action, 3) *
2062 * software clears the mark bit, and finally 4) software writes to *
2063 * the ICDR register to return the CRB entry to the list of free CRB *
2064 * entries. *
2065 * *
2066 ************************************************************************/
2067
2068typedef union ii_icdr_u {
2069 u64 ii_icdr_regval;
2070 struct {
2071 u64 i_crb_num:4;
2072 u64 i_pnd:1;
2073 u64 i_rsvd:59;
2074 } ii_icdr_fld_s;
2075} ii_icdr_u_t;
2076
2077/************************************************************************
2078 * *
2079 * This register provides debug access to two FIFOs inside of II. *
2080 * Both IOQ_MAX* fields of this register contain the instantaneous *
2081 * depth (in units of the number of available entries) of the *
2082 * associated IOQ FIFO. A read of this register will return the *
2083 * number of free entries on each FIFO at the time of the read. So *
2084 * when a FIFO is idle, the associated field contains the maximum *
2085 * depth of the FIFO. This register is writable for debug reasons *
2086 * and is intended to be written with the maximum desired FIFO depth *
2087 * while the FIFO is idle. Software must assure that II is idle when *
2088 * this register is written. If there are any active entries in any *
2089 * of these FIFOs when this register is written, the results are *
2090 * undefined. *
2091 * *
2092 ************************************************************************/
2093
2094typedef union ii_ifdr_u {
2095 u64 ii_ifdr_regval;
2096 struct {
2097 u64 i_ioq_max_rq:7;
2098 u64 i_set_ioq_rq:1;
2099 u64 i_ioq_max_rp:7;
2100 u64 i_set_ioq_rp:1;
2101 u64 i_rsvd:48;
2102 } ii_ifdr_fld_s;
2103} ii_ifdr_u_t;
2104
2105/************************************************************************
2106 * *
2107 * This register allows the II to become sluggish in removing *
2108 * messages from its inbound queue (IIQ). This will cause messages to *
2109 * back up in either virtual channel. Disabling the "molasses" mode *
2110 * subsequently allows the II to be tested under stress. In the *
2111 * sluggish ("Molasses") mode, the localized effects of congestion *
2112 * can be observed. *
2113 * *
2114 ************************************************************************/
2115
2116typedef union ii_iiap_u {
2117 u64 ii_iiap_regval;
2118 struct {
2119 u64 i_rq_mls:6;
2120 u64 i_rsvd_1:2;
2121 u64 i_rp_mls:6;
2122 u64 i_rsvd:50;
2123 } ii_iiap_fld_s;
2124} ii_iiap_u_t;
2125
2126/************************************************************************
2127 * *
2128 * This register allows several parameters of CRB operation to be *
2129 * set. Note that writing to this register can have catastrophic side *
2130 * effects, if the CRB is not quiescent, i.e. if the CRB is *
2131 * processing protocol messages when the write occurs. *
2132 * *
2133 ************************************************************************/
2134
2135typedef union ii_icmr_u {
2136 u64 ii_icmr_regval;
2137 struct {
2138 u64 i_sp_msg:1;
2139 u64 i_rd_hdr:1;
2140 u64 i_rsvd_4:2;
2141 u64 i_c_cnt:4;
2142 u64 i_rsvd_3:4;
2143 u64 i_clr_rqpd:1;
2144 u64 i_clr_rppd:1;
2145 u64 i_rsvd_2:2;
2146 u64 i_fc_cnt:4;
2147 u64 i_crb_vld:15;
2148 u64 i_crb_mark:15;
2149 u64 i_rsvd_1:2;
2150 u64 i_precise:1;
2151 u64 i_rsvd:11;
2152 } ii_icmr_fld_s;
2153} ii_icmr_u_t;
2154
2155/************************************************************************
2156 * *
2157 * This register allows control of the table portion of the CRB *
2158 * logic via software. Control operations from this register have *
2159 * priority over all incoming Crosstalk or BTE requests. *
2160 * *
2161 ************************************************************************/
2162
2163typedef union ii_iccr_u {
2164 u64 ii_iccr_regval;
2165 struct {
2166 u64 i_crb_num:4;
2167 u64 i_rsvd_1:4;
2168 u64 i_cmd:8;
2169 u64 i_pending:1;
2170 u64 i_rsvd:47;
2171 } ii_iccr_fld_s;
2172} ii_iccr_u_t;
2173
2174/************************************************************************
2175 * *
2176 * This register allows the maximum timeout value to be programmed. *
2177 * *
2178 ************************************************************************/
2179
2180typedef union ii_icto_u {
2181 u64 ii_icto_regval;
2182 struct {
2183 u64 i_timeout:8;
2184 u64 i_rsvd:56;
2185 } ii_icto_fld_s;
2186} ii_icto_u_t;
2187
2188/************************************************************************
2189 * *
2190 * This register allows the timeout prescalar to be programmed. An *
2191 * internal counter is associated with this register. When the *
2192 * internal counter reaches the value of the PRESCALE field, the *
2193 * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] *
2194 * field). The internal counter resets to zero, and then continues *
2195 * counting. *
2196 * *
2197 ************************************************************************/
2198
2199typedef union ii_ictp_u {
2200 u64 ii_ictp_regval;
2201 struct {
2202 u64 i_prescale:24;
2203 u64 i_rsvd:40;
2204 } ii_ictp_fld_s;
2205} ii_ictp_u_t;
2206
2207/************************************************************************
2208 * *
2209 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2210 * used for Crosstalk operations (both cacheline and partial *
2211 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2212 * registers (_A to _E) are required to read and write each entry. *
2213 * The CRB Entry registers can be conceptualized as rows and columns *
2214 * (illustrated in the table above). Each row contains the 4 *
2215 * registers required for a single CRB Entry. The first doubleword *
2216 * (column) for each entry is labeled A, and the second doubleword *
2217 * (higher address) is labeled B, the third doubleword is labeled C, *
2218 * the fourth doubleword is labeled D and the fifth doubleword is *
2219 * labeled E. All CRB entries have their addresses on a quarter *
2220 * cacheline aligned boundary. *
2221 * Upon reset, only the following fields are initialized: valid *
2222 * (VLD), priority count, timeout, timeout valid, and context valid. *
2223 * All other bits should be cleared by software before use (after *
2224 * recovering any potential error state from before the reset). *
2225 * The following four tables summarize the format for the four *
2226 * registers that are used for each ICRB# Entry. *
2227 * *
2228 ************************************************************************/
2229
2230typedef union ii_icrb0_a_u {
2231 u64 ii_icrb0_a_regval;
2232 struct {
2233 u64 ia_iow:1;
2234 u64 ia_vld:1;
2235 u64 ia_addr:47;
2236 u64 ia_tnum:5;
2237 u64 ia_sidn:4;
2238 u64 ia_rsvd:6;
2239 } ii_icrb0_a_fld_s;
2240} ii_icrb0_a_u_t;
2241
2242/************************************************************************
2243 * *
2244 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2245 * used for Crosstalk operations (both cacheline and partial *
2246 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2247 * registers (_A to _E) are required to read and write each entry. *
2248 * *
2249 ************************************************************************/
2250
2251typedef union ii_icrb0_b_u {
2252 u64 ii_icrb0_b_regval;
2253 struct {
2254 u64 ib_xt_err:1;
2255 u64 ib_mark:1;
2256 u64 ib_ln_uce:1;
2257 u64 ib_errcode:3;
2258 u64 ib_error:1;
2259 u64 ib_stall__bte_1:1;
2260 u64 ib_stall__bte_0:1;
2261 u64 ib_stall__intr:1;
2262 u64 ib_stall_ib:1;
2263 u64 ib_intvn:1;
2264 u64 ib_wb:1;
2265 u64 ib_hold:1;
2266 u64 ib_ack:1;
2267 u64 ib_resp:1;
2268 u64 ib_ack_cnt:11;
2269 u64 ib_rsvd:7;
2270 u64 ib_exc:5;
2271 u64 ib_init:3;
2272 u64 ib_imsg:8;
2273 u64 ib_imsgtype:2;
2274 u64 ib_use_old:1;
2275 u64 ib_rsvd_1:11;
2276 } ii_icrb0_b_fld_s;
2277} ii_icrb0_b_u_t;
2278
2279/************************************************************************
2280 * *
2281 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2282 * used for Crosstalk operations (both cacheline and partial *
2283 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2284 * registers (_A to _E) are required to read and write each entry. *
2285 * *
2286 ************************************************************************/
2287
2288typedef union ii_icrb0_c_u {
2289 u64 ii_icrb0_c_regval;
2290 struct {
2291 u64 ic_source:15;
2292 u64 ic_size:2;
2293 u64 ic_ct:1;
2294 u64 ic_bte_num:1;
2295 u64 ic_gbr:1;
2296 u64 ic_resprqd:1;
2297 u64 ic_bo:1;
2298 u64 ic_suppl:15;
2299 u64 ic_rsvd:27;
2300 } ii_icrb0_c_fld_s;
2301} ii_icrb0_c_u_t;
2302
2303/************************************************************************
2304 * *
2305 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2306 * used for Crosstalk operations (both cacheline and partial *
2307 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2308 * registers (_A to _E) are required to read and write each entry. *
2309 * *
2310 ************************************************************************/
2311
2312typedef union ii_icrb0_d_u {
2313 u64 ii_icrb0_d_regval;
2314 struct {
2315 u64 id_pa_be:43;
2316 u64 id_bte_op:1;
2317 u64 id_pr_psc:4;
2318 u64 id_pr_cnt:4;
2319 u64 id_sleep:1;
2320 u64 id_rsvd:11;
2321 } ii_icrb0_d_fld_s;
2322} ii_icrb0_d_u_t;
2323
2324/************************************************************************
2325 * *
2326 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2327 * used for Crosstalk operations (both cacheline and partial *
2328 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2329 * registers (_A to _E) are required to read and write each entry. *
2330 * *
2331 ************************************************************************/
2332
2333typedef union ii_icrb0_e_u {
2334 u64 ii_icrb0_e_regval;
2335 struct {
2336 u64 ie_timeout:8;
2337 u64 ie_context:15;
2338 u64 ie_rsvd:1;
2339 u64 ie_tvld:1;
2340 u64 ie_cvld:1;
2341 u64 ie_rsvd_0:38;
2342 } ii_icrb0_e_fld_s;
2343} ii_icrb0_e_u_t;
2344
2345/************************************************************************
2346 * *
2347 * This register contains the lower 64 bits of the header of the *
2348 * spurious message captured by II. Valid when the SP_MSG bit in ICMR *
2349 * register is set. *
2350 * *
2351 ************************************************************************/
2352
2353typedef union ii_icsml_u {
2354 u64 ii_icsml_regval;
2355 struct {
2356 u64 i_tt_addr:47;
2357 u64 i_newsuppl_ex:14;
2358 u64 i_reserved:2;
2359 u64 i_overflow:1;
2360 } ii_icsml_fld_s;
2361} ii_icsml_u_t;
2362
2363/************************************************************************
2364 * *
2365 * This register contains the middle 64 bits of the header of the *
2366 * spurious message captured by II. Valid when the SP_MSG bit in ICMR *
2367 * register is set. *
2368 * *
2369 ************************************************************************/
2370
2371typedef union ii_icsmm_u {
2372 u64 ii_icsmm_regval;
2373 struct {
2374 u64 i_tt_ack_cnt:11;
2375 u64 i_reserved:53;
2376 } ii_icsmm_fld_s;
2377} ii_icsmm_u_t;
2378
2379/************************************************************************
2380 * *
2381 * This register contains the microscopic state, all the inputs to *
2382 * the protocol table, captured with the spurious message. Valid when *
2383 * the SP_MSG bit in the ICMR register is set. *
2384 * *
2385 ************************************************************************/
2386
2387typedef union ii_icsmh_u {
2388 u64 ii_icsmh_regval;
2389 struct {
2390 u64 i_tt_vld:1;
2391 u64 i_xerr:1;
2392 u64 i_ft_cwact_o:1;
2393 u64 i_ft_wact_o:1;
2394 u64 i_ft_active_o:1;
2395 u64 i_sync:1;
2396 u64 i_mnusg:1;
2397 u64 i_mnusz:1;
2398 u64 i_plusz:1;
2399 u64 i_plusg:1;
2400 u64 i_tt_exc:5;
2401 u64 i_tt_wb:1;
2402 u64 i_tt_hold:1;
2403 u64 i_tt_ack:1;
2404 u64 i_tt_resp:1;
2405 u64 i_tt_intvn:1;
2406 u64 i_g_stall_bte1:1;
2407 u64 i_g_stall_bte0:1;
2408 u64 i_g_stall_il:1;
2409 u64 i_g_stall_ib:1;
2410 u64 i_tt_imsg:8;
2411 u64 i_tt_imsgtype:2;
2412 u64 i_tt_use_old:1;
2413 u64 i_tt_respreqd:1;
2414 u64 i_tt_bte_num:1;
2415 u64 i_cbn:1;
2416 u64 i_match:1;
2417 u64 i_rpcnt_lt_34:1;
2418 u64 i_rpcnt_ge_34:1;
2419 u64 i_rpcnt_lt_18:1;
2420 u64 i_rpcnt_ge_18:1;
2421 u64 i_rpcnt_lt_2:1;
2422 u64 i_rpcnt_ge_2:1;
2423 u64 i_rqcnt_lt_18:1;
2424 u64 i_rqcnt_ge_18:1;
2425 u64 i_rqcnt_lt_2:1;
2426 u64 i_rqcnt_ge_2:1;
2427 u64 i_tt_device:7;
2428 u64 i_tt_init:3;
2429 u64 i_reserved:5;
2430 } ii_icsmh_fld_s;
2431} ii_icsmh_u_t;
2432
2433/************************************************************************
2434 * *
2435 * The Shub DEBUG unit provides a 3-bit selection signal to the *
2436 * II core and a 3-bit selection signal to the fsbclk domain in the II *
2437 * wrapper. *
2438 * *
2439 ************************************************************************/
2440
2441typedef union ii_idbss_u {
2442 u64 ii_idbss_regval;
2443 struct {
2444 u64 i_iioclk_core_submenu:3;
2445 u64 i_rsvd:5;
2446 u64 i_fsbclk_wrapper_submenu:3;
2447 u64 i_rsvd_1:5;
2448 u64 i_iioclk_menu:5;
2449 u64 i_rsvd_2:43;
2450 } ii_idbss_fld_s;
2451} ii_idbss_u_t;
2452
2453/************************************************************************
2454 * *
2455 * Description: This register is used to set up the length for a *
2456 * transfer and then to monitor the progress of that transfer. This *
2457 * register needs to be initialized before a transfer is started. A *
2458 * legitimate write to this register will set the Busy bit, clear the *
2459 * Error bit, and initialize the length to the value desired. *
2460 * While the transfer is in progress, hardware will decrement the *
2461 * length field with each successful block that is copied. Once the *
2462 * transfer completes, hardware will clear the Busy bit. The length *
2463 * field will also contain the number of cache lines left to be *
2464 * transferred. *
2465 * *
2466 ************************************************************************/
2467
2468typedef union ii_ibls0_u {
2469 u64 ii_ibls0_regval;
2470 struct {
2471 u64 i_length:16;
2472 u64 i_error:1;
2473 u64 i_rsvd_1:3;
2474 u64 i_busy:1;
2475 u64 i_rsvd:43;
2476 } ii_ibls0_fld_s;
2477} ii_ibls0_u_t;
2478
2479/************************************************************************
2480 * *
2481 * This register should be loaded before a transfer is started. The *
2482 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2483 * address as described in Section 1.3, Figure2 and Figure3. Since *
2484 * the bottom 7 bits of the address are always taken to be zero, BTE *
2485 * transfers are always cacheline-aligned. *
2486 * *
2487 ************************************************************************/
2488
2489typedef union ii_ibsa0_u {
2490 u64 ii_ibsa0_regval;
2491 struct {
2492 u64 i_rsvd_1:7;
2493 u64 i_addr:42;
2494 u64 i_rsvd:15;
2495 } ii_ibsa0_fld_s;
2496} ii_ibsa0_u_t;
2497
2498/************************************************************************
2499 * *
2500 * This register should be loaded before a transfer is started. The *
2501 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2502 * address as described in Section 1.3, Figure2 and Figure3. Since *
2503 * the bottom 7 bits of the address are always taken to be zero, BTE *
2504 * transfers are always cacheline-aligned. *
2505 * *
2506 ************************************************************************/
2507
2508typedef union ii_ibda0_u {
2509 u64 ii_ibda0_regval;
2510 struct {
2511 u64 i_rsvd_1:7;
2512 u64 i_addr:42;
2513 u64 i_rsvd:15;
2514 } ii_ibda0_fld_s;
2515} ii_ibda0_u_t;
2516
2517/************************************************************************
2518 * *
2519 * Writing to this register sets up the attributes of the transfer *
2520 * and initiates the transfer operation. Reading this register has *
2521 * the side effect of terminating any transfer in progress. Note: *
2522 * stopping a transfer midstream could have an adverse impact on the *
2523 * other BTE. If a BTE stream has to be stopped (due to error *
2524 * handling for example), both BTE streams should be stopped and *
2525 * their transfers discarded. *
2526 * *
2527 ************************************************************************/
2528
2529typedef union ii_ibct0_u {
2530 u64 ii_ibct0_regval;
2531 struct {
2532 u64 i_zerofill:1;
2533 u64 i_rsvd_2:3;
2534 u64 i_notify:1;
2535 u64 i_rsvd_1:3;
2536 u64 i_poison:1;
2537 u64 i_rsvd:55;
2538 } ii_ibct0_fld_s;
2539} ii_ibct0_u_t;
2540
2541/************************************************************************
2542 * *
2543 * This register contains the address to which the WINV is sent. *
2544 * This address has to be cache line aligned. *
2545 * *
2546 ************************************************************************/
2547
2548typedef union ii_ibna0_u {
2549 u64 ii_ibna0_regval;
2550 struct {
2551 u64 i_rsvd_1:7;
2552 u64 i_addr:42;
2553 u64 i_rsvd:15;
2554 } ii_ibna0_fld_s;
2555} ii_ibna0_u_t;
2556
2557/************************************************************************
2558 * *
2559 * This register contains the programmable level as well as the node *
2560 * ID and PI unit of the processor to which the interrupt will be *
2561 * sent. *
2562 * *
2563 ************************************************************************/
2564
2565typedef union ii_ibia0_u {
2566 u64 ii_ibia0_regval;
2567 struct {
2568 u64 i_rsvd_2:1;
2569 u64 i_node_id:11;
2570 u64 i_rsvd_1:4;
2571 u64 i_level:7;
2572 u64 i_rsvd:41;
2573 } ii_ibia0_fld_s;
2574} ii_ibia0_u_t;
2575
2576/************************************************************************
2577 * *
2578 * Description: This register is used to set up the length for a *
2579 * transfer and then to monitor the progress of that transfer. This *
2580 * register needs to be initialized before a transfer is started. A *
2581 * legitimate write to this register will set the Busy bit, clear the *
2582 * Error bit, and initialize the length to the value desired. *
2583 * While the transfer is in progress, hardware will decrement the *
2584 * length field with each successful block that is copied. Once the *
2585 * transfer completes, hardware will clear the Busy bit. The length *
2586 * field will also contain the number of cache lines left to be *
2587 * transferred. *
2588 * *
2589 ************************************************************************/
2590
2591typedef union ii_ibls1_u {
2592 u64 ii_ibls1_regval;
2593 struct {
2594 u64 i_length:16;
2595 u64 i_error:1;
2596 u64 i_rsvd_1:3;
2597 u64 i_busy:1;
2598 u64 i_rsvd:43;
2599 } ii_ibls1_fld_s;
2600} ii_ibls1_u_t;
2601
2602/************************************************************************
2603 * *
2604 * This register should be loaded before a transfer is started. The *
2605 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2606 * address as described in Section 1.3, Figure2 and Figure3. Since *
2607 * the bottom 7 bits of the address are always taken to be zero, BTE *
2608 * transfers are always cacheline-aligned. *
2609 * *
2610 ************************************************************************/
2611
2612typedef union ii_ibsa1_u {
2613 u64 ii_ibsa1_regval;
2614 struct {
2615 u64 i_rsvd_1:7;
2616 u64 i_addr:33;
2617 u64 i_rsvd:24;
2618 } ii_ibsa1_fld_s;
2619} ii_ibsa1_u_t;
2620
2621/************************************************************************
2622 * *
2623 * This register should be loaded before a transfer is started. The *
2624 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2625 * address as described in Section 1.3, Figure2 and Figure3. Since *
2626 * the bottom 7 bits of the address are always taken to be zero, BTE *
2627 * transfers are always cacheline-aligned. *
2628 * *
2629 ************************************************************************/
2630
2631typedef union ii_ibda1_u {
2632 u64 ii_ibda1_regval;
2633 struct {
2634 u64 i_rsvd_1:7;
2635 u64 i_addr:33;
2636 u64 i_rsvd:24;
2637 } ii_ibda1_fld_s;
2638} ii_ibda1_u_t;
2639
2640/************************************************************************
2641 * *
2642 * Writing to this register sets up the attributes of the transfer *
2643 * and initiates the transfer operation. Reading this register has *
2644 * the side effect of terminating any transfer in progress. Note: *
2645 * stopping a transfer midstream could have an adverse impact on the *
2646 * other BTE. If a BTE stream has to be stopped (due to error *
2647 * handling for example), both BTE streams should be stopped and *
2648 * their transfers discarded. *
2649 * *
2650 ************************************************************************/
2651
2652typedef union ii_ibct1_u {
2653 u64 ii_ibct1_regval;
2654 struct {
2655 u64 i_zerofill:1;
2656 u64 i_rsvd_2:3;
2657 u64 i_notify:1;
2658 u64 i_rsvd_1:3;
2659 u64 i_poison:1;
2660 u64 i_rsvd:55;
2661 } ii_ibct1_fld_s;
2662} ii_ibct1_u_t;
2663
2664/************************************************************************
2665 * *
2666 * This register contains the address to which the WINV is sent. *
2667 * This address has to be cache line aligned. *
2668 * *
2669 ************************************************************************/
2670
2671typedef union ii_ibna1_u {
2672 u64 ii_ibna1_regval;
2673 struct {
2674 u64 i_rsvd_1:7;
2675 u64 i_addr:33;
2676 u64 i_rsvd:24;
2677 } ii_ibna1_fld_s;
2678} ii_ibna1_u_t;
2679
2680/************************************************************************
2681 * *
2682 * This register contains the programmable level as well as the node *
2683 * ID and PI unit of the processor to which the interrupt will be *
2684 * sent. *
2685 * *
2686 ************************************************************************/
2687
2688typedef union ii_ibia1_u {
2689 u64 ii_ibia1_regval;
2690 struct {
2691 u64 i_pi_id:1;
2692 u64 i_node_id:8;
2693 u64 i_rsvd_1:7;
2694 u64 i_level:7;
2695 u64 i_rsvd:41;
2696 } ii_ibia1_fld_s;
2697} ii_ibia1_u_t;
2698
2699/************************************************************************
2700 * *
2701 * This register defines the resources that feed information into *
2702 * the two performance counters located in the IO Performance *
2703 * Profiling Register. There are 17 different quantities that can be *
2704 * measured. Given these 17 different options, the two performance *
2705 * counters have 15 of them in common; menu selections 0 through 0xE *
2706 * are identical for each performance counter. As for the other two *
2707 * options, one is available from one performance counter and the *
2708 * other is available from the other performance counter. Hence, the *
2709 * II supports all 17*16=272 possible combinations of quantities to *
2710 * measure. *
2711 * *
2712 ************************************************************************/
2713
2714typedef union ii_ipcr_u {
2715 u64 ii_ipcr_regval;
2716 struct {
2717 u64 i_ippr0_c:4;
2718 u64 i_ippr1_c:4;
2719 u64 i_icct:8;
2720 u64 i_rsvd:48;
2721 } ii_ipcr_fld_s;
2722} ii_ipcr_u_t;
2723
2724/************************************************************************
2725 * *
2726 * *
2727 * *
2728 ************************************************************************/
2729
2730typedef union ii_ippr_u {
2731 u64 ii_ippr_regval;
2732 struct {
2733 u64 i_ippr0:32;
2734 u64 i_ippr1:32;
2735 } ii_ippr_fld_s;
2736} ii_ippr_u_t;
2737
2738/************************************************************************
2739 * *
2740 * The following defines which were not formed into structures are *
2741 * probably indentical to another register, and the name of the *
2742 * register is provided against each of these registers. This *
2743 * information needs to be checked carefully *
2744 * *
2745 * IIO_ICRB1_A IIO_ICRB0_A *
2746 * IIO_ICRB1_B IIO_ICRB0_B *
2747 * IIO_ICRB1_C IIO_ICRB0_C *
2748 * IIO_ICRB1_D IIO_ICRB0_D *
2749 * IIO_ICRB1_E IIO_ICRB0_E *
2750 * IIO_ICRB2_A IIO_ICRB0_A *
2751 * IIO_ICRB2_B IIO_ICRB0_B *
2752 * IIO_ICRB2_C IIO_ICRB0_C *
2753 * IIO_ICRB2_D IIO_ICRB0_D *
2754 * IIO_ICRB2_E IIO_ICRB0_E *
2755 * IIO_ICRB3_A IIO_ICRB0_A *
2756 * IIO_ICRB3_B IIO_ICRB0_B *
2757 * IIO_ICRB3_C IIO_ICRB0_C *
2758 * IIO_ICRB3_D IIO_ICRB0_D *
2759 * IIO_ICRB3_E IIO_ICRB0_E *
2760 * IIO_ICRB4_A IIO_ICRB0_A *
2761 * IIO_ICRB4_B IIO_ICRB0_B *
2762 * IIO_ICRB4_C IIO_ICRB0_C *
2763 * IIO_ICRB4_D IIO_ICRB0_D *
2764 * IIO_ICRB4_E IIO_ICRB0_E *
2765 * IIO_ICRB5_A IIO_ICRB0_A *
2766 * IIO_ICRB5_B IIO_ICRB0_B *
2767 * IIO_ICRB5_C IIO_ICRB0_C *
2768 * IIO_ICRB5_D IIO_ICRB0_D *
2769 * IIO_ICRB5_E IIO_ICRB0_E *
2770 * IIO_ICRB6_A IIO_ICRB0_A *
2771 * IIO_ICRB6_B IIO_ICRB0_B *
2772 * IIO_ICRB6_C IIO_ICRB0_C *
2773 * IIO_ICRB6_D IIO_ICRB0_D *
2774 * IIO_ICRB6_E IIO_ICRB0_E *
2775 * IIO_ICRB7_A IIO_ICRB0_A *
2776 * IIO_ICRB7_B IIO_ICRB0_B *
2777 * IIO_ICRB7_C IIO_ICRB0_C *
2778 * IIO_ICRB7_D IIO_ICRB0_D *
2779 * IIO_ICRB7_E IIO_ICRB0_E *
2780 * IIO_ICRB8_A IIO_ICRB0_A *
2781 * IIO_ICRB8_B IIO_ICRB0_B *
2782 * IIO_ICRB8_C IIO_ICRB0_C *
2783 * IIO_ICRB8_D IIO_ICRB0_D *
2784 * IIO_ICRB8_E IIO_ICRB0_E *
2785 * IIO_ICRB9_A IIO_ICRB0_A *
2786 * IIO_ICRB9_B IIO_ICRB0_B *
2787 * IIO_ICRB9_C IIO_ICRB0_C *
2788 * IIO_ICRB9_D IIO_ICRB0_D *
2789 * IIO_ICRB9_E IIO_ICRB0_E *
2790 * IIO_ICRBA_A IIO_ICRB0_A *
2791 * IIO_ICRBA_B IIO_ICRB0_B *
2792 * IIO_ICRBA_C IIO_ICRB0_C *
2793 * IIO_ICRBA_D IIO_ICRB0_D *
2794 * IIO_ICRBA_E IIO_ICRB0_E *
2795 * IIO_ICRBB_A IIO_ICRB0_A *
2796 * IIO_ICRBB_B IIO_ICRB0_B *
2797 * IIO_ICRBB_C IIO_ICRB0_C *
2798 * IIO_ICRBB_D IIO_ICRB0_D *
2799 * IIO_ICRBB_E IIO_ICRB0_E *
2800 * IIO_ICRBC_A IIO_ICRB0_A *
2801 * IIO_ICRBC_B IIO_ICRB0_B *
2802 * IIO_ICRBC_C IIO_ICRB0_C *
2803 * IIO_ICRBC_D IIO_ICRB0_D *
2804 * IIO_ICRBC_E IIO_ICRB0_E *
2805 * IIO_ICRBD_A IIO_ICRB0_A *
2806 * IIO_ICRBD_B IIO_ICRB0_B *
2807 * IIO_ICRBD_C IIO_ICRB0_C *
2808 * IIO_ICRBD_D IIO_ICRB0_D *
2809 * IIO_ICRBD_E IIO_ICRB0_E *
2810 * IIO_ICRBE_A IIO_ICRB0_A *
2811 * IIO_ICRBE_B IIO_ICRB0_B *
2812 * IIO_ICRBE_C IIO_ICRB0_C *
2813 * IIO_ICRBE_D IIO_ICRB0_D *
2814 * IIO_ICRBE_E IIO_ICRB0_E *
2815 * *
2816 ************************************************************************/
2817
2818/*
2819 * Slightly friendlier names for some common registers.
2820 */
2821#define IIO_WIDGET IIO_WID /* Widget identification */
2822#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */
2823#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */
2824#define IIO_PROTECT IIO_ILAPR /* IO interface protection */
2825#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */
2826#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */
2827#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */
2828#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */
2829#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */
2830#define IIO_LLP_LOG IIO_ILLR /* LLP log */
2831#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout */
2832#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */
2833#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */
2834#define IIO_IGFX_0 IIO_IGFX0
2835#define IIO_IGFX_1 IIO_IGFX1
2836#define IIO_IBCT_0 IIO_IBCT0
2837#define IIO_IBCT_1 IIO_IBCT1
2838#define IIO_IBLS_0 IIO_IBLS0
2839#define IIO_IBLS_1 IIO_IBLS1
2840#define IIO_IBSA_0 IIO_IBSA0
2841#define IIO_IBSA_1 IIO_IBSA1
2842#define IIO_IBDA_0 IIO_IBDA0
2843#define IIO_IBDA_1 IIO_IBDA1
2844#define IIO_IBNA_0 IIO_IBNA0
2845#define IIO_IBNA_1 IIO_IBNA1
2846#define IIO_IBIA_0 IIO_IBIA0
2847#define IIO_IBIA_1 IIO_IBIA1
2848#define IIO_IOPRB_0 IIO_IPRB0
2849
2850#define IIO_PRTE_A(_x) (IIO_IPRTE0_A + (8 * (_x)))
2851#define IIO_PRTE_B(_x) (IIO_IPRTE0_B + (8 * (_x)))
2852#define IIO_NUM_PRTES 8 /* Total number of PRB table entries */
2853#define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
2854#define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */
2855
2856#define IIO_NUM_IPRBS 9
2857
2858#define IIO_LLP_CSR_IS_UP 0x00002000
2859#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
2860#define IIO_LLP_CSR_LLP_STAT_SHFT 12
2861
2862#define IIO_LLP_CB_MAX 0xffff /* in ILLR CB_CNT, Max Check Bit errors */
2863#define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */
2864
2865/* key to IIO_PROTECT_OVRRD */
2866#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */
2867
2868/* BTE register names */
2869#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */
2870#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */
2871#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */
2872#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */
2873#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */
2874#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */
2875#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */
2876#define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */
2877
2878/* BTE register offsets from base */
2879#define BTEOFF_STAT 0
2880#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
2881#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
2882#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
2883#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
2884#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
2885
2886/* names used in shub diags */
2887#define IIO_BASE_BTE0 IIO_IBLS_0
2888#define IIO_BASE_BTE1 IIO_IBLS_1
2889
2890/*
2891 * Macro which takes the widget number, and returns the
2892 * IO PRB address of that widget.
2893 * value _x is expected to be a widget number in the range
2894 * 0, 8 - 0xF
2895 */
2896#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
2897 (_x) : \
2898 (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
2899
2900/* GFX Flow Control Node/Widget Register */
2901#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */
2902#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
2903#define IIO_IGFX_W_NUM_SHIFT 0
2904#define IIO_IGFX_PI_NUM_BITS 1 /* size of PI num field */
2905#define IIO_IGFX_PI_NUM_MASK ((1<<IIO_IGFX_PI_NUM_BITS)-1)
2906#define IIO_IGFX_PI_NUM_SHIFT 4
2907#define IIO_IGFX_N_NUM_BITS 8 /* size of node num field */
2908#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
2909#define IIO_IGFX_N_NUM_SHIFT 5
2910#define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */
2911#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
2912#define IIO_IGFX_P_NUM_SHIFT 16
2913#define IIO_IGFX_INIT(widget, pi, node, cpu) (\
2914 (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \
2915 (((pi) & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)| \
2916 (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \
2917 (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
2918
2919/* Scratch registers (all bits available) */
2920#define IIO_SCRATCH_REG0 IIO_ISCR0
2921#define IIO_SCRATCH_REG1 IIO_ISCR1
2922#define IIO_SCRATCH_MASK 0xffffffffffffffffUL
2923
2924#define IIO_SCRATCH_BIT0_0 0x0000000000000001UL
2925#define IIO_SCRATCH_BIT0_1 0x0000000000000002UL
2926#define IIO_SCRATCH_BIT0_2 0x0000000000000004UL
2927#define IIO_SCRATCH_BIT0_3 0x0000000000000008UL
2928#define IIO_SCRATCH_BIT0_4 0x0000000000000010UL
2929#define IIO_SCRATCH_BIT0_5 0x0000000000000020UL
2930#define IIO_SCRATCH_BIT0_6 0x0000000000000040UL
2931#define IIO_SCRATCH_BIT0_7 0x0000000000000080UL
2932#define IIO_SCRATCH_BIT0_8 0x0000000000000100UL
2933#define IIO_SCRATCH_BIT0_9 0x0000000000000200UL
2934#define IIO_SCRATCH_BIT0_A 0x0000000000000400UL
2935
2936#define IIO_SCRATCH_BIT1_0 0x0000000000000001UL
2937#define IIO_SCRATCH_BIT1_1 0x0000000000000002UL
2938/* IO Translation Table Entries */
2939#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */
2940 /* Hw manuals number them 1..7! */
2941/*
2942 * IIO_IMEM Register fields.
2943 */
2944#define IIO_IMEM_W0ESD 0x1UL /* Widget 0 shut down due to error */
2945#define IIO_IMEM_B0ESD (1UL << 4) /* BTE 0 shut down due to error */
2946#define IIO_IMEM_B1ESD (1UL << 8) /* BTE 1 Shut down due to error */
2947
2948/*
2949 * As a permanent workaround for a bug in the PI side of the shub, we've
2950 * redefined big window 7 as small window 0.
2951 XXX does this still apply for SN1??
2952 */
2953#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
2954
2955/*
2956 * Use the top big window as a surrogate for the first small window
2957 */
2958#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
2959
2960#define ILCSR_WARM_RESET 0x100
2961
2962/*
2963 * CRB manipulation macros
2964 * The CRB macros are slightly complicated, since there are up to
2965 * four registers associated with each CRB entry.
2966 */
2967#define IIO_NUM_CRBS 15 /* Number of CRBs */
2968#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */
2969#define IIO_ICRB_OFFSET 8
2970#define IIO_ICRB_0 IIO_ICRB0_A
2971#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
2972/* XXX - This is now tuneable:
2973 #define IIO_FIRST_PC_ENTRY 12
2974 */
2975
2976#define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))))
2977#define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET))
2978#define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET))
2979#define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET))
2980#define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET))
2981
2982#define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7)
2983
2984/*
2985 * values for "ecode" field
2986 */
2987#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */
2988#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */
2989#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access
2990 * e.g. WINV to a Read only line. */
2991#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */
2992#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */
2993#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */
2994#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */
2995#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */
2996
2997/*
2998 * Values for field imsgtype
2999 */
3000#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */
3001#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */
3002#define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */
3003#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */
3004
3005/*
3006 * values for field initiator.
3007 */
3008#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */
3009#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */
3010#define IIO_ICRB_INIT_SN1NET 0x2 /* Message originated in SN1net */
3011#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */
3012#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */
3013
3014/*
3015 * Number of credits Hub widget has while sending req/response to
3016 * xbow.
3017 * Value of 3 is required by Xbow 1.1
3018 * We may be able to increase this to 4 with Xbow 1.2.
3019 */
3020#define HUBII_XBOW_CREDIT 3
3021#define HUBII_XBOW_REV2_CREDIT 4
3022
3023/*
3024 * Number of credits that xtalk devices should use when communicating
3025 * with a SHub (depth of SHub's queue).
3026 */
3027#define HUB_CREDIT 4
3028
3029/*
3030 * Some IIO_PRB fields
3031 */
3032#define IIO_PRB_MULTI_ERR (1LL << 63)
3033#define IIO_PRB_SPUR_RD (1LL << 51)
3034#define IIO_PRB_SPUR_WR (1LL << 50)
3035#define IIO_PRB_RD_TO (1LL << 49)
3036#define IIO_PRB_ERROR (1LL << 48)
3037
3038/*************************************************************************
3039
3040 Some of the IIO field masks and shifts are defined here.
3041 This is in order to maintain compatibility in SN0 and SN1 code
3042
3043**************************************************************************/
3044
3045/*
3046 * ICMR register fields
3047 * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not
3048 * present in SHub)
3049 */
3050
3051#define IIO_ICMR_CRB_VLD_SHFT 20
3052#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
3053
3054#define IIO_ICMR_FC_CNT_SHFT 16
3055#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT)
3056
3057#define IIO_ICMR_C_CNT_SHFT 4
3058#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT)
3059
3060#define IIO_ICMR_PRECISE (1UL << 52)
3061#define IIO_ICMR_CLR_RPPD (1UL << 13)
3062#define IIO_ICMR_CLR_RQPD (1UL << 12)
3063
3064/*
3065 * IIO PIO Deallocation register field masks : (IIO_IPDR)
3066 XXX present but not needed in bedrock? See the manual.
3067 */
3068#define IIO_IPDR_PND (1 << 4)
3069
3070/*
3071 * IIO CRB deallocation register field masks: (IIO_ICDR)
3072 */
3073#define IIO_ICDR_PND (1 << 4)
3074
3075/*
3076 * IO BTE Length/Status (IIO_IBLS) register bit field definitions
3077 */
3078#define IBLS_BUSY (0x1UL << 20)
3079#define IBLS_ERROR_SHFT 16
3080#define IBLS_ERROR (0x1UL << IBLS_ERROR_SHFT)
3081#define IBLS_LENGTH_MASK 0xffff
3082
3083/*
3084 * IO BTE Control/Terminate register (IBCT) register bit field definitions
3085 */
3086#define IBCT_POISON (0x1UL << 8)
3087#define IBCT_NOTIFY (0x1UL << 4)
3088#define IBCT_ZFIL_MODE (0x1UL << 0)
3089
3090/*
3091 * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2)
3092 */
3093#define IIEPH1_VALID (1UL << 44)
3094#define IIEPH1_OVERRUN (1UL << 40)
3095#define IIEPH1_ERR_TYPE_SHFT 32
3096#define IIEPH1_ERR_TYPE_MASK 0xf
3097#define IIEPH1_SOURCE_SHFT 20
3098#define IIEPH1_SOURCE_MASK 11
3099#define IIEPH1_SUPPL_SHFT 8
3100#define IIEPH1_SUPPL_MASK 11
3101#define IIEPH1_CMD_SHFT 0
3102#define IIEPH1_CMD_MASK 7
3103
3104#define IIEPH2_TAIL (1UL << 40)
3105#define IIEPH2_ADDRESS_SHFT 0
3106#define IIEPH2_ADDRESS_MASK 38
3107
3108#define IIEPH1_ERR_SHORT_REQ 2
3109#define IIEPH1_ERR_SHORT_REPLY 3
3110#define IIEPH1_ERR_LONG_REQ 4
3111#define IIEPH1_ERR_LONG_REPLY 5
3112
3113/*
3114 * IO Error Clear register bit field definitions
3115 */
3116#define IECLR_PI1_FWD_INT (1UL << 31) /* clear PI1_FORWARD_INT in iidsr */
3117#define IECLR_PI0_FWD_INT (1UL << 30) /* clear PI0_FORWARD_INT in iidsr */
3118#define IECLR_SPUR_RD_HDR (1UL << 29) /* clear valid bit in ixss reg */
3119#define IECLR_BTE1 (1UL << 18) /* clear bte error 1 */
3120#define IECLR_BTE0 (1UL << 17) /* clear bte error 0 */
3121#define IECLR_CRAZY (1UL << 16) /* clear crazy bit in wstat reg */
3122#define IECLR_PRB_F (1UL << 15) /* clear err bit in PRB_F reg */
3123#define IECLR_PRB_E (1UL << 14) /* clear err bit in PRB_E reg */
3124#define IECLR_PRB_D (1UL << 13) /* clear err bit in PRB_D reg */
3125#define IECLR_PRB_C (1UL << 12) /* clear err bit in PRB_C reg */
3126#define IECLR_PRB_B (1UL << 11) /* clear err bit in PRB_B reg */
3127#define IECLR_PRB_A (1UL << 10) /* clear err bit in PRB_A reg */
3128#define IECLR_PRB_9 (1UL << 9) /* clear err bit in PRB_9 reg */
3129#define IECLR_PRB_8 (1UL << 8) /* clear err bit in PRB_8 reg */
3130#define IECLR_PRB_0 (1UL << 0) /* clear err bit in PRB_0 reg */
3131
3132/*
3133 * IIO CRB control register Fields: IIO_ICCR
3134 */
3135#define IIO_ICCR_PENDING 0x10000
3136#define IIO_ICCR_CMD_MASK 0xFF
3137#define IIO_ICCR_CMD_SHFT 7
3138#define IIO_ICCR_CMD_NOP 0x0 /* No Op */
3139#define IIO_ICCR_CMD_WAKE 0x100 /* Reactivate CRB entry and process */
3140#define IIO_ICCR_CMD_TIMEOUT 0x200 /* Make CRB timeout & mark invalid */
3141#define IIO_ICCR_CMD_EJECT 0x400 /* Contents of entry written to memory
3142 * via a WB
3143 */
3144#define IIO_ICCR_CMD_FLUSH 0x800
3145
3146/*
3147 *
3148 * CRB Register description.
3149 *
3150 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3151 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3152 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3153 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3154 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3155 *
3156 * Many of the fields in CRB are status bits used by hardware
3157 * for implementation of the protocol. It's very dangerous to
3158 * mess around with the CRB registers.
3159 *
3160 * It's OK to read the CRB registers and try to make sense out of the
3161 * fields in CRB.
3162 *
3163 * Updating CRB requires all activities in Hub IIO to be quiesced.
3164 * otherwise, a write to CRB could corrupt other CRB entries.
3165 * CRBs are here only as a back door peek to shub IIO's status.
3166 * Quiescing implies no dmas no PIOs
3167 * either directly from the cpu or from sn0net.
3168 * this is not something that can be done easily. So, AVOID updating
3169 * CRBs.
3170 */
3171
3172/*
3173 * Easy access macros for CRBs, all 5 registers (A-E)
3174 */
3175typedef ii_icrb0_a_u_t icrba_t;
3176#define a_sidn ii_icrb0_a_fld_s.ia_sidn
3177#define a_tnum ii_icrb0_a_fld_s.ia_tnum
3178#define a_addr ii_icrb0_a_fld_s.ia_addr
3179#define a_valid ii_icrb0_a_fld_s.ia_vld
3180#define a_iow ii_icrb0_a_fld_s.ia_iow
3181#define a_regvalue ii_icrb0_a_regval
3182
3183typedef ii_icrb0_b_u_t icrbb_t;
3184#define b_use_old ii_icrb0_b_fld_s.ib_use_old
3185#define b_imsgtype ii_icrb0_b_fld_s.ib_imsgtype
3186#define b_imsg ii_icrb0_b_fld_s.ib_imsg
3187#define b_initiator ii_icrb0_b_fld_s.ib_init
3188#define b_exc ii_icrb0_b_fld_s.ib_exc
3189#define b_ackcnt ii_icrb0_b_fld_s.ib_ack_cnt
3190#define b_resp ii_icrb0_b_fld_s.ib_resp
3191#define b_ack ii_icrb0_b_fld_s.ib_ack
3192#define b_hold ii_icrb0_b_fld_s.ib_hold
3193#define b_wb ii_icrb0_b_fld_s.ib_wb
3194#define b_intvn ii_icrb0_b_fld_s.ib_intvn
3195#define b_stall_ib ii_icrb0_b_fld_s.ib_stall_ib
3196#define b_stall_int ii_icrb0_b_fld_s.ib_stall__intr
3197#define b_stall_bte_0 ii_icrb0_b_fld_s.ib_stall__bte_0
3198#define b_stall_bte_1 ii_icrb0_b_fld_s.ib_stall__bte_1
3199#define b_error ii_icrb0_b_fld_s.ib_error
3200#define b_ecode ii_icrb0_b_fld_s.ib_errcode
3201#define b_lnetuce ii_icrb0_b_fld_s.ib_ln_uce
3202#define b_mark ii_icrb0_b_fld_s.ib_mark
3203#define b_xerr ii_icrb0_b_fld_s.ib_xt_err
3204#define b_regvalue ii_icrb0_b_regval
3205
3206typedef ii_icrb0_c_u_t icrbc_t;
3207#define c_suppl ii_icrb0_c_fld_s.ic_suppl
3208#define c_barrop ii_icrb0_c_fld_s.ic_bo
3209#define c_doresp ii_icrb0_c_fld_s.ic_resprqd
3210#define c_gbr ii_icrb0_c_fld_s.ic_gbr
3211#define c_btenum ii_icrb0_c_fld_s.ic_bte_num
3212#define c_cohtrans ii_icrb0_c_fld_s.ic_ct
3213#define c_xtsize ii_icrb0_c_fld_s.ic_size
3214#define c_source ii_icrb0_c_fld_s.ic_source
3215#define c_regvalue ii_icrb0_c_regval
3216
3217typedef ii_icrb0_d_u_t icrbd_t;
3218#define d_sleep ii_icrb0_d_fld_s.id_sleep
3219#define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt
3220#define d_pripsc ii_icrb0_d_fld_s.id_pr_psc
3221#define d_bteop ii_icrb0_d_fld_s.id_bte_op
3222#define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */
3223#define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */
3224#define d_regvalue ii_icrb0_d_regval
3225
3226typedef ii_icrb0_e_u_t icrbe_t;
3227#define icrbe_ctxtvld ii_icrb0_e_fld_s.ie_cvld
3228#define icrbe_toutvld ii_icrb0_e_fld_s.ie_tvld
3229#define icrbe_context ii_icrb0_e_fld_s.ie_context
3230#define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout
3231#define e_regvalue ii_icrb0_e_regval
3232
3233/* Number of widgets supported by shub */
3234#define HUB_NUM_WIDGET 9
3235#define HUB_WIDGET_ID_MIN 0x8
3236#define HUB_WIDGET_ID_MAX 0xf
3237
3238#define HUB_WIDGET_PART_NUM 0xc120
3239#define MAX_HUBS_PER_XBOW 2
3240
3241/* A few more #defines for backwards compatibility */
3242#define iprb_t ii_iprb0_u_t
3243#define iprb_regval ii_iprb0_regval
3244#define iprb_mult_err ii_iprb0_fld_s.i_mult_err
3245#define iprb_spur_rd ii_iprb0_fld_s.i_spur_rd
3246#define iprb_spur_wr ii_iprb0_fld_s.i_spur_wr
3247#define iprb_rd_to ii_iprb0_fld_s.i_rd_to
3248#define iprb_ovflow ii_iprb0_fld_s.i_of_cnt
3249#define iprb_error ii_iprb0_fld_s.i_error
3250#define iprb_ff ii_iprb0_fld_s.i_f
3251#define iprb_mode ii_iprb0_fld_s.i_m
3252#define iprb_bnakctr ii_iprb0_fld_s.i_nb
3253#define iprb_anakctr ii_iprb0_fld_s.i_na
3254#define iprb_xtalkctr ii_iprb0_fld_s.i_c
3255
3256#define LNK_STAT_WORKING 0x2 /* LLP is working */
3257
3258#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */
3259#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */
3260#define IIO_WSTAT_TXRETRY_MASK 0x7F /* should be 0xFF?? */
3261#define IIO_WSTAT_TXRETRY_SHFT 16
3262#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
3263 IIO_WSTAT_TXRETRY_MASK)
3264
3265/* Number of II perf. counters we can multiplex at once */
3266
3267#define IO_PERF_SETS 32
3268
3269/* Bit for the widget in inbound access register */
3270#define IIO_IIWA_WIDGET(_w) ((u64)(1ULL << _w))
3271/* Bit for the widget in outbound access register */
3272#define IIO_IOWA_WIDGET(_w) ((u64)(1ULL << _w))
3273
3274/* NOTE: The following define assumes that we are going to get
3275 * widget numbers from 8 thru F and the device numbers within
3276 * widget from 0 thru 7.
3277 */
3278#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((u64)(1ULL << (8 * ((w) - 8) + (d))))
3279
3280/* IO Interrupt Destination Register */
3281#define IIO_IIDSR_SENT_SHIFT 28
3282#define IIO_IIDSR_SENT_MASK 0x30000000
3283#define IIO_IIDSR_ENB_SHIFT 24
3284#define IIO_IIDSR_ENB_MASK 0x01000000
3285#define IIO_IIDSR_NODE_SHIFT 9
3286#define IIO_IIDSR_NODE_MASK 0x000ff700
3287#define IIO_IIDSR_PI_ID_SHIFT 8
3288#define IIO_IIDSR_PI_ID_MASK 0x00000100
3289#define IIO_IIDSR_LVL_SHIFT 0
3290#define IIO_IIDSR_LVL_MASK 0x000000ff
3291
3292/* Xtalk timeout threshhold register (IIO_IXTT) */
3293#define IXTT_RRSP_TO_SHFT 55 /* read response timeout */
3294#define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT)
3295#define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */
3296#define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
3297#define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */
3298#define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
3299
3300/*
3301 * The IO LLP control status register and widget control register
3302 */
3303
3304typedef union hubii_wcr_u {
3305 u64 wcr_reg_value;
3306 struct {
3307 u64 wcr_widget_id:4, /* LLP crossbar credit */
3308 wcr_tag_mode:1, /* Tag mode */
3309 wcr_rsvd1:8, /* Reserved */
3310 wcr_xbar_crd:3, /* LLP crossbar credit */
3311 wcr_f_bad_pkt:1, /* Force bad llp pkt enable */
3312 wcr_dir_con:1, /* widget direct connect */
3313 wcr_e_thresh:5, /* elasticity threshold */
3314 wcr_rsvd:41; /* unused */
3315 } wcr_fields_s;
3316} hubii_wcr_t;
3317
3318#define iwcr_dir_con wcr_fields_s.wcr_dir_con
3319
3320/* The structures below are defined to extract and modify the ii
3321performance registers */
3322
3323/* io_perf_sel allows the caller to specify what tests will be
3324 performed */
3325
3326typedef union io_perf_sel {
3327 u64 perf_sel_reg;
3328 struct {
3329 u64 perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48;
3330 } perf_sel_bits;
3331} io_perf_sel_t;
3332
3333/* io_perf_cnt is to extract the count from the shub registers. Due to
3334 hardware problems there is only one counter, not two. */
3335
3336typedef union io_perf_cnt {
3337 u64 perf_cnt;
3338 struct {
3339 u64 perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32;
3340 } perf_cnt_bits;
3341
3342} io_perf_cnt_t;
3343
3344typedef union iprte_a {
3345 u64 entry;
3346 struct {
3347 u64 i_rsvd_1:3;
3348 u64 i_addr:38;
3349 u64 i_init:3;
3350 u64 i_source:8;
3351 u64 i_rsvd:2;
3352 u64 i_widget:4;
3353 u64 i_to_cnt:5;
3354 u64 i_vld:1;
3355 } iprte_fields;
3356} iprte_a_t;
3357
3358#endif /* _ASM_IA64_SN_SHUBIO_H */
diff --git a/include/asm-ia64/sn/simulator.h b/include/asm-ia64/sn/simulator.h
deleted file mode 100644
index c2611f6cfe33..000000000000
--- a/include/asm-ia64/sn/simulator.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
6 */
7
8#ifndef _ASM_IA64_SN_SIMULATOR_H
9#define _ASM_IA64_SN_SIMULATOR_H
10
11#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2) || defined(CONFIG_IA64_SGI_UV)
12#define SNMAGIC 0xaeeeeeee8badbeefL
13#define IS_MEDUSA() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
14
15#define SIMULATOR_SLEEP() asm("nop.i 0x8beef")
16#define IS_RUNNING_ON_SIMULATOR() (sn_prom_type)
17#define IS_RUNNING_ON_FAKE_PROM() (sn_prom_type == 2)
18extern int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
19#else
20#define IS_MEDUSA() 0
21#define SIMULATOR_SLEEP()
22#define IS_RUNNING_ON_SIMULATOR() 0
23#endif
24
25#endif /* _ASM_IA64_SN_SIMULATOR_H */
diff --git a/include/asm-ia64/sn/sn2/sn_hwperf.h b/include/asm-ia64/sn/sn2/sn_hwperf.h
deleted file mode 100644
index e61ebac38cdd..000000000000
--- a/include/asm-ia64/sn/sn2/sn_hwperf.h
+++ /dev/null
@@ -1,242 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
7 *
8 * Data types used by the SN_SAL_HWPERF_OP SAL call for monitoring
9 * SGI Altix node and router hardware
10 *
11 * Mark Goodwin <markgw@sgi.com> Mon Aug 30 12:23:46 EST 2004
12 */
13
14#ifndef SN_HWPERF_H
15#define SN_HWPERF_H
16
17/*
18 * object structure. SN_HWPERF_ENUM_OBJECTS and SN_HWPERF_GET_CPU_INFO
19 * return an array of these. Do not change this without also
20 * changing the corresponding SAL code.
21 */
22#define SN_HWPERF_MAXSTRING 128
23struct sn_hwperf_object_info {
24 u32 id;
25 union {
26 struct {
27 u64 this_part:1;
28 u64 is_shared:1;
29 } fields;
30 struct {
31 u64 flags;
32 u64 reserved;
33 } b;
34 } f;
35 char name[SN_HWPERF_MAXSTRING];
36 char location[SN_HWPERF_MAXSTRING];
37 u32 ports;
38};
39
40#define sn_hwp_this_part f.fields.this_part
41#define sn_hwp_is_shared f.fields.is_shared
42#define sn_hwp_flags f.b.flags
43
44/* macros for object classification */
45#define SN_HWPERF_IS_NODE(x) ((x) && strstr((x)->name, "SHub"))
46#define SN_HWPERF_IS_NODE_SHUB2(x) ((x) && strstr((x)->name, "SHub 2."))
47#define SN_HWPERF_IS_IONODE(x) ((x) && strstr((x)->name, "TIO"))
48#define SN_HWPERF_IS_NL3ROUTER(x) ((x) && strstr((x)->name, "NL3Router"))
49#define SN_HWPERF_IS_NL4ROUTER(x) ((x) && strstr((x)->name, "NL4Router"))
50#define SN_HWPERF_IS_OLDROUTER(x) ((x) && strstr((x)->name, "Router"))
51#define SN_HWPERF_IS_ROUTER(x) (SN_HWPERF_IS_NL3ROUTER(x) || \
52 SN_HWPERF_IS_NL4ROUTER(x) || \
53 SN_HWPERF_IS_OLDROUTER(x))
54#define SN_HWPERF_FOREIGN(x) ((x) && !(x)->sn_hwp_this_part && !(x)->sn_hwp_is_shared)
55#define SN_HWPERF_SAME_OBJTYPE(x,y) ((SN_HWPERF_IS_NODE(x) && SN_HWPERF_IS_NODE(y)) ||\
56 (SN_HWPERF_IS_IONODE(x) && SN_HWPERF_IS_IONODE(y)) ||\
57 (SN_HWPERF_IS_ROUTER(x) && SN_HWPERF_IS_ROUTER(y)))
58
59/* numa port structure, SN_HWPERF_ENUM_PORTS returns an array of these */
60struct sn_hwperf_port_info {
61 u32 port;
62 u32 conn_id;
63 u32 conn_port;
64};
65
66/* for HWPERF_{GET,SET}_MMRS */
67struct sn_hwperf_data {
68 u64 addr;
69 u64 data;
70};
71
72/* user ioctl() argument, see below */
73struct sn_hwperf_ioctl_args {
74 u64 arg; /* argument, usually an object id */
75 u64 sz; /* size of transfer */
76 void *ptr; /* pointer to source/target */
77 u32 v0; /* second return value */
78};
79
80/*
81 * For SN_HWPERF_{GET,SET}_MMRS and SN_HWPERF_OBJECT_DISTANCE,
82 * sn_hwperf_ioctl_args.arg can be used to specify a CPU on which
83 * to call SAL, and whether to use an interprocessor interrupt
84 * or task migration in order to do so. If the CPU specified is
85 * SN_HWPERF_ARG_ANY_CPU, then the current CPU will be used.
86 */
87#define SN_HWPERF_ARG_ANY_CPU 0x7fffffffUL
88#define SN_HWPERF_ARG_CPU_MASK 0x7fffffff00000000ULL
89#define SN_HWPERF_ARG_USE_IPI_MASK 0x8000000000000000ULL
90#define SN_HWPERF_ARG_OBJID_MASK 0x00000000ffffffffULL
91
92/*
93 * ioctl requests on the "sn_hwperf" misc device that call SAL.
94 */
95#define SN_HWPERF_OP_MEM_COPYIN 0x1000
96#define SN_HWPERF_OP_MEM_COPYOUT 0x2000
97#define SN_HWPERF_OP_MASK 0x0fff
98
99/*
100 * Determine mem requirement.
101 * arg don't care
102 * sz 8
103 * p pointer to u64 integer
104 */
105#define SN_HWPERF_GET_HEAPSIZE 1
106
107/*
108 * Install mem for SAL drvr
109 * arg don't care
110 * sz sizeof buffer pointed to by p
111 * p pointer to buffer for scratch area
112 */
113#define SN_HWPERF_INSTALL_HEAP 2
114
115/*
116 * Determine number of objects
117 * arg don't care
118 * sz 8
119 * p pointer to u64 integer
120 */
121#define SN_HWPERF_OBJECT_COUNT (10|SN_HWPERF_OP_MEM_COPYOUT)
122
123/*
124 * Determine object "distance", relative to a cpu. This operation can
125 * execute on a designated logical cpu number, using either an IPI or
126 * via task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
127 * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
128 *
129 * arg bitmap of IPI flag, cpu number and object id
130 * sz 8
131 * p pointer to u64 integer
132 */
133#define SN_HWPERF_OBJECT_DISTANCE (11|SN_HWPERF_OP_MEM_COPYOUT)
134
135/*
136 * Enumerate objects. Special case if sz == 8, returns the required
137 * buffer size.
138 * arg don't care
139 * sz sizeof buffer pointed to by p
140 * p pointer to array of struct sn_hwperf_object_info
141 */
142#define SN_HWPERF_ENUM_OBJECTS (12|SN_HWPERF_OP_MEM_COPYOUT)
143
144/*
145 * Enumerate NumaLink ports for an object. Special case if sz == 8,
146 * returns the required buffer size.
147 * arg object id
148 * sz sizeof buffer pointed to by p
149 * p pointer to array of struct sn_hwperf_port_info
150 */
151#define SN_HWPERF_ENUM_PORTS (13|SN_HWPERF_OP_MEM_COPYOUT)
152
153/*
154 * SET/GET memory mapped registers. These operations can execute
155 * on a designated logical cpu number, using either an IPI or via
156 * task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
157 * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
158 *
159 * arg bitmap of ipi flag, cpu number and object id
160 * sz sizeof buffer pointed to by p
161 * p pointer to array of struct sn_hwperf_data
162 */
163#define SN_HWPERF_SET_MMRS (14|SN_HWPERF_OP_MEM_COPYIN)
164#define SN_HWPERF_GET_MMRS (15|SN_HWPERF_OP_MEM_COPYOUT| \
165 SN_HWPERF_OP_MEM_COPYIN)
166/*
167 * Lock a shared object
168 * arg object id
169 * sz don't care
170 * p don't care
171 */
172#define SN_HWPERF_ACQUIRE 16
173
174/*
175 * Unlock a shared object
176 * arg object id
177 * sz don't care
178 * p don't care
179 */
180#define SN_HWPERF_RELEASE 17
181
182/*
183 * Break a lock on a shared object
184 * arg object id
185 * sz don't care
186 * p don't care
187 */
188#define SN_HWPERF_FORCE_RELEASE 18
189
190/*
191 * ioctl requests on "sn_hwperf" that do not call SAL
192 */
193
194/*
195 * get cpu info as an array of hwperf_object_info_t.
196 * id is logical CPU number, name is description, location
197 * is geoid (e.g. 001c04#1c). Special case if sz == 8,
198 * returns the required buffer size.
199 *
200 * arg don't care
201 * sz sizeof buffer pointed to by p
202 * p pointer to array of struct sn_hwperf_object_info
203 */
204#define SN_HWPERF_GET_CPU_INFO (100|SN_HWPERF_OP_MEM_COPYOUT)
205
206/*
207 * Given an object id, return it's node number (aka cnode).
208 * arg object id
209 * sz 8
210 * p pointer to u64 integer
211 */
212#define SN_HWPERF_GET_OBJ_NODE (101|SN_HWPERF_OP_MEM_COPYOUT)
213
214/*
215 * Given a node number (cnode), return it's nasid.
216 * arg ordinal node number (aka cnodeid)
217 * sz 8
218 * p pointer to u64 integer
219 */
220#define SN_HWPERF_GET_NODE_NASID (102|SN_HWPERF_OP_MEM_COPYOUT)
221
222/*
223 * Given a node id, determine the id of the nearest node with CPUs
224 * and the id of the nearest node that has memory. The argument
225 * node would normally be a "headless" node, e.g. an "IO node".
226 * Return 0 on success.
227 */
228extern int sn_hwperf_get_nearest_node(cnodeid_t node,
229 cnodeid_t *near_mem, cnodeid_t *near_cpu);
230
231/* return codes */
232#define SN_HWPERF_OP_OK 0
233#define SN_HWPERF_OP_NOMEM 1
234#define SN_HWPERF_OP_NO_PERM 2
235#define SN_HWPERF_OP_IO_ERROR 3
236#define SN_HWPERF_OP_BUSY 4
237#define SN_HWPERF_OP_RECONFIGURE 253
238#define SN_HWPERF_OP_INVAL 254
239
240int sn_topology_open(struct inode *inode, struct file *file);
241int sn_topology_release(struct inode *inode, struct file *file);
242#endif /* SN_HWPERF_H */
diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h
deleted file mode 100644
index a676dd9ace3e..000000000000
--- a/include/asm-ia64/sn/sn_cpuid.h
+++ /dev/null
@@ -1,132 +0,0 @@
1/*
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
8 */
9
10
11#ifndef _ASM_IA64_SN_SN_CPUID_H
12#define _ASM_IA64_SN_SN_CPUID_H
13
14#include <linux/smp.h>
15#include <asm/sn/addrs.h>
16#include <asm/sn/pda.h>
17#include <asm/intrinsics.h>
18
19
20/*
21 * Functions for converting between cpuids, nodeids and NASIDs.
22 *
23 * These are for SGI platforms only.
24 *
25 */
26
27
28
29
30/*
31 * Definitions of terms (these definitions are for IA64 ONLY. Other architectures
32 * use cpuid/cpunum quite defferently):
33 *
34 * CPUID - a number in range of 0..NR_CPUS-1 that uniquely identifies
35 * the cpu. The value cpuid has no significance on IA64 other than
36 * the boot cpu is 0.
37 * smp_processor_id() returns the cpuid of the current cpu.
38 *
39 * CPU_PHYSICAL_ID (also known as HARD_PROCESSOR_ID)
40 * This is the same as 31:24 of the processor LID register
41 * hard_smp_processor_id()- cpu_physical_id of current processor
42 * cpu_physical_id(cpuid) - convert a <cpuid> to a <physical_cpuid>
43 * cpu_logical_id(phy_id) - convert a <physical_cpuid> to a <cpuid>
44 * * not real efficient - don't use in perf critical code
45 *
46 * SLICE - a number in the range of 0 - 3 (typically) that represents the
47 * cpu number on a brick.
48 *
49 * SUBNODE - (almost obsolete) the number of the FSB that a cpu is
50 * connected to. This is also the same as the PI number. Usually 0 or 1.
51 *
52 * NOTE!!!: the value of the bits in the cpu physical id (SAPICid or LID) of a cpu has no
53 * significance. The SAPIC id (LID) is a 16-bit cookie that has meaning only to the PROM.
54 *
55 *
56 * The macros convert between cpu physical ids & slice/nasid/cnodeid.
57 * These terms are described below:
58 *
59 *
60 * Brick
61 * ----- ----- ----- ----- CPU
62 * | 0 | | 1 | | 0 | | 1 | SLICE
63 * ----- ----- ----- -----
64 * | | | |
65 * | | | |
66 * 0 | | 2 0 | | 2 FSB SLOT
67 * ------- -------
68 * | |
69 * | |
70 * | |
71 * ------------ -------------
72 * | | | |
73 * | SHUB | | SHUB | NASID (0..MAX_NASIDS)
74 * | |----- | | CNODEID (0..num_compact_nodes-1)
75 * | | | |
76 * | | | |
77 * ------------ -------------
78 * | |
79 *
80 *
81 */
82
83#define get_node_number(addr) NASID_GET(addr)
84
85/*
86 * NOTE: on non-MP systems, only cpuid 0 exists
87 */
88
89extern short physical_node_map[]; /* indexed by nasid to get cnode */
90
91/*
92 * Macros for retrieving info about current cpu
93 */
94#define get_nasid() (sn_nodepda->phys_cpuid[smp_processor_id()].nasid)
95#define get_subnode() (sn_nodepda->phys_cpuid[smp_processor_id()].subnode)
96#define get_slice() (sn_nodepda->phys_cpuid[smp_processor_id()].slice)
97#define get_cnode() (sn_nodepda->phys_cpuid[smp_processor_id()].cnode)
98#define get_sapicid() ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff)
99
100/*
101 * Macros for retrieving info about an arbitrary cpu
102 * cpuid - logical cpu id
103 */
104#define cpuid_to_nasid(cpuid) (sn_nodepda->phys_cpuid[cpuid].nasid)
105#define cpuid_to_subnode(cpuid) (sn_nodepda->phys_cpuid[cpuid].subnode)
106#define cpuid_to_slice(cpuid) (sn_nodepda->phys_cpuid[cpuid].slice)
107
108
109/*
110 * Dont use the following in performance critical code. They require scans
111 * of potentially large tables.
112 */
113extern int nasid_slice_to_cpuid(int, int);
114
115/*
116 * cnodeid_to_nasid - convert a cnodeid to a NASID
117 */
118#define cnodeid_to_nasid(cnodeid) (sn_cnodeid_to_nasid[cnodeid])
119
120/*
121 * nasid_to_cnodeid - convert a NASID to a cnodeid
122 */
123#define nasid_to_cnodeid(nasid) (physical_node_map[nasid])
124
125/*
126 * partition_coherence_id - get the coherence ID of the current partition
127 */
128extern u8 sn_coherency_id;
129#define partition_coherence_id() (sn_coherency_id)
130
131#endif /* _ASM_IA64_SN_SN_CPUID_H */
132
diff --git a/include/asm-ia64/sn/sn_feature_sets.h b/include/asm-ia64/sn/sn_feature_sets.h
deleted file mode 100644
index 8e83ac117ace..000000000000
--- a/include/asm-ia64/sn/sn_feature_sets.h
+++ /dev/null
@@ -1,58 +0,0 @@
1#ifndef _ASM_IA64_SN_FEATURE_SETS_H
2#define _ASM_IA64_SN_FEATURE_SETS_H
3
4/*
5 * SN PROM Features
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 *
11 * Copyright (c) 2005-2006 Silicon Graphics, Inc. All rights reserved.
12 */
13
14
15/* --------------------- PROM Features -----------------------------*/
16extern int sn_prom_feature_available(int id);
17
18#define MAX_PROM_FEATURE_SETS 2
19
20/*
21 * The following defines features that may or may not be supported by the
22 * current PROM. The OS uses sn_prom_feature_available(feature) to test for
23 * the presence of a PROM feature. Down rev (old) PROMs will always test
24 * "false" for new features.
25 *
26 * Use:
27 * if (sn_prom_feature_available(PRF_XXX))
28 * ...
29 */
30
31#define PRF_PAL_CACHE_FLUSH_SAFE 0
32#define PRF_DEVICE_FLUSH_LIST 1
33#define PRF_HOTPLUG_SUPPORT 2
34#define PRF_CPU_DISABLE_SUPPORT 3
35
36/* --------------------- OS Features -------------------------------*/
37
38/*
39 * The following defines OS features that are optionally present in
40 * the operating system.
41 * During boot, PROM is notified of these features via a series of calls:
42 *
43 * ia64_sn_set_os_feature(feature1);
44 *
45 * Once enabled, a feature cannot be disabled.
46 *
47 * By default, features are disabled unless explicitly enabled.
48 *
49 * These defines must be kept in sync with the corresponding
50 * PROM definitions in feature_sets.h.
51 */
52#define OSF_MCA_SLV_TO_OS_INIT_SLV 0
53#define OSF_FEAT_LOG_SBES 1
54#define OSF_ACPI_ENABLE 2
55#define OSF_PCISEGMENT_ENABLE 3
56
57
58#endif /* _ASM_IA64_SN_FEATURE_SETS_H */
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
deleted file mode 100644
index 676b31a08c61..000000000000
--- a/include/asm-ia64/sn/sn_sal.h
+++ /dev/null
@@ -1,1188 +0,0 @@
1#ifndef _ASM_IA64_SN_SN_SAL_H
2#define _ASM_IA64_SN_SN_SAL_H
3
4/*
5 * System Abstraction Layer definitions for IA64
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 *
11 * Copyright (c) 2000-2006 Silicon Graphics, Inc. All rights reserved.
12 */
13
14
15#include <asm/sal.h>
16#include <asm/sn/sn_cpuid.h>
17#include <asm/sn/arch.h>
18#include <asm/sn/geo.h>
19#include <asm/sn/nodepda.h>
20#include <asm/sn/shub_mmr.h>
21
22// SGI Specific Calls
23#define SN_SAL_POD_MODE 0x02000001
24#define SN_SAL_SYSTEM_RESET 0x02000002
25#define SN_SAL_PROBE 0x02000003
26#define SN_SAL_GET_MASTER_NASID 0x02000004
27#define SN_SAL_GET_KLCONFIG_ADDR 0x02000005
28#define SN_SAL_LOG_CE 0x02000006
29#define SN_SAL_REGISTER_CE 0x02000007
30#define SN_SAL_GET_PARTITION_ADDR 0x02000009
31#define SN_SAL_XP_ADDR_REGION 0x0200000f
32#define SN_SAL_NO_FAULT_ZONE_VIRTUAL 0x02000010
33#define SN_SAL_NO_FAULT_ZONE_PHYSICAL 0x02000011
34#define SN_SAL_PRINT_ERROR 0x02000012
35#define SN_SAL_REGISTER_PMI_HANDLER 0x02000014
36#define SN_SAL_SET_ERROR_HANDLING_FEATURES 0x0200001a // reentrant
37#define SN_SAL_GET_FIT_COMPT 0x0200001b // reentrant
38#define SN_SAL_GET_SAPIC_INFO 0x0200001d
39#define SN_SAL_GET_SN_INFO 0x0200001e
40#define SN_SAL_CONSOLE_PUTC 0x02000021
41#define SN_SAL_CONSOLE_GETC 0x02000022
42#define SN_SAL_CONSOLE_PUTS 0x02000023
43#define SN_SAL_CONSOLE_GETS 0x02000024
44#define SN_SAL_CONSOLE_GETS_TIMEOUT 0x02000025
45#define SN_SAL_CONSOLE_POLL 0x02000026
46#define SN_SAL_CONSOLE_INTR 0x02000027
47#define SN_SAL_CONSOLE_PUTB 0x02000028
48#define SN_SAL_CONSOLE_XMIT_CHARS 0x0200002a
49#define SN_SAL_CONSOLE_READC 0x0200002b
50#define SN_SAL_SYSCTL_OP 0x02000030
51#define SN_SAL_SYSCTL_MODID_GET 0x02000031
52#define SN_SAL_SYSCTL_GET 0x02000032
53#define SN_SAL_SYSCTL_IOBRICK_MODULE_GET 0x02000033
54#define SN_SAL_SYSCTL_IO_PORTSPEED_GET 0x02000035
55#define SN_SAL_SYSCTL_SLAB_GET 0x02000036
56#define SN_SAL_BUS_CONFIG 0x02000037
57#define SN_SAL_SYS_SERIAL_GET 0x02000038
58#define SN_SAL_PARTITION_SERIAL_GET 0x02000039
59#define SN_SAL_SYSCTL_PARTITION_GET 0x0200003a
60#define SN_SAL_SYSTEM_POWER_DOWN 0x0200003b
61#define SN_SAL_GET_MASTER_BASEIO_NASID 0x0200003c
62#define SN_SAL_COHERENCE 0x0200003d
63#define SN_SAL_MEMPROTECT 0x0200003e
64#define SN_SAL_SYSCTL_FRU_CAPTURE 0x0200003f
65
66#define SN_SAL_SYSCTL_IOBRICK_PCI_OP 0x02000042 // reentrant
67#define SN_SAL_IROUTER_OP 0x02000043
68#define SN_SAL_SYSCTL_EVENT 0x02000044
69#define SN_SAL_IOIF_INTERRUPT 0x0200004a
70#define SN_SAL_HWPERF_OP 0x02000050 // lock
71#define SN_SAL_IOIF_ERROR_INTERRUPT 0x02000051
72#define SN_SAL_IOIF_PCI_SAFE 0x02000052
73#define SN_SAL_IOIF_SLOT_ENABLE 0x02000053
74#define SN_SAL_IOIF_SLOT_DISABLE 0x02000054
75#define SN_SAL_IOIF_GET_HUBDEV_INFO 0x02000055
76#define SN_SAL_IOIF_GET_PCIBUS_INFO 0x02000056
77#define SN_SAL_IOIF_GET_PCIDEV_INFO 0x02000057
78#define SN_SAL_IOIF_GET_WIDGET_DMAFLUSH_LIST 0x02000058 // deprecated
79#define SN_SAL_IOIF_GET_DEVICE_DMAFLUSH_LIST 0x0200005a
80
81#define SN_SAL_IOIF_INIT 0x0200005f
82#define SN_SAL_HUB_ERROR_INTERRUPT 0x02000060
83#define SN_SAL_BTE_RECOVER 0x02000061
84#define SN_SAL_RESERVED_DO_NOT_USE 0x02000062
85#define SN_SAL_IOIF_GET_PCI_TOPOLOGY 0x02000064
86
87#define SN_SAL_GET_PROM_FEATURE_SET 0x02000065
88#define SN_SAL_SET_OS_FEATURE_SET 0x02000066
89#define SN_SAL_INJECT_ERROR 0x02000067
90#define SN_SAL_SET_CPU_NUMBER 0x02000068
91
92#define SN_SAL_KERNEL_LAUNCH_EVENT 0x02000069
93
94/*
95 * Service-specific constants
96 */
97
98/* Console interrupt manipulation */
99 /* action codes */
100#define SAL_CONSOLE_INTR_OFF 0 /* turn the interrupt off */
101#define SAL_CONSOLE_INTR_ON 1 /* turn the interrupt on */
102#define SAL_CONSOLE_INTR_STATUS 2 /* retrieve the interrupt status */
103 /* interrupt specification & status return codes */
104#define SAL_CONSOLE_INTR_XMIT 1 /* output interrupt */
105#define SAL_CONSOLE_INTR_RECV 2 /* input interrupt */
106
107/* interrupt handling */
108#define SAL_INTR_ALLOC 1
109#define SAL_INTR_FREE 2
110#define SAL_INTR_REDIRECT 3
111
112/*
113 * operations available on the generic SN_SAL_SYSCTL_OP
114 * runtime service
115 */
116#define SAL_SYSCTL_OP_IOBOARD 0x0001 /* retrieve board type */
117#define SAL_SYSCTL_OP_TIO_JLCK_RST 0x0002 /* issue TIO clock reset */
118
119/*
120 * IRouter (i.e. generalized system controller) operations
121 */
122#define SAL_IROUTER_OPEN 0 /* open a subchannel */
123#define SAL_IROUTER_CLOSE 1 /* close a subchannel */
124#define SAL_IROUTER_SEND 2 /* send part of an IRouter packet */
125#define SAL_IROUTER_RECV 3 /* receive part of an IRouter packet */
126#define SAL_IROUTER_INTR_STATUS 4 /* check the interrupt status for
127 * an open subchannel
128 */
129#define SAL_IROUTER_INTR_ON 5 /* enable an interrupt */
130#define SAL_IROUTER_INTR_OFF 6 /* disable an interrupt */
131#define SAL_IROUTER_INIT 7 /* initialize IRouter driver */
132
133/* IRouter interrupt mask bits */
134#define SAL_IROUTER_INTR_XMIT SAL_CONSOLE_INTR_XMIT
135#define SAL_IROUTER_INTR_RECV SAL_CONSOLE_INTR_RECV
136
137/*
138 * Error Handling Features
139 */
140#define SAL_ERR_FEAT_MCA_SLV_TO_OS_INIT_SLV 0x1 // obsolete
141#define SAL_ERR_FEAT_LOG_SBES 0x2 // obsolete
142#define SAL_ERR_FEAT_MFR_OVERRIDE 0x4
143#define SAL_ERR_FEAT_SBE_THRESHOLD 0xffff0000
144
145/*
146 * SAL Error Codes
147 */
148#define SALRET_MORE_PASSES 1
149#define SALRET_OK 0
150#define SALRET_NOT_IMPLEMENTED (-1)
151#define SALRET_INVALID_ARG (-2)
152#define SALRET_ERROR (-3)
153
154#define SN_SAL_FAKE_PROM 0x02009999
155
156/**
157 * sn_sal_revision - get the SGI SAL revision number
158 *
159 * The SGI PROM stores its version in the sal_[ab]_rev_(major|minor).
160 * This routine simply extracts the major and minor values and
161 * presents them in a u32 format.
162 *
163 * For example, version 4.05 would be represented at 0x0405.
164 */
165static inline u32
166sn_sal_rev(void)
167{
168 struct ia64_sal_systab *systab = __va(efi.sal_systab);
169
170 return (u32)(systab->sal_b_rev_major << 8 | systab->sal_b_rev_minor);
171}
172
173/*
174 * Returns the master console nasid, if the call fails, return an illegal
175 * value.
176 */
177static inline u64
178ia64_sn_get_console_nasid(void)
179{
180 struct ia64_sal_retval ret_stuff;
181
182 ret_stuff.status = 0;
183 ret_stuff.v0 = 0;
184 ret_stuff.v1 = 0;
185 ret_stuff.v2 = 0;
186 SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_NASID, 0, 0, 0, 0, 0, 0, 0);
187
188 if (ret_stuff.status < 0)
189 return ret_stuff.status;
190
191 /* Master console nasid is in 'v0' */
192 return ret_stuff.v0;
193}
194
195/*
196 * Returns the master baseio nasid, if the call fails, return an illegal
197 * value.
198 */
199static inline u64
200ia64_sn_get_master_baseio_nasid(void)
201{
202 struct ia64_sal_retval ret_stuff;
203
204 ret_stuff.status = 0;
205 ret_stuff.v0 = 0;
206 ret_stuff.v1 = 0;
207 ret_stuff.v2 = 0;
208 SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_BASEIO_NASID, 0, 0, 0, 0, 0, 0, 0);
209
210 if (ret_stuff.status < 0)
211 return ret_stuff.status;
212
213 /* Master baseio nasid is in 'v0' */
214 return ret_stuff.v0;
215}
216
217static inline void *
218ia64_sn_get_klconfig_addr(nasid_t nasid)
219{
220 struct ia64_sal_retval ret_stuff;
221
222 ret_stuff.status = 0;
223 ret_stuff.v0 = 0;
224 ret_stuff.v1 = 0;
225 ret_stuff.v2 = 0;
226 SAL_CALL(ret_stuff, SN_SAL_GET_KLCONFIG_ADDR, (u64)nasid, 0, 0, 0, 0, 0, 0);
227 return ret_stuff.v0 ? __va(ret_stuff.v0) : NULL;
228}
229
230/*
231 * Returns the next console character.
232 */
233static inline u64
234ia64_sn_console_getc(int *ch)
235{
236 struct ia64_sal_retval ret_stuff;
237
238 ret_stuff.status = 0;
239 ret_stuff.v0 = 0;
240 ret_stuff.v1 = 0;
241 ret_stuff.v2 = 0;
242 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_GETC, 0, 0, 0, 0, 0, 0, 0);
243
244 /* character is in 'v0' */
245 *ch = (int)ret_stuff.v0;
246
247 return ret_stuff.status;
248}
249
250/*
251 * Read a character from the SAL console device, after a previous interrupt
252 * or poll operation has given us to know that a character is available
253 * to be read.
254 */
255static inline u64
256ia64_sn_console_readc(void)
257{
258 struct ia64_sal_retval ret_stuff;
259
260 ret_stuff.status = 0;
261 ret_stuff.v0 = 0;
262 ret_stuff.v1 = 0;
263 ret_stuff.v2 = 0;
264 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_READC, 0, 0, 0, 0, 0, 0, 0);
265
266 /* character is in 'v0' */
267 return ret_stuff.v0;
268}
269
270/*
271 * Sends the given character to the console.
272 */
273static inline u64
274ia64_sn_console_putc(char ch)
275{
276 struct ia64_sal_retval ret_stuff;
277
278 ret_stuff.status = 0;
279 ret_stuff.v0 = 0;
280 ret_stuff.v1 = 0;
281 ret_stuff.v2 = 0;
282 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (u64)ch, 0, 0, 0, 0, 0, 0);
283
284 return ret_stuff.status;
285}
286
287/*
288 * Sends the given buffer to the console.
289 */
290static inline u64
291ia64_sn_console_putb(const char *buf, int len)
292{
293 struct ia64_sal_retval ret_stuff;
294
295 ret_stuff.status = 0;
296 ret_stuff.v0 = 0;
297 ret_stuff.v1 = 0;
298 ret_stuff.v2 = 0;
299 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (u64)buf, (u64)len, 0, 0, 0, 0, 0);
300
301 if ( ret_stuff.status == 0 ) {
302 return ret_stuff.v0;
303 }
304 return (u64)0;
305}
306
307/*
308 * Print a platform error record
309 */
310static inline u64
311ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec)
312{
313 struct ia64_sal_retval ret_stuff;
314
315 ret_stuff.status = 0;
316 ret_stuff.v0 = 0;
317 ret_stuff.v1 = 0;
318 ret_stuff.v2 = 0;
319 SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (u64)hook, (u64)rec, 0, 0, 0, 0, 0);
320
321 return ret_stuff.status;
322}
323
324/*
325 * Check for Platform errors
326 */
327static inline u64
328ia64_sn_plat_cpei_handler(void)
329{
330 struct ia64_sal_retval ret_stuff;
331
332 ret_stuff.status = 0;
333 ret_stuff.v0 = 0;
334 ret_stuff.v1 = 0;
335 ret_stuff.v2 = 0;
336 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_LOG_CE, 0, 0, 0, 0, 0, 0, 0);
337
338 return ret_stuff.status;
339}
340
341/*
342 * Set Error Handling Features (Obsolete)
343 */
344static inline u64
345ia64_sn_plat_set_error_handling_features(void)
346{
347 struct ia64_sal_retval ret_stuff;
348
349 ret_stuff.status = 0;
350 ret_stuff.v0 = 0;
351 ret_stuff.v1 = 0;
352 ret_stuff.v2 = 0;
353 SAL_CALL_REENTRANT(ret_stuff, SN_SAL_SET_ERROR_HANDLING_FEATURES,
354 SAL_ERR_FEAT_LOG_SBES,
355 0, 0, 0, 0, 0, 0);
356
357 return ret_stuff.status;
358}
359
360/*
361 * Checks for console input.
362 */
363static inline u64
364ia64_sn_console_check(int *result)
365{
366 struct ia64_sal_retval ret_stuff;
367
368 ret_stuff.status = 0;
369 ret_stuff.v0 = 0;
370 ret_stuff.v1 = 0;
371 ret_stuff.v2 = 0;
372 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_POLL, 0, 0, 0, 0, 0, 0, 0);
373
374 /* result is in 'v0' */
375 *result = (int)ret_stuff.v0;
376
377 return ret_stuff.status;
378}
379
380/*
381 * Checks console interrupt status
382 */
383static inline u64
384ia64_sn_console_intr_status(void)
385{
386 struct ia64_sal_retval ret_stuff;
387
388 ret_stuff.status = 0;
389 ret_stuff.v0 = 0;
390 ret_stuff.v1 = 0;
391 ret_stuff.v2 = 0;
392 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR,
393 0, SAL_CONSOLE_INTR_STATUS,
394 0, 0, 0, 0, 0);
395
396 if (ret_stuff.status == 0) {
397 return ret_stuff.v0;
398 }
399
400 return 0;
401}
402
403/*
404 * Enable an interrupt on the SAL console device.
405 */
406static inline void
407ia64_sn_console_intr_enable(u64 intr)
408{
409 struct ia64_sal_retval ret_stuff;
410
411 ret_stuff.status = 0;
412 ret_stuff.v0 = 0;
413 ret_stuff.v1 = 0;
414 ret_stuff.v2 = 0;
415 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR,
416 intr, SAL_CONSOLE_INTR_ON,
417 0, 0, 0, 0, 0);
418}
419
420/*
421 * Disable an interrupt on the SAL console device.
422 */
423static inline void
424ia64_sn_console_intr_disable(u64 intr)
425{
426 struct ia64_sal_retval ret_stuff;
427
428 ret_stuff.status = 0;
429 ret_stuff.v0 = 0;
430 ret_stuff.v1 = 0;
431 ret_stuff.v2 = 0;
432 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR,
433 intr, SAL_CONSOLE_INTR_OFF,
434 0, 0, 0, 0, 0);
435}
436
437/*
438 * Sends a character buffer to the console asynchronously.
439 */
440static inline u64
441ia64_sn_console_xmit_chars(char *buf, int len)
442{
443 struct ia64_sal_retval ret_stuff;
444
445 ret_stuff.status = 0;
446 ret_stuff.v0 = 0;
447 ret_stuff.v1 = 0;
448 ret_stuff.v2 = 0;
449 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_XMIT_CHARS,
450 (u64)buf, (u64)len,
451 0, 0, 0, 0, 0);
452
453 if (ret_stuff.status == 0) {
454 return ret_stuff.v0;
455 }
456
457 return 0;
458}
459
460/*
461 * Returns the iobrick module Id
462 */
463static inline u64
464ia64_sn_sysctl_iobrick_module_get(nasid_t nasid, int *result)
465{
466 struct ia64_sal_retval ret_stuff;
467
468 ret_stuff.status = 0;
469 ret_stuff.v0 = 0;
470 ret_stuff.v1 = 0;
471 ret_stuff.v2 = 0;
472 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYSCTL_IOBRICK_MODULE_GET, nasid, 0, 0, 0, 0, 0, 0);
473
474 /* result is in 'v0' */
475 *result = (int)ret_stuff.v0;
476
477 return ret_stuff.status;
478}
479
480/**
481 * ia64_sn_pod_mode - call the SN_SAL_POD_MODE function
482 *
483 * SN_SAL_POD_MODE actually takes an argument, but it's always
484 * 0 when we call it from the kernel, so we don't have to expose
485 * it to the caller.
486 */
487static inline u64
488ia64_sn_pod_mode(void)
489{
490 struct ia64_sal_retval isrv;
491 SAL_CALL_REENTRANT(isrv, SN_SAL_POD_MODE, 0, 0, 0, 0, 0, 0, 0);
492 if (isrv.status)
493 return 0;
494 return isrv.v0;
495}
496
497/**
498 * ia64_sn_probe_mem - read from memory safely
499 * @addr: address to probe
500 * @size: number bytes to read (1,2,4,8)
501 * @data_ptr: address to store value read by probe (-1 returned if probe fails)
502 *
503 * Call into the SAL to do a memory read. If the read generates a machine
504 * check, this routine will recover gracefully and return -1 to the caller.
505 * @addr is usually a kernel virtual address in uncached space (i.e. the
506 * address starts with 0xc), but if called in physical mode, @addr should
507 * be a physical address.
508 *
509 * Return values:
510 * 0 - probe successful
511 * 1 - probe failed (generated MCA)
512 * 2 - Bad arg
513 * <0 - PAL error
514 */
515static inline u64
516ia64_sn_probe_mem(long addr, long size, void *data_ptr)
517{
518 struct ia64_sal_retval isrv;
519
520 SAL_CALL(isrv, SN_SAL_PROBE, addr, size, 0, 0, 0, 0, 0);
521
522 if (data_ptr) {
523 switch (size) {
524 case 1:
525 *((u8*)data_ptr) = (u8)isrv.v0;
526 break;
527 case 2:
528 *((u16*)data_ptr) = (u16)isrv.v0;
529 break;
530 case 4:
531 *((u32*)data_ptr) = (u32)isrv.v0;
532 break;
533 case 8:
534 *((u64*)data_ptr) = (u64)isrv.v0;
535 break;
536 default:
537 isrv.status = 2;
538 }
539 }
540 return isrv.status;
541}
542
543/*
544 * Retrieve the system serial number as an ASCII string.
545 */
546static inline u64
547ia64_sn_sys_serial_get(char *buf)
548{
549 struct ia64_sal_retval ret_stuff;
550 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYS_SERIAL_GET, buf, 0, 0, 0, 0, 0, 0);
551 return ret_stuff.status;
552}
553
554extern char sn_system_serial_number_string[];
555extern u64 sn_partition_serial_number;
556
557static inline char *
558sn_system_serial_number(void) {
559 if (sn_system_serial_number_string[0]) {
560 return(sn_system_serial_number_string);
561 } else {
562 ia64_sn_sys_serial_get(sn_system_serial_number_string);
563 return(sn_system_serial_number_string);
564 }
565}
566
567
568/*
569 * Returns a unique id number for this system and partition (suitable for
570 * use with license managers), based in part on the system serial number.
571 */
572static inline u64
573ia64_sn_partition_serial_get(void)
574{
575 struct ia64_sal_retval ret_stuff;
576 ia64_sal_oemcall_reentrant(&ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0,
577 0, 0, 0, 0, 0, 0);
578 if (ret_stuff.status != 0)
579 return 0;
580 return ret_stuff.v0;
581}
582
583static inline u64
584sn_partition_serial_number_val(void) {
585 if (unlikely(sn_partition_serial_number == 0)) {
586 sn_partition_serial_number = ia64_sn_partition_serial_get();
587 }
588 return sn_partition_serial_number;
589}
590
591/*
592 * Returns the partition id of the nasid passed in as an argument,
593 * or INVALID_PARTID if the partition id cannot be retrieved.
594 */
595static inline partid_t
596ia64_sn_sysctl_partition_get(nasid_t nasid)
597{
598 struct ia64_sal_retval ret_stuff;
599 SAL_CALL(ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid,
600 0, 0, 0, 0, 0, 0);
601 if (ret_stuff.status != 0)
602 return -1;
603 return ((partid_t)ret_stuff.v0);
604}
605
606/*
607 * Returns the physical address of the partition's reserved page through
608 * an iterative number of calls.
609 *
610 * On first call, 'cookie' and 'len' should be set to 0, and 'addr'
611 * set to the nasid of the partition whose reserved page's address is
612 * being sought.
613 * On subsequent calls, pass the values, that were passed back on the
614 * previous call.
615 *
616 * While the return status equals SALRET_MORE_PASSES, keep calling
617 * this function after first copying 'len' bytes starting at 'addr'
618 * into 'buf'. Once the return status equals SALRET_OK, 'addr' will
619 * be the physical address of the partition's reserved page. If the
620 * return status equals neither of these, an error as occurred.
621 */
622static inline s64
623sn_partition_reserved_page_pa(u64 buf, u64 *cookie, u64 *addr, u64 *len)
624{
625 struct ia64_sal_retval rv;
626 ia64_sal_oemcall_reentrant(&rv, SN_SAL_GET_PARTITION_ADDR, *cookie,
627 *addr, buf, *len, 0, 0, 0);
628 *cookie = rv.v0;
629 *addr = rv.v1;
630 *len = rv.v2;
631 return rv.status;
632}
633
634/*
635 * Register or unregister a physical address range being referenced across
636 * a partition boundary for which certain SAL errors should be scanned for,
637 * cleaned up and ignored. This is of value for kernel partitioning code only.
638 * Values for the operation argument:
639 * 1 = register this address range with SAL
640 * 0 = unregister this address range with SAL
641 *
642 * SAL maintains a reference count on an address range in case it is registered
643 * multiple times.
644 *
645 * On success, returns the reference count of the address range after the SAL
646 * call has performed the current registration/unregistration. Returns a
647 * negative value if an error occurred.
648 */
649static inline int
650sn_register_xp_addr_region(u64 paddr, u64 len, int operation)
651{
652 struct ia64_sal_retval ret_stuff;
653 ia64_sal_oemcall(&ret_stuff, SN_SAL_XP_ADDR_REGION, paddr, len,
654 (u64)operation, 0, 0, 0, 0);
655 return ret_stuff.status;
656}
657
658/*
659 * Register or unregister an instruction range for which SAL errors should
660 * be ignored. If an error occurs while in the registered range, SAL jumps
661 * to return_addr after ignoring the error. Values for the operation argument:
662 * 1 = register this instruction range with SAL
663 * 0 = unregister this instruction range with SAL
664 *
665 * Returns 0 on success, or a negative value if an error occurred.
666 */
667static inline int
668sn_register_nofault_code(u64 start_addr, u64 end_addr, u64 return_addr,
669 int virtual, int operation)
670{
671 struct ia64_sal_retval ret_stuff;
672 u64 call;
673 if (virtual) {
674 call = SN_SAL_NO_FAULT_ZONE_VIRTUAL;
675 } else {
676 call = SN_SAL_NO_FAULT_ZONE_PHYSICAL;
677 }
678 ia64_sal_oemcall(&ret_stuff, call, start_addr, end_addr, return_addr,
679 (u64)1, 0, 0, 0);
680 return ret_stuff.status;
681}
682
683/*
684 * Register or unregister a function to handle a PMI received by a CPU.
685 * Before calling the registered handler, SAL sets r1 to the value that
686 * was passed in as the global_pointer.
687 *
688 * If the handler pointer is NULL, then the currently registered handler
689 * will be unregistered.
690 *
691 * Returns 0 on success, or a negative value if an error occurred.
692 */
693static inline int
694sn_register_pmi_handler(u64 handler, u64 global_pointer)
695{
696 struct ia64_sal_retval ret_stuff;
697 ia64_sal_oemcall(&ret_stuff, SN_SAL_REGISTER_PMI_HANDLER, handler,
698 global_pointer, 0, 0, 0, 0, 0);
699 return ret_stuff.status;
700}
701
702/*
703 * Change or query the coherence domain for this partition. Each cpu-based
704 * nasid is represented by a bit in an array of 64-bit words:
705 * 0 = not in this partition's coherency domain
706 * 1 = in this partition's coherency domain
707 *
708 * It is not possible for the local system's nasids to be removed from
709 * the coherency domain. Purpose of the domain arguments:
710 * new_domain = set the coherence domain to the given nasids
711 * old_domain = return the current coherence domain
712 *
713 * Returns 0 on success, or a negative value if an error occurred.
714 */
715static inline int
716sn_change_coherence(u64 *new_domain, u64 *old_domain)
717{
718 struct ia64_sal_retval ret_stuff;
719 ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_COHERENCE, (u64)new_domain,
720 (u64)old_domain, 0, 0, 0, 0, 0);
721 return ret_stuff.status;
722}
723
724/*
725 * Change memory access protections for a physical address range.
726 * nasid_array is not used on Altix, but may be in future architectures.
727 * Available memory protection access classes are defined after the function.
728 */
729static inline int
730sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array)
731{
732 struct ia64_sal_retval ret_stuff;
733
734 ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_MEMPROTECT, paddr, len,
735 (u64)nasid_array, perms, 0, 0, 0);
736 return ret_stuff.status;
737}
738#define SN_MEMPROT_ACCESS_CLASS_0 0x14a080
739#define SN_MEMPROT_ACCESS_CLASS_1 0x2520c2
740#define SN_MEMPROT_ACCESS_CLASS_2 0x14a1ca
741#define SN_MEMPROT_ACCESS_CLASS_3 0x14a290
742#define SN_MEMPROT_ACCESS_CLASS_6 0x084080
743#define SN_MEMPROT_ACCESS_CLASS_7 0x021080
744
745/*
746 * Turns off system power.
747 */
748static inline void
749ia64_sn_power_down(void)
750{
751 struct ia64_sal_retval ret_stuff;
752 SAL_CALL(ret_stuff, SN_SAL_SYSTEM_POWER_DOWN, 0, 0, 0, 0, 0, 0, 0);
753 while(1)
754 cpu_relax();
755 /* never returns */
756}
757
758/**
759 * ia64_sn_fru_capture - tell the system controller to capture hw state
760 *
761 * This routine will call the SAL which will tell the system controller(s)
762 * to capture hw mmr information from each SHub in the system.
763 */
764static inline u64
765ia64_sn_fru_capture(void)
766{
767 struct ia64_sal_retval isrv;
768 SAL_CALL(isrv, SN_SAL_SYSCTL_FRU_CAPTURE, 0, 0, 0, 0, 0, 0, 0);
769 if (isrv.status)
770 return 0;
771 return isrv.v0;
772}
773
774/*
775 * Performs an operation on a PCI bus or slot -- power up, power down
776 * or reset.
777 */
778static inline u64
779ia64_sn_sysctl_iobrick_pci_op(nasid_t n, u64 connection_type,
780 u64 bus, char slot,
781 u64 action)
782{
783 struct ia64_sal_retval rv = {0, 0, 0, 0};
784
785 SAL_CALL_NOLOCK(rv, SN_SAL_SYSCTL_IOBRICK_PCI_OP, connection_type, n, action,
786 bus, (u64) slot, 0, 0);
787 if (rv.status)
788 return rv.v0;
789 return 0;
790}
791
792
793/*
794 * Open a subchannel for sending arbitrary data to the system
795 * controller network via the system controller device associated with
796 * 'nasid'. Return the subchannel number or a negative error code.
797 */
798static inline int
799ia64_sn_irtr_open(nasid_t nasid)
800{
801 struct ia64_sal_retval rv;
802 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_OPEN, nasid,
803 0, 0, 0, 0, 0);
804 return (int) rv.v0;
805}
806
807/*
808 * Close system controller subchannel 'subch' previously opened on 'nasid'.
809 */
810static inline int
811ia64_sn_irtr_close(nasid_t nasid, int subch)
812{
813 struct ia64_sal_retval rv;
814 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_CLOSE,
815 (u64) nasid, (u64) subch, 0, 0, 0, 0);
816 return (int) rv.status;
817}
818
819/*
820 * Read data from system controller associated with 'nasid' on
821 * subchannel 'subch'. The buffer to be filled is pointed to by
822 * 'buf', and its capacity is in the integer pointed to by 'len'. The
823 * referent of 'len' is set to the number of bytes read by the SAL
824 * call. The return value is either SALRET_OK (for bytes read) or
825 * SALRET_ERROR (for error or "no data available").
826 */
827static inline int
828ia64_sn_irtr_recv(nasid_t nasid, int subch, char *buf, int *len)
829{
830 struct ia64_sal_retval rv;
831 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_RECV,
832 (u64) nasid, (u64) subch, (u64) buf, (u64) len,
833 0, 0);
834 return (int) rv.status;
835}
836
837/*
838 * Write data to the system controller network via the system
839 * controller associated with 'nasid' on suchannel 'subch'. The
840 * buffer to be written out is pointed to by 'buf', and 'len' is the
841 * number of bytes to be written. The return value is either the
842 * number of bytes written (which could be zero) or a negative error
843 * code.
844 */
845static inline int
846ia64_sn_irtr_send(nasid_t nasid, int subch, char *buf, int len)
847{
848 struct ia64_sal_retval rv;
849 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_SEND,
850 (u64) nasid, (u64) subch, (u64) buf, (u64) len,
851 0, 0);
852 return (int) rv.v0;
853}
854
855/*
856 * Check whether any interrupts are pending for the system controller
857 * associated with 'nasid' and its subchannel 'subch'. The return
858 * value is a mask of pending interrupts (SAL_IROUTER_INTR_XMIT and/or
859 * SAL_IROUTER_INTR_RECV).
860 */
861static inline int
862ia64_sn_irtr_intr(nasid_t nasid, int subch)
863{
864 struct ia64_sal_retval rv;
865 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_STATUS,
866 (u64) nasid, (u64) subch, 0, 0, 0, 0);
867 return (int) rv.v0;
868}
869
870/*
871 * Enable the interrupt indicated by the intr parameter (either
872 * SAL_IROUTER_INTR_XMIT or SAL_IROUTER_INTR_RECV).
873 */
874static inline int
875ia64_sn_irtr_intr_enable(nasid_t nasid, int subch, u64 intr)
876{
877 struct ia64_sal_retval rv;
878 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_ON,
879 (u64) nasid, (u64) subch, intr, 0, 0, 0);
880 return (int) rv.v0;
881}
882
883/*
884 * Disable the interrupt indicated by the intr parameter (either
885 * SAL_IROUTER_INTR_XMIT or SAL_IROUTER_INTR_RECV).
886 */
887static inline int
888ia64_sn_irtr_intr_disable(nasid_t nasid, int subch, u64 intr)
889{
890 struct ia64_sal_retval rv;
891 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_OFF,
892 (u64) nasid, (u64) subch, intr, 0, 0, 0);
893 return (int) rv.v0;
894}
895
896/*
897 * Set up a node as the point of contact for system controller
898 * environmental event delivery.
899 */
900static inline int
901ia64_sn_sysctl_event_init(nasid_t nasid)
902{
903 struct ia64_sal_retval rv;
904 SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_EVENT, (u64) nasid,
905 0, 0, 0, 0, 0, 0);
906 return (int) rv.v0;
907}
908
909/*
910 * Ask the system controller on the specified nasid to reset
911 * the CX corelet clock. Only valid on TIO nodes.
912 */
913static inline int
914ia64_sn_sysctl_tio_clock_reset(nasid_t nasid)
915{
916 struct ia64_sal_retval rv;
917 SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_TIO_JLCK_RST,
918 nasid, 0, 0, 0, 0, 0);
919 if (rv.status != 0)
920 return (int)rv.status;
921 if (rv.v0 != 0)
922 return (int)rv.v0;
923
924 return 0;
925}
926
927/*
928 * Get the associated ioboard type for a given nasid.
929 */
930static inline s64
931ia64_sn_sysctl_ioboard_get(nasid_t nasid, u16 *ioboard)
932{
933 struct ia64_sal_retval isrv;
934 SAL_CALL_REENTRANT(isrv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_IOBOARD,
935 nasid, 0, 0, 0, 0, 0);
936 if (isrv.v0 != 0) {
937 *ioboard = isrv.v0;
938 return isrv.status;
939 }
940 if (isrv.v1 != 0) {
941 *ioboard = isrv.v1;
942 return isrv.status;
943 }
944
945 return isrv.status;
946}
947
948/**
949 * ia64_sn_get_fit_compt - read a FIT entry from the PROM header
950 * @nasid: NASID of node to read
951 * @index: FIT entry index to be retrieved (0..n)
952 * @fitentry: 16 byte buffer where FIT entry will be stored.
953 * @banbuf: optional buffer for retrieving banner
954 * @banlen: length of banner buffer
955 *
956 * Access to the physical PROM chips needs to be serialized since reads and
957 * writes can't occur at the same time, so we need to call into the SAL when
958 * we want to look at the FIT entries on the chips.
959 *
960 * Returns:
961 * %SALRET_OK if ok
962 * %SALRET_INVALID_ARG if index too big
963 * %SALRET_NOT_IMPLEMENTED if running on older PROM
964 * ??? if nasid invalid OR banner buffer not large enough
965 */
966static inline int
967ia64_sn_get_fit_compt(u64 nasid, u64 index, void *fitentry, void *banbuf,
968 u64 banlen)
969{
970 struct ia64_sal_retval rv;
971 SAL_CALL_NOLOCK(rv, SN_SAL_GET_FIT_COMPT, nasid, index, fitentry,
972 banbuf, banlen, 0, 0);
973 return (int) rv.status;
974}
975
976/*
977 * Initialize the SAL components of the system controller
978 * communication driver; specifically pass in a sizable buffer that
979 * can be used for allocation of subchannel queues as new subchannels
980 * are opened. "buf" points to the buffer, and "len" specifies its
981 * length.
982 */
983static inline int
984ia64_sn_irtr_init(nasid_t nasid, void *buf, int len)
985{
986 struct ia64_sal_retval rv;
987 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INIT,
988 (u64) nasid, (u64) buf, (u64) len, 0, 0, 0);
989 return (int) rv.status;
990}
991
992/*
993 * Returns the nasid, subnode & slice corresponding to a SAPIC ID
994 *
995 * In:
996 * arg0 - SN_SAL_GET_SAPIC_INFO
997 * arg1 - sapicid (lid >> 16)
998 * Out:
999 * v0 - nasid
1000 * v1 - subnode
1001 * v2 - slice
1002 */
1003static inline u64
1004ia64_sn_get_sapic_info(int sapicid, int *nasid, int *subnode, int *slice)
1005{
1006 struct ia64_sal_retval ret_stuff;
1007
1008 ret_stuff.status = 0;
1009 ret_stuff.v0 = 0;
1010 ret_stuff.v1 = 0;
1011 ret_stuff.v2 = 0;
1012 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SAPIC_INFO, sapicid, 0, 0, 0, 0, 0, 0);
1013
1014/***** BEGIN HACK - temp til old proms no longer supported ********/
1015 if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
1016 if (nasid) *nasid = sapicid & 0xfff;
1017 if (subnode) *subnode = (sapicid >> 13) & 1;
1018 if (slice) *slice = (sapicid >> 12) & 3;
1019 return 0;
1020 }
1021/***** END HACK *******/
1022
1023 if (ret_stuff.status < 0)
1024 return ret_stuff.status;
1025
1026 if (nasid) *nasid = (int) ret_stuff.v0;
1027 if (subnode) *subnode = (int) ret_stuff.v1;
1028 if (slice) *slice = (int) ret_stuff.v2;
1029 return 0;
1030}
1031
1032/*
1033 * Returns information about the HUB/SHUB.
1034 * In:
1035 * arg0 - SN_SAL_GET_SN_INFO
1036 * arg1 - 0 (other values reserved for future use)
1037 * Out:
1038 * v0
1039 * [7:0] - shub type (0=shub1, 1=shub2)
1040 * [15:8] - Log2 max number of nodes in entire system (includes
1041 * C-bricks, I-bricks, etc)
1042 * [23:16] - Log2 of nodes per sharing domain
1043 * [31:24] - partition ID
1044 * [39:32] - coherency_id
1045 * [47:40] - regionsize
1046 * v1
1047 * [15:0] - nasid mask (ex., 0x7ff for 11 bit nasid)
1048 * [23:15] - bit position of low nasid bit
1049 */
1050static inline u64
1051ia64_sn_get_sn_info(int fc, u8 *shubtype, u16 *nasid_bitmask, u8 *nasid_shift,
1052 u8 *systemsize, u8 *sharing_domain_size, u8 *partid, u8 *coher, u8 *reg)
1053{
1054 struct ia64_sal_retval ret_stuff;
1055
1056 ret_stuff.status = 0;
1057 ret_stuff.v0 = 0;
1058 ret_stuff.v1 = 0;
1059 ret_stuff.v2 = 0;
1060 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SN_INFO, fc, 0, 0, 0, 0, 0, 0);
1061
1062/***** BEGIN HACK - temp til old proms no longer supported ********/
1063 if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
1064 int nasid = get_sapicid() & 0xfff;
1065#define SH_SHUB_ID_NODES_PER_BIT_MASK 0x001f000000000000UL
1066#define SH_SHUB_ID_NODES_PER_BIT_SHFT 48
1067 if (shubtype) *shubtype = 0;
1068 if (nasid_bitmask) *nasid_bitmask = 0x7ff;
1069 if (nasid_shift) *nasid_shift = 38;
1070 if (systemsize) *systemsize = 10;
1071 if (sharing_domain_size) *sharing_domain_size = 8;
1072 if (partid) *partid = ia64_sn_sysctl_partition_get(nasid);
1073 if (coher) *coher = nasid >> 9;
1074 if (reg) *reg = (HUB_L((u64 *) LOCAL_MMR_ADDR(SH1_SHUB_ID)) & SH_SHUB_ID_NODES_PER_BIT_MASK) >>
1075 SH_SHUB_ID_NODES_PER_BIT_SHFT;
1076 return 0;
1077 }
1078/***** END HACK *******/
1079
1080 if (ret_stuff.status < 0)
1081 return ret_stuff.status;
1082
1083 if (shubtype) *shubtype = ret_stuff.v0 & 0xff;
1084 if (systemsize) *systemsize = (ret_stuff.v0 >> 8) & 0xff;
1085 if (sharing_domain_size) *sharing_domain_size = (ret_stuff.v0 >> 16) & 0xff;
1086 if (partid) *partid = (ret_stuff.v0 >> 24) & 0xff;
1087 if (coher) *coher = (ret_stuff.v0 >> 32) & 0xff;
1088 if (reg) *reg = (ret_stuff.v0 >> 40) & 0xff;
1089 if (nasid_bitmask) *nasid_bitmask = (ret_stuff.v1 & 0xffff);
1090 if (nasid_shift) *nasid_shift = (ret_stuff.v1 >> 16) & 0xff;
1091 return 0;
1092}
1093
1094/*
1095 * This is the access point to the Altix PROM hardware performance
1096 * and status monitoring interface. For info on using this, see
1097 * include/asm-ia64/sn/sn2/sn_hwperf.h
1098 */
1099static inline int
1100ia64_sn_hwperf_op(nasid_t nasid, u64 opcode, u64 a0, u64 a1, u64 a2,
1101 u64 a3, u64 a4, int *v0)
1102{
1103 struct ia64_sal_retval rv;
1104 SAL_CALL_NOLOCK(rv, SN_SAL_HWPERF_OP, (u64)nasid,
1105 opcode, a0, a1, a2, a3, a4);
1106 if (v0)
1107 *v0 = (int) rv.v0;
1108 return (int) rv.status;
1109}
1110
1111static inline int
1112ia64_sn_ioif_get_pci_topology(u64 buf, u64 len)
1113{
1114 struct ia64_sal_retval rv;
1115 SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY, buf, len, 0, 0, 0, 0, 0);
1116 return (int) rv.status;
1117}
1118
1119/*
1120 * BTE error recovery is implemented in SAL
1121 */
1122static inline int
1123ia64_sn_bte_recovery(nasid_t nasid)
1124{
1125 struct ia64_sal_retval rv;
1126
1127 rv.status = 0;
1128 SAL_CALL_NOLOCK(rv, SN_SAL_BTE_RECOVER, (u64)nasid, 0, 0, 0, 0, 0, 0);
1129 if (rv.status == SALRET_NOT_IMPLEMENTED)
1130 return 0;
1131 return (int) rv.status;
1132}
1133
1134static inline int
1135ia64_sn_is_fake_prom(void)
1136{
1137 struct ia64_sal_retval rv;
1138 SAL_CALL_NOLOCK(rv, SN_SAL_FAKE_PROM, 0, 0, 0, 0, 0, 0, 0);
1139 return (rv.status == 0);
1140}
1141
1142static inline int
1143ia64_sn_get_prom_feature_set(int set, unsigned long *feature_set)
1144{
1145 struct ia64_sal_retval rv;
1146
1147 SAL_CALL_NOLOCK(rv, SN_SAL_GET_PROM_FEATURE_SET, set, 0, 0, 0, 0, 0, 0);
1148 if (rv.status != 0)
1149 return rv.status;
1150 *feature_set = rv.v0;
1151 return 0;
1152}
1153
1154static inline int
1155ia64_sn_set_os_feature(int feature)
1156{
1157 struct ia64_sal_retval rv;
1158
1159 SAL_CALL_NOLOCK(rv, SN_SAL_SET_OS_FEATURE_SET, feature, 0, 0, 0, 0, 0, 0);
1160 return rv.status;
1161}
1162
1163static inline int
1164sn_inject_error(u64 paddr, u64 *data, u64 *ecc)
1165{
1166 struct ia64_sal_retval ret_stuff;
1167
1168 ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_INJECT_ERROR, paddr, (u64)data,
1169 (u64)ecc, 0, 0, 0, 0);
1170 return ret_stuff.status;
1171}
1172
1173static inline int
1174ia64_sn_set_cpu_number(int cpu)
1175{
1176 struct ia64_sal_retval rv;
1177
1178 SAL_CALL_NOLOCK(rv, SN_SAL_SET_CPU_NUMBER, cpu, 0, 0, 0, 0, 0, 0);
1179 return rv.status;
1180}
1181static inline int
1182ia64_sn_kernel_launch_event(void)
1183{
1184 struct ia64_sal_retval rv;
1185 SAL_CALL_NOLOCK(rv, SN_SAL_KERNEL_LAUNCH_EVENT, 0, 0, 0, 0, 0, 0, 0);
1186 return rv.status;
1187}
1188#endif /* _ASM_IA64_SN_SN_SAL_H */
diff --git a/include/asm-ia64/sn/tioca.h b/include/asm-ia64/sn/tioca.h
deleted file mode 100644
index 666222d7f0f6..000000000000
--- a/include/asm-ia64/sn/tioca.h
+++ /dev/null
@@ -1,596 +0,0 @@
1#ifndef _ASM_IA64_SN_TIO_TIOCA_H
2#define _ASM_IA64_SN_TIO_TIOCA_H
3
4/*
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
10 */
11
12
13#define TIOCA_PART_NUM 0xE020
14#define TIOCA_MFGR_NUM 0x24
15#define TIOCA_REV_A 0x1
16
17/*
18 * Register layout for TIO:CA. See below for bitmasks for each register.
19 */
20
21struct tioca {
22 u64 ca_id; /* 0x000000 */
23 u64 ca_control1; /* 0x000008 */
24 u64 ca_control2; /* 0x000010 */
25 u64 ca_status1; /* 0x000018 */
26 u64 ca_status2; /* 0x000020 */
27 u64 ca_gart_aperature; /* 0x000028 */
28 u64 ca_gfx_detach; /* 0x000030 */
29 u64 ca_inta_dest_addr; /* 0x000038 */
30 u64 ca_intb_dest_addr; /* 0x000040 */
31 u64 ca_err_int_dest_addr; /* 0x000048 */
32 u64 ca_int_status; /* 0x000050 */
33 u64 ca_int_status_alias; /* 0x000058 */
34 u64 ca_mult_error; /* 0x000060 */
35 u64 ca_mult_error_alias; /* 0x000068 */
36 u64 ca_first_error; /* 0x000070 */
37 u64 ca_int_mask; /* 0x000078 */
38 u64 ca_crm_pkterr_type; /* 0x000080 */
39 u64 ca_crm_pkterr_type_alias; /* 0x000088 */
40 u64 ca_crm_ct_error_detail_1; /* 0x000090 */
41 u64 ca_crm_ct_error_detail_2; /* 0x000098 */
42 u64 ca_crm_tnumto; /* 0x0000A0 */
43 u64 ca_gart_err; /* 0x0000A8 */
44 u64 ca_pcierr_type; /* 0x0000B0 */
45 u64 ca_pcierr_addr; /* 0x0000B8 */
46
47 u64 ca_pad_0000C0[3]; /* 0x0000{C0..D0} */
48
49 u64 ca_pci_rd_buf_flush; /* 0x0000D8 */
50 u64 ca_pci_dma_addr_extn; /* 0x0000E0 */
51 u64 ca_agp_dma_addr_extn; /* 0x0000E8 */
52 u64 ca_force_inta; /* 0x0000F0 */
53 u64 ca_force_intb; /* 0x0000F8 */
54 u64 ca_debug_vector_sel; /* 0x000100 */
55 u64 ca_debug_mux_core_sel; /* 0x000108 */
56 u64 ca_debug_mux_pci_sel; /* 0x000110 */
57 u64 ca_debug_domain_sel; /* 0x000118 */
58
59 u64 ca_pad_000120[28]; /* 0x0001{20..F8} */
60
61 u64 ca_gart_ptr_table; /* 0x200 */
62 u64 ca_gart_tlb_addr[8]; /* 0x2{08..40} */
63};
64
65/*
66 * Mask/shift definitions for TIO:CA registers. The convention here is
67 * to mainly use the names as they appear in the "TIO AEGIS Programmers'
68 * Reference" with a CA_ prefix added. Some exceptions were made to fix
69 * duplicate field names or to generalize fields that are common to
70 * different registers (ca_debug_mux_core_sel and ca_debug_mux_pci_sel for
71 * example).
72 *
73 * Fields consisting of a single bit have a single #define have a single
74 * macro declaration to mask the bit. Fields consisting of multiple bits
75 * have two declarations: one to mask the proper bits in a register, and
76 * a second with the suffix "_SHFT" to identify how far the mask needs to
77 * be shifted right to get its base value.
78 */
79
80/* ==== ca_control1 */
81#define CA_SYS_BIG_END (1ull << 0)
82#define CA_DMA_AGP_SWAP (1ull << 1)
83#define CA_DMA_PCI_SWAP (1ull << 2)
84#define CA_PIO_IO_SWAP (1ull << 3)
85#define CA_PIO_MEM_SWAP (1ull << 4)
86#define CA_GFX_WR_SWAP (1ull << 5)
87#define CA_AGP_FW_ENABLE (1ull << 6)
88#define CA_AGP_CAL_CYCLE (0x7ull << 7)
89#define CA_AGP_CAL_CYCLE_SHFT 7
90#define CA_AGP_CAL_PRSCL_BYP (1ull << 10)
91#define CA_AGP_INIT_CAL_ENB (1ull << 11)
92#define CA_INJ_ADDR_PERR (1ull << 12)
93#define CA_INJ_DATA_PERR (1ull << 13)
94 /* bits 15:14 unused */
95#define CA_PCIM_IO_NBE_AD (0x7ull << 16)
96#define CA_PCIM_IO_NBE_AD_SHFT 16
97#define CA_PCIM_FAST_BTB_ENB (1ull << 19)
98 /* bits 23:20 unused */
99#define CA_PIO_ADDR_OFFSET (0xffull << 24)
100#define CA_PIO_ADDR_OFFSET_SHFT 24
101 /* bits 35:32 unused */
102#define CA_AGPDMA_OP_COMBDELAY (0x1full << 36)
103#define CA_AGPDMA_OP_COMBDELAY_SHFT 36
104 /* bit 41 unused */
105#define CA_AGPDMA_OP_ENB_COMBDELAY (1ull << 42)
106#define CA_PCI_INT_LPCNT (0xffull << 44)
107#define CA_PCI_INT_LPCNT_SHFT 44
108 /* bits 63:52 unused */
109
110/* ==== ca_control2 */
111#define CA_AGP_LATENCY_TO (0xffull << 0)
112#define CA_AGP_LATENCY_TO_SHFT 0
113#define CA_PCI_LATENCY_TO (0xffull << 8)
114#define CA_PCI_LATENCY_TO_SHFT 8
115#define CA_PCI_MAX_RETRY (0x3ffull << 16)
116#define CA_PCI_MAX_RETRY_SHFT 16
117 /* bits 27:26 unused */
118#define CA_RT_INT_EN (0x3ull << 28)
119#define CA_RT_INT_EN_SHFT 28
120#define CA_MSI_INT_ENB (1ull << 30)
121#define CA_PCI_ARB_ERR_ENB (1ull << 31)
122#define CA_GART_MEM_PARAM (0x3ull << 32)
123#define CA_GART_MEM_PARAM_SHFT 32
124#define CA_GART_RD_PREFETCH_ENB (1ull << 34)
125#define CA_GART_WR_PREFETCH_ENB (1ull << 35)
126#define CA_GART_FLUSH_TLB (1ull << 36)
127 /* bits 39:37 unused */
128#define CA_CRM_TNUMTO_PERIOD (0x1fffull << 40)
129#define CA_CRM_TNUMTO_PERIOD_SHFT 40
130 /* bits 55:53 unused */
131#define CA_CRM_TNUMTO_ENB (1ull << 56)
132#define CA_CRM_PRESCALER_BYP (1ull << 57)
133 /* bits 59:58 unused */
134#define CA_CRM_MAX_CREDIT (0x7ull << 60)
135#define CA_CRM_MAX_CREDIT_SHFT 60
136 /* bit 63 unused */
137
138/* ==== ca_status1 */
139#define CA_CORELET_ID (0x3ull << 0)
140#define CA_CORELET_ID_SHFT 0
141#define CA_INTA_N (1ull << 2)
142#define CA_INTB_N (1ull << 3)
143#define CA_CRM_CREDIT_AVAIL (0x7ull << 4)
144#define CA_CRM_CREDIT_AVAIL_SHFT 4
145 /* bit 7 unused */
146#define CA_CRM_SPACE_AVAIL (0x7full << 8)
147#define CA_CRM_SPACE_AVAIL_SHFT 8
148 /* bit 15 unused */
149#define CA_GART_TLB_VAL (0xffull << 16)
150#define CA_GART_TLB_VAL_SHFT 16
151 /* bits 63:24 unused */
152
153/* ==== ca_status2 */
154#define CA_GFX_CREDIT_AVAIL (0xffull << 0)
155#define CA_GFX_CREDIT_AVAIL_SHFT 0
156#define CA_GFX_OPQ_AVAIL (0xffull << 8)
157#define CA_GFX_OPQ_AVAIL_SHFT 8
158#define CA_GFX_WRBUFF_AVAIL (0xffull << 16)
159#define CA_GFX_WRBUFF_AVAIL_SHFT 16
160#define CA_ADMA_OPQ_AVAIL (0xffull << 24)
161#define CA_ADMA_OPQ_AVAIL_SHFT 24
162#define CA_ADMA_WRBUFF_AVAIL (0xffull << 32)
163#define CA_ADMA_WRBUFF_AVAIL_SHFT 32
164#define CA_ADMA_RDBUFF_AVAIL (0x7full << 40)
165#define CA_ADMA_RDBUFF_AVAIL_SHFT 40
166#define CA_PCI_PIO_OP_STAT (1ull << 47)
167#define CA_PDMA_OPQ_AVAIL (0xfull << 48)
168#define CA_PDMA_OPQ_AVAIL_SHFT 48
169#define CA_PDMA_WRBUFF_AVAIL (0xfull << 52)
170#define CA_PDMA_WRBUFF_AVAIL_SHFT 52
171#define CA_PDMA_RDBUFF_AVAIL (0x3ull << 56)
172#define CA_PDMA_RDBUFF_AVAIL_SHFT 56
173 /* bits 63:58 unused */
174
175/* ==== ca_gart_aperature */
176#define CA_GART_AP_ENB_AGP (1ull << 0)
177#define CA_GART_PAGE_SIZE (1ull << 1)
178#define CA_GART_AP_ENB_PCI (1ull << 2)
179 /* bits 11:3 unused */
180#define CA_GART_AP_SIZE (0x3ffull << 12)
181#define CA_GART_AP_SIZE_SHFT 12
182#define CA_GART_AP_BASE (0x3ffffffffffull << 22)
183#define CA_GART_AP_BASE_SHFT 22
184
185/* ==== ca_inta_dest_addr
186 ==== ca_intb_dest_addr
187 ==== ca_err_int_dest_addr */
188 /* bits 2:0 unused */
189#define CA_INT_DEST_ADDR (0x7ffffffffffffull << 3)
190#define CA_INT_DEST_ADDR_SHFT 3
191 /* bits 55:54 unused */
192#define CA_INT_DEST_VECT (0xffull << 56)
193#define CA_INT_DEST_VECT_SHFT 56
194
195/* ==== ca_int_status */
196/* ==== ca_int_status_alias */
197/* ==== ca_mult_error */
198/* ==== ca_mult_error_alias */
199/* ==== ca_first_error */
200/* ==== ca_int_mask */
201#define CA_PCI_ERR (1ull << 0)
202 /* bits 3:1 unused */
203#define CA_GART_FETCH_ERR (1ull << 4)
204#define CA_GFX_WR_OVFLW (1ull << 5)
205#define CA_PIO_REQ_OVFLW (1ull << 6)
206#define CA_CRM_PKTERR (1ull << 7)
207#define CA_CRM_DVERR (1ull << 8)
208#define CA_TNUMTO (1ull << 9)
209#define CA_CXM_RSP_CRED_OVFLW (1ull << 10)
210#define CA_CXM_REQ_CRED_OVFLW (1ull << 11)
211#define CA_PIO_INVALID_ADDR (1ull << 12)
212#define CA_PCI_ARB_TO (1ull << 13)
213#define CA_AGP_REQ_OFLOW (1ull << 14)
214#define CA_SBA_TYPE1_ERR (1ull << 15)
215 /* bit 16 unused */
216#define CA_INTA (1ull << 17)
217#define CA_INTB (1ull << 18)
218#define CA_MULT_INTA (1ull << 19)
219#define CA_MULT_INTB (1ull << 20)
220#define CA_GFX_CREDIT_OVFLW (1ull << 21)
221 /* bits 63:22 unused */
222
223/* ==== ca_crm_pkterr_type */
224/* ==== ca_crm_pkterr_type_alias */
225#define CA_CRM_PKTERR_SBERR_HDR (1ull << 0)
226#define CA_CRM_PKTERR_DIDN (1ull << 1)
227#define CA_CRM_PKTERR_PACTYPE (1ull << 2)
228#define CA_CRM_PKTERR_INV_TNUM (1ull << 3)
229#define CA_CRM_PKTERR_ADDR_RNG (1ull << 4)
230#define CA_CRM_PKTERR_ADDR_ALGN (1ull << 5)
231#define CA_CRM_PKTERR_HDR_PARAM (1ull << 6)
232#define CA_CRM_PKTERR_CW_ERR (1ull << 7)
233#define CA_CRM_PKTERR_SBERR_NH (1ull << 8)
234#define CA_CRM_PKTERR_EARLY_TERM (1ull << 9)
235#define CA_CRM_PKTERR_EARLY_TAIL (1ull << 10)
236#define CA_CRM_PKTERR_MSSNG_TAIL (1ull << 11)
237#define CA_CRM_PKTERR_MSSNG_HDR (1ull << 12)
238 /* bits 15:13 unused */
239#define CA_FIRST_CRM_PKTERR_SBERR_HDR (1ull << 16)
240#define CA_FIRST_CRM_PKTERR_DIDN (1ull << 17)
241#define CA_FIRST_CRM_PKTERR_PACTYPE (1ull << 18)
242#define CA_FIRST_CRM_PKTERR_INV_TNUM (1ull << 19)
243#define CA_FIRST_CRM_PKTERR_ADDR_RNG (1ull << 20)
244#define CA_FIRST_CRM_PKTERR_ADDR_ALGN (1ull << 21)
245#define CA_FIRST_CRM_PKTERR_HDR_PARAM (1ull << 22)
246#define CA_FIRST_CRM_PKTERR_CW_ERR (1ull << 23)
247#define CA_FIRST_CRM_PKTERR_SBERR_NH (1ull << 24)
248#define CA_FIRST_CRM_PKTERR_EARLY_TERM (1ull << 25)
249#define CA_FIRST_CRM_PKTERR_EARLY_TAIL (1ull << 26)
250#define CA_FIRST_CRM_PKTERR_MSSNG_TAIL (1ull << 27)
251#define CA_FIRST_CRM_PKTERR_MSSNG_HDR (1ull << 28)
252 /* bits 63:29 unused */
253
254/* ==== ca_crm_ct_error_detail_1 */
255#define CA_PKT_TYPE (0xfull << 0)
256#define CA_PKT_TYPE_SHFT 0
257#define CA_SRC_ID (0x3ull << 4)
258#define CA_SRC_ID_SHFT 4
259#define CA_DATA_SZ (0x3ull << 6)
260#define CA_DATA_SZ_SHFT 6
261#define CA_TNUM (0xffull << 8)
262#define CA_TNUM_SHFT 8
263#define CA_DW_DATA_EN (0xffull << 16)
264#define CA_DW_DATA_EN_SHFT 16
265#define CA_GFX_CRED (0xffull << 24)
266#define CA_GFX_CRED_SHFT 24
267#define CA_MEM_RD_PARAM (0x3ull << 32)
268#define CA_MEM_RD_PARAM_SHFT 32
269#define CA_PIO_OP (1ull << 34)
270#define CA_CW_ERR (1ull << 35)
271 /* bits 62:36 unused */
272#define CA_VALID (1ull << 63)
273
274/* ==== ca_crm_ct_error_detail_2 */
275 /* bits 2:0 unused */
276#define CA_PKT_ADDR (0x1fffffffffffffull << 3)
277#define CA_PKT_ADDR_SHFT 3
278 /* bits 63:56 unused */
279
280/* ==== ca_crm_tnumto */
281#define CA_CRM_TNUMTO_VAL (0xffull << 0)
282#define CA_CRM_TNUMTO_VAL_SHFT 0
283#define CA_CRM_TNUMTO_WR (1ull << 8)
284 /* bits 63:9 unused */
285
286/* ==== ca_gart_err */
287#define CA_GART_ERR_SOURCE (0x3ull << 0)
288#define CA_GART_ERR_SOURCE_SHFT 0
289 /* bits 3:2 unused */
290#define CA_GART_ERR_ADDR (0xfffffffffull << 4)
291#define CA_GART_ERR_ADDR_SHFT 4
292 /* bits 63:40 unused */
293
294/* ==== ca_pcierr_type */
295#define CA_PCIERR_DATA (0xffffffffull << 0)
296#define CA_PCIERR_DATA_SHFT 0
297#define CA_PCIERR_ENB (0xfull << 32)
298#define CA_PCIERR_ENB_SHFT 32
299#define CA_PCIERR_CMD (0xfull << 36)
300#define CA_PCIERR_CMD_SHFT 36
301#define CA_PCIERR_A64 (1ull << 40)
302#define CA_PCIERR_SLV_SERR (1ull << 41)
303#define CA_PCIERR_SLV_WR_PERR (1ull << 42)
304#define CA_PCIERR_SLV_RD_PERR (1ull << 43)
305#define CA_PCIERR_MST_SERR (1ull << 44)
306#define CA_PCIERR_MST_WR_PERR (1ull << 45)
307#define CA_PCIERR_MST_RD_PERR (1ull << 46)
308#define CA_PCIERR_MST_MABT (1ull << 47)
309#define CA_PCIERR_MST_TABT (1ull << 48)
310#define CA_PCIERR_MST_RETRY_TOUT (1ull << 49)
311
312#define CA_PCIERR_TYPES \
313 (CA_PCIERR_A64|CA_PCIERR_SLV_SERR| \
314 CA_PCIERR_SLV_WR_PERR|CA_PCIERR_SLV_RD_PERR| \
315 CA_PCIERR_MST_SERR|CA_PCIERR_MST_WR_PERR|CA_PCIERR_MST_RD_PERR| \
316 CA_PCIERR_MST_MABT|CA_PCIERR_MST_TABT|CA_PCIERR_MST_RETRY_TOUT)
317
318 /* bits 63:50 unused */
319
320/* ==== ca_pci_dma_addr_extn */
321#define CA_UPPER_NODE_OFFSET (0x3full << 0)
322#define CA_UPPER_NODE_OFFSET_SHFT 0
323 /* bits 7:6 unused */
324#define CA_CHIPLET_ID (0x3ull << 8)
325#define CA_CHIPLET_ID_SHFT 8
326 /* bits 11:10 unused */
327#define CA_PCI_DMA_NODE_ID (0xffffull << 12)
328#define CA_PCI_DMA_NODE_ID_SHFT 12
329 /* bits 27:26 unused */
330#define CA_PCI_DMA_PIO_MEM_TYPE (1ull << 28)
331 /* bits 63:29 unused */
332
333
334/* ==== ca_agp_dma_addr_extn */
335 /* bits 19:0 unused */
336#define CA_AGP_DMA_NODE_ID (0xffffull << 20)
337#define CA_AGP_DMA_NODE_ID_SHFT 20
338 /* bits 27:26 unused */
339#define CA_AGP_DMA_PIO_MEM_TYPE (1ull << 28)
340 /* bits 63:29 unused */
341
342/* ==== ca_debug_vector_sel */
343#define CA_DEBUG_MN_VSEL (0xfull << 0)
344#define CA_DEBUG_MN_VSEL_SHFT 0
345#define CA_DEBUG_PP_VSEL (0xfull << 4)
346#define CA_DEBUG_PP_VSEL_SHFT 4
347#define CA_DEBUG_GW_VSEL (0xfull << 8)
348#define CA_DEBUG_GW_VSEL_SHFT 8
349#define CA_DEBUG_GT_VSEL (0xfull << 12)
350#define CA_DEBUG_GT_VSEL_SHFT 12
351#define CA_DEBUG_PD_VSEL (0xfull << 16)
352#define CA_DEBUG_PD_VSEL_SHFT 16
353#define CA_DEBUG_AD_VSEL (0xfull << 20)
354#define CA_DEBUG_AD_VSEL_SHFT 20
355#define CA_DEBUG_CX_VSEL (0xfull << 24)
356#define CA_DEBUG_CX_VSEL_SHFT 24
357#define CA_DEBUG_CR_VSEL (0xfull << 28)
358#define CA_DEBUG_CR_VSEL_SHFT 28
359#define CA_DEBUG_BA_VSEL (0xfull << 32)
360#define CA_DEBUG_BA_VSEL_SHFT 32
361#define CA_DEBUG_PE_VSEL (0xfull << 36)
362#define CA_DEBUG_PE_VSEL_SHFT 36
363#define CA_DEBUG_BO_VSEL (0xfull << 40)
364#define CA_DEBUG_BO_VSEL_SHFT 40
365#define CA_DEBUG_BI_VSEL (0xfull << 44)
366#define CA_DEBUG_BI_VSEL_SHFT 44
367#define CA_DEBUG_AS_VSEL (0xfull << 48)
368#define CA_DEBUG_AS_VSEL_SHFT 48
369#define CA_DEBUG_PS_VSEL (0xfull << 52)
370#define CA_DEBUG_PS_VSEL_SHFT 52
371#define CA_DEBUG_PM_VSEL (0xfull << 56)
372#define CA_DEBUG_PM_VSEL_SHFT 56
373 /* bits 63:60 unused */
374
375/* ==== ca_debug_mux_core_sel */
376/* ==== ca_debug_mux_pci_sel */
377#define CA_DEBUG_MSEL0 (0x7ull << 0)
378#define CA_DEBUG_MSEL0_SHFT 0
379 /* bit 3 unused */
380#define CA_DEBUG_NSEL0 (0x7ull << 4)
381#define CA_DEBUG_NSEL0_SHFT 4
382 /* bit 7 unused */
383#define CA_DEBUG_MSEL1 (0x7ull << 8)
384#define CA_DEBUG_MSEL1_SHFT 8
385 /* bit 11 unused */
386#define CA_DEBUG_NSEL1 (0x7ull << 12)
387#define CA_DEBUG_NSEL1_SHFT 12
388 /* bit 15 unused */
389#define CA_DEBUG_MSEL2 (0x7ull << 16)
390#define CA_DEBUG_MSEL2_SHFT 16
391 /* bit 19 unused */
392#define CA_DEBUG_NSEL2 (0x7ull << 20)
393#define CA_DEBUG_NSEL2_SHFT 20
394 /* bit 23 unused */
395#define CA_DEBUG_MSEL3 (0x7ull << 24)
396#define CA_DEBUG_MSEL3_SHFT 24
397 /* bit 27 unused */
398#define CA_DEBUG_NSEL3 (0x7ull << 28)
399#define CA_DEBUG_NSEL3_SHFT 28
400 /* bit 31 unused */
401#define CA_DEBUG_MSEL4 (0x7ull << 32)
402#define CA_DEBUG_MSEL4_SHFT 32
403 /* bit 35 unused */
404#define CA_DEBUG_NSEL4 (0x7ull << 36)
405#define CA_DEBUG_NSEL4_SHFT 36
406 /* bit 39 unused */
407#define CA_DEBUG_MSEL5 (0x7ull << 40)
408#define CA_DEBUG_MSEL5_SHFT 40
409 /* bit 43 unused */
410#define CA_DEBUG_NSEL5 (0x7ull << 44)
411#define CA_DEBUG_NSEL5_SHFT 44
412 /* bit 47 unused */
413#define CA_DEBUG_MSEL6 (0x7ull << 48)
414#define CA_DEBUG_MSEL6_SHFT 48
415 /* bit 51 unused */
416#define CA_DEBUG_NSEL6 (0x7ull << 52)
417#define CA_DEBUG_NSEL6_SHFT 52
418 /* bit 55 unused */
419#define CA_DEBUG_MSEL7 (0x7ull << 56)
420#define CA_DEBUG_MSEL7_SHFT 56
421 /* bit 59 unused */
422#define CA_DEBUG_NSEL7 (0x7ull << 60)
423#define CA_DEBUG_NSEL7_SHFT 60
424 /* bit 63 unused */
425
426
427/* ==== ca_debug_domain_sel */
428#define CA_DEBUG_DOMAIN_L (1ull << 0)
429#define CA_DEBUG_DOMAIN_H (1ull << 1)
430 /* bits 63:2 unused */
431
432/* ==== ca_gart_ptr_table */
433#define CA_GART_PTR_VAL (1ull << 0)
434 /* bits 11:1 unused */
435#define CA_GART_PTR_ADDR (0xfffffffffffull << 12)
436#define CA_GART_PTR_ADDR_SHFT 12
437 /* bits 63:56 unused */
438
439/* ==== ca_gart_tlb_addr[0-7] */
440#define CA_GART_TLB_ADDR (0xffffffffffffffull << 0)
441#define CA_GART_TLB_ADDR_SHFT 0
442 /* bits 62:56 unused */
443#define CA_GART_TLB_ENTRY_VAL (1ull << 63)
444
445/*
446 * PIO address space ranges for TIO:CA
447 */
448
449/* CA internal registers */
450#define CA_PIO_ADMIN 0x00000000
451#define CA_PIO_ADMIN_LEN 0x00010000
452
453/* GFX Write Buffer - Diagnostics */
454#define CA_PIO_GFX 0x00010000
455#define CA_PIO_GFX_LEN 0x00010000
456
457/* AGP DMA Write Buffer - Diagnostics */
458#define CA_PIO_AGP_DMAWRITE 0x00020000
459#define CA_PIO_AGP_DMAWRITE_LEN 0x00010000
460
461/* AGP DMA READ Buffer - Diagnostics */
462#define CA_PIO_AGP_DMAREAD 0x00030000
463#define CA_PIO_AGP_DMAREAD_LEN 0x00010000
464
465/* PCI Config Type 0 */
466#define CA_PIO_PCI_TYPE0_CONFIG 0x01000000
467#define CA_PIO_PCI_TYPE0_CONFIG_LEN 0x01000000
468
469/* PCI Config Type 1 */
470#define CA_PIO_PCI_TYPE1_CONFIG 0x02000000
471#define CA_PIO_PCI_TYPE1_CONFIG_LEN 0x01000000
472
473/* PCI I/O Cycles - mapped to PCI Address 0x00000000-0x04ffffff */
474#define CA_PIO_PCI_IO 0x03000000
475#define CA_PIO_PCI_IO_LEN 0x05000000
476
477/* PCI MEM Cycles - mapped to PCI with CA_PIO_ADDR_OFFSET of ca_control1 */
478/* use Fast Write if enabled and coretalk packet type is a GFX request */
479#define CA_PIO_PCI_MEM_OFFSET 0x08000000
480#define CA_PIO_PCI_MEM_OFFSET_LEN 0x08000000
481
482/* PCI MEM Cycles - mapped to PCI Address 0x00000000-0xbfffffff */
483/* use Fast Write if enabled and coretalk packet type is a GFX request */
484#define CA_PIO_PCI_MEM 0x40000000
485#define CA_PIO_PCI_MEM_LEN 0xc0000000
486
487/*
488 * DMA space
489 *
490 * The CA aperature (ie. bus address range) mapped by the GART is segmented into
491 * two parts. The lower portion of the aperature is used for mapping 32 bit
492 * PCI addresses which are managed by the dma interfaces in this file. The
493 * upper poprtion of the aperature is used for mapping 48 bit AGP addresses.
494 * The AGP portion of the aperature is managed by the agpgart_be.c driver
495 * in drivers/linux/agp. There are ca-specific hooks in that driver to
496 * manipulate the gart, but management of the AGP portion of the aperature
497 * is the responsibility of that driver.
498 *
499 * CA allows three main types of DMA mapping:
500 *
501 * PCI 64-bit Managed by this driver
502 * PCI 32-bit Managed by this driver
503 * AGP 48-bit Managed by hooks in the /dev/agpgart driver
504 *
505 * All of the above can optionally be remapped through the GART. The following
506 * table lists the combinations of addressing types and GART remapping that
507 * is currently supported by the driver (h/w supports all, s/w limits this):
508 *
509 * PCI64 PCI32 AGP48
510 * GART no yes yes
511 * Direct yes yes no
512 *
513 * GART remapping of PCI64 is not done because there is no need to. The
514 * 64 bit PCI address holds all of the information necessary to target any
515 * memory in the system.
516 *
517 * AGP48 is always mapped through the GART. Management of the AGP48 portion
518 * of the aperature is the responsibility of code in the agpgart_be driver.
519 *
520 * The non-64 bit bus address space will currently be partitioned like this:
521 *
522 * 0xffff_ffff_ffff +--------
523 * | AGP48 direct
524 * | Space managed by this driver
525 * CA_AGP_DIRECT_BASE +--------
526 * | AGP GART mapped (gfx aperature)
527 * | Space managed by /dev/agpgart driver
528 * | This range is exposed to the agpgart
529 * | driver as the "graphics aperature"
530 * CA_AGP_MAPPED_BASE +-----
531 * | PCI GART mapped
532 * | Space managed by this driver
533 * CA_PCI32_MAPPED_BASE +----
534 * | PCI32 direct
535 * | Space managed by this driver
536 * 0xC000_0000 +--------
537 * (CA_PCI32_DIRECT_BASE)
538 *
539 * The bus address range CA_PCI32_MAPPED_BASE through CA_AGP_DIRECT_BASE
540 * is what we call the CA aperature. Addresses falling in this range will
541 * be remapped using the GART.
542 *
543 * The bus address range CA_AGP_MAPPED_BASE through CA_AGP_DIRECT_BASE
544 * is what we call the graphics aperature. This is a subset of the CA
545 * aperature and is under the control of the agpgart_be driver.
546 *
547 * CA_PCI32_MAPPED_BASE, CA_AGP_MAPPED_BASE, and CA_AGP_DIRECT_BASE are
548 * somewhat arbitrary values. The known constraints on choosing these is:
549 *
550 * 1) CA_AGP_DIRECT_BASE-CA_PCI32_MAPPED_BASE+1 (the CA aperature size)
551 * must be one of the values supported by the ca_gart_aperature register.
552 * Currently valid values are: 4MB through 4096MB in powers of 2 increments
553 *
554 * 2) CA_AGP_DIRECT_BASE-CA_AGP_MAPPED_BASE+1 (the gfx aperature size)
555 * must be in MB units since that's what the agpgart driver assumes.
556 */
557
558/*
559 * Define Bus DMA ranges. These are configurable (see constraints above)
560 * and will probably need tuning based on experience.
561 */
562
563
564/*
565 * 11/24/03
566 * CA has an addressing glitch w.r.t. PCI direct 32 bit DMA that makes it
567 * generally unusable. The problem is that for PCI direct 32
568 * DMA's, all 32 bits of the bus address are used to form the lower 32 bits
569 * of the coretalk address, and coretalk bits 38:32 come from a register.
570 * Since only PCI bus addresses 0xC0000000-0xFFFFFFFF (1GB) are available
571 * for DMA (the rest is allocated to PIO), host node addresses need to be
572 * such that their lower 32 bits fall in the 0xC0000000-0xffffffff range
573 * as well. So there can be no PCI32 direct DMA below 3GB!! For this
574 * reason we set the CA_PCI32_DIRECT_SIZE to 0 which essentially makes
575 * tioca_dma_direct32() a noop but preserves the code flow should this issue
576 * be fixed in a respin.
577 *
578 * For now, all PCI32 DMA's must be mapped through the GART.
579 */
580
581#define CA_PCI32_DIRECT_BASE 0xC0000000UL /* BASE not configurable */
582#define CA_PCI32_DIRECT_SIZE 0x00000000UL /* 0 MB */
583
584#define CA_PCI32_MAPPED_BASE 0xC0000000UL
585#define CA_PCI32_MAPPED_SIZE 0x40000000UL /* 2GB */
586
587#define CA_AGP_MAPPED_BASE 0x80000000UL
588#define CA_AGP_MAPPED_SIZE 0x40000000UL /* 2GB */
589
590#define CA_AGP_DIRECT_BASE 0x40000000UL /* 2GB */
591#define CA_AGP_DIRECT_SIZE 0x40000000UL
592
593#define CA_APERATURE_BASE (CA_AGP_MAPPED_BASE)
594#define CA_APERATURE_SIZE (CA_AGP_MAPPED_SIZE+CA_PCI32_MAPPED_SIZE)
595
596#endif /* _ASM_IA64_SN_TIO_TIOCA_H */
diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h
deleted file mode 100644
index 9a820ac61be3..000000000000
--- a/include/asm-ia64/sn/tioca_provider.h
+++ /dev/null
@@ -1,207 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
10#define _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
11
12#include <asm/sn/tioca.h>
13
14/*
15 * WAR enables
16 * Defines for individual WARs. Each is a bitmask of applicable
17 * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B,
18 * (3 << 1) == (rev A or rev B), etc
19 */
20
21#define TIOCA_WAR_ENABLED(pv, tioca_common) \
22 ((1 << tioca_common->ca_rev) & pv)
23
24 /* TIO:ICE:FRZ:Freezer loses a PIO data ucred on PIO RD RSP with CW error */
25#define PV907908 (1 << 1)
26 /* ATI config space problems after BIOS execution starts */
27#define PV908234 (1 << 1)
28 /* CA:AGPDMA write request data mismatch with ABC1CL merge */
29#define PV895469 (1 << 1)
30 /* TIO:CA TLB invalidate of written GART entries possibly not occurring in CA*/
31#define PV910244 (1 << 1)
32
33struct tioca_dmamap{
34 struct list_head cad_list; /* headed by ca_list */
35
36 dma_addr_t cad_dma_addr; /* Linux dma handle */
37 uint cad_gart_entry; /* start entry in ca_gart_pagemap */
38 uint cad_gart_size; /* #entries for this map */
39};
40
41/*
42 * Kernel only fields. Prom may look at this stuff for debugging only.
43 * Access this structure through the ca_kernel_private ptr.
44 */
45
46struct tioca_common ;
47
48struct tioca_kernel {
49 struct tioca_common *ca_common; /* tioca this belongs to */
50 struct list_head ca_list; /* list of all ca's */
51 struct list_head ca_dmamaps;
52 spinlock_t ca_lock; /* Kernel lock */
53 cnodeid_t ca_closest_node;
54 struct list_head *ca_devices; /* bus->devices */
55
56 /*
57 * General GART stuff
58 */
59 u64 ca_ap_size; /* size of aperature in bytes */
60 u32 ca_gart_entries; /* # u64 entries in gart */
61 u32 ca_ap_pagesize; /* aperature page size in bytes */
62 u64 ca_ap_bus_base; /* bus address of CA aperature */
63 u64 ca_gart_size; /* gart size in bytes */
64 u64 *ca_gart; /* gart table vaddr */
65 u64 ca_gart_coretalk_addr; /* gart coretalk addr */
66 u8 ca_gart_iscoherent; /* used in tioca_tlbflush */
67
68 /* PCI GART convenience values */
69 u64 ca_pciap_base; /* pci aperature bus base address */
70 u64 ca_pciap_size; /* pci aperature size (bytes) */
71 u64 ca_pcigart_base; /* gfx GART bus base address */
72 u64 *ca_pcigart; /* gfx GART vm address */
73 u32 ca_pcigart_entries;
74 u32 ca_pcigart_start; /* PCI start index in ca_gart */
75 void *ca_pcigart_pagemap;
76
77 /* AGP GART convenience values */
78 u64 ca_gfxap_base; /* gfx aperature bus base address */
79 u64 ca_gfxap_size; /* gfx aperature size (bytes) */
80 u64 ca_gfxgart_base; /* gfx GART bus base address */
81 u64 *ca_gfxgart; /* gfx GART vm address */
82 u32 ca_gfxgart_entries;
83 u32 ca_gfxgart_start; /* agpgart start index in ca_gart */
84};
85
86/*
87 * Common tioca info shared between kernel and prom
88 *
89 * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES
90 * TO THE PROM VERSION.
91 */
92
93struct tioca_common {
94 struct pcibus_bussoft ca_common; /* common pciio header */
95
96 u32 ca_rev;
97 u32 ca_closest_nasid;
98
99 u64 ca_prom_private;
100 u64 ca_kernel_private;
101};
102
103/**
104 * tioca_paddr_to_gart - Convert an SGI coretalk address to a CA GART entry
105 * @paddr: page address to convert
106 *
107 * Convert a system [coretalk] address to a GART entry. GART entries are
108 * formed using the following:
109 *
110 * data = ( (1<<63) | ( (REMAP_NODE_ID << 40) | (MD_CHIPLET_ID << 38) |
111 * (REMAP_SYS_ADDR) ) >> 12 )
112 *
113 * DATA written to 1 GART TABLE Entry in system memory is remapped system
114 * addr for 1 page
115 *
116 * The data is for coretalk address format right shifted 12 bits with a
117 * valid bit.
118 *
119 * GART_TABLE_ENTRY [ 25:0 ] -- REMAP_SYS_ADDRESS[37:12].
120 * GART_TABLE_ENTRY [ 27:26 ] -- SHUB MD chiplet id.
121 * GART_TABLE_ENTRY [ 41:28 ] -- REMAP_NODE_ID.
122 * GART_TABLE_ENTRY [ 63 ] -- Valid Bit
123 */
124static inline u64
125tioca_paddr_to_gart(unsigned long paddr)
126{
127 /*
128 * We are assuming right now that paddr already has the correct
129 * format since the address from xtalk_dmaXXX should already have
130 * NODE_ID, CHIPLET_ID, and SYS_ADDR in the correct locations.
131 */
132
133 return ((paddr) >> 12) | (1UL << 63);
134}
135
136/**
137 * tioca_physpage_to_gart - Map a host physical page for SGI CA based DMA
138 * @page_addr: system page address to map
139 */
140
141static inline unsigned long
142tioca_physpage_to_gart(u64 page_addr)
143{
144 u64 coretalk_addr;
145
146 coretalk_addr = PHYS_TO_TIODMA(page_addr);
147 if (!coretalk_addr) {
148 return 0;
149 }
150
151 return tioca_paddr_to_gart(coretalk_addr);
152}
153
154/**
155 * tioca_tlbflush - invalidate cached SGI CA GART TLB entries
156 * @tioca_kernel: CA context
157 *
158 * Invalidate tlb entries for a given CA GART. Main complexity is to account
159 * for revA bug.
160 */
161static inline void
162tioca_tlbflush(struct tioca_kernel *tioca_kernel)
163{
164 volatile u64 tmp;
165 volatile struct tioca __iomem *ca_base;
166 struct tioca_common *tioca_common;
167
168 tioca_common = tioca_kernel->ca_common;
169 ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
170
171 /*
172 * Explicit flushes not needed if GART is in cached mode
173 */
174 if (tioca_kernel->ca_gart_iscoherent) {
175 if (TIOCA_WAR_ENABLED(PV910244, tioca_common)) {
176 /*
177 * PV910244: RevA CA needs explicit flushes.
178 * Need to put GART into uncached mode before
179 * flushing otherwise the explicit flush is ignored.
180 *
181 * Alternate WAR would be to leave GART cached and
182 * touch every CL aligned GART entry.
183 */
184
185 __sn_clrq_relaxed(&ca_base->ca_control2, CA_GART_MEM_PARAM);
186 __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
187 __sn_setq_relaxed(&ca_base->ca_control2,
188 (0x2ull << CA_GART_MEM_PARAM_SHFT));
189 tmp = __sn_readq_relaxed(&ca_base->ca_control2);
190 }
191
192 return;
193 }
194
195 /*
196 * Gart in uncached mode ... need an explicit flush.
197 */
198
199 __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
200 tmp = __sn_readq_relaxed(&ca_base->ca_control2);
201}
202
203extern u32 tioca_gart_found;
204extern struct list_head tioca_list;
205extern int tioca_init_provider(void);
206extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
207#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */
diff --git a/include/asm-ia64/sn/tioce.h b/include/asm-ia64/sn/tioce.h
deleted file mode 100644
index 893468e1b41b..000000000000
--- a/include/asm-ia64/sn/tioce.h
+++ /dev/null
@@ -1,760 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef __ASM_IA64_SN_TIOCE_H__
10#define __ASM_IA64_SN_TIOCE_H__
11
12/* CE ASIC part & mfgr information */
13#define TIOCE_PART_NUM 0xCE00
14#define TIOCE_SRC_ID 0x01
15#define TIOCE_REV_A 0x1
16
17/* CE Virtual PPB Vendor/Device IDs */
18#define CE_VIRT_PPB_VENDOR_ID 0x10a9
19#define CE_VIRT_PPB_DEVICE_ID 0x4002
20
21/* CE Host Bridge Vendor/Device IDs */
22#define CE_HOST_BRIDGE_VENDOR_ID 0x10a9
23#define CE_HOST_BRIDGE_DEVICE_ID 0x4001
24
25
26#define TIOCE_NUM_M40_ATES 4096
27#define TIOCE_NUM_M3240_ATES 2048
28#define TIOCE_NUM_PORTS 2
29
30/*
31 * Register layout for TIOCE. MMR offsets are shown at the far right of the
32 * structure definition.
33 */
34typedef volatile struct tioce {
35 /*
36 * ADMIN : Administration Registers
37 */
38 u64 ce_adm_id; /* 0x000000 */
39 u64 ce_pad_000008; /* 0x000008 */
40 u64 ce_adm_dyn_credit_status; /* 0x000010 */
41 u64 ce_adm_last_credit_status; /* 0x000018 */
42 u64 ce_adm_credit_limit; /* 0x000020 */
43 u64 ce_adm_force_credit; /* 0x000028 */
44 u64 ce_adm_control; /* 0x000030 */
45 u64 ce_adm_mmr_chn_timeout; /* 0x000038 */
46 u64 ce_adm_ssp_ure_timeout; /* 0x000040 */
47 u64 ce_adm_ssp_dre_timeout; /* 0x000048 */
48 u64 ce_adm_ssp_debug_sel; /* 0x000050 */
49 u64 ce_adm_int_status; /* 0x000058 */
50 u64 ce_adm_int_status_alias; /* 0x000060 */
51 u64 ce_adm_int_mask; /* 0x000068 */
52 u64 ce_adm_int_pending; /* 0x000070 */
53 u64 ce_adm_force_int; /* 0x000078 */
54 u64 ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */
55 u64 ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */
56 u64 ce_adm_error_summary; /* 0x000100 */
57 u64 ce_adm_error_summary_alias; /* 0x000108 */
58 u64 ce_adm_error_mask; /* 0x000110 */
59 u64 ce_adm_first_error; /* 0x000118 */
60 u64 ce_adm_error_overflow; /* 0x000120 */
61 u64 ce_adm_error_overflow_alias; /* 0x000128 */
62 u64 ce_pad_000130[2]; /* 0x000130 -- 0x000138 */
63 u64 ce_adm_tnum_error; /* 0x000140 */
64 u64 ce_adm_mmr_err_detail; /* 0x000148 */
65 u64 ce_adm_msg_sram_perr_detail; /* 0x000150 */
66 u64 ce_adm_bap_sram_perr_detail; /* 0x000158 */
67 u64 ce_adm_ce_sram_perr_detail; /* 0x000160 */
68 u64 ce_adm_ce_credit_oflow_detail; /* 0x000168 */
69 u64 ce_adm_tx_link_idle_max_timer; /* 0x000170 */
70 u64 ce_adm_pcie_debug_sel; /* 0x000178 */
71 u64 ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */
72
73 u64 ce_adm_pcie_debug_sel_top; /* 0x000200 */
74 u64 ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */
75 u64 ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */
76 u64 ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */
77 u64 ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */
78 u64 ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */
79 u64 ce_adm_pcie_trig_compare_top; /* 0x000230 */
80 u64 ce_adm_pcie_trig_compare_en_top; /* 0x000238 */
81 u64 ce_adm_ssp_debug_sel_top; /* 0x000240 */
82 u64 ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */
83 u64 ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */
84 u64 ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */
85 u64 ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */
86 u64 ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */
87 u64 ce_adm_ssp_trig_compare_top; /* 0x000270 */
88 u64 ce_adm_ssp_trig_compare_en_top; /* 0x000278 */
89 u64 ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */
90
91 u64 ce_adm_bap_ctrl; /* 0x000400 */
92 u64 ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */
93
94 u64 ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */
95 u64 ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */
96
97 u64 ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */
98 u64 ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */
99
100 u64 ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */
101 u64 ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */
102
103 u64 ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */
104
105 /*
106 * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2)
107 * Link#1 MMRs at start at 0x002000, Link#2 MMRs at 0x003000
108 * NOTE: the comment offsets at far right: let 'z' = {2 or 3}
109 */
110 #define ce_lsi(link_num) ce_lsi[link_num-1]
111 struct ce_lsi_reg {
112 u64 ce_lsi_lpu_id; /* 0x00z000 */
113 u64 ce_lsi_rst; /* 0x00z008 */
114 u64 ce_lsi_dbg_stat; /* 0x00z010 */
115 u64 ce_lsi_dbg_cfg; /* 0x00z018 */
116 u64 ce_lsi_ltssm_ctrl; /* 0x00z020 */
117 u64 ce_lsi_lk_stat; /* 0x00z028 */
118 u64 ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */
119 u64 ce_lsi_int_and_stat; /* 0x00z040 */
120 u64 ce_lsi_int_mask; /* 0x00z048 */
121 u64 ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */
122 u64 ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */
123 u64 ce_pad_00z108; /* 0x00z108 */
124 u64 ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */
125 u64 ce_pad_00z118; /* 0x00z118 */
126 u64 ce_lsi_lk_perf_cnt1; /* 0x00z120 */
127 u64 ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */
128 u64 ce_lsi_lk_perf_cnt2; /* 0x00z130 */
129 u64 ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */
130 u64 ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */
131 u64 ce_lsi_lk_lyr_cfg; /* 0x00z200 */
132 u64 ce_lsi_lk_lyr_status; /* 0x00z208 */
133 u64 ce_lsi_lk_lyr_int_stat; /* 0x00z210 */
134 u64 ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */
135 u64 ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */
136 u64 ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */
137 u64 ce_lsi_fc_upd_ctl; /* 0x00z240 */
138 u64 ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */
139 u64 ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */
140 u64 ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */
141 u64 ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */
142 u64 ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */
143 u64 ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */
144 u64 ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */
145 u64 ce_lsi_rply_tmr_thr; /* 0x00z410 */
146 u64 ce_lsi_rply_tmr; /* 0x00z418 */
147 u64 ce_lsi_rply_num_stat; /* 0x00z420 */
148 u64 ce_lsi_rty_buf_max_addr; /* 0x00z428 */
149 u64 ce_lsi_rty_fifo_ptr; /* 0x00z430 */
150 u64 ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */
151 u64 ce_lsi_rty_fifo_cred; /* 0x00z440 */
152 u64 ce_lsi_seq_cnt; /* 0x00z448 */
153 u64 ce_lsi_ack_sent_seq_num; /* 0x00z450 */
154 u64 ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */
155 u64 ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */
156 u64 ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */
157 u64 ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */
158 u64 ce_pad_00z478; /* 0x00z478 */
159 u64 ce_lsi_mem_addr_ctl; /* 0x00z480 */
160 u64 ce_lsi_mem_d_ld0; /* 0x00z488 */
161 u64 ce_lsi_mem_d_ld1; /* 0x00z490 */
162 u64 ce_lsi_mem_d_ld2; /* 0x00z498 */
163 u64 ce_lsi_mem_d_ld3; /* 0x00z4A0 */
164 u64 ce_lsi_mem_d_ld4; /* 0x00z4A8 */
165 u64 ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */
166 u64 ce_lsi_rty_d_cnt; /* 0x00z4C0 */
167 u64 ce_lsi_seq_buf_cnt; /* 0x00z4C8 */
168 u64 ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */
169 u64 ce_pad_00z4D8; /* 0x00z4D8 */
170 u64 ce_lsi_ack_lat_thr; /* 0x00z4E0 */
171 u64 ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */
172 u64 ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */
173 u64 ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */
174 u64 ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */
175 u64 ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */
176 u64 ce_lsi_phy_lyr_cfg; /* 0x00z600 */
177 u64 ce_pad_00z608; /* 0x00z608 */
178 u64 ce_lsi_phy_lyr_int_stat; /* 0x00z610 */
179 u64 ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */
180 u64 ce_lsi_phy_lyr_int_mask; /* 0x00z620 */
181 u64 ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */
182 u64 ce_lsi_rcv_phy_cfg; /* 0x00z680 */
183 u64 ce_lsi_rcv_phy_stat1; /* 0x00z688 */
184 u64 ce_lsi_rcv_phy_stat2; /* 0x00z690 */
185 u64 ce_lsi_rcv_phy_stat3; /* 0x00z698 */
186 u64 ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */
187 u64 ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */
188 u64 ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */
189 u64 ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */
190 u64 ce_lsi_tx_phy_cfg; /* 0x00z700 */
191 u64 ce_lsi_tx_phy_stat; /* 0x00z708 */
192 u64 ce_lsi_tx_phy_int_stat; /* 0x00z710 */
193 u64 ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */
194 u64 ce_lsi_tx_phy_int_mask; /* 0x00z720 */
195 u64 ce_lsi_tx_phy_stat2; /* 0x00z728 */
196 u64 ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */
197 u64 ce_lsi_ltssm_cfg1; /* 0x00z780 */
198 u64 ce_lsi_ltssm_cfg2; /* 0x00z788 */
199 u64 ce_lsi_ltssm_cfg3; /* 0x00z790 */
200 u64 ce_lsi_ltssm_cfg4; /* 0x00z798 */
201 u64 ce_lsi_ltssm_cfg5; /* 0x00z7A0 */
202 u64 ce_lsi_ltssm_stat1; /* 0x00z7A8 */
203 u64 ce_lsi_ltssm_stat2; /* 0x00z7B0 */
204 u64 ce_lsi_ltssm_int_stat; /* 0x00z7B8 */
205 u64 ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */
206 u64 ce_lsi_ltssm_int_mask; /* 0x00z7C8 */
207 u64 ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */
208 u64 ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */
209 u64 ce_lsi_gb_cfg1; /* 0x00z800 */
210 u64 ce_lsi_gb_cfg2; /* 0x00z808 */
211 u64 ce_lsi_gb_cfg3; /* 0x00z810 */
212 u64 ce_lsi_gb_cfg4; /* 0x00z818 */
213 u64 ce_lsi_gb_stat; /* 0x00z820 */
214 u64 ce_lsi_gb_int_stat; /* 0x00z828 */
215 u64 ce_lsi_gb_int_stat_test; /* 0x00z830 */
216 u64 ce_lsi_gb_int_mask; /* 0x00z838 */
217 u64 ce_lsi_gb_pwr_dn1; /* 0x00z840 */
218 u64 ce_lsi_gb_pwr_dn2; /* 0x00z848 */
219 u64 ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
220 } ce_lsi[2];
221
222 u64 ce_pad_004000[10]; /* 0x004000 -- 0x004048 */
223
224 /*
225 * CRM: Coretalk Receive Module Registers
226 */
227 u64 ce_crm_debug_mux; /* 0x004050 */
228 u64 ce_pad_004058; /* 0x004058 */
229 u64 ce_crm_ssp_err_cmd_wrd; /* 0x004060 */
230 u64 ce_crm_ssp_err_addr; /* 0x004068 */
231 u64 ce_crm_ssp_err_syn; /* 0x004070 */
232
233 u64 ce_pad_004078[499]; /* 0x004078 -- 0x005008 */
234
235 /*
236 * CXM: Coretalk Xmit Module Registers
237 */
238 u64 ce_cxm_dyn_credit_status; /* 0x005010 */
239 u64 ce_cxm_last_credit_status; /* 0x005018 */
240 u64 ce_cxm_credit_limit; /* 0x005020 */
241 u64 ce_cxm_force_credit; /* 0x005028 */
242 u64 ce_cxm_disable_bypass; /* 0x005030 */
243 u64 ce_pad_005038[3]; /* 0x005038 -- 0x005048 */
244 u64 ce_cxm_debug_mux; /* 0x005050 */
245
246 u64 ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */
247
248 /*
249 * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
250 * DTL: Link#1 MMRs at start at 0x006000, Link#2 MMRs at 0x008000
251 * DTL: the comment offsets at far right: let 'y' = {6 or 8}
252 *
253 * UTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
254 * UTL: Link#1 MMRs at start at 0x007000, Link#2 MMRs at 0x009000
255 * UTL: the comment offsets at far right: let 'z' = {7 or 9}
256 */
257 #define ce_dtl(link_num) ce_dtl_utl[link_num-1]
258 #define ce_utl(link_num) ce_dtl_utl[link_num-1]
259 struct ce_dtl_utl_reg {
260 /* DTL */
261 u64 ce_dtl_dtdr_credit_limit; /* 0x00y000 */
262 u64 ce_dtl_dtdr_credit_force; /* 0x00y008 */
263 u64 ce_dtl_dyn_credit_status; /* 0x00y010 */
264 u64 ce_dtl_dtl_last_credit_stat; /* 0x00y018 */
265 u64 ce_dtl_dtl_ctrl; /* 0x00y020 */
266 u64 ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */
267 u64 ce_dtl_debug_sel; /* 0x00y050 */
268 u64 ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */
269
270 /* UTL */
271 u64 ce_utl_utl_ctrl; /* 0x00z000 */
272 u64 ce_utl_debug_sel; /* 0x00z008 */
273 u64 ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
274 } ce_dtl_utl[2];
275
276 u64 ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */
277
278 /*
279 * URE: Upstream Request Engine
280 */
281 u64 ce_ure_dyn_credit_status; /* 0x00B010 */
282 u64 ce_ure_last_credit_status; /* 0x00B018 */
283 u64 ce_ure_credit_limit; /* 0x00B020 */
284 u64 ce_pad_00B028; /* 0x00B028 */
285 u64 ce_ure_control; /* 0x00B030 */
286 u64 ce_ure_status; /* 0x00B038 */
287 u64 ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */
288 u64 ce_ure_debug_sel; /* 0x00B050 */
289 u64 ce_ure_pcie_debug_sel; /* 0x00B058 */
290 u64 ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */
291 u64 ce_ure_ssp_err_addr; /* 0x00B068 */
292 u64 ce_ure_page_map; /* 0x00B070 */
293 u64 ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */
294 u64 ce_ure_pipe_sel1; /* 0x00B088 */
295 u64 ce_ure_pipe_mask1; /* 0x00B090 */
296 u64 ce_ure_pipe_sel2; /* 0x00B098 */
297 u64 ce_ure_pipe_mask2; /* 0x00B0A0 */
298 u64 ce_ure_pcie1_credits_sent; /* 0x00B0A8 */
299 u64 ce_ure_pcie1_credits_used; /* 0x00B0B0 */
300 u64 ce_ure_pcie1_credit_limit; /* 0x00B0B8 */
301 u64 ce_ure_pcie2_credits_sent; /* 0x00B0C0 */
302 u64 ce_ure_pcie2_credits_used; /* 0x00B0C8 */
303 u64 ce_ure_pcie2_credit_limit; /* 0x00B0D0 */
304 u64 ce_ure_pcie_force_credit; /* 0x00B0D8 */
305 u64 ce_ure_rd_tnum_val; /* 0x00B0E0 */
306 u64 ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */
307 u64 ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */
308 u64 ce_ure_rd_tnum_error; /* 0x00B0F8 */
309 u64 ce_ure_rd_tnum_first_cl; /* 0x00B100 */
310 u64 ce_ure_rd_tnum_link_buf; /* 0x00B108 */
311 u64 ce_ure_wr_tnum_val; /* 0x00B110 */
312 u64 ce_ure_sram_err_addr0; /* 0x00B118 */
313 u64 ce_ure_sram_err_addr1; /* 0x00B120 */
314 u64 ce_ure_sram_err_addr2; /* 0x00B128 */
315 u64 ce_ure_sram_rd_addr0; /* 0x00B130 */
316 u64 ce_ure_sram_rd_addr1; /* 0x00B138 */
317 u64 ce_ure_sram_rd_addr2; /* 0x00B140 */
318 u64 ce_ure_sram_wr_addr0; /* 0x00B148 */
319 u64 ce_ure_sram_wr_addr1; /* 0x00B150 */
320 u64 ce_ure_sram_wr_addr2; /* 0x00B158 */
321 u64 ce_ure_buf_flush10; /* 0x00B160 */
322 u64 ce_ure_buf_flush11; /* 0x00B168 */
323 u64 ce_ure_buf_flush12; /* 0x00B170 */
324 u64 ce_ure_buf_flush13; /* 0x00B178 */
325 u64 ce_ure_buf_flush20; /* 0x00B180 */
326 u64 ce_ure_buf_flush21; /* 0x00B188 */
327 u64 ce_ure_buf_flush22; /* 0x00B190 */
328 u64 ce_ure_buf_flush23; /* 0x00B198 */
329 u64 ce_ure_pcie_control1; /* 0x00B1A0 */
330 u64 ce_ure_pcie_control2; /* 0x00B1A8 */
331
332 u64 ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */
333
334 /* Upstream Data Buffer, Port1 */
335 struct ce_ure_maint_ups_dat1_data {
336 u64 data63_0[512]; /* 0x00C000 -- 0x00CFF8 */
337 u64 data127_64[512]; /* 0x00D000 -- 0x00DFF8 */
338 u64 parity[512]; /* 0x00E000 -- 0x00EFF8 */
339 } ce_ure_maint_ups_dat1;
340
341 /* Upstream Header Buffer, Port1 */
342 struct ce_ure_maint_ups_hdr1_data {
343 u64 data63_0[512]; /* 0x00F000 -- 0x00FFF8 */
344 u64 data127_64[512]; /* 0x010000 -- 0x010FF8 */
345 u64 parity[512]; /* 0x011000 -- 0x011FF8 */
346 } ce_ure_maint_ups_hdr1;
347
348 /* Upstream Data Buffer, Port2 */
349 struct ce_ure_maint_ups_dat2_data {
350 u64 data63_0[512]; /* 0x012000 -- 0x012FF8 */
351 u64 data127_64[512]; /* 0x013000 -- 0x013FF8 */
352 u64 parity[512]; /* 0x014000 -- 0x014FF8 */
353 } ce_ure_maint_ups_dat2;
354
355 /* Upstream Header Buffer, Port2 */
356 struct ce_ure_maint_ups_hdr2_data {
357 u64 data63_0[512]; /* 0x015000 -- 0x015FF8 */
358 u64 data127_64[512]; /* 0x016000 -- 0x016FF8 */
359 u64 parity[512]; /* 0x017000 -- 0x017FF8 */
360 } ce_ure_maint_ups_hdr2;
361
362 /* Downstream Data Buffer */
363 struct ce_ure_maint_dns_dat_data {
364 u64 data63_0[512]; /* 0x018000 -- 0x018FF8 */
365 u64 data127_64[512]; /* 0x019000 -- 0x019FF8 */
366 u64 parity[512]; /* 0x01A000 -- 0x01AFF8 */
367 } ce_ure_maint_dns_dat;
368
369 /* Downstream Header Buffer */
370 struct ce_ure_maint_dns_hdr_data {
371 u64 data31_0[64]; /* 0x01B000 -- 0x01B1F8 */
372 u64 data95_32[64]; /* 0x01B200 -- 0x01B3F8 */
373 u64 parity[64]; /* 0x01B400 -- 0x01B5F8 */
374 } ce_ure_maint_dns_hdr;
375
376 /* RCI Buffer Data */
377 struct ce_ure_maint_rci_data {
378 u64 data41_0[64]; /* 0x01B600 -- 0x01B7F8 */
379 u64 data69_42[64]; /* 0x01B800 -- 0x01B9F8 */
380 } ce_ure_maint_rci;
381
382 /* Response Queue */
383 u64 ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */
384
385 u64 ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */
386
387 /* Admin Build-a-Packet Buffer */
388 struct ce_adm_maint_bap_buf_data {
389 u64 data63_0[258]; /* 0x024000 -- 0x024808 */
390 u64 data127_64[258]; /* 0x024810 -- 0x025018 */
391 u64 parity[258]; /* 0x025020 -- 0x025828 */
392 } ce_adm_maint_bap_buf;
393
394 u64 ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */
395
396 /* URE: 40bit PMU ATE Buffer */ /* 0x030000 -- 0x037FF8 */
397 u64 ce_ure_ate40[TIOCE_NUM_M40_ATES];
398
399 /* URE: 32/40bit PMU ATE Buffer */ /* 0x038000 -- 0x03BFF8 */
400 u64 ce_ure_ate3240[TIOCE_NUM_M3240_ATES];
401
402 u64 ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */
403
404 /*
405 * DRE: Down Stream Request Engine
406 */
407 u64 ce_dre_dyn_credit_status1; /* 0x040010 */
408 u64 ce_dre_dyn_credit_status2; /* 0x040018 */
409 u64 ce_dre_last_credit_status1; /* 0x040020 */
410 u64 ce_dre_last_credit_status2; /* 0x040028 */
411 u64 ce_dre_credit_limit1; /* 0x040030 */
412 u64 ce_dre_credit_limit2; /* 0x040038 */
413 u64 ce_dre_force_credit1; /* 0x040040 */
414 u64 ce_dre_force_credit2; /* 0x040048 */
415 u64 ce_dre_debug_mux1; /* 0x040050 */
416 u64 ce_dre_debug_mux2; /* 0x040058 */
417 u64 ce_dre_ssp_err_cmd_wrd; /* 0x040060 */
418 u64 ce_dre_ssp_err_addr; /* 0x040068 */
419 u64 ce_dre_comp_err_cmd_wrd; /* 0x040070 */
420 u64 ce_dre_comp_err_addr; /* 0x040078 */
421 u64 ce_dre_req_status; /* 0x040080 */
422 u64 ce_dre_config1; /* 0x040088 */
423 u64 ce_dre_config2; /* 0x040090 */
424 u64 ce_dre_config_req_status; /* 0x040098 */
425 u64 ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */
426 u64 ce_dre_dyn_fifo; /* 0x040100 */
427 u64 ce_pad_040108[3]; /* 0x040108 -- 0x040118 */
428 u64 ce_dre_last_fifo; /* 0x040120 */
429
430 u64 ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */
431
432 /* DRE Downstream Head Queue */
433 struct ce_dre_maint_ds_head_queue {
434 u64 data63_0[32]; /* 0x040200 -- 0x0402F8 */
435 u64 data127_64[32]; /* 0x040300 -- 0x0403F8 */
436 u64 parity[32]; /* 0x040400 -- 0x0404F8 */
437 } ce_dre_maint_ds_head_q;
438
439 u64 ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */
440
441 /* DRE Downstream Data Queue */
442 struct ce_dre_maint_ds_data_queue {
443 u64 data63_0[256]; /* 0x041000 -- 0x0417F8 */
444 u64 ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
445 u64 data127_64[256]; /* 0x042000 -- 0x0427F8 */
446 u64 ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
447 u64 parity[256]; /* 0x043000 -- 0x0437F8 */
448 u64 ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
449 } ce_dre_maint_ds_data_q;
450
451 /* DRE URE Upstream Response Queue */
452 struct ce_dre_maint_ure_us_rsp_queue {
453 u64 data63_0[8]; /* 0x044000 -- 0x044038 */
454 u64 ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */
455 u64 data127_64[8]; /* 0x044100 -- 0x044138 */
456 u64 ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */
457 u64 parity[8]; /* 0x044200 -- 0x044238 */
458 u64 ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */
459 } ce_dre_maint_ure_us_rsp_q;
460
461 u64 ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */
462
463 u64 ce_end_of_struct; /* 0x044400 */
464} tioce_t;
465
466/* ce_lsiX_gb_cfg1 register bit masks & shifts */
467#define CE_LSI_GB_CFG1_RXL0S_THS_SHFT 0
468#define CE_LSI_GB_CFG1_RXL0S_THS_MASK (0xffULL << 0)
469#define CE_LSI_GB_CFG1_RXL0S_SMP_SHFT 8
470#define CE_LSI_GB_CFG1_RXL0S_SMP_MASK (0xfULL << 8);
471#define CE_LSI_GB_CFG1_RXL0S_ADJ_SHFT 12
472#define CE_LSI_GB_CFG1_RXL0S_ADJ_MASK (0x7ULL << 12)
473#define CE_LSI_GB_CFG1_RXL0S_FLT_SHFT 15
474#define CE_LSI_GB_CFG1_RXL0S_FLT_MASK (0x1ULL << 15)
475#define CE_LSI_GB_CFG1_LPBK_SEL_SHFT 16
476#define CE_LSI_GB_CFG1_LPBK_SEL_MASK (0x3ULL << 16)
477#define CE_LSI_GB_CFG1_LPBK_EN_SHFT 18
478#define CE_LSI_GB_CFG1_LPBK_EN_MASK (0x1ULL << 18)
479#define CE_LSI_GB_CFG1_RVRS_LB_SHFT 19
480#define CE_LSI_GB_CFG1_RVRS_LB_MASK (0x1ULL << 19)
481#define CE_LSI_GB_CFG1_RVRS_CLK_SHFT 20
482#define CE_LSI_GB_CFG1_RVRS_CLK_MASK (0x3ULL << 20)
483#define CE_LSI_GB_CFG1_SLF_TS_SHFT 24
484#define CE_LSI_GB_CFG1_SLF_TS_MASK (0xfULL << 24)
485
486/* ce_adm_int_mask/ce_adm_int_status register bit defines */
487#define CE_ADM_INT_CE_ERROR_SHFT 0
488#define CE_ADM_INT_LSI1_IP_ERROR_SHFT 1
489#define CE_ADM_INT_LSI2_IP_ERROR_SHFT 2
490#define CE_ADM_INT_PCIE_ERROR_SHFT 3
491#define CE_ADM_INT_PORT1_HOTPLUG_EVENT_SHFT 4
492#define CE_ADM_INT_PORT2_HOTPLUG_EVENT_SHFT 5
493#define CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT 6
494#define CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT 7
495#define CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT 8
496#define CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT 9
497#define CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT 10
498#define CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT 11
499#define CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT 12
500#define CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT 13
501#define CE_ADM_INT_PCIE_MSG_SHFT 14 /*see int_dest_14*/
502#define CE_ADM_INT_PCIE_MSG_SLOT_0_SHFT 14
503#define CE_ADM_INT_PCIE_MSG_SLOT_1_SHFT 15
504#define CE_ADM_INT_PCIE_MSG_SLOT_2_SHFT 16
505#define CE_ADM_INT_PCIE_MSG_SLOT_3_SHFT 17
506#define CE_ADM_INT_PORT1_PM_PME_MSG_SHFT 22
507#define CE_ADM_INT_PORT2_PM_PME_MSG_SHFT 23
508
509/* ce_adm_force_int register bit defines */
510#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT 0
511#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT 1
512#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT 2
513#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT 3
514#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT 4
515#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT 5
516#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT 6
517#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT 7
518#define CE_ADM_FORCE_INT_ALWAYS_SHFT 8
519
520/* ce_adm_int_dest register bit masks & shifts */
521#define INTR_VECTOR_SHFT 56
522
523/* ce_adm_error_mask and ce_adm_error_summary register bit masks */
524#define CE_ADM_ERR_CRM_SSP_REQ_INVALID (0x1ULL << 0)
525#define CE_ADM_ERR_SSP_REQ_HEADER (0x1ULL << 1)
526#define CE_ADM_ERR_SSP_RSP_HEADER (0x1ULL << 2)
527#define CE_ADM_ERR_SSP_PROTOCOL_ERROR (0x1ULL << 3)
528#define CE_ADM_ERR_SSP_SBE (0x1ULL << 4)
529#define CE_ADM_ERR_SSP_MBE (0x1ULL << 5)
530#define CE_ADM_ERR_CXM_CREDIT_OFLOW (0x1ULL << 6)
531#define CE_ADM_ERR_DRE_SSP_REQ_INVAL (0x1ULL << 7)
532#define CE_ADM_ERR_SSP_REQ_LONG (0x1ULL << 8)
533#define CE_ADM_ERR_SSP_REQ_OFLOW (0x1ULL << 9)
534#define CE_ADM_ERR_SSP_REQ_SHORT (0x1ULL << 10)
535#define CE_ADM_ERR_SSP_REQ_SIDEBAND (0x1ULL << 11)
536#define CE_ADM_ERR_SSP_REQ_ADDR_ERR (0x1ULL << 12)
537#define CE_ADM_ERR_SSP_REQ_BAD_BE (0x1ULL << 13)
538#define CE_ADM_ERR_PCIE_COMPL_TIMEOUT (0x1ULL << 14)
539#define CE_ADM_ERR_PCIE_UNEXP_COMPL (0x1ULL << 15)
540#define CE_ADM_ERR_PCIE_ERR_COMPL (0x1ULL << 16)
541#define CE_ADM_ERR_DRE_CREDIT_OFLOW (0x1ULL << 17)
542#define CE_ADM_ERR_DRE_SRAM_PE (0x1ULL << 18)
543#define CE_ADM_ERR_SSP_RSP_INVALID (0x1ULL << 19)
544#define CE_ADM_ERR_SSP_RSP_LONG (0x1ULL << 20)
545#define CE_ADM_ERR_SSP_RSP_SHORT (0x1ULL << 21)
546#define CE_ADM_ERR_SSP_RSP_SIDEBAND (0x1ULL << 22)
547#define CE_ADM_ERR_URE_SSP_RSP_UNEXP (0x1ULL << 23)
548#define CE_ADM_ERR_URE_SSP_WR_REQ_TIMEOUT (0x1ULL << 24)
549#define CE_ADM_ERR_URE_SSP_RD_REQ_TIMEOUT (0x1ULL << 25)
550#define CE_ADM_ERR_URE_ATE3240_PAGE_FAULT (0x1ULL << 26)
551#define CE_ADM_ERR_URE_ATE40_PAGE_FAULT (0x1ULL << 27)
552#define CE_ADM_ERR_URE_CREDIT_OFLOW (0x1ULL << 28)
553#define CE_ADM_ERR_URE_SRAM_PE (0x1ULL << 29)
554#define CE_ADM_ERR_ADM_SSP_RSP_UNEXP (0x1ULL << 30)
555#define CE_ADM_ERR_ADM_SSP_REQ_TIMEOUT (0x1ULL << 31)
556#define CE_ADM_ERR_MMR_ACCESS_ERROR (0x1ULL << 32)
557#define CE_ADM_ERR_MMR_ADDR_ERROR (0x1ULL << 33)
558#define CE_ADM_ERR_ADM_CREDIT_OFLOW (0x1ULL << 34)
559#define CE_ADM_ERR_ADM_SRAM_PE (0x1ULL << 35)
560#define CE_ADM_ERR_DTL1_MIN_PDATA_CREDIT_ERR (0x1ULL << 36)
561#define CE_ADM_ERR_DTL1_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 37)
562#define CE_ADM_ERR_DTL1_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 38)
563#define CE_ADM_ERR_DTL1_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 39)
564#define CE_ADM_ERR_DTL1_COMP_HD_CRED_MAX_ERR (0x1ULL << 40)
565#define CE_ADM_ERR_DTL1_COMP_D_CRED_MAX_ERR (0x1ULL << 41)
566#define CE_ADM_ERR_DTL1_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 42)
567#define CE_ADM_ERR_DTL1_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 43)
568#define CE_ADM_ERR_DTL1_POSTED_HD_CRED_MAX_ERR (0x1ULL << 44)
569#define CE_ADM_ERR_DTL1_POSTED_D_CRED_MAX_ERR (0x1ULL << 45)
570#define CE_ADM_ERR_DTL2_MIN_PDATA_CREDIT_ERR (0x1ULL << 46)
571#define CE_ADM_ERR_DTL2_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 47)
572#define CE_ADM_ERR_DTL2_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 48)
573#define CE_ADM_ERR_DTL2_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 49)
574#define CE_ADM_ERR_DTL2_COMP_HD_CRED_MAX_ERR (0x1ULL << 50)
575#define CE_ADM_ERR_DTL2_COMP_D_CRED_MAX_ERR (0x1ULL << 51)
576#define CE_ADM_ERR_DTL2_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 52)
577#define CE_ADM_ERR_DTL2_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 53)
578#define CE_ADM_ERR_DTL2_POSTED_HD_CRED_MAX_ERR (0x1ULL << 54)
579#define CE_ADM_ERR_DTL2_POSTED_D_CRED_MAX_ERR (0x1ULL << 55)
580#define CE_ADM_ERR_PORT1_PCIE_COR_ERR (0x1ULL << 56)
581#define CE_ADM_ERR_PORT1_PCIE_NFAT_ERR (0x1ULL << 57)
582#define CE_ADM_ERR_PORT1_PCIE_FAT_ERR (0x1ULL << 58)
583#define CE_ADM_ERR_PORT2_PCIE_COR_ERR (0x1ULL << 59)
584#define CE_ADM_ERR_PORT2_PCIE_NFAT_ERR (0x1ULL << 60)
585#define CE_ADM_ERR_PORT2_PCIE_FAT_ERR (0x1ULL << 61)
586
587/* ce_adm_ure_ups_buf_barrier_flush register bit masks and shifts */
588#define FLUSH_SEL_PORT1_PIPE0_SHFT 0
589#define FLUSH_SEL_PORT1_PIPE1_SHFT 4
590#define FLUSH_SEL_PORT1_PIPE2_SHFT 8
591#define FLUSH_SEL_PORT1_PIPE3_SHFT 12
592#define FLUSH_SEL_PORT2_PIPE0_SHFT 16
593#define FLUSH_SEL_PORT2_PIPE1_SHFT 20
594#define FLUSH_SEL_PORT2_PIPE2_SHFT 24
595#define FLUSH_SEL_PORT2_PIPE3_SHFT 28
596
597/* ce_dre_config1 register bit masks and shifts */
598#define CE_DRE_RO_ENABLE (0x1ULL << 0)
599#define CE_DRE_DYN_RO_ENABLE (0x1ULL << 1)
600#define CE_DRE_SUP_CONFIG_COMP_ERROR (0x1ULL << 2)
601#define CE_DRE_SUP_IO_COMP_ERROR (0x1ULL << 3)
602#define CE_DRE_ADDR_MODE_SHFT 4
603
604/* ce_dre_config_req_status register bit masks */
605#define CE_DRE_LAST_CONFIG_COMPLETION (0x7ULL << 0)
606#define CE_DRE_DOWNSTREAM_CONFIG_ERROR (0x1ULL << 3)
607#define CE_DRE_CONFIG_COMPLETION_VALID (0x1ULL << 4)
608#define CE_DRE_CONFIG_REQUEST_ACTIVE (0x1ULL << 5)
609
610/* ce_ure_control register bit masks & shifts */
611#define CE_URE_RD_MRG_ENABLE (0x1ULL << 0)
612#define CE_URE_WRT_MRG_ENABLE1 (0x1ULL << 4)
613#define CE_URE_WRT_MRG_ENABLE2 (0x1ULL << 5)
614#define CE_URE_WRT_MRG_TIMER_SHFT 12
615#define CE_URE_WRT_MRG_TIMER_MASK (0x7FFULL << CE_URE_WRT_MRG_TIMER_SHFT)
616#define CE_URE_WRT_MRG_TIMER(x) (((u64)(x) << \
617 CE_URE_WRT_MRG_TIMER_SHFT) & \
618 CE_URE_WRT_MRG_TIMER_MASK)
619#define CE_URE_RSPQ_BYPASS_DISABLE (0x1ULL << 24)
620#define CE_URE_UPS_DAT1_PAR_DISABLE (0x1ULL << 32)
621#define CE_URE_UPS_HDR1_PAR_DISABLE (0x1ULL << 33)
622#define CE_URE_UPS_DAT2_PAR_DISABLE (0x1ULL << 34)
623#define CE_URE_UPS_HDR2_PAR_DISABLE (0x1ULL << 35)
624#define CE_URE_ATE_PAR_DISABLE (0x1ULL << 36)
625#define CE_URE_RCI_PAR_DISABLE (0x1ULL << 37)
626#define CE_URE_RSPQ_PAR_DISABLE (0x1ULL << 38)
627#define CE_URE_DNS_DAT_PAR_DISABLE (0x1ULL << 39)
628#define CE_URE_DNS_HDR_PAR_DISABLE (0x1ULL << 40)
629#define CE_URE_MALFORM_DISABLE (0x1ULL << 44)
630#define CE_URE_UNSUP_DISABLE (0x1ULL << 45)
631
632/* ce_ure_page_map register bit masks & shifts */
633#define CE_URE_ATE3240_ENABLE (0x1ULL << 0)
634#define CE_URE_ATE40_ENABLE (0x1ULL << 1)
635#define CE_URE_PAGESIZE_SHFT 4
636#define CE_URE_PAGESIZE_MASK (0x7ULL << CE_URE_PAGESIZE_SHFT)
637#define CE_URE_4K_PAGESIZE (0x0ULL << CE_URE_PAGESIZE_SHFT)
638#define CE_URE_16K_PAGESIZE (0x1ULL << CE_URE_PAGESIZE_SHFT)
639#define CE_URE_64K_PAGESIZE (0x2ULL << CE_URE_PAGESIZE_SHFT)
640#define CE_URE_128K_PAGESIZE (0x3ULL << CE_URE_PAGESIZE_SHFT)
641#define CE_URE_256K_PAGESIZE (0x4ULL << CE_URE_PAGESIZE_SHFT)
642
643/* ce_ure_pipe_sel register bit masks & shifts */
644#define PKT_TRAFIC_SHRT 16
645#define BUS_SRC_ID_SHFT 8
646#define DEV_SRC_ID_SHFT 3
647#define FNC_SRC_ID_SHFT 0
648#define CE_URE_TC_MASK (0x07ULL << PKT_TRAFIC_SHRT)
649#define CE_URE_BUS_MASK (0xFFULL << BUS_SRC_ID_SHFT)
650#define CE_URE_DEV_MASK (0x1FULL << DEV_SRC_ID_SHFT)
651#define CE_URE_FNC_MASK (0x07ULL << FNC_SRC_ID_SHFT)
652#define CE_URE_PIPE_BUS(b) (((u64)(b) << BUS_SRC_ID_SHFT) & \
653 CE_URE_BUS_MASK)
654#define CE_URE_PIPE_DEV(d) (((u64)(d) << DEV_SRC_ID_SHFT) & \
655 CE_URE_DEV_MASK)
656#define CE_URE_PIPE_FNC(f) (((u64)(f) << FNC_SRC_ID_SHFT) & \
657 CE_URE_FNC_MASK)
658
659#define CE_URE_SEL1_SHFT 0
660#define CE_URE_SEL2_SHFT 20
661#define CE_URE_SEL3_SHFT 40
662#define CE_URE_SEL1_MASK (0x7FFFFULL << CE_URE_SEL1_SHFT)
663#define CE_URE_SEL2_MASK (0x7FFFFULL << CE_URE_SEL2_SHFT)
664#define CE_URE_SEL3_MASK (0x7FFFFULL << CE_URE_SEL3_SHFT)
665
666
667/* ce_ure_pipe_mask register bit masks & shifts */
668#define CE_URE_MASK1_SHFT 0
669#define CE_URE_MASK2_SHFT 20
670#define CE_URE_MASK3_SHFT 40
671#define CE_URE_MASK1_MASK (0x7FFFFULL << CE_URE_MASK1_SHFT)
672#define CE_URE_MASK2_MASK (0x7FFFFULL << CE_URE_MASK2_SHFT)
673#define CE_URE_MASK3_MASK (0x7FFFFULL << CE_URE_MASK3_SHFT)
674
675
676/* ce_ure_pcie_control1 register bit masks & shifts */
677#define CE_URE_SI (0x1ULL << 0)
678#define CE_URE_ELAL_SHFT 4
679#define CE_URE_ELAL_MASK (0x7ULL << CE_URE_ELAL_SHFT)
680#define CE_URE_ELAL_SET(n) (((u64)(n) << CE_URE_ELAL_SHFT) & \
681 CE_URE_ELAL_MASK)
682#define CE_URE_ELAL1_SHFT 8
683#define CE_URE_ELAL1_MASK (0x7ULL << CE_URE_ELAL1_SHFT)
684#define CE_URE_ELAL1_SET(n) (((u64)(n) << CE_URE_ELAL1_SHFT) & \
685 CE_URE_ELAL1_MASK)
686#define CE_URE_SCC (0x1ULL << 12)
687#define CE_URE_PN1_SHFT 16
688#define CE_URE_PN1_MASK (0xFFULL << CE_URE_PN1_SHFT)
689#define CE_URE_PN2_SHFT 24
690#define CE_URE_PN2_MASK (0xFFULL << CE_URE_PN2_SHFT)
691#define CE_URE_PN1_SET(n) (((u64)(n) << CE_URE_PN1_SHFT) & \
692 CE_URE_PN1_MASK)
693#define CE_URE_PN2_SET(n) (((u64)(n) << CE_URE_PN2_SHFT) & \
694 CE_URE_PN2_MASK)
695
696/* ce_ure_pcie_control2 register bit masks & shifts */
697#define CE_URE_ABP (0x1ULL << 0)
698#define CE_URE_PCP (0x1ULL << 1)
699#define CE_URE_MSP (0x1ULL << 2)
700#define CE_URE_AIP (0x1ULL << 3)
701#define CE_URE_PIP (0x1ULL << 4)
702#define CE_URE_HPS (0x1ULL << 5)
703#define CE_URE_HPC (0x1ULL << 6)
704#define CE_URE_SPLV_SHFT 7
705#define CE_URE_SPLV_MASK (0xFFULL << CE_URE_SPLV_SHFT)
706#define CE_URE_SPLV_SET(n) (((u64)(n) << CE_URE_SPLV_SHFT) & \
707 CE_URE_SPLV_MASK)
708#define CE_URE_SPLS_SHFT 15
709#define CE_URE_SPLS_MASK (0x3ULL << CE_URE_SPLS_SHFT)
710#define CE_URE_SPLS_SET(n) (((u64)(n) << CE_URE_SPLS_SHFT) & \
711 CE_URE_SPLS_MASK)
712#define CE_URE_PSN1_SHFT 19
713#define CE_URE_PSN1_MASK (0x1FFFULL << CE_URE_PSN1_SHFT)
714#define CE_URE_PSN2_SHFT 32
715#define CE_URE_PSN2_MASK (0x1FFFULL << CE_URE_PSN2_SHFT)
716#define CE_URE_PSN1_SET(n) (((u64)(n) << CE_URE_PSN1_SHFT) & \
717 CE_URE_PSN1_MASK)
718#define CE_URE_PSN2_SET(n) (((u64)(n) << CE_URE_PSN2_SHFT) & \
719 CE_URE_PSN2_MASK)
720
721/*
722 * PIO address space ranges for CE
723 */
724
725/* Local CE Registers Space */
726#define CE_PIO_MMR 0x00000000
727#define CE_PIO_MMR_LEN 0x04000000
728
729/* PCI Compatible Config Space */
730#define CE_PIO_CONFIG_SPACE 0x04000000
731#define CE_PIO_CONFIG_SPACE_LEN 0x04000000
732
733/* PCI I/O Space Alias */
734#define CE_PIO_IO_SPACE_ALIAS 0x08000000
735#define CE_PIO_IO_SPACE_ALIAS_LEN 0x08000000
736
737/* PCI Enhanced Config Space */
738#define CE_PIO_E_CONFIG_SPACE 0x10000000
739#define CE_PIO_E_CONFIG_SPACE_LEN 0x10000000
740
741/* PCI I/O Space */
742#define CE_PIO_IO_SPACE 0x100000000
743#define CE_PIO_IO_SPACE_LEN 0x100000000
744
745/* PCI MEM Space */
746#define CE_PIO_MEM_SPACE 0x200000000
747#define CE_PIO_MEM_SPACE_LEN TIO_HWIN_SIZE
748
749
750/*
751 * CE PCI Enhanced Config Space shifts & masks
752 */
753#define CE_E_CONFIG_BUS_SHFT 20
754#define CE_E_CONFIG_BUS_MASK (0xFF << CE_E_CONFIG_BUS_SHFT)
755#define CE_E_CONFIG_DEVICE_SHFT 15
756#define CE_E_CONFIG_DEVICE_MASK (0x1F << CE_E_CONFIG_DEVICE_SHFT)
757#define CE_E_CONFIG_FUNC_SHFT 12
758#define CE_E_CONFIG_FUNC_MASK (0x7 << CE_E_CONFIG_FUNC_SHFT)
759
760#endif /* __ASM_IA64_SN_TIOCE_H__ */
diff --git a/include/asm-ia64/sn/tioce_provider.h b/include/asm-ia64/sn/tioce_provider.h
deleted file mode 100644
index 32c32f30b099..000000000000
--- a/include/asm-ia64/sn/tioce_provider.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_CE_PROVIDER_H
10#define _ASM_IA64_SN_CE_PROVIDER_H
11
12#include <asm/sn/pcibus_provider_defs.h>
13#include <asm/sn/tioce.h>
14
15/*
16 * Common TIOCE structure shared between the prom and kernel
17 *
18 * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES TO THE
19 * PROM VERSION.
20 */
21struct tioce_common {
22 struct pcibus_bussoft ce_pcibus; /* common pciio header */
23
24 u32 ce_rev;
25 u64 ce_kernel_private;
26 u64 ce_prom_private;
27};
28
29struct tioce_kernel {
30 struct tioce_common *ce_common;
31 spinlock_t ce_lock;
32 struct list_head ce_dmamap_list;
33
34 u64 ce_ate40_shadow[TIOCE_NUM_M40_ATES];
35 u64 ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
36 u32 ce_ate3240_pagesize;
37
38 u8 ce_port1_secondary;
39
40 /* per-port resources */
41 struct {
42 int dirmap_refcnt;
43 u64 dirmap_shadow;
44 } ce_port[TIOCE_NUM_PORTS];
45};
46
47struct tioce_dmamap {
48 struct list_head ce_dmamap_list; /* headed by tioce_kernel */
49 u32 refcnt;
50
51 u64 nbytes; /* # bytes mapped */
52
53 u64 ct_start; /* coretalk start address */
54 u64 pci_start; /* bus start address */
55
56 u64 __iomem *ate_hw;/* hw ptr of first ate in map */
57 u64 *ate_shadow; /* shadow ptr of firat ate */
58 u16 ate_count; /* # ate's in the map */
59};
60
61extern int tioce_init_provider(void);
62
63#endif /* __ASM_IA64_SN_CE_PROVIDER_H */
diff --git a/include/asm-ia64/sn/tiocp.h b/include/asm-ia64/sn/tiocp.h
deleted file mode 100644
index e8ad0bb5b6c5..000000000000
--- a/include/asm-ia64/sn/tiocp.h
+++ /dev/null
@@ -1,257 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_TIOCP_H
9#define _ASM_IA64_SN_PCI_TIOCP_H
10
11#define TIOCP_HOST_INTR_ADDR 0x003FFFFFFFFFFFFFUL
12#define TIOCP_PCI64_CMDTYPE_MEM (0x1ull << 60)
13#define TIOCP_PCI64_CMDTYPE_MSI (0x3ull << 60)
14
15
16/*****************************************************************************
17 *********************** TIOCP MMR structure mapping ***************************
18 *****************************************************************************/
19
20struct tiocp{
21
22 /* 0x000000-0x00FFFF -- Local Registers */
23
24 /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
25 u64 cp_id; /* 0x000000 */
26 u64 cp_stat; /* 0x000008 */
27 u64 cp_err_upper; /* 0x000010 */
28 u64 cp_err_lower; /* 0x000018 */
29 #define cp_err cp_err_lower
30 u64 cp_control; /* 0x000020 */
31 u64 cp_req_timeout; /* 0x000028 */
32 u64 cp_intr_upper; /* 0x000030 */
33 u64 cp_intr_lower; /* 0x000038 */
34 #define cp_intr cp_intr_lower
35 u64 cp_err_cmdword; /* 0x000040 */
36 u64 _pad_000048; /* 0x000048 */
37 u64 cp_tflush; /* 0x000050 */
38
39 /* 0x000058-0x00007F -- Bridge-specific Configuration */
40 u64 cp_aux_err; /* 0x000058 */
41 u64 cp_resp_upper; /* 0x000060 */
42 u64 cp_resp_lower; /* 0x000068 */
43 #define cp_resp cp_resp_lower
44 u64 cp_tst_pin_ctrl; /* 0x000070 */
45 u64 cp_addr_lkerr; /* 0x000078 */
46
47 /* 0x000080-0x00008F -- PMU & MAP */
48 u64 cp_dir_map; /* 0x000080 */
49 u64 _pad_000088; /* 0x000088 */
50
51 /* 0x000090-0x00009F -- SSRAM */
52 u64 cp_map_fault; /* 0x000090 */
53 u64 _pad_000098; /* 0x000098 */
54
55 /* 0x0000A0-0x0000AF -- Arbitration */
56 u64 cp_arb; /* 0x0000A0 */
57 u64 _pad_0000A8; /* 0x0000A8 */
58
59 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
60 u64 cp_ate_parity_err; /* 0x0000B0 */
61 u64 _pad_0000B8; /* 0x0000B8 */
62
63 /* 0x0000C0-0x0000FF -- PCI/GIO */
64 u64 cp_bus_timeout; /* 0x0000C0 */
65 u64 cp_pci_cfg; /* 0x0000C8 */
66 u64 cp_pci_err_upper; /* 0x0000D0 */
67 u64 cp_pci_err_lower; /* 0x0000D8 */
68 #define cp_pci_err cp_pci_err_lower
69 u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
70
71 /* 0x000100-0x0001FF -- Interrupt */
72 u64 cp_int_status; /* 0x000100 */
73 u64 cp_int_enable; /* 0x000108 */
74 u64 cp_int_rst_stat; /* 0x000110 */
75 u64 cp_int_mode; /* 0x000118 */
76 u64 cp_int_device; /* 0x000120 */
77 u64 cp_int_host_err; /* 0x000128 */
78 u64 cp_int_addr[8]; /* 0x0001{30,,,68} */
79 u64 cp_err_int_view; /* 0x000170 */
80 u64 cp_mult_int; /* 0x000178 */
81 u64 cp_force_always[8]; /* 0x0001{80,,,B8} */
82 u64 cp_force_pin[8]; /* 0x0001{C0,,,F8} */
83
84 /* 0x000200-0x000298 -- Device */
85 u64 cp_device[4]; /* 0x0002{00,,,18} */
86 u64 _pad_000220[4]; /* 0x0002{20,,,38} */
87 u64 cp_wr_req_buf[4]; /* 0x0002{40,,,58} */
88 u64 _pad_000260[4]; /* 0x0002{60,,,78} */
89 u64 cp_rrb_map[2]; /* 0x0002{80,,,88} */
90 #define cp_even_resp cp_rrb_map[0] /* 0x000280 */
91 #define cp_odd_resp cp_rrb_map[1] /* 0x000288 */
92 u64 cp_resp_status; /* 0x000290 */
93 u64 cp_resp_clear; /* 0x000298 */
94
95 u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
96
97 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
98 struct {
99 u64 upper; /* 0x0003{00,,,F0} */
100 u64 lower; /* 0x0003{08,,,F8} */
101 } cp_buf_addr_match[16];
102
103 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
104 struct {
105 u64 flush_w_touch; /* 0x000{400,,,5C0} */
106 u64 flush_wo_touch; /* 0x000{408,,,5C8} */
107 u64 inflight; /* 0x000{410,,,5D0} */
108 u64 prefetch; /* 0x000{418,,,5D8} */
109 u64 total_pci_retry; /* 0x000{420,,,5E0} */
110 u64 max_pci_retry; /* 0x000{428,,,5E8} */
111 u64 max_latency; /* 0x000{430,,,5F0} */
112 u64 clear_all; /* 0x000{438,,,5F8} */
113 } cp_buf_count[8];
114
115
116 /* 0x000600-0x0009FF -- PCI/X registers */
117 u64 cp_pcix_bus_err_addr; /* 0x000600 */
118 u64 cp_pcix_bus_err_attr; /* 0x000608 */
119 u64 cp_pcix_bus_err_data; /* 0x000610 */
120 u64 cp_pcix_pio_split_addr; /* 0x000618 */
121 u64 cp_pcix_pio_split_attr; /* 0x000620 */
122 u64 cp_pcix_dma_req_err_attr; /* 0x000628 */
123 u64 cp_pcix_dma_req_err_addr; /* 0x000630 */
124 u64 cp_pcix_timeout; /* 0x000638 */
125
126 u64 _pad_000640[24]; /* 0x000{640,,,6F8} */
127
128 /* 0x000700-0x000737 -- Debug Registers */
129 u64 cp_ct_debug_ctl; /* 0x000700 */
130 u64 cp_br_debug_ctl; /* 0x000708 */
131 u64 cp_mux3_debug_ctl; /* 0x000710 */
132 u64 cp_mux4_debug_ctl; /* 0x000718 */
133 u64 cp_mux5_debug_ctl; /* 0x000720 */
134 u64 cp_mux6_debug_ctl; /* 0x000728 */
135 u64 cp_mux7_debug_ctl; /* 0x000730 */
136
137 u64 _pad_000738[89]; /* 0x000{738,,,9F8} */
138
139 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
140 struct {
141 u64 cp_buf_addr; /* 0x000{A00,,,AF0} */
142 u64 cp_buf_attr; /* 0X000{A08,,,AF8} */
143 } cp_pcix_read_buf_64[16];
144
145 struct {
146 u64 cp_buf_addr; /* 0x000{B00,,,BE0} */
147 u64 cp_buf_attr; /* 0x000{B08,,,BE8} */
148 u64 cp_buf_valid; /* 0x000{B10,,,BF0} */
149 u64 __pad1; /* 0x000{B18,,,BF8} */
150 } cp_pcix_write_buf_64[8];
151
152 /* End of Local Registers -- Start of Address Map space */
153
154 char _pad_000c00[0x010000 - 0x000c00];
155
156 /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
157 u64 cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */
158
159 char _pad_012000[0x14000 - 0x012000];
160
161 /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
162 u64 cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */
163
164 char _pad_016000[0x18000 - 0x016000];
165
166 /* 0x18000-0x197F8 -- TIOCP Write Request Ram */
167 u64 cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
168 u64 cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
169 u64 cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
170
171 char _pad_019800[0x1C000 - 0x019800];
172
173 /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
174 u64 cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */
175 u64 cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */
176 u64 cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */
177
178 char _pad_01F000[0x20000 - 0x01F000];
179
180 /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */
181 char _pad_020000[0x021000 - 0x20000];
182
183 /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
184 union {
185 u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
186 u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
187 u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
188 u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
189 union {
190 u8 c[0x100 / 1];
191 u16 s[0x100 / 2];
192 u32 l[0x100 / 4];
193 u64 d[0x100 / 8];
194 } f[8];
195 } cp_type0_cfg_dev[7]; /* 0x02{1000,,,7FFF} */
196
197 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
198 union {
199 u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
200 u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
201 u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
202 u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
203 union {
204 u8 c[0x100 / 1];
205 u16 s[0x100 / 2];
206 u32 l[0x100 / 4];
207 u64 d[0x100 / 8];
208 } f[8];
209 } cp_type1_cfg; /* 0x028000-0x029000 */
210
211 char _pad_029000[0x030000-0x029000];
212
213 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
214 union {
215 u8 c[8 / 1];
216 u16 s[8 / 2];
217 u32 l[8 / 4];
218 u64 d[8 / 8];
219 } cp_pci_iack; /* 0x030000-0x030007 */
220
221 char _pad_030007[0x040000-0x030008];
222
223 /* 0x040000-0x040007 -- PCIX Special Cycle */
224 union {
225 u8 c[8 / 1];
226 u16 s[8 / 2];
227 u32 l[8 / 4];
228 u64 d[8 / 8];
229 } cp_pcix_cycle; /* 0x040000-0x040007 */
230
231 char _pad_040007[0x200000-0x040008];
232
233 /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
234 union {
235 u8 c[0x100000 / 1];
236 u16 s[0x100000 / 2];
237 u32 l[0x100000 / 4];
238 u64 d[0x100000 / 8];
239 } cp_devio_raw[6]; /* 0x200000-0x7FFFFF */
240
241 #define cp_devio(n) cp_devio_raw[((n)<2)?(n*2):(n+2)]
242
243 char _pad_800000[0xA00000-0x800000];
244
245 /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush */
246 union {
247 u8 c[0x100000 / 1];
248 u16 s[0x100000 / 2];
249 u32 l[0x100000 / 4];
250 u64 d[0x100000 / 8];
251 } cp_devio_raw_flush[6]; /* 0xA00000-0xBFFFFF */
252
253 #define cp_devio_flush(n) cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
254
255};
256
257#endif /* _ASM_IA64_SN_PCI_TIOCP_H */
diff --git a/include/asm-ia64/sn/tiocx.h b/include/asm-ia64/sn/tiocx.h
deleted file mode 100644
index d29728492f36..000000000000
--- a/include/asm-ia64/sn/tiocx.h
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_TIO_TIOCX_H
10#define _ASM_IA64_SN_TIO_TIOCX_H
11
12#ifdef __KERNEL__
13
14struct cx_id_s {
15 unsigned int part_num;
16 unsigned int mfg_num;
17 int nasid;
18};
19
20struct cx_dev {
21 struct cx_id_s cx_id;
22 int bt; /* board/blade type */
23 void *soft; /* driver specific */
24 struct hubdev_info *hubdev;
25 struct device dev;
26 struct cx_drv *driver;
27};
28
29struct cx_device_id {
30 unsigned int part_num;
31 unsigned int mfg_num;
32};
33
34struct cx_drv {
35 char *name;
36 const struct cx_device_id *id_table;
37 struct device_driver driver;
38 int (*probe) (struct cx_dev * dev, const struct cx_device_id * id);
39 int (*remove) (struct cx_dev * dev);
40};
41
42/* create DMA address by stripping AS bits */
43#define TIOCX_DMA_ADDR(a) (u64)((u64)(a) & 0xffffcfffffffffUL)
44
45#define TIOCX_TO_TIOCX_DMA_ADDR(a) (u64)(((u64)(a) & 0xfffffffff) | \
46 ((((u64)(a)) & 0xffffc000000000UL) <<2))
47
48#define TIO_CE_ASIC_PARTNUM 0xce00
49#define TIOCX_CORELET 3
50
51/* These are taken from tio_mmr_as.h */
52#define TIO_ICE_FRZ_CFG TIO_MMR_ADDR_MOD(0x00000000b0008100UL)
53#define TIO_ICE_PMI_TX_CFG TIO_MMR_ADDR_MOD(0x00000000b000b100UL)
54#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3 TIO_MMR_ADDR_MOD(0x00000000b000be18UL)
55#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3_CREDIT_CNT_MASK 0x000000000000000fUL
56
57#define to_cx_dev(n) container_of(n, struct cx_dev, dev)
58#define to_cx_driver(drv) container_of(drv, struct cx_drv, driver)
59
60extern struct sn_irq_info *tiocx_irq_alloc(nasid_t, int, int, nasid_t, int);
61extern void tiocx_irq_free(struct sn_irq_info *);
62extern int cx_device_unregister(struct cx_dev *);
63extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int);
64extern int cx_driver_unregister(struct cx_drv *);
65extern int cx_driver_register(struct cx_drv *);
66extern u64 tiocx_dma_addr(u64 addr);
67extern u64 tiocx_swin_base(int nasid);
68extern void tiocx_mmr_store(int nasid, u64 offset, u64 value);
69extern u64 tiocx_mmr_load(int nasid, u64 offset);
70
71#endif // __KERNEL__
72#endif // _ASM_IA64_SN_TIO_TIOCX__
diff --git a/include/asm-ia64/sn/types.h b/include/asm-ia64/sn/types.h
deleted file mode 100644
index 8e04ee211e59..000000000000
--- a/include/asm-ia64/sn/types.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999,2001-2003 Silicon Graphics, Inc. All Rights Reserved.
7 * Copyright (C) 1999 by Ralf Baechle
8 */
9#ifndef _ASM_IA64_SN_TYPES_H
10#define _ASM_IA64_SN_TYPES_H
11
12#include <linux/types.h>
13
14typedef unsigned long cpuid_t;
15typedef signed short nasid_t; /* node id in numa-as-id space */
16typedef signed char partid_t; /* partition ID type */
17typedef unsigned int moduleid_t; /* user-visible module number type */
18typedef unsigned int cmoduleid_t; /* kernel compact module id type */
19typedef unsigned char slotid_t; /* slot (blade) within module */
20typedef unsigned char slabid_t; /* slab (asic) within slot */
21typedef u64 nic_t;
22typedef unsigned long iopaddr_t;
23typedef unsigned long paddr_t;
24typedef short cnodeid_t;
25
26#endif /* _ASM_IA64_SN_TYPES_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 13:24:48 -0500