aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-ia64/sn/tiocp.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-ia64/sn/tiocp.h')
-rw-r--r--include/asm-ia64/sn/tiocp.h254
1 files changed, 127 insertions, 127 deletions
diff --git a/include/asm-ia64/sn/tiocp.h b/include/asm-ia64/sn/tiocp.h
index 5f2489c9d2dd..f47c08ab483c 100644
--- a/include/asm-ia64/sn/tiocp.h
+++ b/include/asm-ia64/sn/tiocp.h
@@ -21,189 +21,189 @@ struct tiocp{
21 /* 0x000000-0x00FFFF -- Local Registers */ 21 /* 0x000000-0x00FFFF -- Local Registers */
22 22
23 /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */ 23 /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
24 uint64_t cp_id; /* 0x000000 */ 24 u64 cp_id; /* 0x000000 */
25 uint64_t cp_stat; /* 0x000008 */ 25 u64 cp_stat; /* 0x000008 */
26 uint64_t cp_err_upper; /* 0x000010 */ 26 u64 cp_err_upper; /* 0x000010 */
27 uint64_t cp_err_lower; /* 0x000018 */ 27 u64 cp_err_lower; /* 0x000018 */
28 #define cp_err cp_err_lower 28 #define cp_err cp_err_lower
29 uint64_t cp_control; /* 0x000020 */ 29 u64 cp_control; /* 0x000020 */
30 uint64_t cp_req_timeout; /* 0x000028 */ 30 u64 cp_req_timeout; /* 0x000028 */
31 uint64_t cp_intr_upper; /* 0x000030 */ 31 u64 cp_intr_upper; /* 0x000030 */
32 uint64_t cp_intr_lower; /* 0x000038 */ 32 u64 cp_intr_lower; /* 0x000038 */
33 #define cp_intr cp_intr_lower 33 #define cp_intr cp_intr_lower
34 uint64_t cp_err_cmdword; /* 0x000040 */ 34 u64 cp_err_cmdword; /* 0x000040 */
35 uint64_t _pad_000048; /* 0x000048 */ 35 u64 _pad_000048; /* 0x000048 */
36 uint64_t cp_tflush; /* 0x000050 */ 36 u64 cp_tflush; /* 0x000050 */
37 37
38 /* 0x000058-0x00007F -- Bridge-specific Configuration */ 38 /* 0x000058-0x00007F -- Bridge-specific Configuration */
39 uint64_t cp_aux_err; /* 0x000058 */ 39 u64 cp_aux_err; /* 0x000058 */
40 uint64_t cp_resp_upper; /* 0x000060 */ 40 u64 cp_resp_upper; /* 0x000060 */
41 uint64_t cp_resp_lower; /* 0x000068 */ 41 u64 cp_resp_lower; /* 0x000068 */
42 #define cp_resp cp_resp_lower 42 #define cp_resp cp_resp_lower
43 uint64_t cp_tst_pin_ctrl; /* 0x000070 */ 43 u64 cp_tst_pin_ctrl; /* 0x000070 */
44 uint64_t cp_addr_lkerr; /* 0x000078 */ 44 u64 cp_addr_lkerr; /* 0x000078 */
45 45
46 /* 0x000080-0x00008F -- PMU & MAP */ 46 /* 0x000080-0x00008F -- PMU & MAP */
47 uint64_t cp_dir_map; /* 0x000080 */ 47 u64 cp_dir_map; /* 0x000080 */
48 uint64_t _pad_000088; /* 0x000088 */ 48 u64 _pad_000088; /* 0x000088 */
49 49
50 /* 0x000090-0x00009F -- SSRAM */ 50 /* 0x000090-0x00009F -- SSRAM */
51 uint64_t cp_map_fault; /* 0x000090 */ 51 u64 cp_map_fault; /* 0x000090 */
52 uint64_t _pad_000098; /* 0x000098 */ 52 u64 _pad_000098; /* 0x000098 */
53 53
54 /* 0x0000A0-0x0000AF -- Arbitration */ 54 /* 0x0000A0-0x0000AF -- Arbitration */
55 uint64_t cp_arb; /* 0x0000A0 */ 55 u64 cp_arb; /* 0x0000A0 */
56 uint64_t _pad_0000A8; /* 0x0000A8 */ 56 u64 _pad_0000A8; /* 0x0000A8 */
57 57
58 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */ 58 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
59 uint64_t cp_ate_parity_err; /* 0x0000B0 */ 59 u64 cp_ate_parity_err; /* 0x0000B0 */
60 uint64_t _pad_0000B8; /* 0x0000B8 */ 60 u64 _pad_0000B8; /* 0x0000B8 */
61 61
62 /* 0x0000C0-0x0000FF -- PCI/GIO */ 62 /* 0x0000C0-0x0000FF -- PCI/GIO */
63 uint64_t cp_bus_timeout; /* 0x0000C0 */ 63 u64 cp_bus_timeout; /* 0x0000C0 */
64 uint64_t cp_pci_cfg; /* 0x0000C8 */ 64 u64 cp_pci_cfg; /* 0x0000C8 */
65 uint64_t cp_pci_err_upper; /* 0x0000D0 */ 65 u64 cp_pci_err_upper; /* 0x0000D0 */
66 uint64_t cp_pci_err_lower; /* 0x0000D8 */ 66 u64 cp_pci_err_lower; /* 0x0000D8 */
67 #define cp_pci_err cp_pci_err_lower 67 #define cp_pci_err cp_pci_err_lower
68 uint64_t _pad_0000E0[4]; /* 0x0000{E0..F8} */ 68 u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
69 69
70 /* 0x000100-0x0001FF -- Interrupt */ 70 /* 0x000100-0x0001FF -- Interrupt */
71 uint64_t cp_int_status; /* 0x000100 */ 71 u64 cp_int_status; /* 0x000100 */
72 uint64_t cp_int_enable; /* 0x000108 */ 72 u64 cp_int_enable; /* 0x000108 */
73 uint64_t cp_int_rst_stat; /* 0x000110 */ 73 u64 cp_int_rst_stat; /* 0x000110 */
74 uint64_t cp_int_mode; /* 0x000118 */ 74 u64 cp_int_mode; /* 0x000118 */
75 uint64_t cp_int_device; /* 0x000120 */ 75 u64 cp_int_device; /* 0x000120 */
76 uint64_t cp_int_host_err; /* 0x000128 */ 76 u64 cp_int_host_err; /* 0x000128 */
77 uint64_t cp_int_addr[8]; /* 0x0001{30,,,68} */ 77 u64 cp_int_addr[8]; /* 0x0001{30,,,68} */
78 uint64_t cp_err_int_view; /* 0x000170 */ 78 u64 cp_err_int_view; /* 0x000170 */
79 uint64_t cp_mult_int; /* 0x000178 */ 79 u64 cp_mult_int; /* 0x000178 */
80 uint64_t cp_force_always[8]; /* 0x0001{80,,,B8} */ 80 u64 cp_force_always[8]; /* 0x0001{80,,,B8} */
81 uint64_t cp_force_pin[8]; /* 0x0001{C0,,,F8} */ 81 u64 cp_force_pin[8]; /* 0x0001{C0,,,F8} */
82 82
83 /* 0x000200-0x000298 -- Device */ 83 /* 0x000200-0x000298 -- Device */
84 uint64_t cp_device[4]; /* 0x0002{00,,,18} */ 84 u64 cp_device[4]; /* 0x0002{00,,,18} */
85 uint64_t _pad_000220[4]; /* 0x0002{20,,,38} */ 85 u64 _pad_000220[4]; /* 0x0002{20,,,38} */
86 uint64_t cp_wr_req_buf[4]; /* 0x0002{40,,,58} */ 86 u64 cp_wr_req_buf[4]; /* 0x0002{40,,,58} */
87 uint64_t _pad_000260[4]; /* 0x0002{60,,,78} */ 87 u64 _pad_000260[4]; /* 0x0002{60,,,78} */
88 uint64_t cp_rrb_map[2]; /* 0x0002{80,,,88} */ 88 u64 cp_rrb_map[2]; /* 0x0002{80,,,88} */
89 #define cp_even_resp cp_rrb_map[0] /* 0x000280 */ 89 #define cp_even_resp cp_rrb_map[0] /* 0x000280 */
90 #define cp_odd_resp cp_rrb_map[1] /* 0x000288 */ 90 #define cp_odd_resp cp_rrb_map[1] /* 0x000288 */
91 uint64_t cp_resp_status; /* 0x000290 */ 91 u64 cp_resp_status; /* 0x000290 */
92 uint64_t cp_resp_clear; /* 0x000298 */ 92 u64 cp_resp_clear; /* 0x000298 */
93 93
94 uint64_t _pad_0002A0[12]; /* 0x0002{A0..F8} */ 94 u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
95 95
96 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */ 96 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
97 struct { 97 struct {
98 uint64_t upper; /* 0x0003{00,,,F0} */ 98 u64 upper; /* 0x0003{00,,,F0} */
99 uint64_t lower; /* 0x0003{08,,,F8} */ 99 u64 lower; /* 0x0003{08,,,F8} */
100 } cp_buf_addr_match[16]; 100 } cp_buf_addr_match[16];
101 101
102 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */ 102 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
103 struct { 103 struct {
104 uint64_t flush_w_touch; /* 0x000{400,,,5C0} */ 104 u64 flush_w_touch; /* 0x000{400,,,5C0} */
105 uint64_t flush_wo_touch; /* 0x000{408,,,5C8} */ 105 u64 flush_wo_touch; /* 0x000{408,,,5C8} */
106 uint64_t inflight; /* 0x000{410,,,5D0} */ 106 u64 inflight; /* 0x000{410,,,5D0} */
107 uint64_t prefetch; /* 0x000{418,,,5D8} */ 107 u64 prefetch; /* 0x000{418,,,5D8} */
108 uint64_t total_pci_retry; /* 0x000{420,,,5E0} */ 108 u64 total_pci_retry; /* 0x000{420,,,5E0} */
109 uint64_t max_pci_retry; /* 0x000{428,,,5E8} */ 109 u64 max_pci_retry; /* 0x000{428,,,5E8} */
110 uint64_t max_latency; /* 0x000{430,,,5F0} */ 110 u64 max_latency; /* 0x000{430,,,5F0} */
111 uint64_t clear_all; /* 0x000{438,,,5F8} */ 111 u64 clear_all; /* 0x000{438,,,5F8} */
112 } cp_buf_count[8]; 112 } cp_buf_count[8];
113 113
114 114
115 /* 0x000600-0x0009FF -- PCI/X registers */ 115 /* 0x000600-0x0009FF -- PCI/X registers */
116 uint64_t cp_pcix_bus_err_addr; /* 0x000600 */ 116 u64 cp_pcix_bus_err_addr; /* 0x000600 */
117 uint64_t cp_pcix_bus_err_attr; /* 0x000608 */ 117 u64 cp_pcix_bus_err_attr; /* 0x000608 */
118 uint64_t cp_pcix_bus_err_data; /* 0x000610 */ 118 u64 cp_pcix_bus_err_data; /* 0x000610 */
119 uint64_t cp_pcix_pio_split_addr; /* 0x000618 */ 119 u64 cp_pcix_pio_split_addr; /* 0x000618 */
120 uint64_t cp_pcix_pio_split_attr; /* 0x000620 */ 120 u64 cp_pcix_pio_split_attr; /* 0x000620 */
121 uint64_t cp_pcix_dma_req_err_attr; /* 0x000628 */ 121 u64 cp_pcix_dma_req_err_attr; /* 0x000628 */
122 uint64_t cp_pcix_dma_req_err_addr; /* 0x000630 */ 122 u64 cp_pcix_dma_req_err_addr; /* 0x000630 */
123 uint64_t cp_pcix_timeout; /* 0x000638 */ 123 u64 cp_pcix_timeout; /* 0x000638 */
124 124
125 uint64_t _pad_000640[24]; /* 0x000{640,,,6F8} */ 125 u64 _pad_000640[24]; /* 0x000{640,,,6F8} */
126 126
127 /* 0x000700-0x000737 -- Debug Registers */ 127 /* 0x000700-0x000737 -- Debug Registers */
128 uint64_t cp_ct_debug_ctl; /* 0x000700 */ 128 u64 cp_ct_debug_ctl; /* 0x000700 */
129 uint64_t cp_br_debug_ctl; /* 0x000708 */ 129 u64 cp_br_debug_ctl; /* 0x000708 */
130 uint64_t cp_mux3_debug_ctl; /* 0x000710 */ 130 u64 cp_mux3_debug_ctl; /* 0x000710 */
131 uint64_t cp_mux4_debug_ctl; /* 0x000718 */ 131 u64 cp_mux4_debug_ctl; /* 0x000718 */
132 uint64_t cp_mux5_debug_ctl; /* 0x000720 */ 132 u64 cp_mux5_debug_ctl; /* 0x000720 */
133 uint64_t cp_mux6_debug_ctl; /* 0x000728 */ 133 u64 cp_mux6_debug_ctl; /* 0x000728 */
134 uint64_t cp_mux7_debug_ctl; /* 0x000730 */ 134 u64 cp_mux7_debug_ctl; /* 0x000730 */
135 135
136 uint64_t _pad_000738[89]; /* 0x000{738,,,9F8} */ 136 u64 _pad_000738[89]; /* 0x000{738,,,9F8} */
137 137
138 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */ 138 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
139 struct { 139 struct {
140 uint64_t cp_buf_addr; /* 0x000{A00,,,AF0} */ 140 u64 cp_buf_addr; /* 0x000{A00,,,AF0} */
141 uint64_t cp_buf_attr; /* 0X000{A08,,,AF8} */ 141 u64 cp_buf_attr; /* 0X000{A08,,,AF8} */
142 } cp_pcix_read_buf_64[16]; 142 } cp_pcix_read_buf_64[16];
143 143
144 struct { 144 struct {
145 uint64_t cp_buf_addr; /* 0x000{B00,,,BE0} */ 145 u64 cp_buf_addr; /* 0x000{B00,,,BE0} */
146 uint64_t cp_buf_attr; /* 0x000{B08,,,BE8} */ 146 u64 cp_buf_attr; /* 0x000{B08,,,BE8} */
147 uint64_t cp_buf_valid; /* 0x000{B10,,,BF0} */ 147 u64 cp_buf_valid; /* 0x000{B10,,,BF0} */
148 uint64_t __pad1; /* 0x000{B18,,,BF8} */ 148 u64 __pad1; /* 0x000{B18,,,BF8} */
149 } cp_pcix_write_buf_64[8]; 149 } cp_pcix_write_buf_64[8];
150 150
151 /* End of Local Registers -- Start of Address Map space */ 151 /* End of Local Registers -- Start of Address Map space */
152 152
153 char _pad_000c00[0x010000 - 0x000c00]; 153 char _pad_000c00[0x010000 - 0x000c00];
154 154
155 /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */ 155 /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
156 uint64_t cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */ 156 u64 cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */
157 157
158 char _pad_012000[0x14000 - 0x012000]; 158 char _pad_012000[0x14000 - 0x012000];
159 159
160 /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */ 160 /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
161 uint64_t cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */ 161 u64 cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */
162 162
163 char _pad_016000[0x18000 - 0x016000]; 163 char _pad_016000[0x18000 - 0x016000];
164 164
165 /* 0x18000-0x197F8 -- TIOCP Write Request Ram */ 165 /* 0x18000-0x197F8 -- TIOCP Write Request Ram */
166 uint64_t cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */ 166 u64 cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
167 uint64_t cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */ 167 u64 cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
168 uint64_t cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */ 168 u64 cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
169 169
170 char _pad_019800[0x1C000 - 0x019800]; 170 char _pad_019800[0x1C000 - 0x019800];
171 171
172 /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */ 172 /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
173 uint64_t cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */ 173 u64 cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */
174 uint64_t cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */ 174 u64 cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */
175 uint64_t cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */ 175 u64 cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */
176 176
177 char _pad_01F000[0x20000 - 0x01F000]; 177 char _pad_01F000[0x20000 - 0x01F000];
178 178
179 /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */ 179 /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */
180 char _pad_020000[0x021000 - 0x20000]; 180 char _pad_020000[0x021000 - 0x20000];
181 181
182 /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */ 182 /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
183 union { 183 union {
184 uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ 184 u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
185 uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ 185 u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
186 uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ 186 u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
187 uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ 187 u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
188 union { 188 union {
189 uint8_t c[0x100 / 1]; 189 u8 c[0x100 / 1];
190 uint16_t s[0x100 / 2]; 190 u16 s[0x100 / 2];
191 uint32_t l[0x100 / 4]; 191 u32 l[0x100 / 4];
192 uint64_t d[0x100 / 8]; 192 u64 d[0x100 / 8];
193 } f[8]; 193 } f[8];
194 } cp_type0_cfg_dev[7]; /* 0x02{1000,,,7FFF} */ 194 } cp_type0_cfg_dev[7]; /* 0x02{1000,,,7FFF} */
195 195
196 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */ 196 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
197 union { 197 union {
198 uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */ 198 u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
199 uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */ 199 u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
200 uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */ 200 u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
201 uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */ 201 u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
202 union { 202 union {
203 uint8_t c[0x100 / 1]; 203 u8 c[0x100 / 1];
204 uint16_t s[0x100 / 2]; 204 u16 s[0x100 / 2];
205 uint32_t l[0x100 / 4]; 205 u32 l[0x100 / 4];
206 uint64_t d[0x100 / 8]; 206 u64 d[0x100 / 8];
207 } f[8]; 207 } f[8];
208 } cp_type1_cfg; /* 0x028000-0x029000 */ 208 } cp_type1_cfg; /* 0x028000-0x029000 */
209 209
@@ -211,30 +211,30 @@ struct tiocp{
211 211
212 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */ 212 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
213 union { 213 union {
214 uint8_t c[8 / 1]; 214 u8 c[8 / 1];
215 uint16_t s[8 / 2]; 215 u16 s[8 / 2];
216 uint32_t l[8 / 4]; 216 u32 l[8 / 4];
217 uint64_t d[8 / 8]; 217 u64 d[8 / 8];
218 } cp_pci_iack; /* 0x030000-0x030007 */ 218 } cp_pci_iack; /* 0x030000-0x030007 */
219 219
220 char _pad_030007[0x040000-0x030008]; 220 char _pad_030007[0x040000-0x030008];
221 221
222 /* 0x040000-0x040007 -- PCIX Special Cycle */ 222 /* 0x040000-0x040007 -- PCIX Special Cycle */
223 union { 223 union {
224 uint8_t c[8 / 1]; 224 u8 c[8 / 1];
225 uint16_t s[8 / 2]; 225 u16 s[8 / 2];
226 uint32_t l[8 / 4]; 226 u32 l[8 / 4];
227 uint64_t d[8 / 8]; 227 u64 d[8 / 8];
228 } cp_pcix_cycle; /* 0x040000-0x040007 */ 228 } cp_pcix_cycle; /* 0x040000-0x040007 */
229 229
230 char _pad_040007[0x200000-0x040008]; 230 char _pad_040007[0x200000-0x040008];
231 231
232 /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */ 232 /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
233 union { 233 union {
234 uint8_t c[0x100000 / 1]; 234 u8 c[0x100000 / 1];
235 uint16_t s[0x100000 / 2]; 235 u16 s[0x100000 / 2];
236 uint32_t l[0x100000 / 4]; 236 u32 l[0x100000 / 4];
237 uint64_t d[0x100000 / 8]; 237 u64 d[0x100000 / 8];
238 } cp_devio_raw[6]; /* 0x200000-0x7FFFFF */ 238 } cp_devio_raw[6]; /* 0x200000-0x7FFFFF */
239 239
240 #define cp_devio(n) cp_devio_raw[((n)<2)?(n*2):(n+2)] 240 #define cp_devio(n) cp_devio_raw[((n)<2)?(n*2):(n+2)]
@@ -243,10 +243,10 @@ struct tiocp{
243 243
244 /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush */ 244 /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush */
245 union { 245 union {
246 uint8_t c[0x100000 / 1]; 246 u8 c[0x100000 / 1];
247 uint16_t s[0x100000 / 2]; 247 u16 s[0x100000 / 2];
248 uint32_t l[0x100000 / 4]; 248 u32 l[0x100000 / 4];
249 uint64_t d[0x100000 / 8]; 249 u64 d[0x100000 / 8];
250 } cp_devio_raw_flush[6]; /* 0xA00000-0xBFFFFF */ 250 } cp_devio_raw_flush[6]; /* 0xA00000-0xBFFFFF */
251 251
252 #define cp_devio_flush(n) cp_devio_raw_flush[((n)<2)?(n*2):(n+2)] 252 #define cp_devio_flush(n) cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-09 01:10:56 -0500