diff options
Diffstat (limited to 'include/asm-ia64/sn/tioca.h')
| -rw-r--r-- | include/asm-ia64/sn/tioca.h | 596 |
1 files changed, 596 insertions, 0 deletions
diff --git a/include/asm-ia64/sn/tioca.h b/include/asm-ia64/sn/tioca.h new file mode 100644 index 000000000000..bc1aacfb9483 --- /dev/null +++ b/include/asm-ia64/sn/tioca.h | |||
| @@ -0,0 +1,596 @@ | |||
| 1 | #ifndef _ASM_IA64_SN_TIO_TIOCA_H | ||
| 2 | #define _ASM_IA64_SN_TIO_TIOCA_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 6 | * License. See the file "COPYING" in the main directory of this archive | ||
| 7 | * for more details. | ||
| 8 | * | ||
| 9 | * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved. | ||
| 10 | */ | ||
| 11 | |||
| 12 | |||
| 13 | #define TIOCA_PART_NUM 0xE020 | ||
| 14 | #define TIOCA_MFGR_NUM 0x24 | ||
| 15 | #define TIOCA_REV_A 0x1 | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Register layout for TIO:CA. See below for bitmasks for each register. | ||
| 19 | */ | ||
| 20 | |||
| 21 | struct tioca { | ||
| 22 | uint64_t ca_id; /* 0x000000 */ | ||
| 23 | uint64_t ca_control1; /* 0x000008 */ | ||
| 24 | uint64_t ca_control2; /* 0x000010 */ | ||
| 25 | uint64_t ca_status1; /* 0x000018 */ | ||
| 26 | uint64_t ca_status2; /* 0x000020 */ | ||
| 27 | uint64_t ca_gart_aperature; /* 0x000028 */ | ||
| 28 | uint64_t ca_gfx_detach; /* 0x000030 */ | ||
| 29 | uint64_t ca_inta_dest_addr; /* 0x000038 */ | ||
| 30 | uint64_t ca_intb_dest_addr; /* 0x000040 */ | ||
| 31 | uint64_t ca_err_int_dest_addr; /* 0x000048 */ | ||
| 32 | uint64_t ca_int_status; /* 0x000050 */ | ||
| 33 | uint64_t ca_int_status_alias; /* 0x000058 */ | ||
| 34 | uint64_t ca_mult_error; /* 0x000060 */ | ||
| 35 | uint64_t ca_mult_error_alias; /* 0x000068 */ | ||
| 36 | uint64_t ca_first_error; /* 0x000070 */ | ||
| 37 | uint64_t ca_int_mask; /* 0x000078 */ | ||
| 38 | uint64_t ca_crm_pkterr_type; /* 0x000080 */ | ||
| 39 | uint64_t ca_crm_pkterr_type_alias; /* 0x000088 */ | ||
| 40 | uint64_t ca_crm_ct_error_detail_1; /* 0x000090 */ | ||
| 41 | uint64_t ca_crm_ct_error_detail_2; /* 0x000098 */ | ||
| 42 | uint64_t ca_crm_tnumto; /* 0x0000A0 */ | ||
| 43 | uint64_t ca_gart_err; /* 0x0000A8 */ | ||
| 44 | uint64_t ca_pcierr_type; /* 0x0000B0 */ | ||
| 45 | uint64_t ca_pcierr_addr; /* 0x0000B8 */ | ||
| 46 | |||
| 47 | uint64_t ca_pad_0000C0[3]; /* 0x0000{C0..D0} */ | ||
| 48 | |||
| 49 | uint64_t ca_pci_rd_buf_flush; /* 0x0000D8 */ | ||
| 50 | uint64_t ca_pci_dma_addr_extn; /* 0x0000E0 */ | ||
| 51 | uint64_t ca_agp_dma_addr_extn; /* 0x0000E8 */ | ||
| 52 | uint64_t ca_force_inta; /* 0x0000F0 */ | ||
| 53 | uint64_t ca_force_intb; /* 0x0000F8 */ | ||
| 54 | uint64_t ca_debug_vector_sel; /* 0x000100 */ | ||
| 55 | uint64_t ca_debug_mux_core_sel; /* 0x000108 */ | ||
| 56 | uint64_t ca_debug_mux_pci_sel; /* 0x000110 */ | ||
| 57 | uint64_t ca_debug_domain_sel; /* 0x000118 */ | ||
| 58 | |||
| 59 | uint64_t ca_pad_000120[28]; /* 0x0001{20..F8} */ | ||
| 60 | |||
| 61 | uint64_t ca_gart_ptr_table; /* 0x200 */ | ||
| 62 | uint64_t ca_gart_tlb_addr[8]; /* 0x2{08..40} */ | ||
| 63 | }; | ||
| 64 | |||
| 65 | /* | ||
| 66 | * Mask/shift definitions for TIO:CA registers. The convention here is | ||
| 67 | * to mainly use the names as they appear in the "TIO AEGIS Programmers' | ||
| 68 | * Reference" with a CA_ prefix added. Some exceptions were made to fix | ||
| 69 | * duplicate field names or to generalize fields that are common to | ||
| 70 | * different registers (ca_debug_mux_core_sel and ca_debug_mux_pci_sel for | ||
| 71 | * example). | ||
| 72 | * | ||
| 73 | * Fields consisting of a single bit have a single #define have a single | ||
| 74 | * macro declaration to mask the bit. Fields consisting of multiple bits | ||
| 75 | * have two declarations: one to mask the proper bits in a register, and | ||
| 76 | * a second with the suffix "_SHFT" to identify how far the mask needs to | ||
| 77 | * be shifted right to get its base value. | ||
| 78 | */ | ||
| 79 | |||
| 80 | /* ==== ca_control1 */ | ||
| 81 | #define CA_SYS_BIG_END (1ull << 0) | ||
| 82 | #define CA_DMA_AGP_SWAP (1ull << 1) | ||
| 83 | #define CA_DMA_PCI_SWAP (1ull << 2) | ||
| 84 | #define CA_PIO_IO_SWAP (1ull << 3) | ||
| 85 | #define CA_PIO_MEM_SWAP (1ull << 4) | ||
| 86 | #define CA_GFX_WR_SWAP (1ull << 5) | ||
| 87 | #define CA_AGP_FW_ENABLE (1ull << 6) | ||
| 88 | #define CA_AGP_CAL_CYCLE (0x7ull << 7) | ||
| 89 | #define CA_AGP_CAL_CYCLE_SHFT 7 | ||
| 90 | #define CA_AGP_CAL_PRSCL_BYP (1ull << 10) | ||
| 91 | #define CA_AGP_INIT_CAL_ENB (1ull << 11) | ||
| 92 | #define CA_INJ_ADDR_PERR (1ull << 12) | ||
| 93 | #define CA_INJ_DATA_PERR (1ull << 13) | ||
| 94 | /* bits 15:14 unused */ | ||
| 95 | #define CA_PCIM_IO_NBE_AD (0x7ull << 16) | ||
| 96 | #define CA_PCIM_IO_NBE_AD_SHFT 16 | ||
| 97 | #define CA_PCIM_FAST_BTB_ENB (1ull << 19) | ||
| 98 | /* bits 23:20 unused */ | ||
| 99 | #define CA_PIO_ADDR_OFFSET (0xffull << 24) | ||
| 100 | #define CA_PIO_ADDR_OFFSET_SHFT 24 | ||
| 101 | /* bits 35:32 unused */ | ||
| 102 | #define CA_AGPDMA_OP_COMBDELAY (0x1full << 36) | ||
| 103 | #define CA_AGPDMA_OP_COMBDELAY_SHFT 36 | ||
| 104 | /* bit 41 unused */ | ||
| 105 | #define CA_AGPDMA_OP_ENB_COMBDELAY (1ull << 42) | ||
| 106 | #define CA_PCI_INT_LPCNT (0xffull << 44) | ||
| 107 | #define CA_PCI_INT_LPCNT_SHFT 44 | ||
| 108 | /* bits 63:52 unused */ | ||
| 109 | |||
| 110 | /* ==== ca_control2 */ | ||
| 111 | #define CA_AGP_LATENCY_TO (0xffull << 0) | ||
| 112 | #define CA_AGP_LATENCY_TO_SHFT 0 | ||
| 113 | #define CA_PCI_LATENCY_TO (0xffull << 8) | ||
| 114 | #define CA_PCI_LATENCY_TO_SHFT 8 | ||
| 115 | #define CA_PCI_MAX_RETRY (0x3ffull << 16) | ||
| 116 | #define CA_PCI_MAX_RETRY_SHFT 16 | ||
| 117 | /* bits 27:26 unused */ | ||
| 118 | #define CA_RT_INT_EN (0x3ull << 28) | ||
| 119 | #define CA_RT_INT_EN_SHFT 28 | ||
| 120 | #define CA_MSI_INT_ENB (1ull << 30) | ||
| 121 | #define CA_PCI_ARB_ERR_ENB (1ull << 31) | ||
| 122 | #define CA_GART_MEM_PARAM (0x3ull << 32) | ||
| 123 | #define CA_GART_MEM_PARAM_SHFT 32 | ||
| 124 | #define CA_GART_RD_PREFETCH_ENB (1ull << 34) | ||
| 125 | #define CA_GART_WR_PREFETCH_ENB (1ull << 35) | ||
| 126 | #define CA_GART_FLUSH_TLB (1ull << 36) | ||
| 127 | /* bits 39:37 unused */ | ||
| 128 | #define CA_CRM_TNUMTO_PERIOD (0x1fffull << 40) | ||
| 129 | #define CA_CRM_TNUMTO_PERIOD_SHFT 40 | ||
| 130 | /* bits 55:53 unused */ | ||
| 131 | #define CA_CRM_TNUMTO_ENB (1ull << 56) | ||
| 132 | #define CA_CRM_PRESCALER_BYP (1ull << 57) | ||
| 133 | /* bits 59:58 unused */ | ||
| 134 | #define CA_CRM_MAX_CREDIT (0x7ull << 60) | ||
| 135 | #define CA_CRM_MAX_CREDIT_SHFT 60 | ||
| 136 | /* bit 63 unused */ | ||
| 137 | |||
| 138 | /* ==== ca_status1 */ | ||
| 139 | #define CA_CORELET_ID (0x3ull << 0) | ||
| 140 | #define CA_CORELET_ID_SHFT 0 | ||
| 141 | #define CA_INTA_N (1ull << 2) | ||
| 142 | #define CA_INTB_N (1ull << 3) | ||
| 143 | #define CA_CRM_CREDIT_AVAIL (0x7ull << 4) | ||
| 144 | #define CA_CRM_CREDIT_AVAIL_SHFT 4 | ||
| 145 | /* bit 7 unused */ | ||
| 146 | #define CA_CRM_SPACE_AVAIL (0x7full << 8) | ||
| 147 | #define CA_CRM_SPACE_AVAIL_SHFT 8 | ||
| 148 | /* bit 15 unused */ | ||
| 149 | #define CA_GART_TLB_VAL (0xffull << 16) | ||
| 150 | #define CA_GART_TLB_VAL_SHFT 16 | ||
| 151 | /* bits 63:24 unused */ | ||
| 152 | |||
| 153 | /* ==== ca_status2 */ | ||
| 154 | #define CA_GFX_CREDIT_AVAIL (0xffull << 0) | ||
| 155 | #define CA_GFX_CREDIT_AVAIL_SHFT 0 | ||
| 156 | #define CA_GFX_OPQ_AVAIL (0xffull << 8) | ||
| 157 | #define CA_GFX_OPQ_AVAIL_SHFT 8 | ||
| 158 | #define CA_GFX_WRBUFF_AVAIL (0xffull << 16) | ||
| 159 | #define CA_GFX_WRBUFF_AVAIL_SHFT 16 | ||
| 160 | #define CA_ADMA_OPQ_AVAIL (0xffull << 24) | ||
| 161 | #define CA_ADMA_OPQ_AVAIL_SHFT 24 | ||
| 162 | #define CA_ADMA_WRBUFF_AVAIL (0xffull << 32) | ||
| 163 | #define CA_ADMA_WRBUFF_AVAIL_SHFT 32 | ||
| 164 | #define CA_ADMA_RDBUFF_AVAIL (0x7full << 40) | ||
| 165 | #define CA_ADMA_RDBUFF_AVAIL_SHFT 40 | ||
| 166 | #define CA_PCI_PIO_OP_STAT (1ull << 47) | ||
| 167 | #define CA_PDMA_OPQ_AVAIL (0xfull << 48) | ||
| 168 | #define CA_PDMA_OPQ_AVAIL_SHFT 48 | ||
| 169 | #define CA_PDMA_WRBUFF_AVAIL (0xfull << 52) | ||
| 170 | #define CA_PDMA_WRBUFF_AVAIL_SHFT 52 | ||
| 171 | #define CA_PDMA_RDBUFF_AVAIL (0x3ull << 56) | ||
| 172 | #define CA_PDMA_RDBUFF_AVAIL_SHFT 56 | ||
| 173 | /* bits 63:58 unused */ | ||
| 174 | |||
| 175 | /* ==== ca_gart_aperature */ | ||
| 176 | #define CA_GART_AP_ENB_AGP (1ull << 0) | ||
| 177 | #define CA_GART_PAGE_SIZE (1ull << 1) | ||
| 178 | #define CA_GART_AP_ENB_PCI (1ull << 2) | ||
| 179 | /* bits 11:3 unused */ | ||
| 180 | #define CA_GART_AP_SIZE (0x3ffull << 12) | ||
| 181 | #define CA_GART_AP_SIZE_SHFT 12 | ||
| 182 | #define CA_GART_AP_BASE (0x3ffffffffffull << 22) | ||
| 183 | #define CA_GART_AP_BASE_SHFT 22 | ||
| 184 | |||
| 185 | /* ==== ca_inta_dest_addr | ||
| 186 | ==== ca_intb_dest_addr | ||
| 187 | ==== ca_err_int_dest_addr */ | ||
| 188 | /* bits 2:0 unused */ | ||
| 189 | #define CA_INT_DEST_ADDR (0x7ffffffffffffull << 3) | ||
| 190 | #define CA_INT_DEST_ADDR_SHFT 3 | ||
| 191 | /* bits 55:54 unused */ | ||
| 192 | #define CA_INT_DEST_VECT (0xffull << 56) | ||
| 193 | #define CA_INT_DEST_VECT_SHFT 56 | ||
| 194 | |||
| 195 | /* ==== ca_int_status */ | ||
| 196 | /* ==== ca_int_status_alias */ | ||
| 197 | /* ==== ca_mult_error */ | ||
| 198 | /* ==== ca_mult_error_alias */ | ||
| 199 | /* ==== ca_first_error */ | ||
| 200 | /* ==== ca_int_mask */ | ||
| 201 | #define CA_PCI_ERR (1ull << 0) | ||
| 202 | /* bits 3:1 unused */ | ||
| 203 | #define CA_GART_FETCH_ERR (1ull << 4) | ||
| 204 | #define CA_GFX_WR_OVFLW (1ull << 5) | ||
| 205 | #define CA_PIO_REQ_OVFLW (1ull << 6) | ||
| 206 | #define CA_CRM_PKTERR (1ull << 7) | ||
| 207 | #define CA_CRM_DVERR (1ull << 8) | ||
| 208 | #define CA_TNUMTO (1ull << 9) | ||
| 209 | #define CA_CXM_RSP_CRED_OVFLW (1ull << 10) | ||
| 210 | #define CA_CXM_REQ_CRED_OVFLW (1ull << 11) | ||
| 211 | #define CA_PIO_INVALID_ADDR (1ull << 12) | ||
| 212 | #define CA_PCI_ARB_TO (1ull << 13) | ||
| 213 | #define CA_AGP_REQ_OFLOW (1ull << 14) | ||
| 214 | #define CA_SBA_TYPE1_ERR (1ull << 15) | ||
| 215 | /* bit 16 unused */ | ||
| 216 | #define CA_INTA (1ull << 17) | ||
| 217 | #define CA_INTB (1ull << 18) | ||
| 218 | #define CA_MULT_INTA (1ull << 19) | ||
| 219 | #define CA_MULT_INTB (1ull << 20) | ||
| 220 | #define CA_GFX_CREDIT_OVFLW (1ull << 21) | ||
| 221 | /* bits 63:22 unused */ | ||
| 222 | |||
| 223 | /* ==== ca_crm_pkterr_type */ | ||
| 224 | /* ==== ca_crm_pkterr_type_alias */ | ||
| 225 | #define CA_CRM_PKTERR_SBERR_HDR (1ull << 0) | ||
| 226 | #define CA_CRM_PKTERR_DIDN (1ull << 1) | ||
| 227 | #define CA_CRM_PKTERR_PACTYPE (1ull << 2) | ||
| 228 | #define CA_CRM_PKTERR_INV_TNUM (1ull << 3) | ||
| 229 | #define CA_CRM_PKTERR_ADDR_RNG (1ull << 4) | ||
| 230 | #define CA_CRM_PKTERR_ADDR_ALGN (1ull << 5) | ||
| 231 | #define CA_CRM_PKTERR_HDR_PARAM (1ull << 6) | ||
| 232 | #define CA_CRM_PKTERR_CW_ERR (1ull << 7) | ||
| 233 | #define CA_CRM_PKTERR_SBERR_NH (1ull << 8) | ||
| 234 | #define CA_CRM_PKTERR_EARLY_TERM (1ull << 9) | ||
| 235 | #define CA_CRM_PKTERR_EARLY_TAIL (1ull << 10) | ||
| 236 | #define CA_CRM_PKTERR_MSSNG_TAIL (1ull << 11) | ||
| 237 | #define CA_CRM_PKTERR_MSSNG_HDR (1ull << 12) | ||
| 238 | /* bits 15:13 unused */ | ||
| 239 | #define CA_FIRST_CRM_PKTERR_SBERR_HDR (1ull << 16) | ||
| 240 | #define CA_FIRST_CRM_PKTERR_DIDN (1ull << 17) | ||
| 241 | #define CA_FIRST_CRM_PKTERR_PACTYPE (1ull << 18) | ||
| 242 | #define CA_FIRST_CRM_PKTERR_INV_TNUM (1ull << 19) | ||
| 243 | #define CA_FIRST_CRM_PKTERR_ADDR_RNG (1ull << 20) | ||
| 244 | #define CA_FIRST_CRM_PKTERR_ADDR_ALGN (1ull << 21) | ||
| 245 | #define CA_FIRST_CRM_PKTERR_HDR_PARAM (1ull << 22) | ||
| 246 | #define CA_FIRST_CRM_PKTERR_CW_ERR (1ull << 23) | ||
| 247 | #define CA_FIRST_CRM_PKTERR_SBERR_NH (1ull << 24) | ||
| 248 | #define CA_FIRST_CRM_PKTERR_EARLY_TERM (1ull << 25) | ||
| 249 | #define CA_FIRST_CRM_PKTERR_EARLY_TAIL (1ull << 26) | ||
| 250 | #define CA_FIRST_CRM_PKTERR_MSSNG_TAIL (1ull << 27) | ||
| 251 | #define CA_FIRST_CRM_PKTERR_MSSNG_HDR (1ull << 28) | ||
| 252 | /* bits 63:29 unused */ | ||
| 253 | |||
| 254 | /* ==== ca_crm_ct_error_detail_1 */ | ||
| 255 | #define CA_PKT_TYPE (0xfull << 0) | ||
| 256 | #define CA_PKT_TYPE_SHFT 0 | ||
| 257 | #define CA_SRC_ID (0x3ull << 4) | ||
| 258 | #define CA_SRC_ID_SHFT 4 | ||
| 259 | #define CA_DATA_SZ (0x3ull << 6) | ||
| 260 | #define CA_DATA_SZ_SHFT 6 | ||
| 261 | #define CA_TNUM (0xffull << 8) | ||
| 262 | #define CA_TNUM_SHFT 8 | ||
| 263 | #define CA_DW_DATA_EN (0xffull << 16) | ||
| 264 | #define CA_DW_DATA_EN_SHFT 16 | ||
| 265 | #define CA_GFX_CRED (0xffull << 24) | ||
| 266 | #define CA_GFX_CRED_SHFT 24 | ||
| 267 | #define CA_MEM_RD_PARAM (0x3ull << 32) | ||
| 268 | #define CA_MEM_RD_PARAM_SHFT 32 | ||
| 269 | #define CA_PIO_OP (1ull << 34) | ||
| 270 | #define CA_CW_ERR (1ull << 35) | ||
| 271 | /* bits 62:36 unused */ | ||
| 272 | #define CA_VALID (1ull << 63) | ||
| 273 | |||
| 274 | /* ==== ca_crm_ct_error_detail_2 */ | ||
| 275 | /* bits 2:0 unused */ | ||
| 276 | #define CA_PKT_ADDR (0x1fffffffffffffull << 3) | ||
| 277 | #define CA_PKT_ADDR_SHFT 3 | ||
| 278 | /* bits 63:56 unused */ | ||
| 279 | |||
| 280 | /* ==== ca_crm_tnumto */ | ||
| 281 | #define CA_CRM_TNUMTO_VAL (0xffull << 0) | ||
| 282 | #define CA_CRM_TNUMTO_VAL_SHFT 0 | ||
| 283 | #define CA_CRM_TNUMTO_WR (1ull << 8) | ||
| 284 | /* bits 63:9 unused */ | ||
| 285 | |||
| 286 | /* ==== ca_gart_err */ | ||
| 287 | #define CA_GART_ERR_SOURCE (0x3ull << 0) | ||
| 288 | #define CA_GART_ERR_SOURCE_SHFT 0 | ||
| 289 | /* bits 3:2 unused */ | ||
| 290 | #define CA_GART_ERR_ADDR (0xfffffffffull << 4) | ||
| 291 | #define CA_GART_ERR_ADDR_SHFT 4 | ||
| 292 | /* bits 63:40 unused */ | ||
| 293 | |||
| 294 | /* ==== ca_pcierr_type */ | ||
| 295 | #define CA_PCIERR_DATA (0xffffffffull << 0) | ||
| 296 | #define CA_PCIERR_DATA_SHFT 0 | ||
| 297 | #define CA_PCIERR_ENB (0xfull << 32) | ||
| 298 | #define CA_PCIERR_ENB_SHFT 32 | ||
| 299 | #define CA_PCIERR_CMD (0xfull << 36) | ||
| 300 | #define CA_PCIERR_CMD_SHFT 36 | ||
| 301 | #define CA_PCIERR_A64 (1ull << 40) | ||
| 302 | #define CA_PCIERR_SLV_SERR (1ull << 41) | ||
| 303 | #define CA_PCIERR_SLV_WR_PERR (1ull << 42) | ||
| 304 | #define CA_PCIERR_SLV_RD_PERR (1ull << 43) | ||
| 305 | #define CA_PCIERR_MST_SERR (1ull << 44) | ||
| 306 | #define CA_PCIERR_MST_WR_PERR (1ull << 45) | ||
| 307 | #define CA_PCIERR_MST_RD_PERR (1ull << 46) | ||
| 308 | #define CA_PCIERR_MST_MABT (1ull << 47) | ||
| 309 | #define CA_PCIERR_MST_TABT (1ull << 48) | ||
| 310 | #define CA_PCIERR_MST_RETRY_TOUT (1ull << 49) | ||
| 311 | |||
| 312 | #define CA_PCIERR_TYPES \ | ||
| 313 | (CA_PCIERR_A64|CA_PCIERR_SLV_SERR| \ | ||
| 314 | CA_PCIERR_SLV_WR_PERR|CA_PCIERR_SLV_RD_PERR| \ | ||
| 315 | CA_PCIERR_MST_SERR|CA_PCIERR_MST_WR_PERR|CA_PCIERR_MST_RD_PERR| \ | ||
| 316 | CA_PCIERR_MST_MABT|CA_PCIERR_MST_TABT|CA_PCIERR_MST_RETRY_TOUT) | ||
| 317 | |||
| 318 | /* bits 63:50 unused */ | ||
| 319 | |||
| 320 | /* ==== ca_pci_dma_addr_extn */ | ||
| 321 | #define CA_UPPER_NODE_OFFSET (0x3full << 0) | ||
| 322 | #define CA_UPPER_NODE_OFFSET_SHFT 0 | ||
| 323 | /* bits 7:6 unused */ | ||
| 324 | #define CA_CHIPLET_ID (0x3ull << 8) | ||
| 325 | #define CA_CHIPLET_ID_SHFT 8 | ||
| 326 | /* bits 11:10 unused */ | ||
| 327 | #define CA_PCI_DMA_NODE_ID (0xffffull << 12) | ||
| 328 | #define CA_PCI_DMA_NODE_ID_SHFT 12 | ||
| 329 | /* bits 27:26 unused */ | ||
| 330 | #define CA_PCI_DMA_PIO_MEM_TYPE (1ull << 28) | ||
| 331 | /* bits 63:29 unused */ | ||
| 332 | |||
| 333 | |||
| 334 | /* ==== ca_agp_dma_addr_extn */ | ||
| 335 | /* bits 19:0 unused */ | ||
| 336 | #define CA_AGP_DMA_NODE_ID (0xffffull << 20) | ||
| 337 | #define CA_AGP_DMA_NODE_ID_SHFT 20 | ||
| 338 | /* bits 27:26 unused */ | ||
| 339 | #define CA_AGP_DMA_PIO_MEM_TYPE (1ull << 28) | ||
| 340 | /* bits 63:29 unused */ | ||
| 341 | |||
| 342 | /* ==== ca_debug_vector_sel */ | ||
| 343 | #define CA_DEBUG_MN_VSEL (0xfull << 0) | ||
| 344 | #define CA_DEBUG_MN_VSEL_SHFT 0 | ||
| 345 | #define CA_DEBUG_PP_VSEL (0xfull << 4) | ||
| 346 | #define CA_DEBUG_PP_VSEL_SHFT 4 | ||
| 347 | #define CA_DEBUG_GW_VSEL (0xfull << 8) | ||
| 348 | #define CA_DEBUG_GW_VSEL_SHFT 8 | ||
| 349 | #define CA_DEBUG_GT_VSEL (0xfull << 12) | ||
| 350 | #define CA_DEBUG_GT_VSEL_SHFT 12 | ||
| 351 | #define CA_DEBUG_PD_VSEL (0xfull << 16) | ||
| 352 | #define CA_DEBUG_PD_VSEL_SHFT 16 | ||
| 353 | #define CA_DEBUG_AD_VSEL (0xfull << 20) | ||
| 354 | #define CA_DEBUG_AD_VSEL_SHFT 20 | ||
| 355 | #define CA_DEBUG_CX_VSEL (0xfull << 24) | ||
| 356 | #define CA_DEBUG_CX_VSEL_SHFT 24 | ||
| 357 | #define CA_DEBUG_CR_VSEL (0xfull << 28) | ||
| 358 | #define CA_DEBUG_CR_VSEL_SHFT 28 | ||
| 359 | #define CA_DEBUG_BA_VSEL (0xfull << 32) | ||
| 360 | #define CA_DEBUG_BA_VSEL_SHFT 32 | ||
| 361 | #define CA_DEBUG_PE_VSEL (0xfull << 36) | ||
| 362 | #define CA_DEBUG_PE_VSEL_SHFT 36 | ||
| 363 | #define CA_DEBUG_BO_VSEL (0xfull << 40) | ||
| 364 | #define CA_DEBUG_BO_VSEL_SHFT 40 | ||
| 365 | #define CA_DEBUG_BI_VSEL (0xfull << 44) | ||
| 366 | #define CA_DEBUG_BI_VSEL_SHFT 44 | ||
| 367 | #define CA_DEBUG_AS_VSEL (0xfull << 48) | ||
| 368 | #define CA_DEBUG_AS_VSEL_SHFT 48 | ||
| 369 | #define CA_DEBUG_PS_VSEL (0xfull << 52) | ||
| 370 | #define CA_DEBUG_PS_VSEL_SHFT 52 | ||
| 371 | #define CA_DEBUG_PM_VSEL (0xfull << 56) | ||
| 372 | #define CA_DEBUG_PM_VSEL_SHFT 56 | ||
| 373 | /* bits 63:60 unused */ | ||
| 374 | |||
| 375 | /* ==== ca_debug_mux_core_sel */ | ||
| 376 | /* ==== ca_debug_mux_pci_sel */ | ||
| 377 | #define CA_DEBUG_MSEL0 (0x7ull << 0) | ||
| 378 | #define CA_DEBUG_MSEL0_SHFT 0 | ||
| 379 | /* bit 3 unused */ | ||
| 380 | #define CA_DEBUG_NSEL0 (0x7ull << 4) | ||
| 381 | #define CA_DEBUG_NSEL0_SHFT 4 | ||
| 382 | /* bit 7 unused */ | ||
| 383 | #define CA_DEBUG_MSEL1 (0x7ull << 8) | ||
| 384 | #define CA_DEBUG_MSEL1_SHFT 8 | ||
| 385 | /* bit 11 unused */ | ||
| 386 | #define CA_DEBUG_NSEL1 (0x7ull << 12) | ||
| 387 | #define CA_DEBUG_NSEL1_SHFT 12 | ||
| 388 | /* bit 15 unused */ | ||
| 389 | #define CA_DEBUG_MSEL2 (0x7ull << 16) | ||
| 390 | #define CA_DEBUG_MSEL2_SHFT 16 | ||
| 391 | /* bit 19 unused */ | ||
| 392 | #define CA_DEBUG_NSEL2 (0x7ull << 20) | ||
| 393 | #define CA_DEBUG_NSEL2_SHFT 20 | ||
| 394 | /* bit 23 unused */ | ||
| 395 | #define CA_DEBUG_MSEL3 (0x7ull << 24) | ||
| 396 | #define CA_DEBUG_MSEL3_SHFT 24 | ||
| 397 | /* bit 27 unused */ | ||
| 398 | #define CA_DEBUG_NSEL3 (0x7ull << 28) | ||
| 399 | #define CA_DEBUG_NSEL3_SHFT 28 | ||
| 400 | /* bit 31 unused */ | ||
| 401 | #define CA_DEBUG_MSEL4 (0x7ull << 32) | ||
| 402 | #define CA_DEBUG_MSEL4_SHFT 32 | ||
| 403 | /* bit 35 unused */ | ||
| 404 | #define CA_DEBUG_NSEL4 (0x7ull << 36) | ||
| 405 | #define CA_DEBUG_NSEL4_SHFT 36 | ||
| 406 | /* bit 39 unused */ | ||
| 407 | #define CA_DEBUG_MSEL5 (0x7ull << 40) | ||
| 408 | #define CA_DEBUG_MSEL5_SHFT 40 | ||
| 409 | /* bit 43 unused */ | ||
| 410 | #define CA_DEBUG_NSEL5 (0x7ull << 44) | ||
| 411 | #define CA_DEBUG_NSEL5_SHFT 44 | ||
| 412 | /* bit 47 unused */ | ||
| 413 | #define CA_DEBUG_MSEL6 (0x7ull << 48) | ||
| 414 | #define CA_DEBUG_MSEL6_SHFT 48 | ||
| 415 | /* bit 51 unused */ | ||
| 416 | #define CA_DEBUG_NSEL6 (0x7ull << 52) | ||
| 417 | #define CA_DEBUG_NSEL6_SHFT 52 | ||
| 418 | /* bit 55 unused */ | ||
| 419 | #define CA_DEBUG_MSEL7 (0x7ull << 56) | ||
| 420 | #define CA_DEBUG_MSEL7_SHFT 56 | ||
| 421 | /* bit 59 unused */ | ||
| 422 | #define CA_DEBUG_NSEL7 (0x7ull << 60) | ||
| 423 | #define CA_DEBUG_NSEL7_SHFT 60 | ||
| 424 | /* bit 63 unused */ | ||
| 425 | |||
| 426 | |||
| 427 | /* ==== ca_debug_domain_sel */ | ||
| 428 | #define CA_DEBUG_DOMAIN_L (1ull << 0) | ||
| 429 | #define CA_DEBUG_DOMAIN_H (1ull << 1) | ||
| 430 | /* bits 63:2 unused */ | ||
| 431 | |||
| 432 | /* ==== ca_gart_ptr_table */ | ||
| 433 | #define CA_GART_PTR_VAL (1ull << 0) | ||
| 434 | /* bits 11:1 unused */ | ||
| 435 | #define CA_GART_PTR_ADDR (0xfffffffffffull << 12) | ||
| 436 | #define CA_GART_PTR_ADDR_SHFT 12 | ||
| 437 | /* bits 63:56 unused */ | ||
| 438 | |||
| 439 | /* ==== ca_gart_tlb_addr[0-7] */ | ||
| 440 | #define CA_GART_TLB_ADDR (0xffffffffffffffull << 0) | ||
| 441 | #define CA_GART_TLB_ADDR_SHFT 0 | ||
| 442 | /* bits 62:56 unused */ | ||
| 443 | #define CA_GART_TLB_ENTRY_VAL (1ull << 63) | ||
| 444 | |||
| 445 | /* | ||
| 446 | * PIO address space ranges for TIO:CA | ||
| 447 | */ | ||
| 448 | |||
| 449 | /* CA internal registers */ | ||
| 450 | #define CA_PIO_ADMIN 0x00000000 | ||
| 451 | #define CA_PIO_ADMIN_LEN 0x00010000 | ||
| 452 | |||
| 453 | /* GFX Write Buffer - Diagnostics */ | ||
| 454 | #define CA_PIO_GFX 0x00010000 | ||
| 455 | #define CA_PIO_GFX_LEN 0x00010000 | ||
| 456 | |||
| 457 | /* AGP DMA Write Buffer - Diagnostics */ | ||
| 458 | #define CA_PIO_AGP_DMAWRITE 0x00020000 | ||
| 459 | #define CA_PIO_AGP_DMAWRITE_LEN 0x00010000 | ||
| 460 | |||
| 461 | /* AGP DMA READ Buffer - Diagnostics */ | ||
| 462 | #define CA_PIO_AGP_DMAREAD 0x00030000 | ||
| 463 | #define CA_PIO_AGP_DMAREAD_LEN 0x00010000 | ||
| 464 | |||
| 465 | /* PCI Config Type 0 */ | ||
| 466 | #define CA_PIO_PCI_TYPE0_CONFIG 0x01000000 | ||
| 467 | #define CA_PIO_PCI_TYPE0_CONFIG_LEN 0x01000000 | ||
| 468 | |||
| 469 | /* PCI Config Type 1 */ | ||
| 470 | #define CA_PIO_PCI_TYPE1_CONFIG 0x02000000 | ||
| 471 | #define CA_PIO_PCI_TYPE1_CONFIG_LEN 0x01000000 | ||
| 472 | |||
| 473 | /* PCI I/O Cycles - mapped to PCI Address 0x00000000-0x04ffffff */ | ||
| 474 | #define CA_PIO_PCI_IO 0x03000000 | ||
| 475 | #define CA_PIO_PCI_IO_LEN 0x05000000 | ||
| 476 | |||
| 477 | /* PCI MEM Cycles - mapped to PCI with CA_PIO_ADDR_OFFSET of ca_control1 */ | ||
| 478 | /* use Fast Write if enabled and coretalk packet type is a GFX request */ | ||
| 479 | #define CA_PIO_PCI_MEM_OFFSET 0x08000000 | ||
| 480 | #define CA_PIO_PCI_MEM_OFFSET_LEN 0x08000000 | ||
| 481 | |||
| 482 | /* PCI MEM Cycles - mapped to PCI Address 0x00000000-0xbfffffff */ | ||
| 483 | /* use Fast Write if enabled and coretalk packet type is a GFX request */ | ||
| 484 | #define CA_PIO_PCI_MEM 0x40000000 | ||
| 485 | #define CA_PIO_PCI_MEM_LEN 0xc0000000 | ||
| 486 | |||
| 487 | /* | ||
| 488 | * DMA space | ||
| 489 | * | ||
| 490 | * The CA aperature (ie. bus address range) mapped by the GART is segmented into | ||
| 491 | * two parts. The lower portion of the aperature is used for mapping 32 bit | ||
| 492 | * PCI addresses which are managed by the dma interfaces in this file. The | ||
| 493 | * upper poprtion of the aperature is used for mapping 48 bit AGP addresses. | ||
| 494 | * The AGP portion of the aperature is managed by the agpgart_be.c driver | ||
| 495 | * in drivers/linux/agp. There are ca-specific hooks in that driver to | ||
| 496 | * manipulate the gart, but management of the AGP portion of the aperature | ||
| 497 | * is the responsibility of that driver. | ||
| 498 | * | ||
| 499 | * CA allows three main types of DMA mapping: | ||
| 500 | * | ||
| 501 | * PCI 64-bit Managed by this driver | ||
| 502 | * PCI 32-bit Managed by this driver | ||
| 503 | * AGP 48-bit Managed by hooks in the /dev/agpgart driver | ||
| 504 | * | ||
| 505 | * All of the above can optionally be remapped through the GART. The following | ||
| 506 | * table lists the combinations of addressing types and GART remapping that | ||
| 507 | * is currently supported by the driver (h/w supports all, s/w limits this): | ||
| 508 | * | ||
| 509 | * PCI64 PCI32 AGP48 | ||
| 510 | * GART no yes yes | ||
| 511 | * Direct yes yes no | ||
| 512 | * | ||
| 513 | * GART remapping of PCI64 is not done because there is no need to. The | ||
| 514 | * 64 bit PCI address holds all of the information necessary to target any | ||
| 515 | * memory in the system. | ||
| 516 | * | ||
| 517 | * AGP48 is always mapped through the GART. Management of the AGP48 portion | ||
| 518 | * of the aperature is the responsibility of code in the agpgart_be driver. | ||
| 519 | * | ||
| 520 | * The non-64 bit bus address space will currently be partitioned like this: | ||
| 521 | * | ||
| 522 | * 0xffff_ffff_ffff +-------- | ||
| 523 | * | AGP48 direct | ||
| 524 | * | Space managed by this driver | ||
| 525 | * CA_AGP_DIRECT_BASE +-------- | ||
| 526 | * | AGP GART mapped (gfx aperature) | ||
| 527 | * | Space managed by /dev/agpgart driver | ||
| 528 | * | This range is exposed to the agpgart | ||
| 529 | * | driver as the "graphics aperature" | ||
| 530 | * CA_AGP_MAPPED_BASE +----- | ||
| 531 | * | PCI GART mapped | ||
| 532 | * | Space managed by this driver | ||
| 533 | * CA_PCI32_MAPPED_BASE +---- | ||
| 534 | * | PCI32 direct | ||
| 535 | * | Space managed by this driver | ||
| 536 | * 0xC000_0000 +-------- | ||
| 537 | * (CA_PCI32_DIRECT_BASE) | ||
| 538 | * | ||
| 539 | * The bus address range CA_PCI32_MAPPED_BASE through CA_AGP_DIRECT_BASE | ||
| 540 | * is what we call the CA aperature. Addresses falling in this range will | ||
| 541 | * be remapped using the GART. | ||
| 542 | * | ||
| 543 | * The bus address range CA_AGP_MAPPED_BASE through CA_AGP_DIRECT_BASE | ||
| 544 | * is what we call the graphics aperature. This is a subset of the CA | ||
| 545 | * aperature and is under the control of the agpgart_be driver. | ||
| 546 | * | ||
| 547 | * CA_PCI32_MAPPED_BASE, CA_AGP_MAPPED_BASE, and CA_AGP_DIRECT_BASE are | ||
| 548 | * somewhat arbitrary values. The known constraints on choosing these is: | ||
| 549 | * | ||
| 550 | * 1) CA_AGP_DIRECT_BASE-CA_PCI32_MAPPED_BASE+1 (the CA aperature size) | ||
| 551 | * must be one of the values supported by the ca_gart_aperature register. | ||
| 552 | * Currently valid values are: 4MB through 4096MB in powers of 2 increments | ||
| 553 | * | ||
| 554 | * 2) CA_AGP_DIRECT_BASE-CA_AGP_MAPPED_BASE+1 (the gfx aperature size) | ||
| 555 | * must be in MB units since that's what the agpgart driver assumes. | ||
| 556 | */ | ||
| 557 | |||
| 558 | /* | ||
| 559 | * Define Bus DMA ranges. These are configurable (see constraints above) | ||
| 560 | * and will probably need tuning based on experience. | ||
| 561 | */ | ||
| 562 | |||
| 563 | |||
| 564 | /* | ||
| 565 | * 11/24/03 | ||
| 566 | * CA has an addressing glitch w.r.t. PCI direct 32 bit DMA that makes it | ||
| 567 | * generally unusable. The problem is that for PCI direct 32 | ||
| 568 | * DMA's, all 32 bits of the bus address are used to form the lower 32 bits | ||
| 569 | * of the coretalk address, and coretalk bits 38:32 come from a register. | ||
| 570 | * Since only PCI bus addresses 0xC0000000-0xFFFFFFFF (1GB) are available | ||
| 571 | * for DMA (the rest is allocated to PIO), host node addresses need to be | ||
| 572 | * such that their lower 32 bits fall in the 0xC0000000-0xffffffff range | ||
| 573 | * as well. So there can be no PCI32 direct DMA below 3GB!! For this | ||
| 574 | * reason we set the CA_PCI32_DIRECT_SIZE to 0 which essentially makes | ||
| 575 | * tioca_dma_direct32() a noop but preserves the code flow should this issue | ||
| 576 | * be fixed in a respin. | ||
| 577 | * | ||
| 578 | * For now, all PCI32 DMA's must be mapped through the GART. | ||
| 579 | */ | ||
| 580 | |||
| 581 | #define CA_PCI32_DIRECT_BASE 0xC0000000UL /* BASE not configurable */ | ||
| 582 | #define CA_PCI32_DIRECT_SIZE 0x00000000UL /* 0 MB */ | ||
| 583 | |||
| 584 | #define CA_PCI32_MAPPED_BASE 0xC0000000UL | ||
| 585 | #define CA_PCI32_MAPPED_SIZE 0x40000000UL /* 2GB */ | ||
| 586 | |||
| 587 | #define CA_AGP_MAPPED_BASE 0x80000000UL | ||
| 588 | #define CA_AGP_MAPPED_SIZE 0x40000000UL /* 2GB */ | ||
| 589 | |||
| 590 | #define CA_AGP_DIRECT_BASE 0x40000000UL /* 2GB */ | ||
| 591 | #define CA_AGP_DIRECT_SIZE 0x40000000UL | ||
| 592 | |||
| 593 | #define CA_APERATURE_BASE (CA_AGP_MAPPED_BASE) | ||
| 594 | #define CA_APERATURE_SIZE (CA_AGP_MAPPED_SIZE+CA_PCI32_MAPPED_SIZE) | ||
| 595 | |||
| 596 | #endif /* _ASM_IA64_SN_TIO_TIOCA_H */ | ||