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-rw-r--r--include/asm-ia64/sn/pic.h204
1 files changed, 102 insertions, 102 deletions
diff --git a/include/asm-ia64/sn/pic.h b/include/asm-ia64/sn/pic.h
index 0de82e6b0893..5f9da5fd6e56 100644
--- a/include/asm-ia64/sn/pic.h
+++ b/include/asm-ia64/sn/pic.h
@@ -74,120 +74,120 @@ struct pic {
74 /* 0x000000-0x00FFFF -- Local Registers */ 74 /* 0x000000-0x00FFFF -- Local Registers */
75 75
76 /* 0x000000-0x000057 -- Standard Widget Configuration */ 76 /* 0x000000-0x000057 -- Standard Widget Configuration */
77 uint64_t p_wid_id; /* 0x000000 */ 77 u64 p_wid_id; /* 0x000000 */
78 uint64_t p_wid_stat; /* 0x000008 */ 78 u64 p_wid_stat; /* 0x000008 */
79 uint64_t p_wid_err_upper; /* 0x000010 */ 79 u64 p_wid_err_upper; /* 0x000010 */
80 uint64_t p_wid_err_lower; /* 0x000018 */ 80 u64 p_wid_err_lower; /* 0x000018 */
81 #define p_wid_err p_wid_err_lower 81 #define p_wid_err p_wid_err_lower
82 uint64_t p_wid_control; /* 0x000020 */ 82 u64 p_wid_control; /* 0x000020 */
83 uint64_t p_wid_req_timeout; /* 0x000028 */ 83 u64 p_wid_req_timeout; /* 0x000028 */
84 uint64_t p_wid_int_upper; /* 0x000030 */ 84 u64 p_wid_int_upper; /* 0x000030 */
85 uint64_t p_wid_int_lower; /* 0x000038 */ 85 u64 p_wid_int_lower; /* 0x000038 */
86 #define p_wid_int p_wid_int_lower 86 #define p_wid_int p_wid_int_lower
87 uint64_t p_wid_err_cmdword; /* 0x000040 */ 87 u64 p_wid_err_cmdword; /* 0x000040 */
88 uint64_t p_wid_llp; /* 0x000048 */ 88 u64 p_wid_llp; /* 0x000048 */
89 uint64_t p_wid_tflush; /* 0x000050 */ 89 u64 p_wid_tflush; /* 0x000050 */
90 90
91 /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */ 91 /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
92 uint64_t p_wid_aux_err; /* 0x000058 */ 92 u64 p_wid_aux_err; /* 0x000058 */
93 uint64_t p_wid_resp_upper; /* 0x000060 */ 93 u64 p_wid_resp_upper; /* 0x000060 */
94 uint64_t p_wid_resp_lower; /* 0x000068 */ 94 u64 p_wid_resp_lower; /* 0x000068 */
95 #define p_wid_resp p_wid_resp_lower 95 #define p_wid_resp p_wid_resp_lower
96 uint64_t p_wid_tst_pin_ctrl; /* 0x000070 */ 96 u64 p_wid_tst_pin_ctrl; /* 0x000070 */
97 uint64_t p_wid_addr_lkerr; /* 0x000078 */ 97 u64 p_wid_addr_lkerr; /* 0x000078 */
98 98
99 /* 0x000080-0x00008F -- PMU & MAP */ 99 /* 0x000080-0x00008F -- PMU & MAP */
100 uint64_t p_dir_map; /* 0x000080 */ 100 u64 p_dir_map; /* 0x000080 */
101 uint64_t _pad_000088; /* 0x000088 */ 101 u64 _pad_000088; /* 0x000088 */
102 102
103 /* 0x000090-0x00009F -- SSRAM */ 103 /* 0x000090-0x00009F -- SSRAM */
104 uint64_t p_map_fault; /* 0x000090 */ 104 u64 p_map_fault; /* 0x000090 */
105 uint64_t _pad_000098; /* 0x000098 */ 105 u64 _pad_000098; /* 0x000098 */
106 106
107 /* 0x0000A0-0x0000AF -- Arbitration */ 107 /* 0x0000A0-0x0000AF -- Arbitration */
108 uint64_t p_arb; /* 0x0000A0 */ 108 u64 p_arb; /* 0x0000A0 */
109 uint64_t _pad_0000A8; /* 0x0000A8 */ 109 u64 _pad_0000A8; /* 0x0000A8 */
110 110
111 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */ 111 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
112 uint64_t p_ate_parity_err; /* 0x0000B0 */ 112 u64 p_ate_parity_err; /* 0x0000B0 */
113 uint64_t _pad_0000B8; /* 0x0000B8 */ 113 u64 _pad_0000B8; /* 0x0000B8 */
114 114
115 /* 0x0000C0-0x0000FF -- PCI/GIO */ 115 /* 0x0000C0-0x0000FF -- PCI/GIO */
116 uint64_t p_bus_timeout; /* 0x0000C0 */ 116 u64 p_bus_timeout; /* 0x0000C0 */
117 uint64_t p_pci_cfg; /* 0x0000C8 */ 117 u64 p_pci_cfg; /* 0x0000C8 */
118 uint64_t p_pci_err_upper; /* 0x0000D0 */ 118 u64 p_pci_err_upper; /* 0x0000D0 */
119 uint64_t p_pci_err_lower; /* 0x0000D8 */ 119 u64 p_pci_err_lower; /* 0x0000D8 */
120 #define p_pci_err p_pci_err_lower 120 #define p_pci_err p_pci_err_lower
121 uint64_t _pad_0000E0[4]; /* 0x0000{E0..F8} */ 121 u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
122 122
123 /* 0x000100-0x0001FF -- Interrupt */ 123 /* 0x000100-0x0001FF -- Interrupt */
124 uint64_t p_int_status; /* 0x000100 */ 124 u64 p_int_status; /* 0x000100 */
125 uint64_t p_int_enable; /* 0x000108 */ 125 u64 p_int_enable; /* 0x000108 */
126 uint64_t p_int_rst_stat; /* 0x000110 */ 126 u64 p_int_rst_stat; /* 0x000110 */
127 uint64_t p_int_mode; /* 0x000118 */ 127 u64 p_int_mode; /* 0x000118 */
128 uint64_t p_int_device; /* 0x000120 */ 128 u64 p_int_device; /* 0x000120 */
129 uint64_t p_int_host_err; /* 0x000128 */ 129 u64 p_int_host_err; /* 0x000128 */
130 uint64_t p_int_addr[8]; /* 0x0001{30,,,68} */ 130 u64 p_int_addr[8]; /* 0x0001{30,,,68} */
131 uint64_t p_err_int_view; /* 0x000170 */ 131 u64 p_err_int_view; /* 0x000170 */
132 uint64_t p_mult_int; /* 0x000178 */ 132 u64 p_mult_int; /* 0x000178 */
133 uint64_t p_force_always[8]; /* 0x0001{80,,,B8} */ 133 u64 p_force_always[8]; /* 0x0001{80,,,B8} */
134 uint64_t p_force_pin[8]; /* 0x0001{C0,,,F8} */ 134 u64 p_force_pin[8]; /* 0x0001{C0,,,F8} */
135 135
136 /* 0x000200-0x000298 -- Device */ 136 /* 0x000200-0x000298 -- Device */
137 uint64_t p_device[4]; /* 0x0002{00,,,18} */ 137 u64 p_device[4]; /* 0x0002{00,,,18} */
138 uint64_t _pad_000220[4]; /* 0x0002{20,,,38} */ 138 u64 _pad_000220[4]; /* 0x0002{20,,,38} */
139 uint64_t p_wr_req_buf[4]; /* 0x0002{40,,,58} */ 139 u64 p_wr_req_buf[4]; /* 0x0002{40,,,58} */
140 uint64_t _pad_000260[4]; /* 0x0002{60,,,78} */ 140 u64 _pad_000260[4]; /* 0x0002{60,,,78} */
141 uint64_t p_rrb_map[2]; /* 0x0002{80,,,88} */ 141 u64 p_rrb_map[2]; /* 0x0002{80,,,88} */
142 #define p_even_resp p_rrb_map[0] /* 0x000280 */ 142 #define p_even_resp p_rrb_map[0] /* 0x000280 */
143 #define p_odd_resp p_rrb_map[1] /* 0x000288 */ 143 #define p_odd_resp p_rrb_map[1] /* 0x000288 */
144 uint64_t p_resp_status; /* 0x000290 */ 144 u64 p_resp_status; /* 0x000290 */
145 uint64_t p_resp_clear; /* 0x000298 */ 145 u64 p_resp_clear; /* 0x000298 */
146 146
147 uint64_t _pad_0002A0[12]; /* 0x0002{A0..F8} */ 147 u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
148 148
149 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */ 149 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
150 struct { 150 struct {
151 uint64_t upper; /* 0x0003{00,,,F0} */ 151 u64 upper; /* 0x0003{00,,,F0} */
152 uint64_t lower; /* 0x0003{08,,,F8} */ 152 u64 lower; /* 0x0003{08,,,F8} */
153 } p_buf_addr_match[16]; 153 } p_buf_addr_match[16];
154 154
155 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */ 155 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
156 struct { 156 struct {
157 uint64_t flush_w_touch; /* 0x000{400,,,5C0} */ 157 u64 flush_w_touch; /* 0x000{400,,,5C0} */
158 uint64_t flush_wo_touch; /* 0x000{408,,,5C8} */ 158 u64 flush_wo_touch; /* 0x000{408,,,5C8} */
159 uint64_t inflight; /* 0x000{410,,,5D0} */ 159 u64 inflight; /* 0x000{410,,,5D0} */
160 uint64_t prefetch; /* 0x000{418,,,5D8} */ 160 u64 prefetch; /* 0x000{418,,,5D8} */
161 uint64_t total_pci_retry; /* 0x000{420,,,5E0} */ 161 u64 total_pci_retry; /* 0x000{420,,,5E0} */
162 uint64_t max_pci_retry; /* 0x000{428,,,5E8} */ 162 u64 max_pci_retry; /* 0x000{428,,,5E8} */
163 uint64_t max_latency; /* 0x000{430,,,5F0} */ 163 u64 max_latency; /* 0x000{430,,,5F0} */
164 uint64_t clear_all; /* 0x000{438,,,5F8} */ 164 u64 clear_all; /* 0x000{438,,,5F8} */
165 } p_buf_count[8]; 165 } p_buf_count[8];
166 166
167 167
168 /* 0x000600-0x0009FF -- PCI/X registers */ 168 /* 0x000600-0x0009FF -- PCI/X registers */
169 uint64_t p_pcix_bus_err_addr; /* 0x000600 */ 169 u64 p_pcix_bus_err_addr; /* 0x000600 */
170 uint64_t p_pcix_bus_err_attr; /* 0x000608 */ 170 u64 p_pcix_bus_err_attr; /* 0x000608 */
171 uint64_t p_pcix_bus_err_data; /* 0x000610 */ 171 u64 p_pcix_bus_err_data; /* 0x000610 */
172 uint64_t p_pcix_pio_split_addr; /* 0x000618 */ 172 u64 p_pcix_pio_split_addr; /* 0x000618 */
173 uint64_t p_pcix_pio_split_attr; /* 0x000620 */ 173 u64 p_pcix_pio_split_attr; /* 0x000620 */
174 uint64_t p_pcix_dma_req_err_attr; /* 0x000628 */ 174 u64 p_pcix_dma_req_err_attr; /* 0x000628 */
175 uint64_t p_pcix_dma_req_err_addr; /* 0x000630 */ 175 u64 p_pcix_dma_req_err_addr; /* 0x000630 */
176 uint64_t p_pcix_timeout; /* 0x000638 */ 176 u64 p_pcix_timeout; /* 0x000638 */
177 177
178 uint64_t _pad_000640[120]; /* 0x000{640,,,9F8} */ 178 u64 _pad_000640[120]; /* 0x000{640,,,9F8} */
179 179
180 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */ 180 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
181 struct { 181 struct {
182 uint64_t p_buf_addr; /* 0x000{A00,,,AF0} */ 182 u64 p_buf_addr; /* 0x000{A00,,,AF0} */
183 uint64_t p_buf_attr; /* 0X000{A08,,,AF8} */ 183 u64 p_buf_attr; /* 0X000{A08,,,AF8} */
184 } p_pcix_read_buf_64[16]; 184 } p_pcix_read_buf_64[16];
185 185
186 struct { 186 struct {
187 uint64_t p_buf_addr; /* 0x000{B00,,,BE0} */ 187 u64 p_buf_addr; /* 0x000{B00,,,BE0} */
188 uint64_t p_buf_attr; /* 0x000{B08,,,BE8} */ 188 u64 p_buf_attr; /* 0x000{B08,,,BE8} */
189 uint64_t p_buf_valid; /* 0x000{B10,,,BF0} */ 189 u64 p_buf_valid; /* 0x000{B10,,,BF0} */
190 uint64_t __pad1; /* 0x000{B18,,,BF8} */ 190 u64 __pad1; /* 0x000{B18,,,BF8} */
191 } p_pcix_write_buf_64[8]; 191 } p_pcix_write_buf_64[8];
192 192
193 /* End of Local Registers -- Start of Address Map space */ 193 /* End of Local Registers -- Start of Address Map space */
@@ -195,45 +195,45 @@ struct pic {
195 char _pad_000c00[0x010000 - 0x000c00]; 195 char _pad_000c00[0x010000 - 0x000c00];
196 196
197 /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */ 197 /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
198 uint64_t p_int_ate_ram[1024]; /* 0x010000-0x011fff */ 198 u64 p_int_ate_ram[1024]; /* 0x010000-0x011fff */
199 199
200 /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */ 200 /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
201 uint64_t p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */ 201 u64 p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */
202 202
203 char _pad_014000[0x18000 - 0x014000]; 203 char _pad_014000[0x18000 - 0x014000];
204 204
205 /* 0x18000-0x197F8 -- PIC Write Request Ram */ 205 /* 0x18000-0x197F8 -- PIC Write Request Ram */
206 uint64_t p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */ 206 u64 p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
207 uint64_t p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */ 207 u64 p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
208 uint64_t p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */ 208 u64 p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
209 209
210 char _pad_019800[0x20000 - 0x019800]; 210 char _pad_019800[0x20000 - 0x019800];
211 211
212 /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */ 212 /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
213 union { 213 union {
214 uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ 214 u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
215 uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ 215 u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
216 uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ 216 u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
217 uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ 217 u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
218 union { 218 union {
219 uint8_t c[0x100 / 1]; 219 u8 c[0x100 / 1];
220 uint16_t s[0x100 / 2]; 220 u16 s[0x100 / 2];
221 uint32_t l[0x100 / 4]; 221 u32 l[0x100 / 4];
222 uint64_t d[0x100 / 8]; 222 u64 d[0x100 / 8];
223 } f[8]; 223 } f[8];
224 } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */ 224 } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */
225 225
226 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */ 226 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
227 union { 227 union {
228 uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */ 228 u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
229 uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */ 229 u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
230 uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */ 230 u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
231 uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */ 231 u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
232 union { 232 union {
233 uint8_t c[0x100 / 1]; 233 u8 c[0x100 / 1];
234 uint16_t s[0x100 / 2]; 234 u16 s[0x100 / 2];
235 uint32_t l[0x100 / 4]; 235 u32 l[0x100 / 4];
236 uint64_t d[0x100 / 8]; 236 u64 d[0x100 / 8];
237 } f[8]; 237 } f[8];
238 } p_type1_cfg; /* 0x028000-0x029000 */ 238 } p_type1_cfg; /* 0x028000-0x029000 */
239 239
@@ -241,20 +241,20 @@ struct pic {
241 241
242 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */ 242 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
243 union { 243 union {
244 uint8_t c[8 / 1]; 244 u8 c[8 / 1];
245 uint16_t s[8 / 2]; 245 u16 s[8 / 2];
246 uint32_t l[8 / 4]; 246 u32 l[8 / 4];
247 uint64_t d[8 / 8]; 247 u64 d[8 / 8];
248 } p_pci_iack; /* 0x030000-0x030007 */ 248 } p_pci_iack; /* 0x030000-0x030007 */
249 249
250 char _pad_030007[0x040000-0x030008]; 250 char _pad_030007[0x040000-0x030008];
251 251
252 /* 0x040000-0x030007 -- PCIX Special Cycle */ 252 /* 0x040000-0x030007 -- PCIX Special Cycle */
253 union { 253 union {
254 uint8_t c[8 / 1]; 254 u8 c[8 / 1];
255 uint16_t s[8 / 2]; 255 u16 s[8 / 2];
256 uint32_t l[8 / 4]; 256 u32 l[8 / 4];
257 uint64_t d[8 / 8]; 257 u64 d[8 / 8];
258 } p_pcix_cycle; /* 0x040000-0x040007 */ 258 } p_pcix_cycle; /* 0x040000-0x040007 */
259}; 259};
260 260
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 11:37:50 -0500