aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-ia64/sn/pcibr_provider.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-ia64/sn/pcibr_provider.h')
-rw-r--r--include/asm-ia64/sn/pcibr_provider.h48
1 files changed, 24 insertions, 24 deletions
diff --git a/include/asm-ia64/sn/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h
index 2b42d9ece26b..9334078b089a 100644
--- a/include/asm-ia64/sn/pcibr_provider.h
+++ b/include/asm-ia64/sn/pcibr_provider.h
@@ -44,9 +44,9 @@
44#define PCI32_MAPPED_BASE 0x40000000 44#define PCI32_MAPPED_BASE 0x40000000
45#define PCI32_DIRECT_BASE 0x80000000 45#define PCI32_DIRECT_BASE 0x80000000
46 46
47#define IS_PCI32_MAPPED(x) ((uint64_t)(x) < PCI32_DIRECT_BASE && \ 47#define IS_PCI32_MAPPED(x) ((u64)(x) < PCI32_DIRECT_BASE && \
48 (uint64_t)(x) >= PCI32_MAPPED_BASE) 48 (u64)(x) >= PCI32_MAPPED_BASE)
49#define IS_PCI32_DIRECT(x) ((uint64_t)(x) >= PCI32_MAPPED_BASE) 49#define IS_PCI32_DIRECT(x) ((u64)(x) >= PCI32_MAPPED_BASE)
50 50
51 51
52/* 52/*
@@ -63,7 +63,7 @@
63 (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1)) 63 (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
64 64
65#define MINIMAL_ATE_FLAG(addr, size) \ 65#define MINIMAL_ATE_FLAG(addr, size) \
66 (MINIMAL_ATES_REQUIRED((uint64_t)addr, size) ? 1 : 0) 66 (MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0)
67 67
68/* bit 29 of the pci address is the SWAP bit */ 68/* bit 29 of the pci address is the SWAP bit */
69#define ATE_SWAPSHIFT 29 69#define ATE_SWAPSHIFT 29
@@ -90,27 +90,27 @@
90 * PMU resources. 90 * PMU resources.
91 */ 91 */
92struct ate_resource{ 92struct ate_resource{
93 uint64_t *ate; 93 u64 *ate;
94 uint64_t num_ate; 94 u64 num_ate;
95 uint64_t lowest_free_index; 95 u64 lowest_free_index;
96}; 96};
97 97
98struct pcibus_info { 98struct pcibus_info {
99 struct pcibus_bussoft pbi_buscommon; /* common header */ 99 struct pcibus_bussoft pbi_buscommon; /* common header */
100 uint32_t pbi_moduleid; 100 u32 pbi_moduleid;
101 short pbi_bridge_type; 101 short pbi_bridge_type;
102 short pbi_bridge_mode; 102 short pbi_bridge_mode;
103 103
104 struct ate_resource pbi_int_ate_resource; 104 struct ate_resource pbi_int_ate_resource;
105 uint64_t pbi_int_ate_size; 105 u64 pbi_int_ate_size;
106 106
107 uint64_t pbi_dir_xbase; 107 u64 pbi_dir_xbase;
108 char pbi_hub_xid; 108 char pbi_hub_xid;
109 109
110 uint64_t pbi_devreg[8]; 110 u64 pbi_devreg[8];
111 111
112 uint32_t pbi_valid_devices; 112 u32 pbi_valid_devices;
113 uint32_t pbi_enabled_devices; 113 u32 pbi_enabled_devices;
114 114
115 spinlock_t pbi_lock; 115 spinlock_t pbi_lock;
116}; 116};
@@ -136,22 +136,22 @@ extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
136/* 136/*
137 * prototypes for the bridge asic register access routines in pcibr_reg.c 137 * prototypes for the bridge asic register access routines in pcibr_reg.c
138 */ 138 */
139extern void pcireg_control_bit_clr(struct pcibus_info *, uint64_t); 139extern void pcireg_control_bit_clr(struct pcibus_info *, u64);
140extern void pcireg_control_bit_set(struct pcibus_info *, uint64_t); 140extern void pcireg_control_bit_set(struct pcibus_info *, u64);
141extern uint64_t pcireg_tflush_get(struct pcibus_info *); 141extern u64 pcireg_tflush_get(struct pcibus_info *);
142extern uint64_t pcireg_intr_status_get(struct pcibus_info *); 142extern u64 pcireg_intr_status_get(struct pcibus_info *);
143extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, uint64_t); 143extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, u64);
144extern void pcireg_intr_enable_bit_set(struct pcibus_info *, uint64_t); 144extern void pcireg_intr_enable_bit_set(struct pcibus_info *, u64);
145extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, uint64_t); 145extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64);
146extern void pcireg_force_intr_set(struct pcibus_info *, int); 146extern void pcireg_force_intr_set(struct pcibus_info *, int);
147extern uint64_t pcireg_wrb_flush_get(struct pcibus_info *, int); 147extern u64 pcireg_wrb_flush_get(struct pcibus_info *, int);
148extern void pcireg_int_ate_set(struct pcibus_info *, int, uint64_t); 148extern void pcireg_int_ate_set(struct pcibus_info *, int, u64);
149extern uint64_t * pcireg_int_ate_addr(struct pcibus_info *, int); 149extern u64 * pcireg_int_ate_addr(struct pcibus_info *, int);
150extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info); 150extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
151extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info); 151extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
152extern int pcibr_ate_alloc(struct pcibus_info *, int); 152extern int pcibr_ate_alloc(struct pcibus_info *, int);
153extern void pcibr_ate_free(struct pcibus_info *, int); 153extern void pcibr_ate_free(struct pcibus_info *, int);
154extern void ate_write(struct pcibus_info *, int, int, uint64_t); 154extern void ate_write(struct pcibus_info *, int, int, u64);
155extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device, 155extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
156 void *resp); 156 void *resp);
157extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device, 157extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,