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-rw-r--r--include/asm-ia64/sn/addrs.h74
1 files changed, 56 insertions, 18 deletions
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
index b6e85e454456..8881882ccafb 100644
--- a/include/asm-ia64/sn/addrs.h
+++ b/include/asm-ia64/sn/addrs.h
@@ -126,6 +126,7 @@
126#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a)) 126#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
127#define GLOBAL_CAC_ADDR(n,a) (CAC_BASE | REMOTE_ADDR(n,a)) 127#define GLOBAL_CAC_ADDR(n,a) (CAC_BASE | REMOTE_ADDR(n,a))
128#define CHANGE_NASID(n,x) ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n))) 128#define CHANGE_NASID(n,x) ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
129#define IS_TIO_NASID(n) ((n) & 1)
129 130
130 131
131/* non-II mmr's start at top of big window space (4G) */ 132/* non-II mmr's start at top of big window space (4G) */
@@ -155,10 +156,28 @@
155 * the chiplet id is zero. If we implement TIO-TIO dma, we might need 156 * the chiplet id is zero. If we implement TIO-TIO dma, we might need
156 * to insert a chiplet id into this macro. However, it is our belief 157 * to insert a chiplet id into this macro. However, it is our belief
157 * right now that this chiplet id will be ICE, which is also zero. 158 * right now that this chiplet id will be ICE, which is also zero.
158 * Nasid starts on bit 40.
159 */ 159 */
160#define PHYS_TO_TIODMA(x) ( (((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x)) 160#define SH1_TIO_PHYS_TO_DMA(x) \
161#define PHYS_TO_DMA(x) ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x)) 161 ((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
162
163#define SH2_NETWORK_BANK_OFFSET(x) \
164 ((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
165
166#define SH2_NETWORK_BANK_SELECT(x) \
167 ((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4))) \
168 >> (sn_hub_info->nasid_shift - 4)) << 36)
169
170#define SH2_NETWORK_ADDRESS(x) \
171 (SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
172
173#define SH2_TIO_PHYS_TO_DMA(x) \
174 (((u64)(NASID_GET(x)) << 40) | SH2_NETWORK_ADDRESS(x))
175
176#define PHYS_TO_TIODMA(x) \
177 (is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
178
179#define PHYS_TO_DMA(x) \
180 ((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
162 181
163 182
164/* 183/*
@@ -187,6 +206,7 @@
187#define RAW_NODE_SWIN_BASE(n, w) (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS)) 206#define RAW_NODE_SWIN_BASE(n, w) (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
188#define BWIN_WIDGET_MASK 0x7 207#define BWIN_WIDGET_MASK 0x7
189#define BWIN_WINDOWNUM(x) (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) 208#define BWIN_WINDOWNUM(x) (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
209#define SH1_IS_BIG_WINDOW_ADDR(x) ((x) & BWIN_TOP)
190 210
191#define TIO_BWIN_WINDOW_SELECT_MASK 0x7 211#define TIO_BWIN_WINDOW_SELECT_MASK 0x7
192#define TIO_BWIN_WINDOWNUM(x) (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK) 212#define TIO_BWIN_WINDOWNUM(x) (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
@@ -217,10 +237,6 @@
217#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK) 237#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
218 238
219 239
220#define TIO_IOSPACE_ADDR(n,x) \
221 /* Move in the Chiplet ID for TIO Local Block MMR */ \
222 (REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2))
223
224/* 240/*
225 * The following macros produce the correct base virtual address for 241 * The following macros produce the correct base virtual address for
226 * the hub registers. The REMOTE_HUB_* macro produce 242 * the hub registers. The REMOTE_HUB_* macro produce
@@ -235,18 +251,40 @@
235 * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S(). 251 * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
236 * They're always safe. 252 * They're always safe.
237 */ 253 */
254/* Shub1 TIO & MMR addressing macros */
255#define SH1_TIO_IOSPACE_ADDR(n,x) \
256 GLOBAL_MMR_ADDR(n,x)
257
258#define SH1_REMOTE_BWIN_MMR(n,x) \
259 GLOBAL_MMR_ADDR(n,x)
260
261#define SH1_REMOTE_SWIN_MMR(n,x) \
262 (NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
263
264#define SH1_REMOTE_MMR(n,x) \
265 (SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) : \
266 SH1_REMOTE_SWIN_MMR(n,x))
267
268/* Shub1 TIO & MMR addressing macros */
269#define SH2_TIO_IOSPACE_ADDR(n,x) \
270 ((UNCACHED | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
271
272#define SH2_REMOTE_MMR(n,x) \
273 GLOBAL_MMR_ADDR(n,x)
274
275
276/* TIO & MMR addressing macros that work on both shub1 & shub2 */
277#define TIO_IOSPACE_ADDR(n,x) \
278 ((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) : \
279 SH2_TIO_IOSPACE_ADDR(n,x)))
280
281#define SH_REMOTE_MMR(n,x) \
282 (is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
283
238#define REMOTE_HUB_ADDR(n,x) \ 284#define REMOTE_HUB_ADDR(n,x) \
239 ((n & 1) ? \ 285 (IS_TIO_NASID(n) ? ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) : \
240 /* TIO: */ \ 286 ((volatile u64*)SH_REMOTE_MMR(n,x)))
241 (is_shub2() ? \ 287
242 /* TIO on Shub2 */ \
243 (volatile u64 *)(TIO_IOSPACE_ADDR(n,x)) \
244 : /* TIO on shub1 */ \
245 (volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
246 \
247 : /* SHUB1 and SHUB2 MMRs: */ \
248 (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
249 : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x)))))
250 288
251#define HUB_L(x) (*((volatile typeof(*x) *)x)) 289#define HUB_L(x) (*((volatile typeof(*x) *)x))
252#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d)) 290#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d))