1 files changed, 68 insertions, 0 deletions

diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index 5dd477ffb88e..2303a10ee595 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -67,6 +67,7 @@
 #define PAL_REGISTER_INFO       39      /* return AR and CR register information*/
 #define PAL_SHUTDOWN            40      /* enter processor shutdown state */
 #define PAL_PREFETCH_VISIBILITY 41      /* Make Processor Prefetches Visible */
+#define PAL_LOGICAL_TO_PHYSICAL 42      /* returns information on logical to physical processor mapping */
 
 #define PAL_COPY_PAL            256     /* relocate PAL procedures and PAL PMI */
 #define PAL_HALT_INFO           257     /* return the low power capabilities of processor */
@@ -1559,6 +1560,73 @@ ia64_pal_prefetch_visibility (s64 trans_type)
         return iprv.status;
 }
 
+/* data structure for getting information on logical to physical mappings */
+typedef union pal_log_overview_u {
+        struct {
+                u64     num_log         :16,    /* Total number of logical
+                                                 * processors on this die
+                                                 */
+                        tpc             :8,     /* Threads per core */
+                        reserved3       :8,     /* Reserved */
+                        cpp             :8,     /* Cores per processor */
+                        reserved2       :8,     /* Reserved */
+                        ppid            :8,     /* Physical processor ID */
+                        reserved1       :8;     /* Reserved */
+        } overview_bits;
+        u64 overview_data;
+} pal_log_overview_t;
+
+typedef union pal_proc_n_log_info1_u{
+        struct {
+                u64     tid             :16,    /* Thread id */
+                        reserved2       :16,    /* Reserved */
+                        cid             :16,    /* Core id */
+                        reserved1       :16;    /* Reserved */
+        } ppli1_bits;
+        u64     ppli1_data;
+} pal_proc_n_log_info1_t;
+
+typedef union pal_proc_n_log_info2_u {
+        struct {
+                u64     la              :16,    /* Logical address */
+                        reserved        :48;    /* Reserved */
+        } ppli2_bits;
+        u64     ppli2_data;
+} pal_proc_n_log_info2_t;
+
+typedef struct pal_logical_to_physical_s
+{
+        pal_log_overview_t overview;
+        pal_proc_n_log_info1_t ppli1;
+        pal_proc_n_log_info2_t ppli2;
+} pal_logical_to_physical_t;
+
+#define overview_num_log        overview.overview_bits.num_log
+#define overview_tpc            overview.overview_bits.tpc
+#define overview_cpp            overview.overview_bits.cpp
+#define overview_ppid           overview.overview_bits.ppid
+#define log1_tid                ppli1.ppli1_bits.tid
+#define log1_cid                ppli1.ppli1_bits.cid
+#define log2_la                 ppli2.ppli2_bits.la
+
+/* Get information on logical to physical processor mappings. */
+static inline s64
+ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
+{
+        struct ia64_pal_retval iprv;
+
+        PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
+
+        if (iprv.status == PAL_STATUS_SUCCESS)
+        {
+                if (proc_number == 0)
+                        mapping->overview.overview_data = iprv.v0;
+                mapping->ppli1.ppli1_data = iprv.v1;
+                mapping->ppli2.ppli2_data = iprv.v2;
+        }
+
+        return iprv.status;
+}
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_IA64_PAL_H */