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Diffstat (limited to 'include/asm-ia64/mmu_context.h')
-rw-r--r-- | include/asm-ia64/mmu_context.h | 170 |
1 files changed, 170 insertions, 0 deletions
diff --git a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h new file mode 100644 index 000000000000..0096e7e05012 --- /dev/null +++ b/include/asm-ia64/mmu_context.h | |||
@@ -0,0 +1,170 @@ | |||
1 | #ifndef _ASM_IA64_MMU_CONTEXT_H | ||
2 | #define _ASM_IA64_MMU_CONTEXT_H | ||
3 | |||
4 | /* | ||
5 | * Copyright (C) 1998-2002 Hewlett-Packard Co | ||
6 | * David Mosberger-Tang <davidm@hpl.hp.com> | ||
7 | */ | ||
8 | |||
9 | /* | ||
10 | * Routines to manage the allocation of task context numbers. Task context numbers are | ||
11 | * used to reduce or eliminate the need to perform TLB flushes due to context switches. | ||
12 | * Context numbers are implemented using ia-64 region ids. Since the IA-64 TLB does not | ||
13 | * consider the region number when performing a TLB lookup, we need to assign a unique | ||
14 | * region id to each region in a process. We use the least significant three bits in a | ||
15 | * region id for this purpose. | ||
16 | */ | ||
17 | |||
18 | #define IA64_REGION_ID_KERNEL 0 /* the kernel's region id (tlb.c depends on this being 0) */ | ||
19 | |||
20 | #define ia64_rid(ctx,addr) (((ctx) << 3) | (addr >> 61)) | ||
21 | |||
22 | # ifndef __ASSEMBLY__ | ||
23 | |||
24 | #include <linux/compiler.h> | ||
25 | #include <linux/percpu.h> | ||
26 | #include <linux/sched.h> | ||
27 | #include <linux/spinlock.h> | ||
28 | |||
29 | #include <asm/processor.h> | ||
30 | |||
31 | struct ia64_ctx { | ||
32 | spinlock_t lock; | ||
33 | unsigned int next; /* next context number to use */ | ||
34 | unsigned int limit; /* next >= limit => must call wrap_mmu_context() */ | ||
35 | unsigned int max_ctx; /* max. context value supported by all CPUs */ | ||
36 | }; | ||
37 | |||
38 | extern struct ia64_ctx ia64_ctx; | ||
39 | DECLARE_PER_CPU(u8, ia64_need_tlb_flush); | ||
40 | |||
41 | extern void wrap_mmu_context (struct mm_struct *mm); | ||
42 | |||
43 | static inline void | ||
44 | enter_lazy_tlb (struct mm_struct *mm, struct task_struct *tsk) | ||
45 | { | ||
46 | } | ||
47 | |||
48 | /* | ||
49 | * When the context counter wraps around all TLBs need to be flushed because an old | ||
50 | * context number might have been reused. This is signalled by the ia64_need_tlb_flush | ||
51 | * per-CPU variable, which is checked in the routine below. Called by activate_mm(). | ||
52 | * <efocht@ess.nec.de> | ||
53 | */ | ||
54 | static inline void | ||
55 | delayed_tlb_flush (void) | ||
56 | { | ||
57 | extern void local_flush_tlb_all (void); | ||
58 | |||
59 | if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) { | ||
60 | local_flush_tlb_all(); | ||
61 | __ia64_per_cpu_var(ia64_need_tlb_flush) = 0; | ||
62 | } | ||
63 | } | ||
64 | |||
65 | static inline mm_context_t | ||
66 | get_mmu_context (struct mm_struct *mm) | ||
67 | { | ||
68 | unsigned long flags; | ||
69 | mm_context_t context = mm->context; | ||
70 | |||
71 | if (context) | ||
72 | return context; | ||
73 | |||
74 | spin_lock_irqsave(&ia64_ctx.lock, flags); | ||
75 | { | ||
76 | /* re-check, now that we've got the lock: */ | ||
77 | context = mm->context; | ||
78 | if (context == 0) { | ||
79 | cpus_clear(mm->cpu_vm_mask); | ||
80 | if (ia64_ctx.next >= ia64_ctx.limit) | ||
81 | wrap_mmu_context(mm); | ||
82 | mm->context = context = ia64_ctx.next++; | ||
83 | } | ||
84 | } | ||
85 | spin_unlock_irqrestore(&ia64_ctx.lock, flags); | ||
86 | return context; | ||
87 | } | ||
88 | |||
89 | /* | ||
90 | * Initialize context number to some sane value. MM is guaranteed to be a brand-new | ||
91 | * address-space, so no TLB flushing is needed, ever. | ||
92 | */ | ||
93 | static inline int | ||
94 | init_new_context (struct task_struct *p, struct mm_struct *mm) | ||
95 | { | ||
96 | mm->context = 0; | ||
97 | return 0; | ||
98 | } | ||
99 | |||
100 | static inline void | ||
101 | destroy_context (struct mm_struct *mm) | ||
102 | { | ||
103 | /* Nothing to do. */ | ||
104 | } | ||
105 | |||
106 | static inline void | ||
107 | reload_context (mm_context_t context) | ||
108 | { | ||
109 | unsigned long rid; | ||
110 | unsigned long rid_incr = 0; | ||
111 | unsigned long rr0, rr1, rr2, rr3, rr4, old_rr4; | ||
112 | |||
113 | old_rr4 = ia64_get_rr(0x8000000000000000UL); | ||
114 | rid = context << 3; /* make space for encoding the region number */ | ||
115 | rid_incr = 1 << 8; | ||
116 | |||
117 | /* encode the region id, preferred page size, and VHPT enable bit: */ | ||
118 | rr0 = (rid << 8) | (PAGE_SHIFT << 2) | 1; | ||
119 | rr1 = rr0 + 1*rid_incr; | ||
120 | rr2 = rr0 + 2*rid_incr; | ||
121 | rr3 = rr0 + 3*rid_incr; | ||
122 | rr4 = rr0 + 4*rid_incr; | ||
123 | #ifdef CONFIG_HUGETLB_PAGE | ||
124 | rr4 = (rr4 & (~(0xfcUL))) | (old_rr4 & 0xfc); | ||
125 | #endif | ||
126 | |||
127 | ia64_set_rr(0x0000000000000000UL, rr0); | ||
128 | ia64_set_rr(0x2000000000000000UL, rr1); | ||
129 | ia64_set_rr(0x4000000000000000UL, rr2); | ||
130 | ia64_set_rr(0x6000000000000000UL, rr3); | ||
131 | ia64_set_rr(0x8000000000000000UL, rr4); | ||
132 | ia64_srlz_i(); /* srlz.i implies srlz.d */ | ||
133 | } | ||
134 | |||
135 | static inline void | ||
136 | activate_context (struct mm_struct *mm) | ||
137 | { | ||
138 | mm_context_t context; | ||
139 | |||
140 | do { | ||
141 | context = get_mmu_context(mm); | ||
142 | if (!cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) | ||
143 | cpu_set(smp_processor_id(), mm->cpu_vm_mask); | ||
144 | reload_context(context); | ||
145 | /* in the unlikely event of a TLB-flush by another thread, redo the load: */ | ||
146 | } while (unlikely(context != mm->context)); | ||
147 | } | ||
148 | |||
149 | #define deactivate_mm(tsk,mm) do { } while (0) | ||
150 | |||
151 | /* | ||
152 | * Switch from address space PREV to address space NEXT. | ||
153 | */ | ||
154 | static inline void | ||
155 | activate_mm (struct mm_struct *prev, struct mm_struct *next) | ||
156 | { | ||
157 | delayed_tlb_flush(); | ||
158 | |||
159 | /* | ||
160 | * We may get interrupts here, but that's OK because interrupt handlers cannot | ||
161 | * touch user-space. | ||
162 | */ | ||
163 | ia64_set_kr(IA64_KR_PT_BASE, __pa(next->pgd)); | ||
164 | activate_context(next); | ||
165 | } | ||
166 | |||
167 | #define switch_mm(prev_mm,next_mm,next_task) activate_mm(prev_mm, next_mm) | ||
168 | |||
169 | # endif /* ! __ASSEMBLY__ */ | ||
170 | #endif /* _ASM_IA64_MMU_CONTEXT_H */ | ||