diff options
Diffstat (limited to 'include/asm-i386')
-rw-r--r-- | include/asm-i386/apic.h | 1 | ||||
-rw-r--r-- | include/asm-i386/cpufeature.h | 1 | ||||
-rw-r--r-- | include/asm-i386/elf.h | 10 | ||||
-rw-r--r-- | include/asm-i386/msr.h | 2 | ||||
-rw-r--r-- | include/asm-i386/nmi.h | 2 | ||||
-rw-r--r-- | include/asm-i386/paravirt.h | 5 | ||||
-rw-r--r-- | include/asm-i386/sync_bitops.h | 2 | ||||
-rw-r--r-- | include/asm-i386/termbits.h | 2 | ||||
-rw-r--r-- | include/asm-i386/vmi_time.h | 2 |
9 files changed, 17 insertions, 10 deletions
diff --git a/include/asm-i386/apic.h b/include/asm-i386/apic.h index cc6b1652249a..a19810a08ae9 100644 --- a/include/asm-i386/apic.h +++ b/include/asm-i386/apic.h | |||
@@ -117,6 +117,7 @@ extern void enable_NMI_through_LVT0 (void * dummy); | |||
117 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | 117 | #define ARCH_APICTIMER_STOPS_ON_C3 1 |
118 | 118 | ||
119 | extern int timer_over_8254; | 119 | extern int timer_over_8254; |
120 | extern int local_apic_timer_c2_ok; | ||
120 | 121 | ||
121 | #else /* !CONFIG_X86_LOCAL_APIC */ | 122 | #else /* !CONFIG_X86_LOCAL_APIC */ |
122 | static inline void lapic_shutdown(void) { } | 123 | static inline void lapic_shutdown(void) { } |
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h index 3f92b94e0d75..d1b8e4ab6c1a 100644 --- a/include/asm-i386/cpufeature.h +++ b/include/asm-i386/cpufeature.h | |||
@@ -75,6 +75,7 @@ | |||
75 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ | 75 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ |
76 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ | 76 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ |
77 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ | 77 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ |
78 | #define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */ | ||
78 | 79 | ||
79 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | 80 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
80 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ | 81 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ |
diff --git a/include/asm-i386/elf.h b/include/asm-i386/elf.h index 8d33c9bb7c1c..952b3ee3c9bb 100644 --- a/include/asm-i386/elf.h +++ b/include/asm-i386/elf.h | |||
@@ -88,16 +88,16 @@ typedef struct user_fxsr_struct elf_fpxregset_t; | |||
88 | pr_reg[4] = regs->edi; \ | 88 | pr_reg[4] = regs->edi; \ |
89 | pr_reg[5] = regs->ebp; \ | 89 | pr_reg[5] = regs->ebp; \ |
90 | pr_reg[6] = regs->eax; \ | 90 | pr_reg[6] = regs->eax; \ |
91 | pr_reg[7] = regs->xds; \ | 91 | pr_reg[7] = regs->xds & 0xffff; \ |
92 | pr_reg[8] = regs->xes; \ | 92 | pr_reg[8] = regs->xes & 0xffff; \ |
93 | pr_reg[9] = regs->xfs; \ | 93 | pr_reg[9] = regs->xfs & 0xffff; \ |
94 | savesegment(gs,pr_reg[10]); \ | 94 | savesegment(gs,pr_reg[10]); \ |
95 | pr_reg[11] = regs->orig_eax; \ | 95 | pr_reg[11] = regs->orig_eax; \ |
96 | pr_reg[12] = regs->eip; \ | 96 | pr_reg[12] = regs->eip; \ |
97 | pr_reg[13] = regs->xcs; \ | 97 | pr_reg[13] = regs->xcs & 0xffff; \ |
98 | pr_reg[14] = regs->eflags; \ | 98 | pr_reg[14] = regs->eflags; \ |
99 | pr_reg[15] = regs->esp; \ | 99 | pr_reg[15] = regs->esp; \ |
100 | pr_reg[16] = regs->xss; | 100 | pr_reg[16] = regs->xss & 0xffff; |
101 | 101 | ||
102 | /* This yields a mask that user programs can use to figure out what | 102 | /* This yields a mask that user programs can use to figure out what |
103 | instruction set this CPU supports. This could be done in user space, | 103 | instruction set this CPU supports. This could be done in user space, |
diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h index ec3b6803fd36..2ad3f30b1a68 100644 --- a/include/asm-i386/msr.h +++ b/include/asm-i386/msr.h | |||
@@ -275,6 +275,8 @@ static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) | |||
275 | #define MSR_K7_FID_VID_CTL 0xC0010041 | 275 | #define MSR_K7_FID_VID_CTL 0xC0010041 |
276 | #define MSR_K7_FID_VID_STATUS 0xC0010042 | 276 | #define MSR_K7_FID_VID_STATUS 0xC0010042 |
277 | 277 | ||
278 | #define MSR_K8_ENABLE_C1E 0xC0010055 | ||
279 | |||
278 | /* extended feature register */ | 280 | /* extended feature register */ |
279 | #define MSR_EFER 0xc0000080 | 281 | #define MSR_EFER 0xc0000080 |
280 | 282 | ||
diff --git a/include/asm-i386/nmi.h b/include/asm-i386/nmi.h index 64544cb85d6a..b04333ea6f31 100644 --- a/include/asm-i386/nmi.h +++ b/include/asm-i386/nmi.h | |||
@@ -33,7 +33,7 @@ extern int nmi_watchdog_tick (struct pt_regs * regs, unsigned reason); | |||
33 | 33 | ||
34 | extern atomic_t nmi_active; | 34 | extern atomic_t nmi_active; |
35 | extern unsigned int nmi_watchdog; | 35 | extern unsigned int nmi_watchdog; |
36 | #define NMI_DEFAULT 0 | 36 | #define NMI_DEFAULT -1 |
37 | #define NMI_NONE 0 | 37 | #define NMI_NONE 0 |
38 | #define NMI_IO_APIC 1 | 38 | #define NMI_IO_APIC 1 |
39 | #define NMI_LOCAL_APIC 2 | 39 | #define NMI_LOCAL_APIC 2 |
diff --git a/include/asm-i386/paravirt.h b/include/asm-i386/paravirt.h index f8319cae2ac5..e63f1e444fcf 100644 --- a/include/asm-i386/paravirt.h +++ b/include/asm-i386/paravirt.h | |||
@@ -130,7 +130,7 @@ struct paravirt_ops | |||
130 | void (*flush_tlb_kernel)(void); | 130 | void (*flush_tlb_kernel)(void); |
131 | void (*flush_tlb_single)(u32 addr); | 131 | void (*flush_tlb_single)(u32 addr); |
132 | 132 | ||
133 | void (fastcall *map_pt_hook)(int type, pte_t *va, u32 pfn); | 133 | void (*map_pt_hook)(int type, pte_t *va, u32 pfn); |
134 | 134 | ||
135 | void (*alloc_pt)(u32 pfn); | 135 | void (*alloc_pt)(u32 pfn); |
136 | void (*alloc_pd)(u32 pfn); | 136 | void (*alloc_pd)(u32 pfn); |
@@ -421,14 +421,17 @@ static inline void pmd_clear(pmd_t *pmdp) | |||
421 | #define PARAVIRT_LAZY_NONE 0 | 421 | #define PARAVIRT_LAZY_NONE 0 |
422 | #define PARAVIRT_LAZY_MMU 1 | 422 | #define PARAVIRT_LAZY_MMU 1 |
423 | #define PARAVIRT_LAZY_CPU 2 | 423 | #define PARAVIRT_LAZY_CPU 2 |
424 | #define PARAVIRT_LAZY_FLUSH 3 | ||
424 | 425 | ||
425 | #define __HAVE_ARCH_ENTER_LAZY_CPU_MODE | 426 | #define __HAVE_ARCH_ENTER_LAZY_CPU_MODE |
426 | #define arch_enter_lazy_cpu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_CPU) | 427 | #define arch_enter_lazy_cpu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_CPU) |
427 | #define arch_leave_lazy_cpu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_NONE) | 428 | #define arch_leave_lazy_cpu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_NONE) |
429 | #define arch_flush_lazy_cpu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_FLUSH) | ||
428 | 430 | ||
429 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE | 431 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE |
430 | #define arch_enter_lazy_mmu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_MMU) | 432 | #define arch_enter_lazy_mmu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_MMU) |
431 | #define arch_leave_lazy_mmu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_NONE) | 433 | #define arch_leave_lazy_mmu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_NONE) |
434 | #define arch_flush_lazy_mmu_mode() paravirt_ops.set_lazy_mode(PARAVIRT_LAZY_FLUSH) | ||
432 | 435 | ||
433 | /* These all sit in the .parainstructions section to tell us what to patch. */ | 436 | /* These all sit in the .parainstructions section to tell us what to patch. */ |
434 | struct paravirt_patch { | 437 | struct paravirt_patch { |
diff --git a/include/asm-i386/sync_bitops.h b/include/asm-i386/sync_bitops.h index c94d51c993ee..7d72351bea75 100644 --- a/include/asm-i386/sync_bitops.h +++ b/include/asm-i386/sync_bitops.h | |||
@@ -130,7 +130,7 @@ static inline int sync_test_and_change_bit(int nr, volatile unsigned long* addr) | |||
130 | return oldbit; | 130 | return oldbit; |
131 | } | 131 | } |
132 | 132 | ||
133 | static __always_inline int sync_const_test_bit(int nr, const volatile unsigned long *addr) | 133 | static __always_inline int sync_constant_test_bit(int nr, const volatile unsigned long *addr) |
134 | { | 134 | { |
135 | return ((1UL << (nr & 31)) & | 135 | return ((1UL << (nr & 31)) & |
136 | (((const volatile unsigned int *)addr)[nr >> 5])) != 0; | 136 | (((const volatile unsigned int *)addr)[nr >> 5])) != 0; |
diff --git a/include/asm-i386/termbits.h b/include/asm-i386/termbits.h index 12baf1d6343f..2e6237693814 100644 --- a/include/asm-i386/termbits.h +++ b/include/asm-i386/termbits.h | |||
@@ -144,7 +144,7 @@ struct ktermios { | |||
144 | #define B3000000 0010015 | 144 | #define B3000000 0010015 |
145 | #define B3500000 0010016 | 145 | #define B3500000 0010016 |
146 | #define B4000000 0010017 | 146 | #define B4000000 0010017 |
147 | #define CIBAUD 002003600000 /* input baud rate (not used) */ | 147 | #define CIBAUD 002003600000 |
148 | #define CMSPAR 010000000000 /* mark or space (stick) parity */ | 148 | #define CMSPAR 010000000000 /* mark or space (stick) parity */ |
149 | #define CRTSCTS 020000000000 /* flow control */ | 149 | #define CRTSCTS 020000000000 /* flow control */ |
150 | 150 | ||
diff --git a/include/asm-i386/vmi_time.h b/include/asm-i386/vmi_time.h index 94d0a12a4114..c3a1fcf66c96 100644 --- a/include/asm-i386/vmi_time.h +++ b/include/asm-i386/vmi_time.h | |||
@@ -54,7 +54,7 @@ extern unsigned long vmi_cpu_khz(void); | |||
54 | 54 | ||
55 | #ifdef CONFIG_X86_LOCAL_APIC | 55 | #ifdef CONFIG_X86_LOCAL_APIC |
56 | extern void __init vmi_timer_setup_boot_alarm(void); | 56 | extern void __init vmi_timer_setup_boot_alarm(void); |
57 | extern void __init vmi_timer_setup_secondary_alarm(void); | 57 | extern void __devinit vmi_timer_setup_secondary_alarm(void); |
58 | extern void apic_vmi_timer_interrupt(void); | 58 | extern void apic_vmi_timer_interrupt(void); |
59 | #endif | 59 | #endif |
60 | 60 | ||