1 files changed, 0 insertions, 91 deletions
diff --git a/include/asm-i386/processor-flags.h b/include/asm-i386/processor-flags.h
deleted file mode 100644
index 5404e90edd57..000000000000
--- a/include/asm-i386/processor-flags.h
+++ /dev/null
@@ -1,91 +0,0 @@
-#ifndef __ASM_I386_PROCESSOR_FLAGS_H
-#define __ASM_I386_PROCESSOR_FLAGS_H
-/* Various flags defined: can be included from assembler. */
-/*
- * EFLAGS bits
- */
-#define X86_EFLAGS_CF   0x00000001 /* Carry Flag */
-#define X86_EFLAGS_PF   0x00000004 /* Parity Flag */
-#define X86_EFLAGS_AF   0x00000010 /* Auxillary carry Flag */
-#define X86_EFLAGS_ZF   0x00000040 /* Zero Flag */
-#define X86_EFLAGS_SF   0x00000080 /* Sign Flag */
-#define X86_EFLAGS_TF   0x00000100 /* Trap Flag */
-#define X86_EFLAGS_IF   0x00000200 /* Interrupt Flag */
-#define X86_EFLAGS_DF   0x00000400 /* Direction Flag */
-#define X86_EFLAGS_OF   0x00000800 /* Overflow Flag */
-#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
-#define X86_EFLAGS_NT   0x00004000 /* Nested Task */
-#define X86_EFLAGS_RF   0x00010000 /* Resume Flag */
-#define X86_EFLAGS_VM   0x00020000 /* Virtual Mode */
-#define X86_EFLAGS_AC   0x00040000 /* Alignment Check */
-#define X86_EFLAGS_VIF  0x00080000 /* Virtual Interrupt Flag */
-#define X86_EFLAGS_VIP  0x00100000 /* Virtual Interrupt Pending */
-#define X86_EFLAGS_ID   0x00200000 /* CPUID detection flag */
-/*
- * Basic CPU control in CR0
- */
-#define X86_CR0_PE      0x00000001 /* Protection Enable */
-#define X86_CR0_MP      0x00000002 /* Monitor Coprocessor */
-#define X86_CR0_EM      0x00000004 /* Emulation */
-#define X86_CR0_TS      0x00000008 /* Task Switched */
-#define X86_CR0_ET      0x00000010 /* Extension Type */
-#define X86_CR0_NE      0x00000020 /* Numeric Error */
-#define X86_CR0_WP      0x00010000 /* Write Protect */
-#define X86_CR0_AM      0x00040000 /* Alignment Mask */
-#define X86_CR0_NW      0x20000000 /* Not Write-through */
-#define X86_CR0_CD      0x40000000 /* Cache Disable */
-#define X86_CR0_PG      0x80000000 /* Paging */
-/*
- * Paging options in CR3
- */
-#define X86_CR3_PWT     0x00000008 /* Page Write Through */
-#define X86_CR3_PCD     0x00000010 /* Page Cache Disable */
-/*
- * Intel CPU features in CR4
- */
-#define X86_CR4_VME     0x00000001 /* enable vm86 extensions */
-#define X86_CR4_PVI     0x00000002 /* virtual interrupts flag enable */
-#define X86_CR4_TSD     0x00000004 /* disable time stamp at ipl 3 */
-#define X86_CR4_DE      0x00000008 /* enable debugging extensions */
-#define X86_CR4_PSE     0x00000010 /* enable page size extensions */
-#define X86_CR4_PAE     0x00000020 /* enable physical address extensions */
-#define X86_CR4_MCE     0x00000040 /* Machine check enable */
-#define X86_CR4_PGE     0x00000080 /* enable global pages */
-#define X86_CR4_PCE     0x00000100 /* enable performance counters at ipl 3 */
-#define X86_CR4_OSFXSR  0x00000200 /* enable fast FPU save and restore */
-#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
-#define X86_CR4_VMXE    0x00002000 /* enable VMX virtualization */
-/*
- * x86-64 Task Priority Register, CR8
- */
-#define X86_CR8_TPR     0x00000007 /* task priority register */
-/*
- * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
- */
-/*
- *      NSC/Cyrix CPU configuration register indexes
- */
-#define CX86_PCR0       0x20
-#define CX86_GCR        0xb8
-#define CX86_CCR0       0xc0
-#define CX86_CCR1       0xc1
-#define CX86_CCR2       0xc2
-#define CX86_CCR3       0xc3
-#define CX86_CCR4       0xe8
-#define CX86_CCR5       0xe9
-#define CX86_CCR6       0xea
-#define CX86_CCR7       0xeb
-#define CX86_PCR1       0xf0
-#define CX86_DIR0       0xfe
-#define CX86_DIR1       0xff
-#define CX86_ARR_BASE   0xc4
-#define CX86_RCR_BASE   0xdc
-#endif  /* __ASM_I386_PROCESSOR_FLAGS_H */

diff --git a/include/asm-i386/processor-flags.h b/include/asm-i386/processor-flags.h deleted file mode 100644 index 5404e90edd57..000000000000 --- a/include/asm-i386/processor-flags.h +++ /dev/null
@@ -1,91 +0,0 @@
1	#ifndef __ASM_I386_PROCESSOR_FLAGS_H
2	#define __ASM_I386_PROCESSOR_FLAGS_H
3	/* Various flags defined: can be included from assembler. */
4
5	/*
6	* EFLAGS bits
7	*/
8	#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
9	#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
10	#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
11	#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
12	#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
13	#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
14	#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
15	#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
16	#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
17	#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
18	#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
19	#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
20	#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
21	#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
22	#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
23	#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
24	#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
25
26	/*
27	* Basic CPU control in CR0
28	*/
29	#define X86_CR0_PE 0x00000001 /* Protection Enable */
30	#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */
31	#define X86_CR0_EM 0x00000004 /* Emulation */
32	#define X86_CR0_TS 0x00000008 /* Task Switched */
33	#define X86_CR0_ET 0x00000010 /* Extension Type */
34	#define X86_CR0_NE 0x00000020 /* Numeric Error */
35	#define X86_CR0_WP 0x00010000 /* Write Protect */
36	#define X86_CR0_AM 0x00040000 /* Alignment Mask */
37	#define X86_CR0_NW 0x20000000 /* Not Write-through */
38	#define X86_CR0_CD 0x40000000 /* Cache Disable */
39	#define X86_CR0_PG 0x80000000 /* Paging */
40
41	/*
42	* Paging options in CR3
43	*/
44	#define X86_CR3_PWT 0x00000008 /* Page Write Through */
45	#define X86_CR3_PCD 0x00000010 /* Page Cache Disable */
46
47	/*
48	* Intel CPU features in CR4
49	*/
50	#define X86_CR4_VME 0x00000001 /* enable vm86 extensions */
51	#define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */
52	#define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */
53	#define X86_CR4_DE 0x00000008 /* enable debugging extensions */
54	#define X86_CR4_PSE 0x00000010 /* enable page size extensions */
55	#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */
56	#define X86_CR4_MCE 0x00000040 /* Machine check enable */
57	#define X86_CR4_PGE 0x00000080 /* enable global pages */
58	#define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */
59	#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */
60	#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
61	#define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */
62
63	/*
64	* x86-64 Task Priority Register, CR8
65	*/
66	#define X86_CR8_TPR 0x00000007 /* task priority register */
67
68	/*
69	* AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
70	*/
71
72	/*
73	* NSC/Cyrix CPU configuration register indexes
74	*/
75	#define CX86_PCR0 0x20
76	#define CX86_GCR 0xb8
77	#define CX86_CCR0 0xc0
78	#define CX86_CCR1 0xc1
79	#define CX86_CCR2 0xc2
80	#define CX86_CCR3 0xc3
81	#define CX86_CCR4 0xe8
82	#define CX86_CCR5 0xe9
83	#define CX86_CCR6 0xea
84	#define CX86_CCR7 0xeb
85	#define CX86_PCR1 0xf0
86	#define CX86_DIR0 0xfe
87	#define CX86_DIR1 0xff
88	#define CX86_ARR_BASE 0xc4
89	#define CX86_RCR_BASE 0xdc
90
91	#endif /* __ASM_I386_PROCESSOR_FLAGS_H */