diff options
Diffstat (limited to 'include/asm-i386/pgtable-3level.h')
-rw-r--r-- | include/asm-i386/pgtable-3level.h | 40 |
1 files changed, 21 insertions, 19 deletions
diff --git a/include/asm-i386/pgtable-3level.h b/include/asm-i386/pgtable-3level.h index c2d701ea35be..2a6e67db8bc3 100644 --- a/include/asm-i386/pgtable-3level.h +++ b/include/asm-i386/pgtable-3level.h | |||
@@ -44,6 +44,7 @@ static inline int pte_exec_kernel(pte_t pte) | |||
44 | return pte_x(pte); | 44 | return pte_x(pte); |
45 | } | 45 | } |
46 | 46 | ||
47 | #ifndef CONFIG_PARAVIRT | ||
47 | /* Rules for using set_pte: the pte being assigned *must* be | 48 | /* Rules for using set_pte: the pte being assigned *must* be |
48 | * either not present or in a state where the hardware will | 49 | * either not present or in a state where the hardware will |
49 | * not attempt to update the pte. In places where this is | 50 | * not attempt to update the pte. In places where this is |
@@ -81,25 +82,6 @@ static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, pte | |||
81 | (*(pudptr) = (pudval)) | 82 | (*(pudptr) = (pudval)) |
82 | 83 | ||
83 | /* | 84 | /* |
84 | * Pentium-II erratum A13: in PAE mode we explicitly have to flush | ||
85 | * the TLB via cr3 if the top-level pgd is changed... | ||
86 | * We do not let the generic code free and clear pgd entries due to | ||
87 | * this erratum. | ||
88 | */ | ||
89 | static inline void pud_clear (pud_t * pud) { } | ||
90 | |||
91 | #define pud_page(pud) \ | ||
92 | ((struct page *) __va(pud_val(pud) & PAGE_MASK)) | ||
93 | |||
94 | #define pud_page_vaddr(pud) \ | ||
95 | ((unsigned long) __va(pud_val(pud) & PAGE_MASK)) | ||
96 | |||
97 | |||
98 | /* Find an entry in the second-level page table.. */ | ||
99 | #define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \ | ||
100 | pmd_index(address)) | ||
101 | |||
102 | /* | ||
103 | * For PTEs and PDEs, we must clear the P-bit first when clearing a page table | 85 | * For PTEs and PDEs, we must clear the P-bit first when clearing a page table |
104 | * entry, so clear the bottom half first and enforce ordering with a compiler | 86 | * entry, so clear the bottom half first and enforce ordering with a compiler |
105 | * barrier. | 87 | * barrier. |
@@ -118,6 +100,26 @@ static inline void pmd_clear(pmd_t *pmd) | |||
118 | smp_wmb(); | 100 | smp_wmb(); |
119 | *(tmp + 1) = 0; | 101 | *(tmp + 1) = 0; |
120 | } | 102 | } |
103 | #endif | ||
104 | |||
105 | /* | ||
106 | * Pentium-II erratum A13: in PAE mode we explicitly have to flush | ||
107 | * the TLB via cr3 if the top-level pgd is changed... | ||
108 | * We do not let the generic code free and clear pgd entries due to | ||
109 | * this erratum. | ||
110 | */ | ||
111 | static inline void pud_clear (pud_t * pud) { } | ||
112 | |||
113 | #define pud_page(pud) \ | ||
114 | ((struct page *) __va(pud_val(pud) & PAGE_MASK)) | ||
115 | |||
116 | #define pud_page_vaddr(pud) \ | ||
117 | ((unsigned long) __va(pud_val(pud) & PAGE_MASK)) | ||
118 | |||
119 | |||
120 | /* Find an entry in the second-level page table.. */ | ||
121 | #define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \ | ||
122 | pmd_index(address)) | ||
121 | 123 | ||
122 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | 124 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR |
123 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) | 125 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |