aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-i386/pgtable-3level.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-i386/pgtable-3level.h')
-rw-r--r--include/asm-i386/pgtable-3level.h45
1 files changed, 22 insertions, 23 deletions
diff --git a/include/asm-i386/pgtable-3level.h b/include/asm-i386/pgtable-3level.h
index c2d701ea35be..7a2318f38303 100644
--- a/include/asm-i386/pgtable-3level.h
+++ b/include/asm-i386/pgtable-3level.h
@@ -1,8 +1,6 @@
1#ifndef _I386_PGTABLE_3LEVEL_H 1#ifndef _I386_PGTABLE_3LEVEL_H
2#define _I386_PGTABLE_3LEVEL_H 2#define _I386_PGTABLE_3LEVEL_H
3 3
4#include <asm-generic/pgtable-nopud.h>
5
6/* 4/*
7 * Intel Physical Address Extension (PAE) Mode - three-level page 5 * Intel Physical Address Extension (PAE) Mode - three-level page
8 * tables on PPro+ CPUs. 6 * tables on PPro+ CPUs.
@@ -44,6 +42,7 @@ static inline int pte_exec_kernel(pte_t pte)
44 return pte_x(pte); 42 return pte_x(pte);
45} 43}
46 44
45#ifndef CONFIG_PARAVIRT
47/* Rules for using set_pte: the pte being assigned *must* be 46/* Rules for using set_pte: the pte being assigned *must* be
48 * either not present or in a state where the hardware will 47 * either not present or in a state where the hardware will
49 * not attempt to update the pte. In places where this is 48 * not attempt to update the pte. In places where this is
@@ -81,25 +80,6 @@ static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, pte
81 (*(pudptr) = (pudval)) 80 (*(pudptr) = (pudval))
82 81
83/* 82/*
84 * Pentium-II erratum A13: in PAE mode we explicitly have to flush
85 * the TLB via cr3 if the top-level pgd is changed...
86 * We do not let the generic code free and clear pgd entries due to
87 * this erratum.
88 */
89static inline void pud_clear (pud_t * pud) { }
90
91#define pud_page(pud) \
92((struct page *) __va(pud_val(pud) & PAGE_MASK))
93
94#define pud_page_vaddr(pud) \
95((unsigned long) __va(pud_val(pud) & PAGE_MASK))
96
97
98/* Find an entry in the second-level page table.. */
99#define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
100 pmd_index(address))
101
102/*
103 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table 83 * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
104 * entry, so clear the bottom half first and enforce ordering with a compiler 84 * entry, so clear the bottom half first and enforce ordering with a compiler
105 * barrier. 85 * barrier.
@@ -118,9 +98,28 @@ static inline void pmd_clear(pmd_t *pmd)
118 smp_wmb(); 98 smp_wmb();
119 *(tmp + 1) = 0; 99 *(tmp + 1) = 0;
120} 100}
101#endif
102
103/*
104 * Pentium-II erratum A13: in PAE mode we explicitly have to flush
105 * the TLB via cr3 if the top-level pgd is changed...
106 * We do not let the generic code free and clear pgd entries due to
107 * this erratum.
108 */
109static inline void pud_clear (pud_t * pud) { }
110
111#define pud_page(pud) \
112((struct page *) __va(pud_val(pud) & PAGE_MASK))
113
114#define pud_page_vaddr(pud) \
115((unsigned long) __va(pud_val(pud) & PAGE_MASK))
116
117
118/* Find an entry in the second-level page table.. */
119#define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
120 pmd_index(address))
121 121
122#define __HAVE_ARCH_PTEP_GET_AND_CLEAR 122static inline pte_t raw_ptep_get_and_clear(pte_t *ptep)
123static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
124{ 123{
125 pte_t res; 124 pte_t res;
126 125