diff options
Diffstat (limited to 'include/asm-i386/cpufeature.h')
-rw-r--r-- | include/asm-i386/cpufeature.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h index d1b8e4ab6c1a..f514e906643a 100644 --- a/include/asm-i386/cpufeature.h +++ b/include/asm-i386/cpufeature.h | |||
@@ -7,7 +7,10 @@ | |||
7 | #ifndef __ASM_I386_CPUFEATURE_H | 7 | #ifndef __ASM_I386_CPUFEATURE_H |
8 | #define __ASM_I386_CPUFEATURE_H | 8 | #define __ASM_I386_CPUFEATURE_H |
9 | 9 | ||
10 | #ifndef __ASSEMBLY__ | ||
10 | #include <linux/bitops.h> | 11 | #include <linux/bitops.h> |
12 | #endif | ||
13 | #include <asm/required-features.h> | ||
11 | 14 | ||
12 | #define NCAPINTS 7 /* N 32-bit words worth of info */ | 15 | #define NCAPINTS 7 /* N 32-bit words worth of info */ |
13 | 16 | ||
@@ -49,6 +52,7 @@ | |||
49 | #define X86_FEATURE_MP (1*32+19) /* MP Capable. */ | 52 | #define X86_FEATURE_MP (1*32+19) /* MP Capable. */ |
50 | #define X86_FEATURE_NX (1*32+20) /* Execute Disable */ | 53 | #define X86_FEATURE_NX (1*32+20) /* Execute Disable */ |
51 | #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ | 54 | #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ |
55 | #define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */ | ||
52 | #define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */ | 56 | #define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */ |
53 | #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ | 57 | #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ |
54 | #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */ | 58 | #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */ |
@@ -76,6 +80,7 @@ | |||
76 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ | 80 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ |
77 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ | 81 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ |
78 | #define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */ | 82 | #define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */ |
83 | #define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */ | ||
79 | 84 | ||
80 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | 85 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
81 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ | 86 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ |
@@ -103,8 +108,12 @@ | |||
103 | #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ | 108 | #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ |
104 | #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ | 109 | #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ |
105 | 110 | ||
106 | #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) | 111 | #define cpu_has(c, bit) \ |
107 | #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) | 112 | ((__builtin_constant_p(bit) && (bit) < 32 && \ |
113 | (1UL << (bit)) & REQUIRED_MASK1) ? \ | ||
114 | 1 : \ | ||
115 | test_bit(bit, (c)->x86_capability)) | ||
116 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) | ||
108 | 117 | ||
109 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) | 118 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |
110 | #define cpu_has_vme boot_cpu_has(X86_FEATURE_VME) | 119 | #define cpu_has_vme boot_cpu_has(X86_FEATURE_VME) |