diff options
Diffstat (limited to 'include/asm-frv/timer-regs.h')
| -rw-r--r-- | include/asm-frv/timer-regs.h | 106 |
1 files changed, 0 insertions, 106 deletions
diff --git a/include/asm-frv/timer-regs.h b/include/asm-frv/timer-regs.h deleted file mode 100644 index 6c5a871ce5e9..000000000000 --- a/include/asm-frv/timer-regs.h +++ /dev/null | |||
| @@ -1,106 +0,0 @@ | |||
| 1 | /* timer-regs.h: hardware timer register definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the License, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_TIMER_REGS_H | ||
| 13 | #define _ASM_TIMER_REGS_H | ||
| 14 | |||
| 15 | #include <asm/sections.h> | ||
| 16 | |||
| 17 | extern unsigned long __nongprelbss __clkin_clock_speed_HZ; | ||
| 18 | extern unsigned long __nongprelbss __ext_bus_clock_speed_HZ; | ||
| 19 | extern unsigned long __nongprelbss __res_bus_clock_speed_HZ; | ||
| 20 | extern unsigned long __nongprelbss __sdram_clock_speed_HZ; | ||
| 21 | extern unsigned long __nongprelbss __core_bus_clock_speed_HZ; | ||
| 22 | extern unsigned long __nongprelbss __core_clock_speed_HZ; | ||
| 23 | extern unsigned long __nongprelbss __dsu_clock_speed_HZ; | ||
| 24 | extern unsigned long __nongprelbss __serial_clock_speed_HZ; | ||
| 25 | |||
| 26 | #define __get_CLKC() ({ *(volatile unsigned long *)(0xfeff9a00); }) | ||
| 27 | |||
| 28 | static inline void __set_CLKC(unsigned long v) | ||
| 29 | { | ||
| 30 | int tmp; | ||
| 31 | |||
| 32 | asm volatile(" st%I0.p %2,%M0 \n" | ||
| 33 | " setlos %3,%1 \n" | ||
| 34 | " membar \n" | ||
| 35 | "0: \n" | ||
| 36 | " subicc %1,#1,%1,icc0 \n" | ||
| 37 | " bnc icc0,#1,0b \n" | ||
| 38 | : "=m"(*(volatile unsigned long *) 0xfeff9a00), "=r"(tmp) | ||
| 39 | : "r"(v), "i"(256) | ||
| 40 | : "icc0"); | ||
| 41 | } | ||
| 42 | |||
| 43 | #define __get_TCTR() ({ *(volatile unsigned long *)(0xfeff9418); }) | ||
| 44 | #define __get_TPRV() ({ *(volatile unsigned long *)(0xfeff9420); }) | ||
| 45 | #define __get_TPRCKSL() ({ *(volatile unsigned long *)(0xfeff9428); }) | ||
| 46 | #define __get_TCSR(T) ({ *(volatile unsigned long *)(0xfeff9400 + 8 * (T)); }) | ||
| 47 | #define __get_TxCKSL(T) ({ *(volatile unsigned long *)(0xfeff9430 + 8 * (T)); }) | ||
| 48 | |||
| 49 | #define __get_TCSR_DATA(T) ({ __get_TCSR(T) >> 24; }) | ||
| 50 | |||
| 51 | #define __set_TCTR(V) do { *(volatile unsigned long *)(0xfeff9418) = (V); mb(); } while(0) | ||
| 52 | #define __set_TPRV(V) do { *(volatile unsigned long *)(0xfeff9420) = (V) << 24; mb(); } while(0) | ||
| 53 | #define __set_TPRCKSL(V) do { *(volatile unsigned long *)(0xfeff9428) = (V); mb(); } while(0) | ||
| 54 | #define __set_TCSR(T,V) \ | ||
| 55 | do { *(volatile unsigned long *)(0xfeff9400 + 8 * (T)) = (V); mb(); } while(0) | ||
| 56 | |||
| 57 | #define __set_TxCKSL(T,V) \ | ||
| 58 | do { *(volatile unsigned long *)(0xfeff9430 + 8 * (T)) = (V); mb(); } while(0) | ||
| 59 | |||
| 60 | #define __set_TCSR_DATA(T,V) __set_TCSR(T, (V) << 24) | ||
| 61 | #define __set_TxCKSL_DATA(T,V) __set_TxCKSL(T, TxCKSL_EIGHT | __TxCKSL_SELECT((V))) | ||
| 62 | |||
| 63 | /* clock control register */ | ||
| 64 | #define CLKC_CMODE 0x0f000000 | ||
| 65 | #define CLKC_SLPL 0x000f0000 | ||
| 66 | #define CLKC_P0 0x00000100 | ||
| 67 | #define CLKC_CM 0x00000003 | ||
| 68 | |||
| 69 | #define CLKC_CMODE_s 24 | ||
| 70 | |||
| 71 | /* timer control register - non-readback mode */ | ||
| 72 | #define TCTR_MODE_0 0x00000000 | ||
| 73 | #define TCTR_MODE_2 0x04000000 | ||
| 74 | #define TCTR_MODE_4 0x08000000 | ||
| 75 | #define TCTR_MODE_5 0x0a000000 | ||
| 76 | #define TCTR_RL_LATCH 0x00000000 | ||
| 77 | #define TCTR_RL_RW_LOW8 0x10000000 | ||
| 78 | #define TCTR_RL_RW_HIGH8 0x20000000 | ||
| 79 | #define TCTR_RL_RW_LH8 0x30000000 | ||
| 80 | #define TCTR_SC_CTR0 0x00000000 | ||
| 81 | #define TCTR_SC_CTR1 0x40000000 | ||
| 82 | #define TCTR_SC_CTR2 0x80000000 | ||
| 83 | |||
| 84 | /* timer control register - readback mode */ | ||
| 85 | #define TCTR_CNT0 0x02000000 | ||
| 86 | #define TCTR_CNT1 0x04000000 | ||
| 87 | #define TCTR_CNT2 0x08000000 | ||
| 88 | #define TCTR_NSTATUS 0x10000000 | ||
| 89 | #define TCTR_NCOUNT 0x20000000 | ||
| 90 | #define TCTR_SC_READBACK 0xc0000000 | ||
| 91 | |||
| 92 | /* timer control status registers - non-readback mode */ | ||
| 93 | #define TCSRx_DATA 0xff000000 | ||
| 94 | |||
| 95 | /* timer control status registers - readback mode */ | ||
| 96 | #define TCSRx_OUTPUT 0x80000000 | ||
| 97 | #define TCSRx_NULLCOUNT 0x40000000 | ||
| 98 | #define TCSRx_RL 0x30000000 | ||
| 99 | #define TCSRx_MODE 0x07000000 | ||
| 100 | |||
| 101 | /* timer clock select registers */ | ||
| 102 | #define TxCKSL_SELECT 0x0f000000 | ||
| 103 | #define __TxCKSL_SELECT(X) ((X) << 24) | ||
| 104 | #define TxCKSL_EIGHT 0xf0000000 | ||
| 105 | |||
| 106 | #endif /* _ASM_TIMER_REGS_H */ | ||