diff options
Diffstat (limited to 'include/asm-frv/irc-regs.h')
-rw-r--r-- | include/asm-frv/irc-regs.h | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/include/asm-frv/irc-regs.h b/include/asm-frv/irc-regs.h deleted file mode 100644 index afa30aeacc82..000000000000 --- a/include/asm-frv/irc-regs.h +++ /dev/null | |||
@@ -1,53 +0,0 @@ | |||
1 | /* irc-regs.h: on-chip interrupt controller registers | ||
2 | * | ||
3 | * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved. | ||
4 | * Written by David Howells (dhowells@redhat.com) | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * as published by the Free Software Foundation; either version | ||
9 | * 2 of the License, or (at your option) any later version. | ||
10 | */ | ||
11 | |||
12 | #ifndef _ASM_IRC_REGS | ||
13 | #define _ASM_IRC_REGS | ||
14 | |||
15 | #define __reg(ADDR) (*(volatile unsigned long *)(ADDR)) | ||
16 | |||
17 | #define __get_TM0() ({ __reg(0xfeff9800); }) | ||
18 | #define __get_TM1() ({ __reg(0xfeff9808); }) | ||
19 | #define __set_TM1(V) do { __reg(0xfeff9808) = (V); mb(); } while(0) | ||
20 | |||
21 | #define __set_TM1x(XI,V) \ | ||
22 | do { \ | ||
23 | int shift = (XI) * 2 + 16; \ | ||
24 | unsigned long tm1 = __reg(0xfeff9808); \ | ||
25 | tm1 &= ~(0x3 << shift); \ | ||
26 | tm1 |= (V) << shift; \ | ||
27 | __reg(0xfeff9808) = tm1; \ | ||
28 | mb(); \ | ||
29 | } while(0) | ||
30 | |||
31 | #define __get_RS(C) ({ (__reg(0xfeff9810) >> ((C)+16)) & 1; }) | ||
32 | |||
33 | #define __clr_RC(C) do { __reg(0xfeff9818) = 1 << ((C)+16); mb(); } while(0) | ||
34 | |||
35 | #define __get_MASK(C) ({ (__reg(0xfeff9820) >> ((C)+16)) & 1; }) | ||
36 | #define __set_MASK(C) do { __reg(0xfeff9820) |= 1 << ((C)+16); mb(); } while(0) | ||
37 | #define __clr_MASK(C) do { __reg(0xfeff9820) &= ~(1 << ((C)+16)); mb(); } while(0) | ||
38 | |||
39 | #define __get_MASK_all() __get_MASK(0) | ||
40 | #define __set_MASK_all() __set_MASK(0) | ||
41 | #define __clr_MASK_all() __clr_MASK(0) | ||
42 | |||
43 | #define __get_IRL() ({ (__reg(0xfeff9828) >> 16) & 0xf; }) | ||
44 | #define __clr_IRL() do { __reg(0xfeff9828) = 0x100000; mb(); } while(0) | ||
45 | |||
46 | #define __get_IRR(N) ({ __reg(0xfeff9840 + (N) * 8); }) | ||
47 | #define __set_IRR(N,V) do { __reg(0xfeff9840 + (N) * 8) = (V); } while(0) | ||
48 | |||
49 | #define __get_IITMR(N) ({ __reg(0xfeff9880 + (N) * 8); }) | ||
50 | #define __set_IITMR(N,V) do { __reg(0xfeff9880 + (N) * 8) = (V); } while(0) | ||
51 | |||
52 | |||
53 | #endif /* _ASM_IRC_REGS */ | ||