1 files changed, 0 insertions, 81 deletions
diff --git a/include/asm-frv/atomic.h b/include/asm-frv/atomic.h
index 6ec494a5bc5a..46d696b331e7 100644
--- a/include/asm-frv/atomic.h
+++ b/include/asm-frv/atomic.h
@@ -125,87 +125,6 @@ static inline void atomic_dec(atomic_t *v)
 #define atomic_dec_and_test(v)          (atomic_sub_return(1, (v)) == 0)
 #define atomic_inc_and_test(v)          (atomic_add_return(1, (v)) == 0)
-#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
-static inline
-unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v)
-{
-        unsigned long old, tmp;
-        asm volatile(
-                "0:                                             \n"
-                "       orcc            gr0,gr0,gr0,icc3        \n"     /* set ICC3.Z */
-                "       ckeq            icc3,cc7                \n"
-                "       ld.p            %M0,%1                  \n"     /* LD.P/ORCR are atomic */
-                "       orcr            cc7,cc7,cc3             \n"     /* set CC3 to true */
-                "       and%I3          %1,%3,%2                \n"
-                "       cst.p           %2,%M0          ,cc3,#1 \n"     /* if store happens... */
-                "       corcc           gr29,gr29,gr0   ,cc3,#1 \n"     /* ... clear ICC3.Z */
-                "       beq             icc3,#0,0b              \n"
-                : "+U"(*v), "=&r"(old), "=r"(tmp)
-                : "NPr"(~mask)
-                : "memory", "cc7", "cc3", "icc3"
-                );
-        return old;
-}
-static inline
-unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v)
-{
-        unsigned long old, tmp;
-        asm volatile(
-                "0:                                             \n"
-                "       orcc            gr0,gr0,gr0,icc3        \n"     /* set ICC3.Z */
-                "       ckeq            icc3,cc7                \n"
-                "       ld.p            %M0,%1                  \n"     /* LD.P/ORCR are atomic */
-                "       orcr            cc7,cc7,cc3             \n"     /* set CC3 to true */
-                "       or%I3           %1,%3,%2                \n"
-                "       cst.p           %2,%M0          ,cc3,#1 \n"     /* if store happens... */
-                "       corcc           gr29,gr29,gr0   ,cc3,#1 \n"     /* ... clear ICC3.Z */
-                "       beq             icc3,#0,0b              \n"
-                : "+U"(*v), "=&r"(old), "=r"(tmp)
-                : "NPr"(mask)
-                : "memory", "cc7", "cc3", "icc3"
-                );
-        return old;
-}
-static inline
-unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v)
-{
-        unsigned long old, tmp;
-        asm volatile(
-                "0:                                             \n"
-                "       orcc            gr0,gr0,gr0,icc3        \n"     /* set ICC3.Z */
-                "       ckeq            icc3,cc7                \n"
-                "       ld.p            %M0,%1                  \n"     /* LD.P/ORCR are atomic */
-                "       orcr            cc7,cc7,cc3             \n"     /* set CC3 to true */
-                "       xor%I3          %1,%3,%2                \n"
-                "       cst.p           %2,%M0          ,cc3,#1 \n"     /* if store happens... */
-                "       corcc           gr29,gr29,gr0   ,cc3,#1 \n"     /* ... clear ICC3.Z */
-                "       beq             icc3,#0,0b              \n"
-                : "+U"(*v), "=&r"(old), "=r"(tmp)
-                : "NPr"(mask)
-                : "memory", "cc7", "cc3", "icc3"
-                );
-        return old;
-}
-#else
-extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v);
-extern unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v);
-extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v);
-#endif
-#define atomic_clear_mask(mask, v)      atomic_test_and_ANDNOT_mask((mask), (v))
-#define atomic_set_mask(mask, v)        atomic_test_and_OR_mask((mask), (v))
 /*****************************************************************************/
 /*
 * exchange value with memory

diff --git a/include/asm-frv/atomic.h b/include/asm-frv/atomic.h index 6ec494a5bc5a..46d696b331e7 100644 --- a/include/asm-frv/atomic.h +++ b/include/asm-frv/atomic.h
@@ -125,87 +125,6 @@ static inline void atomic_dec(atomic_t *v)
125	#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)	125	#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
126	#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)	126	#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
127		127
128	#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
129	static inline
130	unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v)
131	{
132	unsigned long old, tmp;
133
134	asm volatile(
135	"0: \n"
136	" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
137	" ckeq icc3,cc7 \n"
138	" ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
139	" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
140	" and%I3 %1,%3,%2 \n"
141	" cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
142	" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
143	" beq icc3,#0,0b \n"
144	: "+U"(*v), "=&r"(old), "=r"(tmp)
145	: "NPr"(~mask)
146	: "memory", "cc7", "cc3", "icc3"
147	);
148
149	return old;
150	}
151
152	static inline
153	unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v)
154	{
155	unsigned long old, tmp;
156
157	asm volatile(
158	"0: \n"
159	" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
160	" ckeq icc3,cc7 \n"
161	" ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
162	" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
163	" or%I3 %1,%3,%2 \n"
164	" cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
165	" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
166	" beq icc3,#0,0b \n"
167	: "+U"(*v), "=&r"(old), "=r"(tmp)
168	: "NPr"(mask)
169	: "memory", "cc7", "cc3", "icc3"
170	);
171
172	return old;
173	}
174
175	static inline
176	unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v)
177	{
178	unsigned long old, tmp;
179
180	asm volatile(
181	"0: \n"
182	" orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
183	" ckeq icc3,cc7 \n"
184	" ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
185	" orcr cc7,cc7,cc3 \n" /* set CC3 to true */
186	" xor%I3 %1,%3,%2 \n"
187	" cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
188	" corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
189	" beq icc3,#0,0b \n"
190	: "+U"(*v), "=&r"(old), "=r"(tmp)
191	: "NPr"(mask)
192	: "memory", "cc7", "cc3", "icc3"
193	);
194
195	return old;
196	}
197
198	#else
199
200	extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v);
201	extern unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v);
202	extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v);
203
204	#endif
205
206	#define atomic_clear_mask(mask, v) atomic_test_and_ANDNOT_mask((mask), (v))
207	#define atomic_set_mask(mask, v) atomic_test_and_OR_mask((mask), (v))
208
209	/*****************************************************************************/	128	/*****************************************************************************/
210	/*	129	/*
211	* exchange value with memory	130	* exchange value with memory