1 files changed, 128 insertions, 0 deletions
diff --git a/include/asm-cris/arch-v32/hwregs/dma.h b/include/asm-cris/arch-v32/hwregs/dma.h
new file mode 100644
index 000000000000..c31832d3d6be
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/dma.h
@@ -0,0 +1,128 @@
+/* $Id: dma.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
+ *
+ * DMA C definitions and help macros
+ *
+ */
+#ifndef dma_h
+#define dma_h
+/* registers */ /* Really needed, since both are listed in sw.list? */
+#include "dma_defs.h"
+/* descriptors */
+// ------------------------------------------------------------ dma_descr_group
+typedef struct dma_descr_group {
+  struct dma_descr_group       *next;
+  unsigned                      eol        : 1;
+  unsigned                      tol        : 1;
+  unsigned                      bol        : 1;
+  unsigned                                 : 1;
+  unsigned                      intr       : 1;
+  unsigned                                 : 2;
+  unsigned                      en         : 1;
+  unsigned                                 : 7;
+  unsigned                      dis        : 1;
+  unsigned                      md         : 16;
+  struct dma_descr_group       *up;
+  union {
+    struct dma_descr_context   *context;
+    struct dma_descr_group     *group;
+  }                             down;
+} dma_descr_group;
+// ---------------------------------------------------------- dma_descr_context
+typedef struct dma_descr_context {
+  struct dma_descr_context     *next;
+  unsigned                      eol        : 1;
+  unsigned                                 : 3;
+  unsigned                      intr       : 1;
+  unsigned                                 : 1;
+  unsigned                      store_mode : 1;
+  unsigned                      en         : 1;
+  unsigned                                 : 7;
+  unsigned                      dis        : 1;
+  unsigned                      md0        : 16;
+  unsigned                      md1;
+  unsigned                      md2;
+  unsigned                      md3;
+  unsigned                      md4;
+  struct dma_descr_data        *saved_data;
+  char                         *saved_data_buf;
+} dma_descr_context;
+// ------------------------------------------------------------- dma_descr_data
+typedef struct dma_descr_data {
+  struct dma_descr_data        *next;
+  char                         *buf;
+  unsigned                      eol        : 1;
+  unsigned                                 : 2;
+  unsigned                      out_eop    : 1;
+  unsigned                      intr       : 1;
+  unsigned                      wait       : 1;
+  unsigned                                 : 2;
+  unsigned                                 : 3;
+  unsigned                      in_eop     : 1;
+  unsigned                                 : 4;
+  unsigned                      md         : 16;
+  char                         *after;
+} dma_descr_data;
+// --------------------------------------------------------------------- macros
+// enable DMA channel
+#define DMA_ENABLE( inst ) \
+   do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
+        e.en = regk_dma_yes; \
+        REG_WR( dma, inst, rw_cfg, e); } while( 0 )
+// reset DMA channel
+#define DMA_RESET( inst ) \
+   do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
+        r.en = regk_dma_no; \
+        REG_WR( dma, inst, rw_cfg, r); } while( 0 )
+// stop DMA channel
+#define DMA_STOP( inst ) \
+   do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
+        s.stop = regk_dma_yes; \
+        REG_WR( dma, inst, rw_cfg, s); } while( 0 )
+// continue DMA channel operation
+#define DMA_CONTINUE( inst ) \
+   do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\
+        c.stop = regk_dma_no; \
+        REG_WR( dma, inst, rw_cfg, c); } while( 0 )
+// give stream command
+#define DMA_WR_CMD( inst, cmd_par ) \
+   do { reg_dma_rw_stream_cmd r = {0}; \
+        do { r = REG_RD( dma, inst, rw_stream_cmd ); } while( r.busy ); \
+        r.cmd = (cmd_par); \
+        REG_WR( dma, inst, rw_stream_cmd, r ); \
+      } while( 0 )
+// load: g,c,d:burst
+#define DMA_START_GROUP( inst, group_descr ) \
+   do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \
+        DMA_WR_CMD( inst, regk_dma_load_g ); \
+        DMA_WR_CMD( inst, regk_dma_load_c ); \
+        DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
+      } while( 0 )
+// load: c,d:burst
+#define DMA_START_CONTEXT( inst, ctx_descr ) \
+   do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \
+        DMA_WR_CMD( inst, regk_dma_load_c ); \
+        DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
+      } while( 0 )
+// if the DMA is at the end of the data list, the last data descr is reloaded
+#define DMA_CONTINUE_DATA( inst ) \
+do { reg_dma_rw_cmd c = {0}; \
+     c.cont_data = regk_dma_yes;\
+     REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
+#endif

diff --git a/include/asm-cris/arch-v32/hwregs/dma.h b/include/asm-cris/arch-v32/hwregs/dma.h new file mode 100644 index 000000000000..c31832d3d6be --- /dev/null +++ b/include/asm-cris/arch-v32/hwregs/dma.h
@@ -0,0 +1,128 @@
	1	/* $Id: dma.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
	2	*
	3	* DMA C definitions and help macros
	4	*
	5	*/
	6
	7	#ifndef dma_h
	8	#define dma_h
	9
	10	/* registers / / Really needed, since both are listed in sw.list? */
	11	#include "dma_defs.h"
	12
	13
	14	/* descriptors */
	15
	16	// ------------------------------------------------------------ dma_descr_group
	17	typedef struct dma_descr_group {
	18	struct dma_descr_group *next;
	19	unsigned eol : 1;
	20	unsigned tol : 1;
	21	unsigned bol : 1;
	22	unsigned : 1;
	23	unsigned intr : 1;
	24	unsigned : 2;
	25	unsigned en : 1;
	26	unsigned : 7;
	27	unsigned dis : 1;
	28	unsigned md : 16;
	29	struct dma_descr_group *up;
	30	union {
	31	struct dma_descr_context *context;
	32	struct dma_descr_group *group;
	33	} down;
	34	} dma_descr_group;
	35
	36	// ---------------------------------------------------------- dma_descr_context
	37	typedef struct dma_descr_context {
	38	struct dma_descr_context *next;
	39	unsigned eol : 1;
	40	unsigned : 3;
	41	unsigned intr : 1;
	42	unsigned : 1;
	43	unsigned store_mode : 1;
	44	unsigned en : 1;
	45	unsigned : 7;
	46	unsigned dis : 1;
	47	unsigned md0 : 16;
	48	unsigned md1;
	49	unsigned md2;
	50	unsigned md3;
	51	unsigned md4;
	52	struct dma_descr_data *saved_data;
	53	char *saved_data_buf;
	54	} dma_descr_context;
	55
	56	// ------------------------------------------------------------- dma_descr_data
	57	typedef struct dma_descr_data {
	58	struct dma_descr_data *next;
	59	char *buf;
	60	unsigned eol : 1;
	61	unsigned : 2;
	62	unsigned out_eop : 1;
	63	unsigned intr : 1;
	64	unsigned wait : 1;
	65	unsigned : 2;
	66	unsigned : 3;
	67	unsigned in_eop : 1;
	68	unsigned : 4;
	69	unsigned md : 16;
	70	char *after;
	71	} dma_descr_data;
	72
	73	// --------------------------------------------------------------------- macros
	74
	75	// enable DMA channel
	76	#define DMA_ENABLE( inst ) \
	77	do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
	78	e.en = regk_dma_yes; \
	79	REG_WR( dma, inst, rw_cfg, e); } while( 0 )
	80
	81	// reset DMA channel
	82	#define DMA_RESET( inst ) \
	83	do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
	84	r.en = regk_dma_no; \
	85	REG_WR( dma, inst, rw_cfg, r); } while( 0 )
	86
	87	// stop DMA channel
	88	#define DMA_STOP( inst ) \
	89	do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
	90	s.stop = regk_dma_yes; \
	91	REG_WR( dma, inst, rw_cfg, s); } while( 0 )
	92
	93	// continue DMA channel operation
	94	#define DMA_CONTINUE( inst ) \
	95	do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\
	96	c.stop = regk_dma_no; \
	97	REG_WR( dma, inst, rw_cfg, c); } while( 0 )
	98
	99	// give stream command
	100	#define DMA_WR_CMD( inst, cmd_par ) \
	101	do { reg_dma_rw_stream_cmd r = {0}; \
	102	do { r = REG_RD( dma, inst, rw_stream_cmd ); } while( r.busy ); \
	103	r.cmd = (cmd_par); \
	104	REG_WR( dma, inst, rw_stream_cmd, r ); \
	105	} while( 0 )
	106
	107	// load: g,c,d:burst
	108	#define DMA_START_GROUP( inst, group_descr ) \
	109	do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \
	110	DMA_WR_CMD( inst, regk_dma_load_g ); \
	111	DMA_WR_CMD( inst, regk_dma_load_c ); \
	112	DMA_WR_CMD( inst, regk_dma_load_d \| regk_dma_burst ); \
	113	} while( 0 )
	114
	115	// load: c,d:burst
	116	#define DMA_START_CONTEXT( inst, ctx_descr ) \
	117	do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \
	118	DMA_WR_CMD( inst, regk_dma_load_c ); \
	119	DMA_WR_CMD( inst, regk_dma_load_d \| regk_dma_burst ); \
	120	} while( 0 )
	121
	122	// if the DMA is at the end of the data list, the last data descr is reloaded
	123	#define DMA_CONTINUE_DATA( inst ) \
	124	do { reg_dma_rw_cmd c = {0}; \
	125	c.cont_data = regk_dma_yes;\
	126	REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
	127
	128	#endif