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-rw-r--r--include/asm-blackfin/.gitignore1
-rw-r--r--include/asm-blackfin/bfin-global.h10
-rw-r--r--include/asm-blackfin/bug.h13
-rw-r--r--include/asm-blackfin/cplb.h26
-rw-r--r--include/asm-blackfin/dma-mapping.h15
-rw-r--r--include/asm-blackfin/dma.h3
-rw-r--r--include/asm-blackfin/gptimers.h150
-rw-r--r--include/asm-blackfin/mach-bf527/anomaly.h80
-rw-r--r--include/asm-blackfin/mach-bf527/bfin_serial_5xx.h48
-rw-r--r--include/asm-blackfin/mach-bf527/bfin_sir.h133
-rw-r--r--include/asm-blackfin/mach-bf527/blackfin.h15
-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF52x_base.h90
-rw-r--r--include/asm-blackfin/mach-bf527/dma.h3
-rw-r--r--include/asm-blackfin/mach-bf533/anomaly.h10
-rw-r--r--include/asm-blackfin/mach-bf533/bfin_serial_5xx.h50
-rw-r--r--include/asm-blackfin/mach-bf533/bfin_sir.h120
-rw-r--r--include/asm-blackfin/mach-bf533/blackfin.h15
-rw-r--r--include/asm-blackfin/mach-bf533/cdefBF532.h31
-rw-r--r--include/asm-blackfin/mach-bf533/defBF532.h29
-rw-r--r--include/asm-blackfin/mach-bf533/dma.h3
-rw-r--r--include/asm-blackfin/mach-bf533/mem_init.h10
-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h17
-rw-r--r--include/asm-blackfin/mach-bf537/bfin_serial_5xx.h48
-rw-r--r--include/asm-blackfin/mach-bf537/bfin_sir.h133
-rw-r--r--include/asm-blackfin/mach-bf537/blackfin.h39
-rw-r--r--include/asm-blackfin/mach-bf537/cdefBF534.h65
-rw-r--r--include/asm-blackfin/mach-bf537/dma.h3
-rw-r--r--include/asm-blackfin/mach-bf548/anomaly.h1
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_serial_5xx.h48
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_sir.h149
-rw-r--r--include/asm-blackfin/mach-bf548/blackfin.h38
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF542.h12
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF544.h33
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF547.h33
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF548.h33
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF549.h35
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF54x_base.h418
-rw-r--r--include/asm-blackfin/mach-bf548/dma.h2
-rw-r--r--include/asm-blackfin/mach-bf548/mem_init.h20
-rw-r--r--include/asm-blackfin/mach-bf561/anomaly.h6
-rw-r--r--include/asm-blackfin/mach-bf561/bfin_serial_5xx.h50
-rw-r--r--include/asm-blackfin/mach-bf561/bfin_sir.h120
-rw-r--r--include/asm-blackfin/mach-bf561/blackfin.h14
-rw-r--r--include/asm-blackfin/mach-bf561/cdefBF561.h34
-rw-r--r--include/asm-blackfin/mach-bf561/defBF561.h31
-rw-r--r--include/asm-blackfin/mach-bf561/dma.h3
-rw-r--r--include/asm-blackfin/portmux.h4
-rw-r--r--include/asm-blackfin/processor.h5
-rw-r--r--include/asm-blackfin/signal.h2
-rw-r--r--include/asm-blackfin/thread_info.h11
-rw-r--r--include/asm-blackfin/time.h36
-rw-r--r--include/asm-blackfin/timex.h17
-rw-r--r--include/asm-blackfin/trace.h4
-rw-r--r--include/asm-blackfin/uaccess.h4
-rw-r--r--include/asm-blackfin/unistd.h26
55 files changed, 1593 insertions, 756 deletions
diff --git a/include/asm-blackfin/.gitignore b/include/asm-blackfin/.gitignore
new file mode 100644
index 000000000000..7858564a4466
--- /dev/null
+++ b/include/asm-blackfin/.gitignore
@@ -0,0 +1 @@
+mach
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
index 5dba3a735596..716df7c85923 100644
--- a/include/asm-blackfin/bfin-global.h
+++ b/include/asm-blackfin/bfin-global.h
@@ -112,20 +112,10 @@ extern void init_leds(void);
112 112
113extern const char bfin_board_name[]; 113extern const char bfin_board_name[];
114extern unsigned long wall_jiffies; 114extern unsigned long wall_jiffies;
115extern unsigned long ipdt_table[];
116extern unsigned long dpdt_table[];
117extern unsigned long icplb_table[];
118extern unsigned long dcplb_table[];
119
120extern unsigned long ipdt_swapcount_table[];
121extern unsigned long dpdt_swapcount_table[];
122
123extern unsigned long table_start, table_end;
124 115
125extern unsigned long bfin_sic_iwr[]; 116extern unsigned long bfin_sic_iwr[];
126extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ 117extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
127extern struct file_operations dpmc_fops; 118extern struct file_operations dpmc_fops;
128extern char _start;
129extern unsigned long _ramstart, _ramend, _rambase; 119extern unsigned long _ramstart, _ramend, _rambase;
130extern unsigned long memory_start, memory_end, physical_mem_end; 120extern unsigned long memory_start, memory_end, physical_mem_end;
131extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[], 121extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
diff --git a/include/asm-blackfin/bug.h b/include/asm-blackfin/bug.h
index 41e53b29f167..6d3e11b1fc57 100644
--- a/include/asm-blackfin/bug.h
+++ b/include/asm-blackfin/bug.h
@@ -1,4 +1,17 @@
1#ifndef _BLACKFIN_BUG_H 1#ifndef _BLACKFIN_BUG_H
2#define _BLACKFIN_BUG_H 2#define _BLACKFIN_BUG_H
3
4#ifdef CONFIG_BUG
5#define HAVE_ARCH_BUG
6
7#define BUG() do { \
8 dump_bfin_trace_buffer(); \
9 printk(KERN_EMERG "BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
10 panic("BUG!"); \
11} while (0)
12
13#endif
14
3#include <asm-generic/bug.h> 15#include <asm-generic/bug.h>
16
4#endif 17#endif
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index 654375c2b746..5b0da9a69b67 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -74,32 +74,6 @@
74#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ 74#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
75 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) 75 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
76 76
77/*
78* Number of required data CPLB switchtable entries
79* MEMSIZE / 4 (we mostly install 4M page size CPLBs
80* approx 16 for smaller 1MB page size CPLBs for allignment purposes
81* 1 for L1 Data Memory
82* possibly 1 for L2 Data Memory
83* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
84* 1 for ASYNC Memory
85*/
86
87
88#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \
89 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
90
91/*
92* Number of required instruction CPLB switchtable entries
93* MEMSIZE / 4 (we mostly install 4M page size CPLBs
94* approx 12 for smaller 1MB page size CPLBs for allignment purposes
95* 1 for L1 Instruction Memory
96* possibly 1 for L2 Instruction Memory
97* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
98*/
99
100#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
101
102
103#define CPLB_ENABLE_ICACHE_P 0 77#define CPLB_ENABLE_ICACHE_P 0
104#define CPLB_ENABLE_DCACHE_P 1 78#define CPLB_ENABLE_DCACHE_P 1
105#define CPLB_ENABLE_DCACHE2_P 2 79#define CPLB_ENABLE_DCACHE2_P 2
diff --git a/include/asm-blackfin/dma-mapping.h b/include/asm-blackfin/dma-mapping.h
index 282fabccf6a6..1a13c2fc3667 100644
--- a/include/asm-blackfin/dma-mapping.h
+++ b/include/asm-blackfin/dma-mapping.h
@@ -27,6 +27,14 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
27extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, 27extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
28 enum dma_data_direction direction); 28 enum dma_data_direction direction);
29 29
30static inline dma_addr_t
31dma_map_page(struct device *dev, struct page *page,
32 unsigned long offset, size_t size,
33 enum dma_data_direction dir)
34{
35 return dma_map_single(dev, page_address(page) + offset, size, dir);
36}
37
30/* 38/*
31 * Unmap a single streaming mode DMA translation. The dma_addr and size 39 * Unmap a single streaming mode DMA translation. The dma_addr and size
32 * must match what was provided for in a previous pci_map_single call. All 40 * must match what was provided for in a previous pci_map_single call. All
@@ -38,6 +46,13 @@ extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
38extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, 46extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
39 enum dma_data_direction direction); 47 enum dma_data_direction direction);
40 48
49static inline void
50dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
51 enum dma_data_direction dir)
52{
53 dma_unmap_single(dev, dma_addr, size, dir);
54}
55
41/* 56/*
42 * Map a set of buffers described by scatterlist in streaming 57 * Map a set of buffers described by scatterlist in streaming
43 * mode for DMA. This is the scather-gather version of the 58 * mode for DMA. This is the scather-gather version of the
diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h
index 16d493574ba8..c0d5259e315b 100644
--- a/include/asm-blackfin/dma.h
+++ b/include/asm-blackfin/dma.h
@@ -191,4 +191,7 @@ void clear_dma_irqstat(unsigned int channel);
191void *dma_memcpy(void *dest, const void *src, size_t count); 191void *dma_memcpy(void *dest, const void *src, size_t count);
192void *safe_dma_memcpy(void *dest, const void *src, size_t count); 192void *safe_dma_memcpy(void *dest, const void *src, size_t count);
193 193
194extern int channel2irq(unsigned int channel);
195extern struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL];
196
194#endif 197#endif
diff --git a/include/asm-blackfin/gptimers.h b/include/asm-blackfin/gptimers.h
index 4f318f1fd2d9..0520d2aac8f3 100644
--- a/include/asm-blackfin/gptimers.h
+++ b/include/asm-blackfin/gptimers.h
@@ -22,6 +22,18 @@
22# define TIMER0_GROUP_REG TIMER_ENABLE 22# define TIMER0_GROUP_REG TIMER_ENABLE
23#endif 23#endif
24/* 24/*
25 * BF54x: 11 timers (BF542: 8 timers):
26 */
27#if defined(BF548_FAMILY)
28# ifdef CONFIG_BF542
29# define MAX_BLACKFIN_GPTIMERS 8
30# else
31# define MAX_BLACKFIN_GPTIMERS 11
32# define TIMER8_GROUP_REG TIMER_ENABLE1
33# endif
34# define TIMER0_GROUP_REG TIMER_ENABLE0
35#endif
36/*
25 * BF561: 12 timers: 37 * BF561: 12 timers:
26 */ 38 */
27#if defined(CONFIG_BF561) 39#if defined(CONFIG_BF561)
@@ -44,40 +56,28 @@
44#define TIMER0bit 0x0001 /* 0001b */ 56#define TIMER0bit 0x0001 /* 0001b */
45#define TIMER1bit 0x0002 /* 0010b */ 57#define TIMER1bit 0x0002 /* 0010b */
46#define TIMER2bit 0x0004 /* 0100b */ 58#define TIMER2bit 0x0004 /* 0100b */
47 59#define TIMER3bit 0x0008
48#if (MAX_BLACKFIN_GPTIMERS > 3) 60#define TIMER4bit 0x0010
49# define TIMER3bit 0x0008 61#define TIMER5bit 0x0020
50# define TIMER4bit 0x0010 62#define TIMER6bit 0x0040
51# define TIMER5bit 0x0020 63#define TIMER7bit 0x0080
52# define TIMER6bit 0x0040 64#define TIMER8bit 0x0100
53# define TIMER7bit 0x0080 65#define TIMER9bit 0x0200
54#endif 66#define TIMER10bit 0x0400
55 67#define TIMER11bit 0x0800
56#if (MAX_BLACKFIN_GPTIMERS > 8)
57# define TIMER8bit 0x0100
58# define TIMER9bit 0x0200
59# define TIMER10bit 0x0400
60# define TIMER11bit 0x0800
61#endif
62 68
63#define TIMER0_id 0 69#define TIMER0_id 0
64#define TIMER1_id 1 70#define TIMER1_id 1
65#define TIMER2_id 2 71#define TIMER2_id 2
66 72#define TIMER3_id 3
67#if (MAX_BLACKFIN_GPTIMERS > 3) 73#define TIMER4_id 4
68# define TIMER3_id 3 74#define TIMER5_id 5
69# define TIMER4_id 4 75#define TIMER6_id 6
70# define TIMER5_id 5 76#define TIMER7_id 7
71# define TIMER6_id 6 77#define TIMER8_id 8
72# define TIMER7_id 7 78#define TIMER9_id 9
73#endif 79#define TIMER10_id 10
74 80#define TIMER11_id 11
75#if (MAX_BLACKFIN_GPTIMERS > 8)
76# define TIMER8_id 8
77# define TIMER9_id 9
78# define TIMER10_id 10
79# define TIMER11_id 11
80#endif
81 81
82/* associated timers for ppi framesync: */ 82/* associated timers for ppi framesync: */
83 83
@@ -124,45 +124,31 @@
124/* 124/*
125 * Timer Status Register Bits 125 * Timer Status Register Bits
126 */ 126 */
127#define TIMER_STATUS_TIMIL0 0x0001 127#define TIMER_STATUS_TIMIL0 0x0001
128#define TIMER_STATUS_TIMIL1 0x0002 128#define TIMER_STATUS_TIMIL1 0x0002
129#define TIMER_STATUS_TIMIL2 0x0004 129#define TIMER_STATUS_TIMIL2 0x0004
130#if (MAX_BLACKFIN_GPTIMERS > 3) 130#define TIMER_STATUS_TIMIL3 0x00000008
131# define TIMER_STATUS_TIMIL3 0x00000008 131#define TIMER_STATUS_TIMIL4 0x00010000
132# define TIMER_STATUS_TIMIL4 0x00010000 132#define TIMER_STATUS_TIMIL5 0x00020000
133# define TIMER_STATUS_TIMIL5 0x00020000 133#define TIMER_STATUS_TIMIL6 0x00040000
134# define TIMER_STATUS_TIMIL6 0x00040000 134#define TIMER_STATUS_TIMIL7 0x00080000
135# define TIMER_STATUS_TIMIL7 0x00080000 135#define TIMER_STATUS_TIMIL8 0x0001
136# if (MAX_BLACKFIN_GPTIMERS > 8) 136#define TIMER_STATUS_TIMIL9 0x0002
137# define TIMER_STATUS_TIMIL8 0x0001 137#define TIMER_STATUS_TIMIL10 0x0004
138# define TIMER_STATUS_TIMIL9 0x0002 138#define TIMER_STATUS_TIMIL11 0x0008
139# define TIMER_STATUS_TIMIL10 0x0004 139
140# define TIMER_STATUS_TIMIL11 0x0008 140#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */
141# endif 141#define TIMER_STATUS_TOVF1 0x0020
142# define TIMER_STATUS_INTR 0x000F000F 142#define TIMER_STATUS_TOVF2 0x0040
143#else 143#define TIMER_STATUS_TOVF3 0x00000080
144# define TIMER_STATUS_INTR 0x0007 /* any timer interrupt */ 144#define TIMER_STATUS_TOVF4 0x00100000
145#endif 145#define TIMER_STATUS_TOVF5 0x00200000
146 146#define TIMER_STATUS_TOVF6 0x00400000
147#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */ 147#define TIMER_STATUS_TOVF7 0x00800000
148#define TIMER_STATUS_TOVF1 0x0020 148#define TIMER_STATUS_TOVF8 0x0010
149#define TIMER_STATUS_TOVF2 0x0040 149#define TIMER_STATUS_TOVF9 0x0020
150#if (MAX_BLACKFIN_GPTIMERS > 3) 150#define TIMER_STATUS_TOVF10 0x0040
151# define TIMER_STATUS_TOVF3 0x00000080 151#define TIMER_STATUS_TOVF11 0x0080
152# define TIMER_STATUS_TOVF4 0x00100000
153# define TIMER_STATUS_TOVF5 0x00200000
154# define TIMER_STATUS_TOVF6 0x00400000
155# define TIMER_STATUS_TOVF7 0x00800000
156# if (MAX_BLACKFIN_GPTIMERS > 8)
157# define TIMER_STATUS_TOVF8 0x0010
158# define TIMER_STATUS_TOVF9 0x0020
159# define TIMER_STATUS_TOVF10 0x0040
160# define TIMER_STATUS_TOVF11 0x0080
161# endif
162# define TIMER_STATUS_OFLOW 0x00F000F0
163#else
164# define TIMER_STATUS_OFLOW 0x0070 /* any timer overflow */
165#endif
166 152
167/* 153/*
168 * Timer Slave Enable Status : write 1 to clear 154 * Timer Slave Enable Status : write 1 to clear
@@ -170,22 +156,16 @@
170#define TIMER_STATUS_TRUN0 0x1000 156#define TIMER_STATUS_TRUN0 0x1000
171#define TIMER_STATUS_TRUN1 0x2000 157#define TIMER_STATUS_TRUN1 0x2000
172#define TIMER_STATUS_TRUN2 0x4000 158#define TIMER_STATUS_TRUN2 0x4000
173#if (MAX_BLACKFIN_GPTIMERS > 3) 159#define TIMER_STATUS_TRUN3 0x00008000
174# define TIMER_STATUS_TRUN3 0x00008000 160#define TIMER_STATUS_TRUN4 0x10000000
175# define TIMER_STATUS_TRUN4 0x10000000 161#define TIMER_STATUS_TRUN5 0x20000000
176# define TIMER_STATUS_TRUN5 0x20000000 162#define TIMER_STATUS_TRUN6 0x40000000
177# define TIMER_STATUS_TRUN6 0x40000000 163#define TIMER_STATUS_TRUN7 0x80000000
178# define TIMER_STATUS_TRUN7 0x80000000 164#define TIMER_STATUS_TRUN 0xF000F000
179# define TIMER_STATUS_TRUN 0xF000F000 165#define TIMER_STATUS_TRUN8 0x1000
180# if (MAX_BLACKFIN_GPTIMERS > 8) 166#define TIMER_STATUS_TRUN9 0x2000
181# define TIMER_STATUS_TRUN8 0x1000 167#define TIMER_STATUS_TRUN10 0x4000
182# define TIMER_STATUS_TRUN9 0x2000 168#define TIMER_STATUS_TRUN11 0x8000
183# define TIMER_STATUS_TRUN10 0x4000
184# define TIMER_STATUS_TRUN11 0x8000
185# endif
186#else
187# define TIMER_STATUS_TRUN 0x7000
188#endif
189 169
190/* The actual gptimer API */ 170/* The actual gptimer API */
191 171
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h
index a89120445be6..735fa02fafb2 100644
--- a/include/asm-blackfin/mach-bf527/anomaly.h
+++ b/include/asm-blackfin/mach-bf527/anomaly.h
@@ -2,12 +2,12 @@
2 * File: include/asm-blackfin/mach-bf527/anomaly.h 2 * File: include/asm-blackfin/mach-bf527/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2007 Analog Devices Inc. 5 * Copyright (C) 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List 10 * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -15,35 +15,85 @@
15 15
16/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ 16/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
17#define ANOMALY_05000074 (1) 17#define ANOMALY_05000074 (1)
18/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
19#define ANOMALY_05000119 (1)
20/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 18/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
21#define ANOMALY_05000122 (1) 19#define ANOMALY_05000122 (1)
22/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ 20/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
23#define ANOMALY_05000245 (1) 21#define ANOMALY_05000245 (1)
24/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 22/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
25#define ANOMALY_05000265 (1) 23#define ANOMALY_05000265 (1)
26/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
27#define ANOMALY_05000301 (1)
28/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
29#define ANOMALY_05000312 (1)
30/* Incorrect Access of OTP_STATUS During otp_write() Function */ 24/* Incorrect Access of OTP_STATUS During otp_write() Function */
31#define ANOMALY_05000328 (1) 25#define ANOMALY_05000328 (1)
32/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ 26/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
33#define ANOMALY_05000337 (1) 27#define ANOMALY_05000337 (1)
34/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */ 28/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
29#define ANOMALY_05000341 (1)
30/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
35#define ANOMALY_05000342 (1) 31#define ANOMALY_05000342 (1)
36/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ 32/* USB Calibration Value Is Not Initialized */
33#define ANOMALY_05000346 (1)
34/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
37#define ANOMALY_05000347 (1) 35#define ANOMALY_05000347 (1)
36/* Security Features Are Not Functional */
37#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)
38/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
39#define ANOMALY_05000355 (1)
40/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
41#define ANOMALY_05000357 (1)
42/* Incorrect Revision Number in DSPID Register */
43#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)
44/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
45#define ANOMALY_05000366 (1)
46/* New Feature: Higher Default CCLK Rate */
47#define ANOMALY_05000368 (1)
48/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
49#define ANOMALY_05000371 (1)
50/* Authentication Fails To Initiate */
51#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)
52/* Data Read From L3 Memory by USB DMA May be Corrupted */
53#define ANOMALY_05000380 (1)
54/* USB Full-speed Mode not Fully Tested */
55#define ANOMALY_05000381 (1)
56/* New Feature: Boot from OTP Memory */
57#define ANOMALY_05000385 (1)
58/* New Feature: bfrom_SysControl() Routine */
59#define ANOMALY_05000386 (1)
60/* New Feature: Programmable Preboot Settings */
61#define ANOMALY_05000387 (1)
62/* Reset Vector Must Not Be in SDRAM Memory Space */
63#define ANOMALY_05000389 (1)
64/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */
65#define ANOMALY_05000392 (1)
66/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */
67#define ANOMALY_05000393 (1)
68/* New Feature: Log Buffer Functionality */
69#define ANOMALY_05000394 (1)
70/* New Feature: Hook Routine Functionality */
71#define ANOMALY_05000395 (1)
72/* New Feature: Header Indirect Bit */
73#define ANOMALY_05000396 (1)
74/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */
75#define ANOMALY_05000397 (1)
76/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */
77#define ANOMALY_05000398 (1)
78/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */
79#define ANOMALY_05000399 (1)
80/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
81#define ANOMALY_05000401 (1)
38 82
39/* Anomalies that don't exist on this proc */ 83/* Anomalies that don't exist on this proc */
40#define ANOMALY_05000323 (0)
41#define ANOMALY_05000244 (0)
42#define ANOMALY_05000198 (0)
43#define ANOMALY_05000125 (0) 84#define ANOMALY_05000125 (0)
44#define ANOMALY_05000158 (0) 85#define ANOMALY_05000158 (0)
45#define ANOMALY_05000273 (0) 86#define ANOMALY_05000183 (0)
87#define ANOMALY_05000198 (0)
88#define ANOMALY_05000230 (0)
89#define ANOMALY_05000244 (0)
90#define ANOMALY_05000261 (0)
46#define ANOMALY_05000263 (0) 91#define ANOMALY_05000263 (0)
92#define ANOMALY_05000266 (0)
93#define ANOMALY_05000273 (0)
47#define ANOMALY_05000311 (0) 94#define ANOMALY_05000311 (0)
48#define ANOMALY_05000230 (0) 95#define ANOMALY_05000312 (0)
96#define ANOMALY_05000323 (0)
97#define ANOMALY_05000363 (0)
98
49#endif 99#endif
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
index c0694ecd2ecd..f0ab2736a680 100644
--- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
@@ -1,22 +1,38 @@
1/*
2 * file: include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
1#include <linux/serial.h> 32#include <linux/serial.h>
2#include <asm/dma.h> 33#include <asm/dma.h>
3#include <asm/portmux.h> 34#include <asm/portmux.h>
4 35
5#define NR_PORTS 2
6
7#define OFFSET_THR 0x00 /* Transmit Holding register */
8#define OFFSET_RBR 0x00 /* Receive Buffer register */
9#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
10#define OFFSET_IER 0x04 /* Interrupt Enable Register */
11#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
12#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
13#define OFFSET_LCR 0x0C /* Line Control Register */
14#define OFFSET_MCR 0x10 /* Modem Control Register */
15#define OFFSET_LSR 0x14 /* Line Status Register */
16#define OFFSET_MSR 0x18 /* Modem Status Register */
17#define OFFSET_SCR 0x1C /* SCR Scratch Register */
18#define OFFSET_GCTL 0x24 /* Global Control Register */
19
20#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) 36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
21#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) 37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
22#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) 38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
@@ -92,7 +108,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
92 bfin_write16(uart->port.membase + OFFSET_LSR, -1); 108 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
93} 109}
94 110
95struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 111struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
96struct bfin_serial_res { 112struct bfin_serial_res {
97 unsigned long uart_base_addr; 113 unsigned long uart_base_addr;
98 int uart_irq; 114 int uart_irq;
diff --git a/include/asm-blackfin/mach-bf527/bfin_sir.h b/include/asm-blackfin/mach-bf527/bfin_sir.h
new file mode 100644
index 000000000000..0612d0c9501c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/bfin_sir.h
@@ -0,0 +1,133 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART0_RX,
69 CH_UART0_RX,
70 CH_UART0_TX,
71 },
72#endif
73#ifdef CONFIG_BFIN_SIR1
74 {
75 0xFFC02000,
76 IRQ_UART1_RX,
77 CH_UART1_RX,
78 CH_UART1_TX,
79 },
80#endif
81};
82
83int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
84
85struct bfin_sir_self {
86 struct bfin_sir_port *sir_port;
87 spinlock_t lock;
88 unsigned int open;
89 int speed;
90 int newspeed;
91
92 struct sk_buff *txskb;
93 struct sk_buff *rxskb;
94 struct net_device_stats stats;
95 struct device *dev;
96 struct irlap_cb *irlap;
97 struct qos_info qos;
98
99 iobuff_t tx_buff;
100 iobuff_t rx_buff;
101
102 struct work_struct work;
103 int mtt;
104};
105
106static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
107{
108 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
109 port->lsr |= (lsr & (BI|FE|PE|OE));
110 return lsr | port->lsr;
111}
112
113static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
114{
115 port->lsr = 0;
116 bfin_read16(port->membase + OFFSET_LSR);
117}
118
119#define DRIVER_NAME "bfin_sir"
120
121static void bfin_sir_hw_init(void)
122{
123#ifdef CONFIG_BFIN_SIR0
124 peripheral_request(P_UART0_TX, DRIVER_NAME);
125 peripheral_request(P_UART0_RX, DRIVER_NAME);
126#endif
127
128#ifdef CONFIG_BFIN_SIR1
129 peripheral_request(P_UART1_TX, DRIVER_NAME);
130 peripheral_request(P_UART1_RX, DRIVER_NAME);
131#endif
132 SSYNC();
133}
diff --git a/include/asm-blackfin/mach-bf527/blackfin.h b/include/asm-blackfin/mach-bf527/blackfin.h
index 1bd07e30781c..2891727b6176 100644
--- a/include/asm-blackfin/mach-bf527/blackfin.h
+++ b/include/asm-blackfin/mach-bf527/blackfin.h
@@ -64,6 +64,21 @@
64#define STATUS_P1 0x02 64#define STATUS_P1 0x02
65#define STATUS_P0 0x01 65#define STATUS_P0 0x01
66 66
67#define BFIN_UART_NR_PORTS 2
68
69#define OFFSET_THR 0x00 /* Transmit Holding register */
70#define OFFSET_RBR 0x00 /* Receive Buffer register */
71#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
72#define OFFSET_IER 0x04 /* Interrupt Enable Register */
73#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
74#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
75#define OFFSET_LCR 0x0C /* Line Control Register */
76#define OFFSET_MCR 0x10 /* Modem Control Register */
77#define OFFSET_LSR 0x14 /* Line Status Register */
78#define OFFSET_MSR 0x18 /* Modem Status Register */
79#define OFFSET_SCR 0x1C /* SCR Scratch Register */
80#define OFFSET_GCTL 0x24 /* Global Control Register */
81
67/* DPMC*/ 82/* DPMC*/
68#define bfin_read_STOPCK_OFF() bfin_read_STOPCK() 83#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
69#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) 84#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
index 3f4de5d9d4cb..9dbdbec8ea1b 100644
--- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
+++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
@@ -29,18 +29,71 @@
29 */ 29 */
30 30
31#ifndef _CDEF_BF52X_H 31#ifndef _CDEF_BF52X_H
32#define _CDEF_BF52X_H
33
34#include <asm/system.h>
35#include <asm/blackfin.h>
32 36
33#include "defBF52x_base.h" 37#include "defBF52x_base.h"
34 38
39/* Include core specific register pointer definitions */
40#include <asm/mach-common/cdef_LPBlackfin.h>
41
35/* ==== begin from cdefBF534.h ==== */ 42/* ==== begin from cdefBF534.h ==== */
36 43
37/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 44/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
38#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
39#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) 46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 /* Only allow PPL Wakeup) */
59 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
60 bfin_write32(SIC_IWR1, 0);
61
62 bfin_write16(PLL_CTL, val);
63 SSYNC();
64 asm("IDLE;");
65
66 bfin_write32(SIC_IWR0, iwr0);
67 bfin_write32(SIC_IWR1, iwr1);
68 local_irq_restore(flags);
69}
40#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 70#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
41#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 71#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
42#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 72#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
43#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) 73/* Writing to VR_CTL initiates a PLL relock sequence. */
74static __inline__ void bfin_write_VR_CTL(unsigned int val)
75{
76 unsigned long flags, iwr0, iwr1;
77
78 if (val == bfin_read_VR_CTL())
79 return;
80
81 local_irq_save(flags);
82 /* Enable the PLL Wakeup bit in SIC IWR */
83 iwr0 = bfin_read32(SIC_IWR0);
84 iwr1 = bfin_read32(SIC_IWR1);
85 /* Only allow PPL Wakeup) */
86 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
87 bfin_write32(SIC_IWR1, 0);
88
89 bfin_write16(VR_CTL, val);
90 SSYNC();
91 asm("IDLE;");
92
93 bfin_write32(SIC_IWR0, iwr0);
94 bfin_write32(SIC_IWR1, iwr1);
95 local_irq_restore(flags);
96}
44#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 97#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
45#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 98#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
46#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 99#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -873,39 +926,6 @@
873 926
874 927
875/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ 928/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
876#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
877#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val)
878#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
879#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val)
880#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
881#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val)
882#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
883#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
884#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
885#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
886#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
887#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
888#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
889#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
890#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
891#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
892#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
893#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val)
894#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
895#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val)
896#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
897#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val)
898#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
899#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val)
900#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
901#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val)
902#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
903#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
904#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
905#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val)
906#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
907#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
908
909 929
910/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ 930/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
911#define bfin_read_PORTGIO() bfin_read16(PORTGIO) 931#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
diff --git a/include/asm-blackfin/mach-bf527/dma.h b/include/asm-blackfin/mach-bf527/dma.h
index 2dfee12864f6..49dd693223e8 100644
--- a/include/asm-blackfin/mach-bf527/dma.h
+++ b/include/asm-blackfin/mach-bf527/dma.h
@@ -59,7 +59,4 @@
59#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */ 59#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */
60#endif 60#endif
61 61
62extern int channel2irq(unsigned int channel);
63extern struct dma_register *base_addr[];
64
65#endif 62#endif
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
index 98209d40abba..5a6dcc5fa36c 100644
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List 10 * - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -251,10 +251,18 @@
251#define ANOMALY_05000206 (__SILICON_REVISION__ < 3) 251#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
252/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 252/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
253#define ANOMALY_05000357 (1) 253#define ANOMALY_05000357 (1)
254/* UART Break Signal Issues */
255#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
254/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ 256/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
255#define ANOMALY_05000366 (1) 257#define ANOMALY_05000366 (1)
256/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 258/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
257#define ANOMALY_05000371 (1) 259#define ANOMALY_05000371 (1)
260/* PPI Does Not Start Properly In Specific Mode */
261#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
262/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
263#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
264/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
265#define ANOMALY_05000403 (1)
258 266
259/* Anomalies that don't exist on this proc */ 267/* Anomalies that don't exist on this proc */
260#define ANOMALY_05000266 (0) 268#define ANOMALY_05000266 (0)
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index b6f513bee56e..fbe88dee3e2d 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -1,22 +1,38 @@
1/*
2 * file: include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
1#include <linux/serial.h> 32#include <linux/serial.h>
2#include <asm/dma.h> 33#include <asm/dma.h>
3#include <asm/portmux.h> 34#include <asm/portmux.h>
4 35
5#define NR_PORTS 1
6
7#define OFFSET_THR 0x00 /* Transmit Holding register */
8#define OFFSET_RBR 0x00 /* Receive Buffer register */
9#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
10#define OFFSET_IER 0x04 /* Interrupt Enable Register */
11#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
12#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
13#define OFFSET_LCR 0x0C /* Line Control Register */
14#define OFFSET_MCR 0x10 /* Modem Control Register */
15#define OFFSET_LSR 0x14 /* Line Status Register */
16#define OFFSET_MSR 0x18 /* Modem Status Register */
17#define OFFSET_SCR 0x1C /* SCR Scratch Register */
18#define OFFSET_GCTL 0x24 /* Global Control Register */
19
20#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) 36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
21#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) 37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
22#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) 38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
@@ -84,7 +100,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
84 bfin_write16(uart->port.membase + OFFSET_LSR, -1); 100 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
85} 101}
86 102
87struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 103struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
88struct bfin_serial_res { 104struct bfin_serial_res {
89 unsigned long uart_base_addr; 105 unsigned long uart_base_addr;
90 int uart_irq; 106 int uart_irq;
@@ -115,7 +131,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
115 131
116#define DRIVER_NAME "bfin-uart" 132#define DRIVER_NAME "bfin-uart"
117 133
118int nr_ports = NR_PORTS; 134int nr_ports = BFIN_UART_NR_PORTS;
119static void bfin_serial_hw_init(struct bfin_serial_port *uart) 135static void bfin_serial_hw_init(struct bfin_serial_port *uart)
120{ 136{
121 137
diff --git a/include/asm-blackfin/mach-bf533/bfin_sir.h b/include/asm-blackfin/mach-bf533/bfin_sir.h
new file mode 100644
index 000000000000..cefcf8bb505b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/bfin_sir.h
@@ -0,0 +1,120 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART_RX,
69 CH_UART_RX,
70 CH_UART_TX,
71 },
72#endif
73};
74
75int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
76
77struct bfin_sir_self {
78 struct bfin_sir_port *sir_port;
79 spinlock_t lock;
80 unsigned int open;
81 int speed;
82 int newspeed;
83
84 struct sk_buff *txskb;
85 struct sk_buff *rxskb;
86 struct net_device_stats stats;
87 struct device *dev;
88 struct irlap_cb *irlap;
89 struct qos_info qos;
90
91 iobuff_t tx_buff;
92 iobuff_t rx_buff;
93
94 struct work_struct work;
95 int mtt;
96};
97
98static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
99{
100 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
101 port->lsr |= (lsr & (BI|FE|PE|OE));
102 return lsr | port->lsr;
103}
104
105static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
106{
107 port->lsr = 0;
108 bfin_read16(port->membase + OFFSET_LSR);
109}
110
111#define DRIVER_NAME "bfin_sir"
112
113static void bfin_sir_hw_init(void)
114{
115#ifdef CONFIG_BFIN_SIR0
116 peripheral_request(P_UART0_TX, DRIVER_NAME);
117 peripheral_request(P_UART0_RX, DRIVER_NAME);
118#endif
119 SSYNC();
120}
diff --git a/include/asm-blackfin/mach-bf533/blackfin.h b/include/asm-blackfin/mach-bf533/blackfin.h
index f3b240abf170..d80971b4e3aa 100644
--- a/include/asm-blackfin/mach-bf533/blackfin.h
+++ b/include/asm-blackfin/mach-bf533/blackfin.h
@@ -42,4 +42,19 @@
42#include "cdefBF532.h" 42#include "cdefBF532.h"
43#endif 43#endif
44 44
45#define BFIN_UART_NR_PORTS 1
46
47#define OFFSET_THR 0x00 /* Transmit Holding register */
48#define OFFSET_RBR 0x00 /* Receive Buffer register */
49#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
50#define OFFSET_IER 0x04 /* Interrupt Enable Register */
51#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
52#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
53#define OFFSET_LCR 0x0C /* Line Control Register */
54#define OFFSET_MCR 0x10 /* Modem Control Register */
55#define OFFSET_LSR 0x14 /* Line Status Register */
56#define OFFSET_MSR 0x18 /* Modem Status Register */
57#define OFFSET_SCR 0x1C /* SCR Scratch Register */
58#define OFFSET_GCTL 0x24 /* Global Control Register */
59
45#endif /* _MACH_BLACKFIN_H_ */ 60#endif /* _MACH_BLACKFIN_H_ */
diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h
index c803e14b529c..154655452d4c 100644
--- a/include/asm-blackfin/mach-bf533/cdefBF532.h
+++ b/include/asm-blackfin/mach-bf533/cdefBF532.h
@@ -43,7 +43,27 @@
43 43
44/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ 44/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) 46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr = bfin_read32(SIC_IWR);
57 /* Only allow PPL Wakeup) */
58 bfin_write32(SIC_IWR, IWR_ENABLE(0));
59
60 bfin_write16(PLL_CTL, val);
61 SSYNC();
62 asm("IDLE;");
63
64 bfin_write32(SIC_IWR, iwr);
65 local_irq_restore(flags);
66}
47#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 67#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
48#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 68#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
49#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 69#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -57,6 +77,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
57{ 77{
58 unsigned long flags, iwr; 78 unsigned long flags, iwr;
59 79
80 if (val == bfin_read_VR_CTL())
81 return;
82
83 local_irq_save(flags);
60 /* Enable the PLL Wakeup bit in SIC IWR */ 84 /* Enable the PLL Wakeup bit in SIC IWR */
61 iwr = bfin_read32(SIC_IWR); 85 iwr = bfin_read32(SIC_IWR);
62 /* Only allow PPL Wakeup) */ 86 /* Only allow PPL Wakeup) */
@@ -64,11 +88,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
64 88
65 bfin_write16(VR_CTL, val); 89 bfin_write16(VR_CTL, val);
66 SSYNC(); 90 SSYNC();
67
68 local_irq_save(flags);
69 asm("IDLE;"); 91 asm("IDLE;");
70 local_irq_restore(flags); 92
71 bfin_write32(SIC_IWR, iwr); 93 bfin_write32(SIC_IWR, iwr);
94 local_irq_restore(flags);
72} 95}
73 96
74/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ 97/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index 37134aaf9954..17e1548cec08 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -88,20 +88,25 @@
88#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ 88#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
89 89
90/* UART Controller (0xFFC00400 - 0xFFC004FF) */ 90/* UART Controller (0xFFC00400 - 0xFFC004FF) */
91#define UART_THR 0xFFC00400 /* Transmit Holding register */ 91
92#define UART_RBR 0xFFC00400 /* Receive Buffer register */ 92/*
93#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ 93 * Because include/linux/serial_reg.h have defined UART_*,
94#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ 94 * So we define blackfin uart regs to BFIN_UART_*.
95#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ 95 */
96#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ 96#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
97#define UART_LCR 0xFFC0040C /* Line Control Register */ 97#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
98#define UART_MCR 0xFFC00410 /* Modem Control Register */ 98#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
99#define UART_LSR 0xFFC00414 /* Line Status Register */ 99#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
100#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
101#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
102#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
103#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
104#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
100#if 0 105#if 0
101#define UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */ 106#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
102#endif 107#endif
103#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ 108#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
104#define UART_GCTL 0xFFC00424 /* Global Control Register */ 109#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
105 110
106/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ 111/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
107#define SPI0_REGBASE 0xFFC00500 112#define SPI0_REGBASE 0xFFC00500
diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h
index 16c672c01d80..bd9d5e94307d 100644
--- a/include/asm-blackfin/mach-bf533/dma.h
+++ b/include/asm-blackfin/mach-bf533/dma.h
@@ -51,7 +51,4 @@
51#define CH_MEM_STREAM1_DEST 10 /* TX */ 51#define CH_MEM_STREAM1_DEST 10 /* TX */
52#define CH_MEM_STREAM1_SRC 11 /* RX */ 52#define CH_MEM_STREAM1_SRC 11 /* RX */
53 53
54extern int channel2irq(unsigned int channel);
55extern struct dma_register *base_addr[];
56
57#endif 54#endif
diff --git a/include/asm-blackfin/mach-bf533/mem_init.h b/include/asm-blackfin/mach-bf533/mem_init.h
index 1620dae5254d..f8f31901fca9 100644
--- a/include/asm-blackfin/mach-bf533/mem_init.h
+++ b/include/asm-blackfin/mach-bf533/mem_init.h
@@ -29,7 +29,8 @@
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */ 30 */
31 31
32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD) 32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \
33 CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD)
33#if (CONFIG_SCLK_HZ > 119402985) 34#if (CONFIG_SCLK_HZ > 119402985)
34#define SDRAM_tRP TRP_2 35#define SDRAM_tRP TRP_2
35#define SDRAM_tRP_num 2 36#define SDRAM_tRP_num 2
@@ -118,6 +119,13 @@
118#define SDRAM_CL CL_3 119#define SDRAM_CL CL_3
119#endif 120#endif
120 121
122#if (CONFIG_MEM_MT48LC32M16A2TG_75)
123 /*SDRAM INFORMATION: */
124#define SDRAM_Tref 64 /* Refresh period in milliseconds */
125#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
126#define SDRAM_CL CL_3
127#endif
128
121#if (CONFIG_MEM_GENERIC_BOARD) 129#if (CONFIG_MEM_GENERIC_BOARD)
122 /*SDRAM INFORMATION: Modify this for your board */ 130 /*SDRAM INFORMATION: Modify this for your board */
123#define SDRAM_Tref 64 /* Refresh period in milliseconds */ 131#define SDRAM_Tref 64 /* Refresh period in milliseconds */
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 746a794b3119..a6b08facb242 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List 10 * - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -132,10 +132,24 @@
132#define ANOMALY_05000322 (1) 132#define ANOMALY_05000322 (1)
133/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ 133/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
134#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) 134#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
135/* New Feature: UART Remains Enabled after UART Boot (Not Available on Older Silicon) */
136#define ANOMALY_05000350 (__SILICON_REVISION__ < 3)
137/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
138#define ANOMALY_05000355 (1)
135/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 139/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
136#define ANOMALY_05000357 (1) 140#define ANOMALY_05000357 (1)
137/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ 141/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
138#define ANOMALY_05000359 (1) 142#define ANOMALY_05000359 (1)
143/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
144#define ANOMALY_05000366 (1)
145/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
146#define ANOMALY_05000371 (1)
147/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
148#define ANOMALY_05000402 (__SILICON_REVISION__ >= 3)
149/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
150#define ANOMALY_05000403 (1)
151
152
139 153
140/* Anomalies that don't exist on this proc */ 154/* Anomalies that don't exist on this proc */
141#define ANOMALY_05000125 (0) 155#define ANOMALY_05000125 (0)
@@ -146,5 +160,6 @@
146#define ANOMALY_05000266 (0) 160#define ANOMALY_05000266 (0)
147#define ANOMALY_05000311 (0) 161#define ANOMALY_05000311 (0)
148#define ANOMALY_05000323 (0) 162#define ANOMALY_05000323 (0)
163#define ANOMALY_05000363 (0)
149 164
150#endif 165#endif
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
index 8fc672d31057..fd100a415b98 100644
--- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
@@ -1,22 +1,38 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver header files
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
1#include <linux/serial.h> 32#include <linux/serial.h>
2#include <asm/dma.h> 33#include <asm/dma.h>
3#include <asm/portmux.h> 34#include <asm/portmux.h>
4 35
5#define NR_PORTS 2
6
7#define OFFSET_THR 0x00 /* Transmit Holding register */
8#define OFFSET_RBR 0x00 /* Receive Buffer register */
9#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
10#define OFFSET_IER 0x04 /* Interrupt Enable Register */
11#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
12#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
13#define OFFSET_LCR 0x0C /* Line Control Register */
14#define OFFSET_MCR 0x10 /* Modem Control Register */
15#define OFFSET_LSR 0x14 /* Line Status Register */
16#define OFFSET_MSR 0x18 /* Modem Status Register */
17#define OFFSET_SCR 0x1C /* SCR Scratch Register */
18#define OFFSET_GCTL 0x24 /* Global Control Register */
19
20#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) 36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
21#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) 37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
22#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) 38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
@@ -92,7 +108,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
92 bfin_write16(uart->port.membase + OFFSET_LSR, -1); 108 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
93} 109}
94 110
95struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 111struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
96struct bfin_serial_res { 112struct bfin_serial_res {
97 unsigned long uart_base_addr; 113 unsigned long uart_base_addr;
98 int uart_irq; 114 int uart_irq;
diff --git a/include/asm-blackfin/mach-bf537/bfin_sir.h b/include/asm-blackfin/mach-bf537/bfin_sir.h
new file mode 100644
index 000000000000..0612d0c9501c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/bfin_sir.h
@@ -0,0 +1,133 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART0_RX,
69 CH_UART0_RX,
70 CH_UART0_TX,
71 },
72#endif
73#ifdef CONFIG_BFIN_SIR1
74 {
75 0xFFC02000,
76 IRQ_UART1_RX,
77 CH_UART1_RX,
78 CH_UART1_TX,
79 },
80#endif
81};
82
83int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
84
85struct bfin_sir_self {
86 struct bfin_sir_port *sir_port;
87 spinlock_t lock;
88 unsigned int open;
89 int speed;
90 int newspeed;
91
92 struct sk_buff *txskb;
93 struct sk_buff *rxskb;
94 struct net_device_stats stats;
95 struct device *dev;
96 struct irlap_cb *irlap;
97 struct qos_info qos;
98
99 iobuff_t tx_buff;
100 iobuff_t rx_buff;
101
102 struct work_struct work;
103 int mtt;
104};
105
106static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
107{
108 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
109 port->lsr |= (lsr & (BI|FE|PE|OE));
110 return lsr | port->lsr;
111}
112
113static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
114{
115 port->lsr = 0;
116 bfin_read16(port->membase + OFFSET_LSR);
117}
118
119#define DRIVER_NAME "bfin_sir"
120
121static void bfin_sir_hw_init(void)
122{
123#ifdef CONFIG_BFIN_SIR0
124 peripheral_request(P_UART0_TX, DRIVER_NAME);
125 peripheral_request(P_UART0_RX, DRIVER_NAME);
126#endif
127
128#ifdef CONFIG_BFIN_SIR1
129 peripheral_request(P_UART1_TX, DRIVER_NAME);
130 peripheral_request(P_UART1_RX, DRIVER_NAME);
131#endif
132 SSYNC();
133}
diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h
index 53fcfa3408d0..cffc786b2a2b 100644
--- a/include/asm-blackfin/mach-bf537/blackfin.h
+++ b/include/asm-blackfin/mach-bf537/blackfin.h
@@ -82,8 +82,6 @@
82#define STATUS_P1 0x02 82#define STATUS_P1 0x02
83#define STATUS_P0 0x01 83#define STATUS_P0 0x01
84 84
85/* UART 0*/
86
87/* DMA Channnel */ 85/* DMA Channnel */
88#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX() 86#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
89#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val) 87#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
@@ -106,37 +104,52 @@
106/* MMR Registers*/ 104/* MMR Registers*/
107#define bfin_read_UART_THR() bfin_read_UART0_THR() 105#define bfin_read_UART_THR() bfin_read_UART0_THR()
108#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val) 106#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
109#define UART_THR UART0_THR 107#define BFIN_UART_THR UART0_THR
110#define bfin_read_UART_RBR() bfin_read_UART0_RBR() 108#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
111#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val) 109#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
112#define UART_RBR UART0_RBR 110#define BFIN_UART_RBR UART0_RBR
113#define bfin_read_UART_DLL() bfin_read_UART0_DLL() 111#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
114#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val) 112#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
115#define UART_DLL UART0_DLL 113#define BFIN_UART_DLL UART0_DLL
116#define bfin_read_UART_IER() bfin_read_UART0_IER() 114#define bfin_read_UART_IER() bfin_read_UART0_IER()
117#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val) 115#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
118#define UART_IER UART0_IER 116#define BFIN_UART_IER UART0_IER
119#define bfin_read_UART_DLH() bfin_read_UART0_DLH() 117#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
120#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val) 118#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
121#define UART_DLH UART0_DLH 119#define BFIN_UART_DLH UART0_DLH
122#define bfin_read_UART_IIR() bfin_read_UART0_IIR() 120#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
123#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val) 121#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
124#define UART_IIR UART0_IIR 122#define BFIN_UART_IIR UART0_IIR
125#define bfin_read_UART_LCR() bfin_read_UART0_LCR() 123#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
126#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val) 124#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
127#define UART_LCR UART0_LCR 125#define BFIN_UART_LCR UART0_LCR
128#define bfin_read_UART_MCR() bfin_read_UART0_MCR() 126#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
129#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val) 127#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
130#define UART_MCR UART0_MCR 128#define BFIN_UART_MCR UART0_MCR
131#define bfin_read_UART_LSR() bfin_read_UART0_LSR() 129#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
132#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val) 130#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
133#define UART_LSR UART0_LSR 131#define BFIN_UART_LSR UART0_LSR
134#define bfin_read_UART_SCR() bfin_read_UART0_SCR() 132#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
135#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val) 133#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
136#define UART_SCR UART0_SCR 134#define BFIN_UART_SCR UART0_SCR
137#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL() 135#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
138#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val) 136#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
139#define UART_GCTL UART0_GCTL 137#define BFIN_UART_GCTL UART0_GCTL
138
139#define BFIN_UART_NR_PORTS 2
140
141#define OFFSET_THR 0x00 /* Transmit Holding register */
142#define OFFSET_RBR 0x00 /* Receive Buffer register */
143#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
144#define OFFSET_IER 0x04 /* Interrupt Enable Register */
145#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
146#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
147#define OFFSET_LCR 0x0C /* Line Control Register */
148#define OFFSET_MCR 0x10 /* Modem Control Register */
149#define OFFSET_LSR 0x14 /* Line Status Register */
150#define OFFSET_MSR 0x18 /* Modem Status Register */
151#define OFFSET_SCR 0x1C /* SCR Scratch Register */
152#define OFFSET_GCTL 0x24 /* Global Control Register */
140 153
141/* DPMC*/ 154/* DPMC*/
142#define bfin_read_STOPCK_OFF() bfin_read_STOPCK() 155#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h
index 78227bc855df..82de526f8097 100644
--- a/include/asm-blackfin/mach-bf537/cdefBF534.h
+++ b/include/asm-blackfin/mach-bf537/cdefBF534.h
@@ -44,7 +44,27 @@
44 44
45/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 45/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
46#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 46#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
47#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) 47/* Writing to PLL_CTL initiates a PLL relock sequence. */
48static __inline__ void bfin_write_PLL_CTL(unsigned int val)
49{
50 unsigned long flags, iwr;
51
52 if (val == bfin_read_PLL_CTL())
53 return;
54
55 local_irq_save(flags);
56 /* Enable the PLL Wakeup bit in SIC IWR */
57 iwr = bfin_read32(SIC_IWR);
58 /* Only allow PPL Wakeup) */
59 bfin_write32(SIC_IWR, IWR_ENABLE(0));
60
61 bfin_write16(PLL_CTL, val);
62 SSYNC();
63 asm("IDLE;");
64
65 bfin_write32(SIC_IWR, iwr);
66 local_irq_restore(flags);
67}
48#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 68#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
49#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) 69#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
50#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 70#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
@@ -53,6 +73,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
53{ 73{
54 unsigned long flags, iwr; 74 unsigned long flags, iwr;
55 75
76 if (val == bfin_read_VR_CTL())
77 return;
78
79 local_irq_save(flags);
56 /* Enable the PLL Wakeup bit in SIC IWR */ 80 /* Enable the PLL Wakeup bit in SIC IWR */
57 iwr = bfin_read32(SIC_IWR); 81 iwr = bfin_read32(SIC_IWR);
58 /* Only allow PPL Wakeup) */ 82 /* Only allow PPL Wakeup) */
@@ -60,11 +84,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
60 84
61 bfin_write16(VR_CTL, val); 85 bfin_write16(VR_CTL, val);
62 SSYNC(); 86 SSYNC();
63
64 local_irq_save(flags);
65 asm("IDLE;"); 87 asm("IDLE;");
66 local_irq_restore(flags); 88
67 bfin_write32(SIC_IWR, iwr); 89 bfin_write32(SIC_IWR, iwr);
90 local_irq_restore(flags);
68} 91}
69#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 92#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
70#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 93#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
@@ -858,39 +881,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
858#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) 881#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
859#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) 882#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
860 883
861/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ 884/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
862#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
863#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val)
864#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
865#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL,val)
866#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
867#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL,val)
868#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
869#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT,val)
870#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
871#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR,val)
872#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
873#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL,val)
874#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
875#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT,val)
876#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
877#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR,val)
878#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
879#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT,val)
880#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
881#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK,val)
882#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
883#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL,val)
884#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
885#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT,val)
886#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
887#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8,val)
888#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
889#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16,val)
890#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
891#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8,val)
892#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
893#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16,val)
894 885
895/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ 886/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
896#define bfin_read_PORTGIO() bfin_read16(PORTGIO) 887#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
diff --git a/include/asm-blackfin/mach-bf537/dma.h b/include/asm-blackfin/mach-bf537/dma.h
index 021991984e6e..7a964040870a 100644
--- a/include/asm-blackfin/mach-bf537/dma.h
+++ b/include/asm-blackfin/mach-bf537/dma.h
@@ -52,7 +52,4 @@
52#define CH_MEM_STREAM1_DEST 14 /* TX */ 52#define CH_MEM_STREAM1_DEST 14 /* TX */
53#define CH_MEM_STREAM1_SRC 15 /* RX */ 53#define CH_MEM_STREAM1_SRC 15 /* RX */
54 54
55extern int channel2irq(unsigned int channel);
56extern struct dma_register *base_addr[];
57
58#endif 55#endif
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index 850dc12eb7f2..49d3cebc5293 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -93,5 +93,6 @@
93#define ANOMALY_05000273 (0) 93#define ANOMALY_05000273 (0)
94#define ANOMALY_05000311 (0) 94#define ANOMALY_05000311 (0)
95#define ANOMALY_05000323 (0) 95#define ANOMALY_05000323 (0)
96#define ANOMALY_05000363 (0)
96 97
97#endif 98#endif
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
index 7e6339f62a50..6547027cd3e6 100644
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -1,22 +1,38 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
1#include <linux/serial.h> 32#include <linux/serial.h>
2#include <asm/dma.h> 33#include <asm/dma.h>
3#include <asm/portmux.h> 34#include <asm/portmux.h>
4 35
5#define NR_PORTS 4
6
7#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
8#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
9#define OFFSET_GCTL 0x08 /* Global Control Register */
10#define OFFSET_LCR 0x0C /* Line Control Register */
11#define OFFSET_MCR 0x10 /* Modem Control Register */
12#define OFFSET_LSR 0x14 /* Line Status Register */
13#define OFFSET_MSR 0x18 /* Modem Status Register */
14#define OFFSET_SCR 0x1C /* SCR Scratch Register */
15#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
16#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
17#define OFFSET_THR 0x28 /* Transmit Holding register */
18#define OFFSET_RBR 0x2C /* Receive Buffer register */
19
20#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) 36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
21#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) 37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
22#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) 38#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
@@ -80,7 +96,7 @@ struct bfin_serial_port {
80#endif 96#endif
81}; 97};
82 98
83struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 99struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
84struct bfin_serial_res { 100struct bfin_serial_res {
85 unsigned long uart_base_addr; 101 unsigned long uart_base_addr;
86 int uart_irq; 102 int uart_irq;
diff --git a/include/asm-blackfin/mach-bf548/bfin_sir.h b/include/asm-blackfin/mach-bf548/bfin_sir.h
new file mode 100644
index 000000000000..5e94271c7e3b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/bfin_sir.h
@@ -0,0 +1,149 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
21#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v)
27#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
28#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
29#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v)
30#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
31#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1)
32#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
33
34#ifdef CONFIG_SIR_BFIN_DMA
35struct dma_rx_buf {
36 char *buf;
37 int head;
38 int tail;
39 };
40#endif /* CONFIG_SIR_BFIN_DMA */
41
42struct bfin_sir_port {
43 unsigned char __iomem *membase;
44 unsigned int irq;
45 unsigned int lsr;
46 unsigned long clk;
47 struct net_device *dev;
48#ifdef CONFIG_SIR_BFIN_DMA
49 int tx_done;
50 struct dma_rx_buf rx_dma_buf;
51 struct timer_list rx_dma_timer;
52 int rx_dma_nrows;
53#endif /* CONFIG_SIR_BFIN_DMA */
54 unsigned int tx_dma_channel;
55 unsigned int rx_dma_channel;
56};
57
58struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
59
60struct bfin_sir_port_res {
61 unsigned long base_addr;
62 int irq;
63 unsigned int rx_dma_channel;
64 unsigned int tx_dma_channel;
65};
66
67struct bfin_sir_port_res bfin_sir_port_resource[] = {
68#ifdef CONFIG_BFIN_SIR0
69 {
70 0xFFC00400,
71 IRQ_UART0_RX,
72 CH_UART0_RX,
73 CH_UART0_TX,
74 },
75#endif
76#ifdef CONFIG_BFIN_SIR1
77 {
78 0xFFC02000,
79 IRQ_UART1_RX,
80 CH_UART1_RX,
81 CH_UART1_TX,
82 },
83#endif
84#ifdef CONFIG_BFIN_SIR2
85 {
86 0xFFC02100,
87 IRQ_UART2_RX,
88 CH_UART2_RX,
89 CH_UART2_TX,
90 },
91#endif
92#ifdef CONFIG_BFIN_SIR3
93 {
94 0xFFC03100,
95 IRQ_UART3_RX,
96 CH_UART3_RX,
97 CH_UART3_TX,
98 },
99#endif
100};
101
102int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
103
104struct bfin_sir_self {
105 struct bfin_sir_port *sir_port;
106 spinlock_t lock;
107 unsigned int open;
108 int speed;
109 int newspeed;
110
111 struct sk_buff *txskb;
112 struct sk_buff *rxskb;
113 struct net_device_stats stats;
114 struct device *dev;
115 struct irlap_cb *irlap;
116 struct qos_info qos;
117
118 iobuff_t tx_buff;
119 iobuff_t rx_buff;
120
121 struct work_struct work;
122 int mtt;
123};
124
125#define DRIVER_NAME "bfin_sir"
126
127static void bfin_sir_hw_init(void)
128{
129#ifdef CONFIG_BFIN_SIR0
130 peripheral_request(P_UART0_TX, DRIVER_NAME);
131 peripheral_request(P_UART0_RX, DRIVER_NAME);
132#endif
133
134#ifdef CONFIG_BFIN_SIR1
135 peripheral_request(P_UART1_TX, DRIVER_NAME);
136 peripheral_request(P_UART1_RX, DRIVER_NAME);
137#endif
138
139#ifdef CONFIG_BFIN_SIR2
140 peripheral_request(P_UART2_TX, DRIVER_NAME);
141 peripheral_request(P_UART2_RX, DRIVER_NAME);
142#endif
143
144#ifdef CONFIG_BFIN_SIR3
145 peripheral_request(P_UART3_TX, DRIVER_NAME);
146 peripheral_request(P_UART3_RX, DRIVER_NAME);
147#endif
148 SSYNC();
149}
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h
index 3bd67da86053..d6ee74ac0460 100644
--- a/include/asm-blackfin/mach-bf548/blackfin.h
+++ b/include/asm-blackfin/mach-bf548/blackfin.h
@@ -153,17 +153,33 @@
153#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) 153#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
154#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() 154#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
155#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) 155#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
156#define UART_THR UART1_THR 156
157#define UART_RBR UART1_RBR 157#define BFIN_UART_THR UART1_THR
158#define UART_DLL UART1_DLL 158#define BFIN_UART_RBR UART1_RBR
159#define UART_IER UART1_IER 159#define BFIN_UART_DLL UART1_DLL
160#define UART_DLH UART1_DLH 160#define BFIN_UART_IER UART1_IER
161#define UART_IIR UART1_IIR 161#define BFIN_UART_DLH UART1_DLH
162#define UART_LCR UART1_LCR 162#define BFIN_UART_IIR UART1_IIR
163#define UART_MCR UART1_MCR 163#define BFIN_UART_LCR UART1_LCR
164#define UART_LSR UART1_LSR 164#define BFIN_UART_MCR UART1_MCR
165#define UART_SCR UART1_SCR 165#define BFIN_UART_LSR UART1_LSR
166#define UART_GCTL UART1_GCTL 166#define BFIN_UART_SCR UART1_SCR
167#define BFIN_UART_GCTL UART1_GCTL
168
169#define BFIN_UART_NR_PORTS 4
170
171#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
172#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
173#define OFFSET_GCTL 0x08 /* Global Control Register */
174#define OFFSET_LCR 0x0C /* Line Control Register */
175#define OFFSET_MCR 0x10 /* Modem Control Register */
176#define OFFSET_LSR 0x14 /* Line Status Register */
177#define OFFSET_MSR 0x18 /* Modem Status Register */
178#define OFFSET_SCR 0x1C /* SCR Scratch Register */
179#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
180#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
181#define OFFSET_THR 0x28 /* Transmit Holding register */
182#define OFFSET_RBR 0x2C /* Receive Buffer register */
167 183
168/* PLL_DIV Masks */ 184/* PLL_DIV Masks */
169#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ 185#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF542.h b/include/asm-blackfin/mach-bf548/cdefBF542.h
index 308b33ab5311..60b9f77576f1 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF542.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF542.h
@@ -123,12 +123,12 @@
123#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) 123#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
124#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) 124#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
125#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) 125#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
126#define bfin_read_SDH_DATA_CNT() fin_read16(SDH_DATA_CNT) 126#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
127#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) 127#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
128#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) 128#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
129#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) 129#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
130#define bfin_read_SDH_STATUS_CLR() fin_read16(SDH_STATUS_CLR) 130#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
131#define bfin_write_SDH_STATUS_CLR(val) fin_write16(SDH_STATUS_CLR, val) 131#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
132#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) 132#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
133#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) 133#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
134#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) 134#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
@@ -184,8 +184,8 @@
184#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) 184#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
185#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) 185#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
186#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) 186#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
187#define bfin_read_USB_TESTMODE() fin_read16(USB_TESTMODE) 187#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
188#define bfin_write_USB_TESTMODE(val) fin_write16(USB_TESTMODE, val) 188#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
189#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) 189#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
190#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) 190#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
191#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) 191#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
@@ -244,7 +244,7 @@
244#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) 244#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
245#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) 245#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
246#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) 246#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
247#define bfin_write_USB_OTG_VBUS_IRQ(val) fin_write16(USB_OTG_VBUS_IRQ, val) 247#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
248#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) 248#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
249#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) 249#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
250 250
diff --git a/include/asm-blackfin/mach-bf548/cdefBF544.h b/include/asm-blackfin/mach-bf548/cdefBF544.h
index 7a2d177c8dc2..ea9b4ab496f3 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF544.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF544.h
@@ -113,39 +113,6 @@
113 113
114/* Two Wire Interface Registers (TWI1) */ 114/* Two Wire Interface Registers (TWI1) */
115 115
116#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
117#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
118#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
119#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
120#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
121#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
122#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
123#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
124#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
125#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
126#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
127#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
128#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
129#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
130#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
131#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
132#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
133#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
134#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
135#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
136#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
137#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
138#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
139#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
140#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
141#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
142#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
143#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
144#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
145#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
146#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
147#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
148
149/* CAN Controller 1 Config 1 Registers */ 116/* CAN Controller 1 Config 1 Registers */
150 117
151#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) 118#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
diff --git a/include/asm-blackfin/mach-bf548/cdefBF547.h b/include/asm-blackfin/mach-bf548/cdefBF547.h
index d0a200b08abd..ba716277c00d 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF547.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF547.h
@@ -185,39 +185,6 @@
185 185
186/* Two Wire Interface Registers (TWI1) */ 186/* Two Wire Interface Registers (TWI1) */
187 187
188#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
189#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
190#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
191#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
192#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
193#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
194#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
195#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
196#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
197#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
198#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
199#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
200#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
201#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
202#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
203#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
204#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
205#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
206#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
207#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
208#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
209#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
210#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
211#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
212#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
213#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
214#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
215#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
216#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
217#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
218#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
219#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
220
221/* SPI2 Registers */ 188/* SPI2 Registers */
222 189
223#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) 190#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
diff --git a/include/asm-blackfin/mach-bf548/cdefBF548.h b/include/asm-blackfin/mach-bf548/cdefBF548.h
index 674be0216bff..ae971ebff6a0 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF548.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF548.h
@@ -185,39 +185,6 @@
185 185
186/* Two Wire Interface Registers (TWI1) */ 186/* Two Wire Interface Registers (TWI1) */
187 187
188#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
189#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
190#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
191#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
192#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
193#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
194#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
195#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
196#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
197#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
198#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
199#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
200#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
201#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
202#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
203#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
204#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
205#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
206#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
207#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
208#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
209#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
210#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
211#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
212#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
213#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
214#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
215#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
216#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
217#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
218#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
219#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
220
221/* SPI2 Registers */ 188/* SPI2 Registers */
222 189
223#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) 190#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
diff --git a/include/asm-blackfin/mach-bf548/cdefBF549.h b/include/asm-blackfin/mach-bf548/cdefBF549.h
index 2ab5b7c00820..92d07d961999 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF549.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF549.h
@@ -185,39 +185,6 @@
185 185
186/* Two Wire Interface Registers (TWI1) */ 186/* Two Wire Interface Registers (TWI1) */
187 187
188#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
189#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
190#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
191#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
192#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
193#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
194#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
195#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
196#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
197#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
198#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
199#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
200#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
201#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
202#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
203#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
204#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
205#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
206#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
207#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
208#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
209#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
210#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
211#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
212#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
213#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
214#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
215#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
216#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
217#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
218#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
219#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
220
221/* SPI2 Registers */ 188/* SPI2 Registers */
222 189
223#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) 190#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
@@ -1773,7 +1740,7 @@
1773#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) 1740#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
1774#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) 1741#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
1775#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) 1742#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
1776#define bfin_write_USB_DMA5COUNTLOW(val) fin_write16(USB_DMA5COUNTLOW, val) 1743#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
1777#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) 1744#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
1778#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) 1745#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
1779 1746
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index 19ddcd83c71f..57ac8cb9b1f6 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -43,7 +43,33 @@
43/* PLL Registers */ 43/* PLL Registers */
44 44
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) 46/* Writing to PLL_CTL initiates a PLL relock sequence. */
47static __inline__ void bfin_write_PLL_CTL(unsigned int val)
48{
49 unsigned long flags, iwr0, iwr1, iwr2;
50
51 if (val == bfin_read_PLL_CTL())
52 return;
53
54 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 iwr2 = bfin_read32(SIC_IWR2);
59 /* Only allow PPL Wakeup) */
60 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
61 bfin_write32(SIC_IWR1, 0);
62 bfin_write32(SIC_IWR2, 0);
63
64 bfin_write16(PLL_CTL, val);
65 SSYNC();
66 asm("IDLE;");
67
68 bfin_write32(SIC_IWR0, iwr0);
69 bfin_write32(SIC_IWR1, iwr1);
70 bfin_write32(SIC_IWR2, iwr2);
71 local_irq_restore(flags);
72}
47#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 73#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
48#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 74#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
49#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 75#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
@@ -52,6 +78,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
52{ 78{
53 unsigned long flags, iwr0, iwr1, iwr2; 79 unsigned long flags, iwr0, iwr1, iwr2;
54 80
81 if (val == bfin_read_VR_CTL())
82 return;
83
84 local_irq_save(flags);
55 /* Enable the PLL Wakeup bit in SIC IWR */ 85 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0); 86 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1); 87 iwr1 = bfin_read32(SIC_IWR1);
@@ -63,13 +93,12 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
63 93
64 bfin_write16(VR_CTL, val); 94 bfin_write16(VR_CTL, val);
65 SSYNC(); 95 SSYNC();
66
67 local_irq_save(flags);
68 asm("IDLE;"); 96 asm("IDLE;");
69 local_irq_restore(flags); 97
70 bfin_write32(SIC_IWR0, iwr0); 98 bfin_write32(SIC_IWR0, iwr0);
71 bfin_write32(SIC_IWR1, iwr1); 99 bfin_write32(SIC_IWR1, iwr1);
72 bfin_write32(SIC_IWR2, iwr2); 100 bfin_write32(SIC_IWR2, iwr2);
101 local_irq_restore(flags);
73} 102}
74#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 103#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
75#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 104#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
@@ -211,39 +240,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
211 240
212/* Two Wire Interface Registers (TWI0) */ 241/* Two Wire Interface Registers (TWI0) */
213 242
214#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
215#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
216#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
217#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
218#define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
219#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
220#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
221#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
222#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
223#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
224#define bfin_read_TWI0_MASTER_CTRL() bfin_read16(TWI0_MASTER_CTRL)
225#define bfin_write_TWI0_MASTER_CTRL(val) bfin_write16(TWI0_MASTER_CTRL, val)
226#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
227#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
228#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
229#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
230#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
231#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
232#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
233#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
234#define bfin_read_TWI0_FIFO_CTRL() bfin_read16(TWI0_FIFO_CTRL)
235#define bfin_write_TWI0_FIFO_CTRL(val) bfin_write16(TWI0_FIFO_CTRL, val)
236#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
237#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
238#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
239#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
240#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
241#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
242#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
243#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
244#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
245#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
246
247/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ 243/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
248 244
249/* SPORT1 Registers */ 245/* SPORT1 Registers */
@@ -323,7 +319,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
323#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) 319#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
324#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) 320#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
325#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD) 321#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD)
326#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD) 322#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val)
327#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) 323#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
328#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) 324#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
329#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) 325#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
@@ -392,23 +388,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
392/* DMA Channel 0 Registers */ 388/* DMA Channel 0 Registers */
393 389
394#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) 390#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
395#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR) 391#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
396#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) 392#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
397#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR) 393#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
398#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) 394#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
399#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) 395#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
400#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) 396#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
401#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) 397#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
402#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) 398#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
403#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY) 399#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
404#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) 400#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
405#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) 401#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
406#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) 402#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
407#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY) 403#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
408#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) 404#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
409#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR) 405#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
410#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) 406#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
411#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR) 407#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
412#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) 408#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
413#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) 409#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
414#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) 410#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
@@ -421,23 +417,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
421/* DMA Channel 1 Registers */ 417/* DMA Channel 1 Registers */
422 418
423#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) 419#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
424#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR) 420#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
425#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) 421#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
426#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR) 422#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
427#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) 423#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
428#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) 424#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
429#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) 425#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
430#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) 426#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
431#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) 427#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
432#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY) 428#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
433#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) 429#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
434#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) 430#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
435#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) 431#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
436#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY) 432#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
437#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) 433#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
438#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR) 434#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
439#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) 435#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
440#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR) 436#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
441#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) 437#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
442#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) 438#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
443#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) 439#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
@@ -450,23 +446,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
450/* DMA Channel 2 Registers */ 446/* DMA Channel 2 Registers */
451 447
452#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) 448#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
453#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR) 449#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
454#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) 450#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
455#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR) 451#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
456#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) 452#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
457#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) 453#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
458#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) 454#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
459#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) 455#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
460#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) 456#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
461#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY) 457#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
462#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) 458#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
463#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) 459#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
464#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) 460#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
465#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY) 461#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
466#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) 462#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
467#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR) 463#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
468#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) 464#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
469#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR) 465#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
470#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) 466#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
471#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) 467#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
472#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) 468#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
@@ -479,23 +475,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
479/* DMA Channel 3 Registers */ 475/* DMA Channel 3 Registers */
480 476
481#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) 477#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
482#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR) 478#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
483#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) 479#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
484#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR) 480#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
485#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) 481#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
486#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) 482#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
487#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) 483#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
488#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) 484#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
489#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) 485#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
490#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY) 486#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
491#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) 487#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
492#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) 488#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
493#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) 489#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
494#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY) 490#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
495#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) 491#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
496#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR) 492#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
497#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) 493#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
498#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR) 494#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
499#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) 495#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
500#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) 496#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
501#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) 497#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
@@ -508,23 +504,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
508/* DMA Channel 4 Registers */ 504/* DMA Channel 4 Registers */
509 505
510#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) 506#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
511#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR) 507#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
512#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) 508#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
513#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR) 509#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
514#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) 510#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
515#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) 511#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
516#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) 512#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
517#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) 513#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
518#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) 514#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
519#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY) 515#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
520#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) 516#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
521#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) 517#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
522#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) 518#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
523#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY) 519#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
524#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) 520#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
525#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR) 521#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
526#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) 522#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
527#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR) 523#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
528#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) 524#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
529#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) 525#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
530#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) 526#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
@@ -537,23 +533,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
537/* DMA Channel 5 Registers */ 533/* DMA Channel 5 Registers */
538 534
539#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) 535#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
540#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR) 536#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
541#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) 537#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
542#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR) 538#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
543#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) 539#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
544#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) 540#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
545#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) 541#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
546#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) 542#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
547#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) 543#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
548#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY) 544#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
549#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 545#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
550#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) 546#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
551#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) 547#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
552#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY) 548#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
553#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) 549#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
554#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR) 550#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
555#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) 551#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
556#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR) 552#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
557#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) 553#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
558#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) 554#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
559#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) 555#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
@@ -566,23 +562,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
566/* DMA Channel 6 Registers */ 562/* DMA Channel 6 Registers */
567 563
568#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) 564#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
569#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR) 565#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
570#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) 566#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
571#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR) 567#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
572#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) 568#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
573#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) 569#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
574#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) 570#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
575#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) 571#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
576#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) 572#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
577#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY) 573#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
578#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) 574#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
579#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) 575#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
580#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) 576#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
581#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY) 577#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
582#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) 578#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
583#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR) 579#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
584#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) 580#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
585#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR) 581#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
586#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) 582#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
587#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) 583#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
588#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) 584#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
@@ -595,23 +591,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
595/* DMA Channel 7 Registers */ 591/* DMA Channel 7 Registers */
596 592
597#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) 593#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
598#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR) 594#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
599#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) 595#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
600#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR) 596#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
601#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) 597#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
602#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) 598#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
603#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) 599#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
604#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) 600#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
605#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) 601#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
606#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY) 602#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
607#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) 603#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
608#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) 604#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
609#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) 605#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
610#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY) 606#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
611#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) 607#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
612#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR) 608#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
613#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) 609#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
614#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR) 610#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
615#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) 611#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
616#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) 612#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
617#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) 613#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
@@ -624,23 +620,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
624/* DMA Channel 8 Registers */ 620/* DMA Channel 8 Registers */
625 621
626#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) 622#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
627#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR) 623#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
628#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) 624#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
629#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR) 625#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
630#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) 626#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
631#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) 627#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
632#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) 628#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
633#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) 629#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
634#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) 630#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
635#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY) 631#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
636#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) 632#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
637#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) 633#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
638#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) 634#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
639#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY) 635#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
640#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) 636#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
641#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR) 637#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
642#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) 638#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
643#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR) 639#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
644#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) 640#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
645#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) 641#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
646#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) 642#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
@@ -653,23 +649,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
653/* DMA Channel 9 Registers */ 649/* DMA Channel 9 Registers */
654 650
655#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) 651#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
656#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR) 652#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
657#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) 653#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
658#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR) 654#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
659#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) 655#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
660#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) 656#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
661#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) 657#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
662#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) 658#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
663#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) 659#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
664#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY) 660#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
665#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) 661#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
666#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) 662#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
667#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) 663#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
668#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY) 664#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
669#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) 665#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
670#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR) 666#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
671#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) 667#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
672#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR) 668#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
673#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) 669#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
674#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) 670#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
675#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) 671#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
@@ -682,23 +678,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
682/* DMA Channel 10 Registers */ 678/* DMA Channel 10 Registers */
683 679
684#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) 680#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
685#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR) 681#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
686#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) 682#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
687#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR) 683#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
688#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) 684#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
689#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) 685#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
690#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) 686#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
691#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) 687#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
692#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) 688#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
693#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY) 689#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
694#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) 690#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
695#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) 691#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
696#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) 692#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
697#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY) 693#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
698#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) 694#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
699#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR) 695#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
700#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) 696#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
701#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR) 697#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
702#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) 698#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
703#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) 699#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
704#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) 700#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
@@ -711,23 +707,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
711/* DMA Channel 11 Registers */ 707/* DMA Channel 11 Registers */
712 708
713#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) 709#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
714#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR) 710#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
715#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) 711#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
716#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR) 712#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
717#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) 713#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
718#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) 714#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
719#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) 715#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
720#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) 716#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
721#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) 717#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
722#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY) 718#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
723#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) 719#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
724#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) 720#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
725#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) 721#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
726#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY) 722#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
727#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) 723#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
728#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR) 724#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
729#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) 725#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
730#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR) 726#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
731#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) 727#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
732#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) 728#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
733#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) 729#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
@@ -740,7 +736,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
740/* MDMA Stream 0 Registers */ 736/* MDMA Stream 0 Registers */
741 737
742#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) 738#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
743#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR) 739#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
744#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) 740#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
745#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) 741#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
746#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) 742#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
@@ -803,11 +799,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
803#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) 799#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
804#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) 800#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
805#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) 801#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
806#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY) 802#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
807#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) 803#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
808#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) 804#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
809#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) 805#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
810#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY) 806#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
811#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) 807#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
812#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) 808#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
813#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) 809#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
@@ -829,11 +825,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
829#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) 825#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
830#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) 826#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
831#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) 827#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
832#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY) 828#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
833#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) 829#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
834#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) 830#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
835#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) 831#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
836#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY) 832#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
837#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) 833#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
838#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) 834#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
839#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) 835#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
@@ -1246,23 +1242,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1246/* DMA Channel 12 Registers */ 1242/* DMA Channel 12 Registers */
1247 1243
1248#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR) 1244#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
1249#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR) 1245#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
1250#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR) 1246#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
1251#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR) 1247#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
1252#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) 1248#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
1253#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) 1249#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
1254#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) 1250#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
1255#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) 1251#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
1256#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) 1252#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
1257#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY) 1253#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
1258#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) 1254#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
1259#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) 1255#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
1260#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) 1256#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
1261#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY) 1257#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
1262#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR) 1258#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
1263#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR) 1259#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
1264#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR) 1260#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
1265#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR) 1261#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
1266#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) 1262#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
1267#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) 1263#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
1268#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) 1264#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
@@ -1275,23 +1271,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1275/* DMA Channel 13 Registers */ 1271/* DMA Channel 13 Registers */
1276 1272
1277#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR) 1273#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
1278#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR) 1274#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
1279#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR) 1275#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
1280#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR) 1276#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
1281#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) 1277#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
1282#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) 1278#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
1283#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) 1279#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
1284#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) 1280#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
1285#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) 1281#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
1286#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY) 1282#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
1287#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) 1283#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
1288#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) 1284#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
1289#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) 1285#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
1290#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY) 1286#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
1291#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR) 1287#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
1292#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR) 1288#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
1293#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR) 1289#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
1294#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR) 1290#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
1295#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) 1291#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
1296#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) 1292#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
1297#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) 1293#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
@@ -1304,23 +1300,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1304/* DMA Channel 14 Registers */ 1300/* DMA Channel 14 Registers */
1305 1301
1306#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR) 1302#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
1307#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR) 1303#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
1308#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR) 1304#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
1309#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR) 1305#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
1310#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) 1306#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
1311#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) 1307#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
1312#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) 1308#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
1313#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) 1309#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
1314#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) 1310#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
1315#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY) 1311#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
1316#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) 1312#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
1317#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) 1313#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
1318#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) 1314#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
1319#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY) 1315#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
1320#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR) 1316#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
1321#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR) 1317#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
1322#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR) 1318#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
1323#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR) 1319#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
1324#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) 1320#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
1325#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) 1321#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
1326#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) 1322#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
@@ -1333,23 +1329,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1333/* DMA Channel 15 Registers */ 1329/* DMA Channel 15 Registers */
1334 1330
1335#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR) 1331#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
1336#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR) 1332#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
1337#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR) 1333#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
1338#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR) 1334#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
1339#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) 1335#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
1340#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) 1336#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
1341#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) 1337#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
1342#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) 1338#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
1343#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) 1339#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
1344#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY) 1340#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
1345#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) 1341#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
1346#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) 1342#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
1347#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) 1343#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
1348#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY) 1344#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
1349#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR) 1345#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
1350#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR) 1346#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
1351#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR) 1347#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
1352#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR) 1348#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
1353#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) 1349#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
1354#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) 1350#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
1355#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) 1351#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
@@ -1362,23 +1358,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1362/* DMA Channel 16 Registers */ 1358/* DMA Channel 16 Registers */
1363 1359
1364#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR) 1360#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
1365#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR) 1361#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
1366#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR) 1362#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
1367#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR) 1363#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
1368#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) 1364#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
1369#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) 1365#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
1370#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) 1366#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
1371#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) 1367#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
1372#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) 1368#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
1373#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY) 1369#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
1374#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) 1370#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
1375#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) 1371#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
1376#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) 1372#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
1377#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY) 1373#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
1378#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR) 1374#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
1379#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR) 1375#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
1380#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR) 1376#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
1381#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR) 1377#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
1382#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) 1378#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
1383#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) 1379#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
1384#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) 1380#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
@@ -1391,23 +1387,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1391/* DMA Channel 17 Registers */ 1387/* DMA Channel 17 Registers */
1392 1388
1393#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR) 1389#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
1394#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR) 1390#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
1395#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR) 1391#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
1396#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR) 1392#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
1397#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) 1393#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
1398#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) 1394#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
1399#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) 1395#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
1400#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) 1396#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
1401#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) 1397#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
1402#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY) 1398#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
1403#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) 1399#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
1404#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) 1400#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
1405#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) 1401#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
1406#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY) 1402#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
1407#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR) 1403#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
1408#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR) 1404#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
1409#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR) 1405#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
1410#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR) 1406#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
1411#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) 1407#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
1412#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) 1408#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
1413#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) 1409#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
@@ -1420,23 +1416,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1420/* DMA Channel 18 Registers */ 1416/* DMA Channel 18 Registers */
1421 1417
1422#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR) 1418#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
1423#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR) 1419#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
1424#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR) 1420#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
1425#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR) 1421#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
1426#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) 1422#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
1427#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) 1423#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
1428#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) 1424#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
1429#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) 1425#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
1430#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) 1426#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
1431#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY) 1427#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
1432#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) 1428#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
1433#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) 1429#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
1434#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) 1430#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
1435#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY) 1431#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
1436#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR) 1432#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
1437#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR) 1433#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
1438#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR) 1434#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
1439#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR) 1435#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
1440#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) 1436#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
1441#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) 1437#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
1442#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) 1438#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
@@ -1449,23 +1445,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1449/* DMA Channel 19 Registers */ 1445/* DMA Channel 19 Registers */
1450 1446
1451#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR) 1447#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
1452#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR) 1448#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
1453#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR) 1449#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
1454#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR) 1450#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
1455#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) 1451#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
1456#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) 1452#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
1457#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) 1453#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
1458#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) 1454#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
1459#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) 1455#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
1460#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY) 1456#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
1461#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) 1457#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
1462#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) 1458#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
1463#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) 1459#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
1464#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY) 1460#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
1465#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR) 1461#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
1466#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR) 1462#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
1467#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR) 1463#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
1468#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR) 1464#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
1469#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) 1465#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
1470#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) 1466#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
1471#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) 1467#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
@@ -1478,23 +1474,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1478/* DMA Channel 20 Registers */ 1474/* DMA Channel 20 Registers */
1479 1475
1480#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR) 1476#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
1481#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR) 1477#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
1482#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR) 1478#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
1483#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR) 1479#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
1484#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) 1480#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
1485#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) 1481#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
1486#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) 1482#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
1487#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) 1483#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
1488#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) 1484#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
1489#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY) 1485#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
1490#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) 1486#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
1491#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) 1487#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
1492#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) 1488#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
1493#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY) 1489#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
1494#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR) 1490#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
1495#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR) 1491#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
1496#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR) 1492#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
1497#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR) 1493#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
1498#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) 1494#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
1499#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) 1495#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
1500#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) 1496#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
@@ -1507,23 +1503,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1507/* DMA Channel 21 Registers */ 1503/* DMA Channel 21 Registers */
1508 1504
1509#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR) 1505#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR)
1510#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR) 1506#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val)
1511#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR) 1507#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR)
1512#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR) 1508#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val)
1513#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) 1509#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
1514#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) 1510#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
1515#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) 1511#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
1516#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) 1512#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
1517#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) 1513#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
1518#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY) 1514#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
1519#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) 1515#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
1520#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) 1516#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
1521#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) 1517#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
1522#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY) 1518#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
1523#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR) 1519#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR)
1524#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR) 1520#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val)
1525#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR) 1521#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR)
1526#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR) 1522#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val)
1527#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) 1523#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
1528#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) 1524#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
1529#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) 1525#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
@@ -1536,23 +1532,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1536/* DMA Channel 22 Registers */ 1532/* DMA Channel 22 Registers */
1537 1533
1538#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR) 1534#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR)
1539#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR) 1535#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val)
1540#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR) 1536#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR)
1541#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR) 1537#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val)
1542#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) 1538#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
1543#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) 1539#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
1544#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) 1540#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
1545#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) 1541#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
1546#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) 1542#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
1547#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY) 1543#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
1548#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) 1544#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
1549#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) 1545#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
1550#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) 1546#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
1551#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY) 1547#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
1552#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR) 1548#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR)
1553#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR) 1549#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val)
1554#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR) 1550#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR)
1555#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR) 1551#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val)
1556#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) 1552#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
1557#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) 1553#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
1558#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) 1554#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
@@ -1565,23 +1561,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1565/* DMA Channel 23 Registers */ 1561/* DMA Channel 23 Registers */
1566 1562
1567#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR) 1563#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR)
1568#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR) 1564#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val)
1569#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR) 1565#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR)
1570#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR) 1566#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val)
1571#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) 1567#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
1572#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) 1568#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
1573#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) 1569#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
1574#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) 1570#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
1575#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) 1571#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
1576#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY) 1572#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
1577#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) 1573#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
1578#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) 1574#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
1579#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) 1575#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
1580#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY) 1576#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
1581#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR) 1577#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR)
1582#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR) 1578#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val)
1583#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR) 1579#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR)
1584#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR) 1580#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val)
1585#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) 1581#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
1586#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) 1582#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
1587#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) 1583#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
@@ -1594,23 +1590,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1594/* MDMA Stream 2 Registers */ 1590/* MDMA Stream 2 Registers */
1595 1591
1596#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR) 1592#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
1597#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR) 1593#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val)
1598#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR) 1594#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
1599#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR) 1595#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val)
1600#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) 1596#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
1601#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) 1597#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
1602#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) 1598#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
1603#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) 1599#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
1604#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) 1600#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
1605#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY) 1601#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
1606#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) 1602#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
1607#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) 1603#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
1608#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) 1604#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
1609#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY) 1605#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
1610#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR) 1606#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
1611#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR) 1607#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val)
1612#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR) 1608#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
1613#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR) 1609#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val)
1614#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) 1610#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
1615#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) 1611#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
1616#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) 1612#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
@@ -1620,23 +1616,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1620#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) 1616#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
1621#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) 1617#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
1622#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR) 1618#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
1623#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR) 1619#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val)
1624#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR) 1620#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
1625#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR) 1621#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val)
1626#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) 1622#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
1627#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) 1623#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
1628#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) 1624#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
1629#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) 1625#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
1630#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) 1626#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
1631#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY) 1627#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
1632#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) 1628#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
1633#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) 1629#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
1634#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) 1630#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
1635#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY) 1631#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
1636#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR) 1632#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
1637#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR) 1633#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val)
1638#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR) 1634#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
1639#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR) 1635#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val)
1640#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) 1636#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
1641#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) 1637#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
1642#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) 1638#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
@@ -1649,23 +1645,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1649/* MDMA Stream 3 Registers */ 1645/* MDMA Stream 3 Registers */
1650 1646
1651#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR) 1647#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
1652#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR) 1648#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val)
1653#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR) 1649#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
1654#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR) 1650#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val)
1655#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) 1651#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
1656#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) 1652#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
1657#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) 1653#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
1658#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) 1654#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
1659#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) 1655#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
1660#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY) 1656#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
1661#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) 1657#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
1662#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) 1658#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
1663#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) 1659#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
1664#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY) 1660#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
1665#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR) 1661#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
1666#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR) 1662#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val)
1667#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR) 1663#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
1668#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR) 1664#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val)
1669#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) 1665#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
1670#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) 1666#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
1671#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) 1667#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
@@ -1675,23 +1671,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1675#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) 1671#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
1676#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) 1672#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
1677#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR) 1673#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
1678#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR) 1674#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val)
1679#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR) 1675#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
1680#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR) 1676#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val)
1681#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) 1677#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
1682#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) 1678#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
1683#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) 1679#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
1684#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) 1680#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
1685#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) 1681#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
1686#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY) 1682#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
1687#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) 1683#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
1688#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) 1684#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
1689#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) 1685#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
1690#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY) 1686#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
1691#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR) 1687#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
1692#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR) 1688#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val)
1693#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR) 1689#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
1694#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR) 1690#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val)
1695#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) 1691#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
1696#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) 1692#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
1697#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) 1693#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h
index 46ff31f20ae5..36a2ef7e7849 100644
--- a/include/asm-blackfin/mach-bf548/dma.h
+++ b/include/asm-blackfin/mach-bf548/dma.h
@@ -73,6 +73,4 @@
73 73
74#define MAX_BLACKFIN_DMA_CHANNEL 32 74#define MAX_BLACKFIN_DMA_CHANNEL 32
75 75
76extern int channel2irq(unsigned int channel);
77extern struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL];
78#endif 76#endif
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
index befc2903d5a5..ab0b863eee66 100644
--- a/include/asm-blackfin/mach-bf548/mem_init.h
+++ b/include/asm-blackfin/mach-bf548/mem_init.h
@@ -29,16 +29,19 @@
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */ 30 */
31#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1) 31#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
32#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
33#define DDR_CLK_HZ(x) (1000*1000*1000/x)
32 34
33#if (CONFIG_MEM_MT46V32M16_6T) 35#if (CONFIG_MEM_MT46V32M16_6T)
34#define DDR_SIZE DEVSZ_512 36#define DDR_SIZE DEVSZ_512
35#define DDR_WIDTH DEVWD_16 37#define DDR_WIDTH DEVWD_16
38#define DDR_MAX_tCK 13
36 39
37#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60)) 40#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
38#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42)) 41#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
39#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) 42#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
40#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72)) 43#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
41#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800)) 44#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
42 45
43#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) 46#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
44#define DDR_tWTR DDR_TWTR(1) 47#define DDR_tWTR DDR_TWTR(1)
@@ -49,12 +52,13 @@
49#if (CONFIG_MEM_MT46V32M16_5B) 52#if (CONFIG_MEM_MT46V32M16_5B)
50#define DDR_SIZE DEVSZ_512 53#define DDR_SIZE DEVSZ_512
51#define DDR_WIDTH DEVWD_16 54#define DDR_WIDTH DEVWD_16
55#define DDR_MAX_tCK 13
52 56
53#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55)) 57#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
54#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40)) 58#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
55#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) 59#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
56#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70)) 60#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
57#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800)) 61#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
58 62
59#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) 63#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
60#define DDR_tWTR DDR_TWTR(2) 64#define DDR_tWTR DDR_TWTR(2)
@@ -65,6 +69,7 @@
65#if (CONFIG_MEM_GENERIC_BOARD) 69#if (CONFIG_MEM_GENERIC_BOARD)
66#define DDR_SIZE DEVSZ_512 70#define DDR_SIZE DEVSZ_512
67#define DDR_WIDTH DEVWD_16 71#define DDR_WIDTH DEVWD_16
72#define DDR_MAX_tCK 13
68 73
69#define DDR_tRCD DDR_TRCD(3) 74#define DDR_tRCD DDR_TRCD(3)
70#define DDR_tWTR DDR_TWTR(2) 75#define DDR_tWTR DDR_TWTR(2)
@@ -77,14 +82,15 @@
77#define DDR_tREFI DDR_TREFI(1288) 82#define DDR_tREFI DDR_TREFI(1288)
78#endif 83#endif
79 84
80#if (CONFIG_SCLK_HZ <= 133333333) 85#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
81#define DDR_CL CL_2 86# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
82#elif (CONFIG_SCLK_HZ <= 166666666) 87#elif(CONFIG_SCLK_HZ <= 133333333)
83#define DDR_CL CL_2_5 88# define DDR_CL CL_2
84#else 89#else
85#define DDR_CL CL_3 90# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
86#endif 91#endif
87 92
93
88#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI) 94#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
89#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \ 95#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
90 | DDR_tMRD | DDR_tWR | DDR_tRCD) 96 | DDR_tMRD | DDR_tWR | DDR_tRCD)
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index 0c1d46193939..82157caa96a2 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List 10 * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -256,10 +256,14 @@
256#define ANOMALY_05000357 (1) 256#define ANOMALY_05000357 (1)
257/* Conflicting Column Address Widths Causes SDRAM Errors */ 257/* Conflicting Column Address Widths Causes SDRAM Errors */
258#define ANOMALY_05000362 (1) 258#define ANOMALY_05000362 (1)
259/* UART Break Signal Issues */
260#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
259/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ 261/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
260#define ANOMALY_05000366 (1) 262#define ANOMALY_05000366 (1)
261/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 263/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
262#define ANOMALY_05000371 (1) 264#define ANOMALY_05000371 (1)
265/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
266#define ANOMALY_05000403 (1)
263 267
264/* Anomalies that don't exist on this proc */ 268/* Anomalies that don't exist on this proc */
265#define ANOMALY_05000158 (0) 269#define ANOMALY_05000158 (0)
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
index b6f513bee56e..8a4e66d1db37 100644
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -1,22 +1,38 @@
1/*
2 * file: include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * blackfin serial driver head file
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
1#include <linux/serial.h> 32#include <linux/serial.h>
2#include <asm/dma.h> 33#include <asm/dma.h>
3#include <asm/portmux.h> 34#include <asm/portmux.h>
4 35
5#define NR_PORTS 1
6
7#define OFFSET_THR 0x00 /* Transmit Holding register */
8#define OFFSET_RBR 0x00 /* Receive Buffer register */
9#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
10#define OFFSET_IER 0x04 /* Interrupt Enable Register */
11#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
12#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
13#define OFFSET_LCR 0x0C /* Line Control Register */
14#define OFFSET_MCR 0x10 /* Modem Control Register */
15#define OFFSET_LSR 0x14 /* Line Status Register */
16#define OFFSET_MSR 0x18 /* Modem Status Register */
17#define OFFSET_SCR 0x1C /* SCR Scratch Register */
18#define OFFSET_GCTL 0x24 /* Global Control Register */
19
20#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) 36#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
21#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) 37#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
22#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) 38#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
@@ -84,7 +100,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
84 bfin_write16(uart->port.membase + OFFSET_LSR, -1); 100 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
85} 101}
86 102
87struct bfin_serial_port bfin_serial_ports[NR_PORTS]; 103struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
88struct bfin_serial_res { 104struct bfin_serial_res {
89 unsigned long uart_base_addr; 105 unsigned long uart_base_addr;
90 int uart_irq; 106 int uart_irq;
@@ -115,7 +131,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
115 131
116#define DRIVER_NAME "bfin-uart" 132#define DRIVER_NAME "bfin-uart"
117 133
118int nr_ports = NR_PORTS; 134int nr_ports = BFIN_UART_NR_PORTS;
119static void bfin_serial_hw_init(struct bfin_serial_port *uart) 135static void bfin_serial_hw_init(struct bfin_serial_port *uart)
120{ 136{
121 137
diff --git a/include/asm-blackfin/mach-bf561/bfin_sir.h b/include/asm-blackfin/mach-bf561/bfin_sir.h
new file mode 100644
index 000000000000..cefcf8bb505b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/bfin_sir.h
@@ -0,0 +1,120 @@
1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <asm/dma.h>
14#include <asm/portmux.h>
15
16#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
17#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
18#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
19#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
20#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
21#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
22#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
23
24#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
25#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
26#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
27#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
28#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
29#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
30
31#ifdef CONFIG_SIR_BFIN_DMA
32struct dma_rx_buf {
33 char *buf;
34 int head;
35 int tail;
36 };
37#endif /* CONFIG_SIR_BFIN_DMA */
38
39struct bfin_sir_port {
40 unsigned char __iomem *membase;
41 unsigned int irq;
42 unsigned int lsr;
43 unsigned long clk;
44 struct net_device *dev;
45#ifdef CONFIG_SIR_BFIN_DMA
46 int tx_done;
47 struct dma_rx_buf rx_dma_buf;
48 struct timer_list rx_dma_timer;
49 int rx_dma_nrows;
50#endif /* CONFIG_SIR_BFIN_DMA */
51 unsigned int tx_dma_channel;
52 unsigned int rx_dma_channel;
53};
54
55struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
56
57struct bfin_sir_port_res {
58 unsigned long base_addr;
59 int irq;
60 unsigned int rx_dma_channel;
61 unsigned int tx_dma_channel;
62};
63
64struct bfin_sir_port_res bfin_sir_port_resource[] = {
65#ifdef CONFIG_BFIN_SIR0
66 {
67 0xFFC00400,
68 IRQ_UART_RX,
69 CH_UART_RX,
70 CH_UART_TX,
71 },
72#endif
73};
74
75int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
76
77struct bfin_sir_self {
78 struct bfin_sir_port *sir_port;
79 spinlock_t lock;
80 unsigned int open;
81 int speed;
82 int newspeed;
83
84 struct sk_buff *txskb;
85 struct sk_buff *rxskb;
86 struct net_device_stats stats;
87 struct device *dev;
88 struct irlap_cb *irlap;
89 struct qos_info qos;
90
91 iobuff_t tx_buff;
92 iobuff_t rx_buff;
93
94 struct work_struct work;
95 int mtt;
96};
97
98static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
99{
100 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
101 port->lsr |= (lsr & (BI|FE|PE|OE));
102 return lsr | port->lsr;
103}
104
105static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
106{
107 port->lsr = 0;
108 bfin_read16(port->membase + OFFSET_LSR);
109}
110
111#define DRIVER_NAME "bfin_sir"
112
113static void bfin_sir_hw_init(void)
114{
115#ifdef CONFIG_BFIN_SIR0
116 peripheral_request(P_UART0_TX, DRIVER_NAME);
117 peripheral_request(P_UART0_RX, DRIVER_NAME);
118#endif
119 SSYNC();
120}
diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h
index 3a16df2c86d8..0ea8666e6764 100644
--- a/include/asm-blackfin/mach-bf561/blackfin.h
+++ b/include/asm-blackfin/mach-bf561/blackfin.h
@@ -69,5 +69,19 @@
69#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) 69#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
70#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) 70#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
71 71
72#define BFIN_UART_NR_PORTS 1
73
74#define OFFSET_THR 0x00 /* Transmit Holding register */
75#define OFFSET_RBR 0x00 /* Receive Buffer register */
76#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
77#define OFFSET_IER 0x04 /* Interrupt Enable Register */
78#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
79#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
80#define OFFSET_LCR 0x0C /* Line Control Register */
81#define OFFSET_MCR 0x10 /* Modem Control Register */
82#define OFFSET_LSR 0x14 /* Line Status Register */
83#define OFFSET_MSR 0x18 /* Modem Status Register */
84#define OFFSET_SCR 0x1C /* SCR Scratch Register */
85#define OFFSET_GCTL 0x24 /* Global Control Register */
72 86
73#endif /* _MACH_BLACKFIN_H_ */ 87#endif /* _MACH_BLACKFIN_H_ */
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
index 1bc8d2f89ccc..b07ffccd66dd 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -47,7 +47,30 @@
47 47
48/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 48/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
49#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 49#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
50#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) 50/* Writing to PLL_CTL initiates a PLL relock sequence. */
51static __inline__ void bfin_write_PLL_CTL(unsigned int val)
52{
53 unsigned long flags, iwr0, iwr1;
54
55 if (val == bfin_read_PLL_CTL())
56 return;
57
58 local_irq_save(flags);
59 /* Enable the PLL Wakeup bit in SIC IWR */
60 iwr0 = bfin_read32(SICA_IWR0);
61 iwr1 = bfin_read32(SICA_IWR1);
62 /* Only allow PPL Wakeup) */
63 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
64 bfin_write32(SICA_IWR1, 0);
65
66 bfin_write16(PLL_CTL, val);
67 SSYNC();
68 asm("IDLE;");
69
70 bfin_write32(SICA_IWR0, iwr0);
71 bfin_write32(SICA_IWR1, iwr1);
72 local_irq_restore(flags);
73}
51#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 74#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
52#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) 75#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
53#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 76#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
@@ -56,6 +79,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
56{ 79{
57 unsigned long flags, iwr0, iwr1; 80 unsigned long flags, iwr0, iwr1;
58 81
82 if (val == bfin_read_VR_CTL())
83 return;
84
85 local_irq_save(flags);
59 /* Enable the PLL Wakeup bit in SIC IWR */ 86 /* Enable the PLL Wakeup bit in SIC IWR */
60 iwr0 = bfin_read32(SICA_IWR0); 87 iwr0 = bfin_read32(SICA_IWR0);
61 iwr1 = bfin_read32(SICA_IWR1); 88 iwr1 = bfin_read32(SICA_IWR1);
@@ -65,12 +92,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
65 92
66 bfin_write16(VR_CTL, val); 93 bfin_write16(VR_CTL, val);
67 SSYNC(); 94 SSYNC();
68
69 local_irq_save(flags);
70 asm("IDLE;"); 95 asm("IDLE;");
71 local_irq_restore(flags); 96
72 bfin_write32(SICA_IWR0, iwr0); 97 bfin_write32(SICA_IWR0, iwr0);
73 bfin_write32(SICA_IWR1, iwr1); 98 bfin_write32(SICA_IWR1, iwr1);
99 local_irq_restore(flags);
74} 100}
75#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 101#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
76#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 102#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index c3c0eb13c819..366c9b9a0cb7 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -110,18 +110,23 @@
110#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */ 110#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
111 111
112/* UART Controller (0xFFC00400 - 0xFFC004FF) */ 112/* UART Controller (0xFFC00400 - 0xFFC004FF) */
113#define UART_THR 0xFFC00400 /* Transmit Holding register */ 113
114#define UART_RBR 0xFFC00400 /* Receive Buffer register */ 114/*
115#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ 115 * Because include/linux/serial_reg.h have defined UART_*,
116#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ 116 * So we define blackfin uart regs to BFIN_UART0_*.
117#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ 117 */
118#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ 118#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
119#define UART_LCR 0xFFC0040C /* Line Control Register */ 119#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
120#define UART_MCR 0xFFC00410 /* Modem Control Register */ 120#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
121#define UART_LSR 0xFFC00414 /* Line Status Register */ 121#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
122#define UART_MSR 0xFFC00418 /* Modem Status Register */ 122#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
123#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ 123#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
124#define UART_GCTL 0xFFC00424 /* Global Control Register */ 124#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
125#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
126#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
127#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */
128#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
129#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
125 130
126/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ 131/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
127#define SPI0_REGBASE 0xFFC00500 132#define SPI0_REGBASE 0xFFC00500
@@ -866,6 +871,8 @@
866/* PLL_DIV Masks */ 871/* PLL_DIV Masks */
867#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ 872#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
868 873
874#define CSEL 0x30 /* Core Select */
875#define SSEL 0xf /* System Select */
869#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ 876#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
870#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ 877#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
871#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ 878#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h
index 766334b7d8ab..21d982003e75 100644
--- a/include/asm-blackfin/mach-bf561/dma.h
+++ b/include/asm-blackfin/mach-bf561/dma.h
@@ -32,7 +32,4 @@
32#define CH_IMEM_STREAM1_SRC 34 32#define CH_IMEM_STREAM1_SRC 34
33#define CH_IMEM_STREAM1_DEST 35 33#define CH_IMEM_STREAM1_DEST 35
34 34
35extern int channel2irq(unsigned int channel);
36extern struct dma_register *base_addr[];
37
38#endif 35#endif
diff --git a/include/asm-blackfin/portmux.h b/include/asm-blackfin/portmux.h
index 0d3f650d2d99..0807b286cd9e 100644
--- a/include/asm-blackfin/portmux.h
+++ b/include/asm-blackfin/portmux.h
@@ -17,8 +17,8 @@
17 17
18int peripheral_request(unsigned short per, const char *label); 18int peripheral_request(unsigned short per, const char *label);
19void peripheral_free(unsigned short per); 19void peripheral_free(unsigned short per);
20int peripheral_request_list(unsigned short per[], const char *label); 20int peripheral_request_list(const unsigned short per[], const char *label);
21void peripheral_free_list(unsigned short per[]); 21void peripheral_free_list(const unsigned short per[]);
22 22
23#include <asm/gpio.h> 23#include <asm/gpio.h>
24#include <asm/mach/portmux.h> 24#include <asm/mach/portmux.h>
diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h
index 1033e5c76011..1c0040724612 100644
--- a/include/asm-blackfin/processor.h
+++ b/include/asm-blackfin/processor.h
@@ -26,9 +26,10 @@ static inline void wrusp(unsigned long usp)
26 26
27/* 27/*
28 * User space process size: 1st byte beyond user address space. 28 * User space process size: 1st byte beyond user address space.
29 * Fairly meaningless on nommu. Parts of user programs can be scattered
30 * in a lot of places, so just disable this by setting it to 0xFFFFFFFF.
29 */ 31 */
30extern unsigned long memory_end; 32#define TASK_SIZE 0xFFFFFFFF
31#define TASK_SIZE (memory_end)
32 33
33#ifdef __KERNEL__ 34#ifdef __KERNEL__
34#define STACK_TOP TASK_SIZE 35#define STACK_TOP TASK_SIZE
diff --git a/include/asm-blackfin/signal.h b/include/asm-blackfin/signal.h
index 0250429b736a..87951d251458 100644
--- a/include/asm-blackfin/signal.h
+++ b/include/asm-blackfin/signal.h
@@ -143,7 +143,7 @@ struct sigaction {
143#endif /* __KERNEL__ */ 143#endif /* __KERNEL__ */
144 144
145typedef struct sigaltstack { 145typedef struct sigaltstack {
146 void *ss_sp; 146 void __user *ss_sp;
147 int ss_flags; 147 int ss_flags;
148 size_t ss_size; 148 size_t ss_size;
149} stack_t; 149} stack_t;
diff --git a/include/asm-blackfin/thread_info.h b/include/asm-blackfin/thread_info.h
index 15b99cf4f50b..bc2fe5accf20 100644
--- a/include/asm-blackfin/thread_info.h
+++ b/include/asm-blackfin/thread_info.h
@@ -81,14 +81,11 @@ struct thread_info {
81#define init_thread_info (init_thread_union.thread_info) 81#define init_thread_info (init_thread_union.thread_info)
82#define init_stack (init_thread_union.stack) 82#define init_stack (init_thread_union.stack)
83 83
84/* How to get the thread information struct from C */ 84/* Given a task stack pointer, you can find its corresponding
85 85 * thread_info structure just by masking it to the THREAD_SIZE
86static inline struct thread_info *current_thread_info(void) 86 * boundary (currently 8K as you can see above).
87 __attribute__ ((__const__));
88
89/* Given a task stack pointer, you can find it's task structure
90 * just by masking it to the 8K boundary.
91 */ 87 */
88__attribute_const__
92static inline struct thread_info *current_thread_info(void) 89static inline struct thread_info *current_thread_info(void)
93{ 90{
94 struct thread_info *ti; 91 struct thread_info *ti;
diff --git a/include/asm-blackfin/time.h b/include/asm-blackfin/time.h
new file mode 100644
index 000000000000..6e5859b6ea32
--- /dev/null
+++ b/include/asm-blackfin/time.h
@@ -0,0 +1,36 @@
1/*
2 * asm-blackfin/time.h:
3 *
4 * Copyright 2004-2008 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef _ASM_BLACKFIN_TIME_H
10#define _ASM_BLACKFIN_TIME_H
11
12/*
13 * The way that the Blackfin core timer works is:
14 * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
15 * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
16 *
17 * If you take the fastest clock (1ns, or 1GHz to make the math work easier)
18 * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
19 * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
20 * to use TSCALE, and program it to zero (which is pass CCLK through).
21 * If you feel like using it, try to keep HZ * TIMESCALE to some
22 * value that divides easy (like power of 2).
23 */
24
25#ifndef CONFIG_CPU_FREQ
26#define TIME_SCALE 1
27#else
28/*
29 * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
30 * Whenever we change the Core Clock frequency changes we immediately
31 * adjust the Core Timer Presale Register. This way we don't lose time.
32 */
33#define TIME_SCALE 4
34#endif
35
36#endif
diff --git a/include/asm-blackfin/timex.h b/include/asm-blackfin/timex.h
index 828590117f51..22b0806161bb 100644
--- a/include/asm-blackfin/timex.h
+++ b/include/asm-blackfin/timex.h
@@ -1,18 +1,23 @@
1/* blackfin architecture timex specifications: Lineo Inc. 2001 1/*
2 * asm-blackfin/timex.h: cpu cycles!
2 * 3 *
3 * Based on: include/asm-m68knommu/timex.h 4 * Copyright 2004-2008 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
4 */ 7 */
5 8
6#ifndef _ASMBLACKFIN_TIMEX_H 9#ifndef _ASM_BLACKFIN_TIMEX_H
7#define _ASMBLACKFIN_TIMEX_H 10#define _ASM_BLACKFIN_TIMEX_H
8 11
9#define CLOCK_TICK_RATE 1000000 /* Underlying HZ */ 12#define CLOCK_TICK_RATE 1000000 /* Underlying HZ */
10 13
11typedef unsigned long cycles_t; 14typedef unsigned long long cycles_t;
12 15
13static inline cycles_t get_cycles(void) 16static inline cycles_t get_cycles(void)
14{ 17{
15 return 0; 18 unsigned long tmp, tmp2;
19 __asm__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2));
20 return tmp | ((cycles_t)tmp2 << 32);
16} 21}
17 22
18#endif 23#endif
diff --git a/include/asm-blackfin/trace.h b/include/asm-blackfin/trace.h
index ef18afbc2101..312b596b9731 100644
--- a/include/asm-blackfin/trace.h
+++ b/include/asm-blackfin/trace.h
@@ -62,14 +62,14 @@ extern unsigned long software_trace_buff[];
62 preg.L = LO(TBUFCTL); \ 62 preg.L = LO(TBUFCTL); \
63 preg.H = HI(TBUFCTL); \ 63 preg.H = HI(TBUFCTL); \
64 dreg = [preg]; \ 64 dreg = [preg]; \
65 [sp++] = dreg; \ 65 [--sp] = dreg; \
66 dreg = 0x1; \ 66 dreg = 0x1; \
67 [preg] = dreg; 67 [preg] = dreg;
68 68
69#define trace_buffer_restore(preg, dreg) \ 69#define trace_buffer_restore(preg, dreg) \
70 preg.L = LO(TBUFCTL); \ 70 preg.L = LO(TBUFCTL); \
71 preg.H = HI(TBUFCTL); \ 71 preg.H = HI(TBUFCTL); \
72 dreg = [sp--]; \ 72 dreg = [sp++]; \
73 [preg] = dreg; 73 [preg] = dreg;
74 74
75#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ 75#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
index 22a410b8003b..d928b8099056 100644
--- a/include/asm-blackfin/uaccess.h
+++ b/include/asm-blackfin/uaccess.h
@@ -133,7 +133,7 @@ static inline int bad_user_access_length(void)
133} 133}
134 134
135#define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\ 135#define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\
136 __FILE__, __LINE__, __FUNCTION__),\ 136 __FILE__, __LINE__, __func__),\
137 bad_user_access_length(), (-EFAULT)) 137 bad_user_access_length(), (-EFAULT))
138 138
139/* 139/*
@@ -177,7 +177,7 @@ static inline int bad_user_access_length(void)
177 default: \ 177 default: \
178 x = 0; \ 178 x = 0; \
179 printk(KERN_INFO "get_user_bad: %s:%d %s\n", \ 179 printk(KERN_INFO "get_user_bad: %s:%d %s\n", \
180 __FILE__, __LINE__, __FUNCTION__); \ 180 __FILE__, __LINE__, __func__); \
181 _err = __get_user_bad(); \ 181 _err = __get_user_bad(); \
182 break; \ 182 break; \
183 } \ 183 } \
diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h
index c18a399f6e3e..42955d0c439b 100644
--- a/include/asm-blackfin/unistd.h
+++ b/include/asm-blackfin/unistd.h
@@ -265,14 +265,14 @@
265 /* 258 __NR_remap_file_pages */ 265 /* 258 __NR_remap_file_pages */
266#define __NR_set_tid_address 259 266#define __NR_set_tid_address 259
267#define __NR_timer_create 260 267#define __NR_timer_create 260
268#define __NR_timer_settime (__NR_timer_create+1) 268#define __NR_timer_settime 261
269#define __NR_timer_gettime (__NR_timer_create+2) 269#define __NR_timer_gettime 262
270#define __NR_timer_getoverrun (__NR_timer_create+3) 270#define __NR_timer_getoverrun 263
271#define __NR_timer_delete (__NR_timer_create+4) 271#define __NR_timer_delete 264
272#define __NR_clock_settime (__NR_timer_create+5) 272#define __NR_clock_settime 265
273#define __NR_clock_gettime (__NR_timer_create+6) 273#define __NR_clock_gettime 266
274#define __NR_clock_getres (__NR_timer_create+7) 274#define __NR_clock_getres 267
275#define __NR_clock_nanosleep (__NR_timer_create+8) 275#define __NR_clock_nanosleep 268
276#define __NR_statfs64 269 276#define __NR_statfs64 269
277#define __NR_fstatfs64 270 277#define __NR_fstatfs64 270
278#define __NR_tgkill 271 278#define __NR_tgkill 271
@@ -283,11 +283,11 @@
283 /* 276 __NR_get_mempolicy */ 283 /* 276 __NR_get_mempolicy */
284 /* 277 __NR_set_mempolicy */ 284 /* 277 __NR_set_mempolicy */
285#define __NR_mq_open 278 285#define __NR_mq_open 278
286#define __NR_mq_unlink (__NR_mq_open+1) 286#define __NR_mq_unlink 279
287#define __NR_mq_timedsend (__NR_mq_open+2) 287#define __NR_mq_timedsend 280
288#define __NR_mq_timedreceive (__NR_mq_open+3) 288#define __NR_mq_timedreceive 281
289#define __NR_mq_notify (__NR_mq_open+4) 289#define __NR_mq_notify 282
290#define __NR_mq_getsetattr (__NR_mq_open+5) 290#define __NR_mq_getsetattr 283
291#define __NR_kexec_load 284 291#define __NR_kexec_load 284
292#define __NR_waitid 285 292#define __NR_waitid 285
293#define __NR_add_key 286 293#define __NR_add_key 286
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