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-rw-r--r--include/asm-blackfin/dpmc.h10
-rw-r--r--include/asm-blackfin/entry.h5
-rw-r--r--include/asm-blackfin/mach-bf527/bfin_serial_5xx.h5
-rw-r--r--include/asm-blackfin/mach-bf533/bfin_serial_5xx.h5
-rw-r--r--include/asm-blackfin/mach-bf533/defBF532.h2
-rw-r--r--include/asm-blackfin/mach-bf533/irq.h14
-rw-r--r--include/asm-blackfin/mach-bf537/bfin_serial_5xx.h5
-rw-r--r--include/asm-blackfin/mach-bf537/irq.h35
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_serial_5xx.h3
-rw-r--r--include/asm-blackfin/mach-bf548/defBF54x_base.h20
-rw-r--r--include/asm-blackfin/mach-bf561/bfin_serial_5xx.h5
-rw-r--r--include/asm-blackfin/mach-bf561/defBF561.h28
-rw-r--r--include/asm-blackfin/mach-bf561/irq.h13
-rw-r--r--include/asm-blackfin/mach-common/context.S5
-rw-r--r--include/asm-blackfin/time.h4
-rw-r--r--include/asm-blackfin/types.h34
-rw-r--r--include/asm-blackfin/unaligned.h13
17 files changed, 135 insertions, 71 deletions
diff --git a/include/asm-blackfin/dpmc.h b/include/asm-blackfin/dpmc.h
index 686cf83a5269..7f34cd384f12 100644
--- a/include/asm-blackfin/dpmc.h
+++ b/include/asm-blackfin/dpmc.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * include/asm-blackfin/dpmc.h - Miscellaneous IOCTL commands for Dynamic Power 2 * include/asm-blackfin/dpmc.h - Miscellaneous IOCTL commands for Dynamic Power
3 * Management Controller Driver. 3 * Management Controller Driver.
4 * Copyright (C) 2004 Analog Device Inc. 4 * Copyright (C) 2004-2008 Analog Device Inc.
5 * 5 *
6 */ 6 */
7#ifndef _BLACKFIN_DPMC_H_ 7#ifndef _BLACKFIN_DPMC_H_
@@ -65,6 +65,14 @@ void disable_wdog_timer(void);
65extern unsigned long get_cclk(void); 65extern unsigned long get_cclk(void);
66extern unsigned long get_sclk(void); 66extern unsigned long get_sclk(void);
67 67
68struct bfin_dpmc_platform_data {
69 const unsigned int *tuple_tab;
70 unsigned short tabsize;
71 unsigned short vr_settling_time; /* in us */
72};
73
74#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
75
68#endif /* __KERNEL__ */ 76#endif /* __KERNEL__ */
69 77
70#endif /*_BLACKFIN_DPMC_H_*/ 78#endif /*_BLACKFIN_DPMC_H_*/
diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h
index 562c6d3a3232..c4f721e0d00d 100644
--- a/include/asm-blackfin/entry.h
+++ b/include/asm-blackfin/entry.h
@@ -17,6 +17,11 @@
17#define PF_DTRACE_OFF 1 17#define PF_DTRACE_OFF 1
18#define PF_DTRACE_BIT 5 18#define PF_DTRACE_BIT 5
19 19
20/*
21 * NOTE! The single-stepping code assumes that all interrupt handlers
22 * start by saving SYSCFG on the stack with their first instruction.
23 */
24
20/* This one is used for exceptions, emulation, and NMI. It doesn't push 25/* This one is used for exceptions, emulation, and NMI. It doesn't push
21 RETI and doesn't do cli. */ 26 RETI and doesn't do cli. */
22#define SAVE_ALL_SYS save_context_no_interrupts 27#define SAVE_ALL_SYS save_context_no_interrupts
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
index f0ab2736a680..26e3c8076b4e 100644
--- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
44#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v) 44#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
45#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v) 45#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
46#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v) 46#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
47#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
48#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
47#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v) 49#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
48#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v) 50#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
49#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v) 51#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
50 52
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55
51#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 56#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
52# define CONFIG_SERIAL_BFIN_CTSRTS 57# define CONFIG_SERIAL_BFIN_CTSRTS
53 58
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index fbe88dee3e2d..d016603b6615 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
44#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) 44#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
45#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) 45#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
46#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) 46#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
47#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
48#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
47#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) 49#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
48#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) 50#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
49#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) 51#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
50 52
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55
51#ifdef CONFIG_BFIN_UART0_CTSRTS 56#ifdef CONFIG_BFIN_UART0_CTSRTS
52# define CONFIG_SERIAL_BFIN_CTSRTS 57# define CONFIG_SERIAL_BFIN_CTSRTS
53# ifndef CONFIG_UART0_CTS_PIN 58# ifndef CONFIG_UART0_CTS_PIN
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index 17e1548cec08..0ab4dd7494cf 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -468,6 +468,8 @@
468#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ 468#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
469#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ 469#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
470#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ 470#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
471#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
472#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
471 473
472#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ 474#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
473#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ 475#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
index 832e6f6122da..5aa38e5da6b7 100644
--- a/include/asm-blackfin/mach-bf533/irq.h
+++ b/include/asm-blackfin/mach-bf533/irq.h
@@ -66,12 +66,13 @@ Core Emulation **
66 DMA8/9 Interrupt IVG13 28 66 DMA8/9 Interrupt IVG13 28
67 DMA10/11 Interrupt IVG13 29 67 DMA10/11 Interrupt IVG13 29
68 Watchdog Timer IVG13 30 68 Watchdog Timer IVG13 30
69 Software Interrupt 1 IVG14 31 69
70 Software Interrupt 2 -- 70 Softirq IVG14 31
71 System Call --
71 (lowest priority) IVG15 32 * 72 (lowest priority) IVG15 32 *
72 */ 73 */
73#define SYS_IRQS 32 74#define SYS_IRQS 31
74#define NR_PERI_INTS 24 75#define NR_PERI_INTS 24
75 76
76/* The ABSTRACT IRQ definitions */ 77/* The ABSTRACT IRQ definitions */
77/** the first seven of the following are fixed, the rest you change if you need to **/ 78/** the first seven of the following are fixed, the rest you change if you need to **/
@@ -96,7 +97,7 @@ Core Emulation **
96#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */ 97#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
97#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */ 98#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
98#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */ 99#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
99#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ 100#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
100#define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */ 101#define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */
101#define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */ 102#define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */
102#define IRQ_TMR0 23 /*Timer 0 */ 103#define IRQ_TMR0 23 /*Timer 0 */
@@ -108,9 +109,6 @@ Core Emulation **
108#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */ 109#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */
109#define IRQ_WATCH 30 /*Watch Dog Timer */ 110#define IRQ_WATCH 30 /*Watch Dog Timer */
110 111
111#define IRQ_SW_INT1 31 /*Software Int 1 */
112#define IRQ_SW_INT2 32 /*Software Int 2 (reserved for SYSCALL) */
113
114#define IRQ_PF0 33 112#define IRQ_PF0 33
115#define IRQ_PF1 34 113#define IRQ_PF1 34
116#define IRQ_PF2 35 114#define IRQ_PF2 35
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
index fd100a415b98..f79d1a0e9129 100644
--- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
44#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) 44#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
45#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) 45#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
46#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) 46#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
47#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
48#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
47#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) 49#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
48#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) 50#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
49#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) 51#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
50 52
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55
51#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 56#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
52# define CONFIG_SERIAL_BFIN_CTSRTS 57# define CONFIG_SERIAL_BFIN_CTSRTS
53 58
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
index be6f2ff77f31..2e68a8a1e730 100644
--- a/include/asm-blackfin/mach-bf537/irq.h
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -34,24 +34,23 @@
34 34
35/* 35/*
36 * Interrupt source definitions 36 * Interrupt source definitions
37 Event Source Core Event Name 37 * Event Source Core Event Name
38Core Emulation ** 38 * Core Emulation **
39 Events (highest priority) EMU 0 39 * Events (highest priority) EMU 0
40 Reset RST 1 40 * Reset RST 1
41 NMI NMI 2 41 * NMI NMI 2
42 Exception EVX 3 42 * Exception EVX 3
43 Reserved -- 4 43 * Reserved -- 4
44 Hardware Error IVHW 5 44 * Hardware Error IVHW 5
45 Core Timer IVTMR 6 * 45 * Core Timer IVTMR 6
46 46 * .....
47..... 47 *
48 48 * Softirq IVG14
49 Software Interrupt 1 IVG14 31 49 * System Call --
50 Software Interrupt 2 -- 50 * (lowest priority) IVG15
51 (lowest priority) IVG15 32 *
52 */ 51 */
53 52
54#define SYS_IRQS 41 53#define SYS_IRQS 39
55#define NR_PERI_INTS 32 54#define NR_PERI_INTS 32
56 55
57/* The ABSTRACT IRQ definitions */ 56/* The ABSTRACT IRQ definitions */
@@ -95,10 +94,8 @@ Core Emulation **
95#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ 94#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
96#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */ 95#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
97#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */ 96#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
98#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */ 97#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
99#define IRQ_WATCH 38 /*Watch Dog Timer */ 98#define IRQ_WATCH 38 /*Watch Dog Timer */
100#define IRQ_SW_INT1 40 /*Software Int 1 */
101#define IRQ_SW_INT2 41 /*Software Int 2 (reserved for SYSCALL) */
102 99
103#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */ 100#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
104#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */ 101#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
index 6547027cd3e6..5eb46a77d919 100644
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -54,6 +54,9 @@
54#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) 54#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
55#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v) 55#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
56 56
57#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */
58#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */
59
57#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 60#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
58# define CONFIG_SERIAL_BFIN_CTSRTS 61# define CONFIG_SERIAL_BFIN_CTSRTS
59 62
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index 08f90c21fe8a..e022e896cb18 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -2329,6 +2329,26 @@
2329#define KPADWE 0x1000 /* Keypad Wake-Up Enable */ 2329#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
2330#define ROTWE 0x2000 /* Rotary Wake-Up Enable */ 2330#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
2331 2331
2332#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
2333#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
2334#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
2335
2336#define GAIN_5 0x0000 /* GAIN = 5*/
2337#define GAIN_10 0x0004 /* GAIN = 1*/
2338#define GAIN_20 0x0008 /* GAIN = 2*/
2339#define GAIN_50 0x000C /* GAIN = 5*/
2340
2341#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
2342#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
2343#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
2344#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
2345#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
2346#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
2347#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
2348#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
2349#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
2350#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
2351
2332/* Bit masks for NFC_CTL */ 2352/* Bit masks for NFC_CTL */
2333 2353
2334#define WR_DLY 0xf /* Write Strobe Delay */ 2354#define WR_DLY 0xf /* Write Strobe Delay */
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
index 8a4e66d1db37..7a9628769296 100644
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
44#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) 44#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
45#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) 45#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
46#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) 46#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
47#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
48#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
47#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) 49#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
48#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) 50#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
49#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) 51#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
50 52
53#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
54#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
55
51#ifdef CONFIG_BFIN_UART0_CTSRTS 56#ifdef CONFIG_BFIN_UART0_CTSRTS
52# define CONFIG_SERIAL_BFIN_CTSRTS 57# define CONFIG_SERIAL_BFIN_CTSRTS
53# ifndef CONFIG_UART0_CTS_PIN 58# ifndef CONFIG_UART0_CTS_PIN
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 366c9b9a0cb7..1ab50e906fe7 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -868,6 +868,34 @@
868#define CHIPID_FAMILY 0x0FFFF000 868#define CHIPID_FAMILY 0x0FFFF000
869#define CHIPID_MANUFACTURE 0x00000FFE 869#define CHIPID_MANUFACTURE 0x00000FFE
870 870
871/* VR_CTL Masks */
872#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
873#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
874#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
875#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
876#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
877
878#define GAIN 0x000C /* Voltage Level Gain */
879#define GAIN_5 0x0000 /* GAIN = 5*/
880#define GAIN_10 0x0004 /* GAIN = 1*/
881#define GAIN_20 0x0008 /* GAIN = 2*/
882#define GAIN_50 0x000C /* GAIN = 5*/
883
884#define VLEV 0x00F0 /* Internal Voltage Level */
885#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
886#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
887#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
888#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
889#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
890#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
891#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
892#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
893#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
894#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
895
896#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
897#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
898
871/* PLL_DIV Masks */ 899/* PLL_DIV Masks */
872#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ 900#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
873 901
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h
index 83f0383957d2..6698389c5564 100644
--- a/include/asm-blackfin/mach-bf561/irq.h
+++ b/include/asm-blackfin/mach-bf561/irq.h
@@ -118,12 +118,13 @@
118 Supplemental interrupt 0 IVG7 69 118 Supplemental interrupt 0 IVG7 69
119 supplemental interrupt 1 IVG7 70 119 supplemental interrupt 1 IVG7 70
120 120
121 Software Interrupt 1 IVG14 71 121 Softirq IVG14
122 Software Interrupt 2 IVG15 72 * 122 System Call --
123 (lowest priority) 123 (lowest priority) IVG15
124
124 **********************************************************************/ 125 **********************************************************************/
125 126
126#define SYS_IRQS 72 127#define SYS_IRQS 71
127#define NR_PERI_INTS 64 128#define NR_PERI_INTS 64
128 129
129/* 130/*
@@ -237,9 +238,7 @@
237#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */ 238#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
238#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */ 239#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */
239#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */ 240#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */
240#define IRQ_SW_INT1 71 /* Software Interrupt 1 */ 241
241#define IRQ_SW_INT2 72 /* Software Interrupt 2 */
242 /* reserved for SYSCALL */
243#define IRQ_PF0 73 242#define IRQ_PF0 73
244#define IRQ_PF1 74 243#define IRQ_PF1 74
245#define IRQ_PF2 75 244#define IRQ_PF2 75
diff --git a/include/asm-blackfin/mach-common/context.S b/include/asm-blackfin/mach-common/context.S
index fd0ebe1862b8..c0e630edfb9a 100644
--- a/include/asm-blackfin/mach-common/context.S
+++ b/include/asm-blackfin/mach-common/context.S
@@ -28,6 +28,11 @@
28 */ 28 */
29 29
30/* 30/*
31 * NOTE! The single-stepping code assumes that all interrupt handlers
32 * start by saving SYSCFG on the stack with their first instruction.
33 */
34
35/*
31 * Code to save processor context. 36 * Code to save processor context.
32 * We even save the register which are preserved by a function call 37 * We even save the register which are preserved by a function call
33 * - r4, r5, r6, r7, p3, p4, p5 38 * - r4, r5, r6, r7, p3, p4, p5
diff --git a/include/asm-blackfin/time.h b/include/asm-blackfin/time.h
index 6e5859b6ea32..ddc43ce38533 100644
--- a/include/asm-blackfin/time.h
+++ b/include/asm-blackfin/time.h
@@ -24,6 +24,8 @@
24 24
25#ifndef CONFIG_CPU_FREQ 25#ifndef CONFIG_CPU_FREQ
26#define TIME_SCALE 1 26#define TIME_SCALE 1
27#define __bfin_cycles_off (0)
28#define __bfin_cycles_mod (0)
27#else 29#else
28/* 30/*
29 * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 . 31 * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
@@ -31,6 +33,8 @@
31 * adjust the Core Timer Presale Register. This way we don't lose time. 33 * adjust the Core Timer Presale Register. This way we don't lose time.
32 */ 34 */
33#define TIME_SCALE 4 35#define TIME_SCALE 4
36extern unsigned long long __bfin_cycles_off;
37extern unsigned int __bfin_cycles_mod;
34#endif 38#endif
35 39
36#endif 40#endif
diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h
index 9785a6d531c6..8441cbc2bf9e 100644
--- a/include/asm-blackfin/types.h
+++ b/include/asm-blackfin/types.h
@@ -8,30 +8,12 @@
8 * not a major issue. However, for interoperability, libraries still 8 * not a major issue. However, for interoperability, libraries still
9 * need to be careful to avoid a name clashes. 9 * need to be careful to avoid a name clashes.
10 */ 10 */
11#include <asm-generic/int-ll64.h>
12
11#ifndef __ASSEMBLY__ 13#ifndef __ASSEMBLY__
12 14
13typedef unsigned short umode_t; 15typedef unsigned short umode_t;
14 16
15/*
16 * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
17 * header files exported to user space
18 */
19
20typedef __signed__ char __s8;
21typedef unsigned char __u8;
22
23typedef __signed__ short __s16;
24typedef unsigned short __u16;
25
26typedef __signed__ int __s32;
27typedef unsigned int __u32;
28
29/* HK0617 -- Changes to unsigned long temporarily */
30#if defined(__GNUC__)
31__extension__ typedef __signed__ long long __s64;
32__extension__ typedef unsigned long long __u64;
33#endif
34
35#endif /* __ASSEMBLY__ */ 17#endif /* __ASSEMBLY__ */
36/* 18/*
37 * These aren't exported outside the kernel to avoid name space clashes 19 * These aren't exported outside the kernel to avoid name space clashes
@@ -42,18 +24,6 @@ __extension__ typedef unsigned long long __u64;
42 24
43#ifndef __ASSEMBLY__ 25#ifndef __ASSEMBLY__
44 26
45typedef signed char s8;
46typedef unsigned char u8;
47
48typedef signed short s16;
49typedef unsigned short u16;
50
51typedef signed int s32;
52typedef unsigned int u32;
53
54typedef signed long long s64;
55typedef unsigned long long u64;
56
57/* Dma addresses are 32-bits wide. */ 27/* Dma addresses are 32-bits wide. */
58 28
59typedef u32 dma_addr_t; 29typedef u32 dma_addr_t;
diff --git a/include/asm-blackfin/unaligned.h b/include/asm-blackfin/unaligned.h
index 10081dc241ef..fd8a1d634945 100644
--- a/include/asm-blackfin/unaligned.h
+++ b/include/asm-blackfin/unaligned.h
@@ -1,6 +1,11 @@
1#ifndef __BFIN_UNALIGNED_H 1#ifndef _ASM_BLACKFIN_UNALIGNED_H
2#define __BFIN_UNALIGNED_H 2#define _ASM_BLACKFIN_UNALIGNED_H
3 3
4#include <asm-generic/unaligned.h> 4#include <linux/unaligned/le_struct.h>
5#include <linux/unaligned/be_byteshift.h>
6#include <linux/unaligned/generic.h>
5 7
6#endif /* __BFIN_UNALIGNED_H */ 8#define get_unaligned __get_unaligned_le
9#define put_unaligned __put_unaligned_le
10
11#endif /* _ASM_BLACKFIN_UNALIGNED_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 01:19:09 -0500