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-rw-r--r--include/asm-blackfin/mach-bf533/bf533.h91
-rw-r--r--include/asm-blackfin/mach-bf537/bf537.h91
-rw-r--r--include/asm-blackfin/mach-bf548/bf548.h87
-rw-r--r--include/asm-blackfin/mach-bf561/bf561.h87
-rw-r--r--include/asm-blackfin/mach-common/clocks.h68
5 files changed, 68 insertions, 356 deletions
diff --git a/include/asm-blackfin/mach-bf533/bf533.h b/include/asm-blackfin/mach-bf533/bf533.h
index 41e4e834e2d3..cb210f6f7689 100644
--- a/include/asm-blackfin/mach-bf533/bf533.h
+++ b/include/asm-blackfin/mach-bf533/bf533.h
@@ -141,97 +141,6 @@
141 141
142#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) 142#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
143 143
144#define MAX_VC 650000000
145#define MIN_VC 50000000
146
147#ifdef CONFIG_BFIN_KERNEL_CLOCK
148/********************************PLL Settings **************************************/
149#if (CONFIG_VCO_MULT < 0)
150#error "VCO Multiplier is less than 0. Please select a different value"
151#endif
152
153#if (CONFIG_VCO_MULT == 0)
154#error "VCO Multiplier should be greater than 0. Please select a different value"
155#endif
156
157#if (CONFIG_VCO_MULT > 64)
158#error "VCO Multiplier is more than 64. Please select a different value"
159#endif
160
161#ifndef CONFIG_CLKIN_HALF
162#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
163#else
164#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
165#endif
166
167#ifndef CONFIG_PLL_BYPASS
168#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
169#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
170#else
171#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
172#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
173#endif
174
175#if (CONFIG_SCLK_DIV < 1)
176#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
177#endif
178
179#if (CONFIG_SCLK_DIV > 15)
180#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
181#endif
182
183#if (CONFIG_CCLK_DIV != 1)
184#if (CONFIG_CCLK_DIV != 2)
185#if (CONFIG_CCLK_DIV != 4)
186#if (CONFIG_CCLK_DIV != 8)
187#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
188#endif
189#endif
190#endif
191#endif
192
193#if (CONFIG_VCO_HZ > MAX_VC)
194#error "VCO selected is more than maximum value. Please change the VCO multipler"
195#endif
196
197#if (CONFIG_SCLK_HZ > 133000000)
198#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
199#endif
200
201#if (CONFIG_SCLK_HZ < 27000000)
202#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
203#endif
204
205#if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ)
206#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
207#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
208#error "Please select sclk less than cclk"
209#endif
210#endif
211#endif
212
213#if (CONFIG_CCLK_DIV == 1)
214#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
215#endif
216#if (CONFIG_CCLK_DIV == 2)
217#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
218#endif
219#if (CONFIG_CCLK_DIV == 4)
220#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
221#endif
222#if (CONFIG_CCLK_DIV == 8)
223#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
224#endif
225#ifndef CONFIG_CCLK_ACT_DIV
226#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
227#endif
228
229#if ANOMALY_05000273 && (CONFIG_CCLK_DIV == 1)
230#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
231#endif
232
233#endif /* CONFIG_BFIN_KERNEL_CLOCK */
234
235#ifdef CONFIG_BF533 144#ifdef CONFIG_BF533
236#define CPU "BF533" 145#define CPU "BF533"
237#define CPUID 0x027a5000 146#define CPUID 0x027a5000
diff --git a/include/asm-blackfin/mach-bf537/bf537.h b/include/asm-blackfin/mach-bf537/bf537.h
index 04b08164e292..603823f51ca0 100644
--- a/include/asm-blackfin/mach-bf537/bf537.h
+++ b/include/asm-blackfin/mach-bf537/bf537.h
@@ -121,97 +121,6 @@
121 121
122#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) 122#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
123 123
124#define MAX_VC 650000000
125#define MIN_VC 50000000
126
127/********************************PLL Settings **************************************/
128#ifdef CONFIG_BFIN_KERNEL_CLOCK
129#if (CONFIG_VCO_MULT < 0)
130#error "VCO Multiplier is less than 0. Please select a different value"
131#endif
132
133#if (CONFIG_VCO_MULT == 0)
134#error "VCO Multiplier should be greater than 0. Please select a different value"
135#endif
136
137#if (CONFIG_VCO_MULT > 64)
138#error "VCO Multiplier is more than 64. Please select a different value"
139#endif
140
141#ifndef CONFIG_CLKIN_HALF
142#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
143#else
144#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
145#endif
146
147#ifndef CONFIG_PLL_BYPASS
148#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
149#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
150#else
151#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
152#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
153#endif
154
155#if (CONFIG_SCLK_DIV < 1)
156#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
157#endif
158
159#if (CONFIG_SCLK_DIV > 15)
160#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
161#endif
162
163#if (CONFIG_CCLK_DIV != 1)
164#if (CONFIG_CCLK_DIV != 2)
165#if (CONFIG_CCLK_DIV != 4)
166#if (CONFIG_CCLK_DIV != 8)
167#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
168#endif
169#endif
170#endif
171#endif
172
173#if (CONFIG_VCO_HZ > MAX_VC)
174#error "VCO selected is more than maximum value. Please change the VCO multipler"
175#endif
176
177#if (CONFIG_SCLK_HZ > 133000000)
178#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
179#endif
180
181#if (CONFIG_SCLK_HZ < 27000000)
182#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
183#endif
184
185#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
186#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
187#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
188#error "Please select sclk less than cclk"
189#endif
190#endif
191#endif
192
193#if (CONFIG_CCLK_DIV == 1)
194#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
195#endif
196#if (CONFIG_CCLK_DIV == 2)
197#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
198#endif
199#if (CONFIG_CCLK_DIV == 4)
200#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
201#endif
202#if (CONFIG_CCLK_DIV == 8)
203#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
204#endif
205#ifndef CONFIG_CCLK_ACT_DIV
206#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
207#endif
208
209#if ANOMALY_05000273 && (CONFIG_CCLK_DIV == 1)
210#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
211#endif
212
213#endif /* CONFIG_BFIN_KERNEL_CLOCK */
214
215#ifdef CONFIG_BF537 124#ifdef CONFIG_BF537
216#define CPU "BF537" 125#define CPU "BF537"
217#define CPUID 0x027c8000 126#define CPUID 0x027c8000
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
index 9498313a2cb7..50306a846628 100644
--- a/include/asm-blackfin/mach-bf548/bf548.h
+++ b/include/asm-blackfin/mach-bf548/bf548.h
@@ -106,93 +106,6 @@
106 106
107#define AMGCTLVAL (V_AMBEN | V_AMCKEN) 107#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
108 108
109#define MAX_VC 650000000
110#define MIN_VC 50000000
111
112/********************************PLL Settings **************************************/
113#ifdef CONFIG_BFIN_KERNEL_CLOCK
114#if (CONFIG_VCO_MULT < 0)
115#error "VCO Multiplier is less than 0. Please select a different value"
116#endif
117
118#if (CONFIG_VCO_MULT == 0)
119#error "VCO Multiplier should be greater than 0. Please select a different value"
120#endif
121
122#if (CONFIG_VCO_MULT > 64)
123#error "VCO Multiplier is more than 64. Please select a different value"
124#endif
125
126#ifndef CONFIG_CLKIN_HALF
127#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
128#else
129#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
130#endif
131
132#ifndef CONFIG_PLL_BYPASS
133#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
134#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
135#else
136#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
137#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
138#endif
139
140#if (CONFIG_SCLK_DIV < 1)
141#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
142#endif
143
144#if (CONFIG_SCLK_DIV > 15)
145#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
146#endif
147
148#if (CONFIG_CCLK_DIV != 1)
149#if (CONFIG_CCLK_DIV != 2)
150#if (CONFIG_CCLK_DIV != 4)
151#if (CONFIG_CCLK_DIV != 8)
152#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
153#endif
154#endif
155#endif
156#endif
157
158#if (CONFIG_VCO_HZ > MAX_VC)
159#error "VCO selected is more than maximum value. Please change the VCO multipler"
160#endif
161
162#if (CONFIG_SCLK_HZ > 133000000)
163#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
164#endif
165
166#if (CONFIG_SCLK_HZ < 27000000)
167#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
168#endif
169
170#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
171#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
172#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
173#error "Please select sclk less than cclk"
174#endif
175#endif
176#endif
177
178#if (CONFIG_CCLK_DIV == 1)
179#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
180#endif
181#if (CONFIG_CCLK_DIV == 2)
182#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
183#endif
184#if (CONFIG_CCLK_DIV == 4)
185#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
186#endif
187#if (CONFIG_CCLK_DIV == 8)
188#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
189#endif
190#ifndef CONFIG_CCLK_ACT_DIV
191#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
192#endif
193
194#endif /* CONFIG_BFIN_KERNEL_CLOCK */
195
196#ifdef CONFIG_BF542 109#ifdef CONFIG_BF542
197#define CPU "BF542" 110#define CPU "BF542"
198#define CPUID 0x027c8000 111#define CPUID 0x027c8000
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
index 8cc2e0033e0a..53b650f31342 100644
--- a/include/asm-blackfin/mach-bf561/bf561.h
+++ b/include/asm-blackfin/mach-bf561/bf561.h
@@ -230,93 +230,6 @@
230 230
231#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002) 231#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
232 232
233#define MAX_VC 600000000
234#define MIN_VC 50000000
235
236/******************************* PLL Settings ********************************/
237#ifdef CONFIG_BFIN_KERNEL_CLOCK
238#if (CONFIG_VCO_MULT < 0)
239#error "VCO Multiplier is less than 0. Please select a different value"
240#endif
241
242#if (CONFIG_VCO_MULT == 0)
243#error "VCO Multiplier should be greater than 0. Please select a different value"
244#endif
245
246#ifndef CONFIG_CLKIN_HALF
247#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
248#else
249#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
250#endif
251
252#ifndef CONFIG_PLL_BYPASS
253#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
254#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
255#else
256#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
257#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
258#endif
259
260#if (CONFIG_SCLK_DIV < 1)
261#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
262#endif
263
264#if (CONFIG_SCLK_DIV > 15)
265#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
266#endif
267
268#if (CONFIG_CCLK_DIV != 1)
269#if (CONFIG_CCLK_DIV != 2)
270#if (CONFIG_CCLK_DIV != 4)
271#if (CONFIG_CCLK_DIV != 8)
272#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
273#endif
274#endif
275#endif
276#endif
277
278#if (CONFIG_VCO_HZ > MAX_VC)
279#error "VCO selected is more than maximum value. Please change the VCO multipler"
280#endif
281
282#if (CONFIG_SCLK_HZ > 133000000)
283#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
284#endif
285
286#if (CONFIG_SCLK_HZ < 27000000)
287#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
288#endif
289
290#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
291#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
292#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
293#error "Please select sclk less than cclk"
294#endif
295#endif
296#endif
297
298#if (CONFIG_CCLK_DIV == 1)
299#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
300#endif
301#if (CONFIG_CCLK_DIV == 2)
302#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
303#endif
304#if (CONFIG_CCLK_DIV == 4)
305#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
306#endif
307#if (CONFIG_CCLK_DIV == 8)
308#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
309#endif
310#ifndef CONFIG_CCLK_ACT_DIV
311#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
312#endif
313
314#if ANOMALY_05000273 && (CONFIG_CCLK_DIV == 1)
315#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
316#endif
317
318#endif /* CONFIG_BFIN_KERNEL_CLOCK */
319
320#ifdef CONFIG_BF561 233#ifdef CONFIG_BF561
321#define CPU "BF561" 234#define CPU "BF561"
322#define CPUID 0x027bb000 235#define CPUID 0x027bb000
diff --git a/include/asm-blackfin/mach-common/clocks.h b/include/asm-blackfin/mach-common/clocks.h
new file mode 100644
index 000000000000..5e8113ee8939
--- /dev/null
+++ b/include/asm-blackfin/mach-common/clocks.h
@@ -0,0 +1,68 @@
1/*
2 * File: include/asm-blackfin/mach-common/clocks.h
3 * Based on: include/asm-blackfin/mach-bf537/bf537.h
4 * Author: Robin Getz <rgetz@blackfin.uclinux.org>
5 *
6 * Created: 25Jul07
7 * Description: Common Clock definitions for various kernel files
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30
31
32#ifdef CONFIG_CCLK_DIV_1
33# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
34# define CONFIG_CCLK_DIV 1
35#endif
36
37#ifdef CONFIG_CCLK_DIV_2
38# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
39# define CONFIG_CCLK_DIV 2
40#endif
41
42#ifdef CONFIG_CCLK_DIV_4
43# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
44# define CONFIG_CCLK_DIV 4
45#endif
46
47#ifdef CONFIG_CCLK_DIV_8
48# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
49# define CONFIG_CCLK_DIV 8
50#endif
51
52#ifndef CONFIG_PLL_BYPASS
53# ifndef CONFIG_CLKIN_HALF
54# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
55# else
56# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
57# endif
58
59# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
60# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
61
62#else
63# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ)
64# define CONFIG_CCLK_HZ (CONFIG_CLKIN_HZ)
65# define CONFIG_SCLK_HZ (CONFIG_CLKIN_HZ)
66# define CONFIG_VCO_MULT 0
67#endif
68
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 22:27:06 -0500