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-rw-r--r--include/asm-blackfin/Kbuild1
-rw-r--r--include/asm-blackfin/a.out.h25
-rw-r--r--include/asm-blackfin/atomic.h144
-rw-r--r--include/asm-blackfin/auxvec.h4
-rw-r--r--include/asm-blackfin/bf5xx_timers.h209
-rw-r--r--include/asm-blackfin/bfin-global.h120
-rw-r--r--include/asm-blackfin/bfin5xx_spi.h170
-rw-r--r--include/asm-blackfin/bfin_simple_timer.h13
-rw-r--r--include/asm-blackfin/bfin_sport.h175
-rw-r--r--include/asm-blackfin/bitops.h213
-rw-r--r--include/asm-blackfin/blackfin.h81
-rw-r--r--include/asm-blackfin/bug.h4
-rw-r--r--include/asm-blackfin/bugs.h16
-rw-r--r--include/asm-blackfin/byteorder.h48
-rw-r--r--include/asm-blackfin/cache.h29
-rw-r--r--include/asm-blackfin/cacheflush.h90
-rw-r--r--include/asm-blackfin/checksum.h101
-rw-r--r--include/asm-blackfin/cplb.h51
-rw-r--r--include/asm-blackfin/cplbinit.h203
-rw-r--r--include/asm-blackfin/cpumask.h6
-rw-r--r--include/asm-blackfin/cputime.h6
-rw-r--r--include/asm-blackfin/current.h23
-rw-r--r--include/asm-blackfin/delay.h44
-rw-r--r--include/asm-blackfin/device.h7
-rw-r--r--include/asm-blackfin/div64.h1
-rw-r--r--include/asm-blackfin/dma-mapping.h66
-rw-r--r--include/asm-blackfin/dma.h188
-rw-r--r--include/asm-blackfin/dpmc.h70
-rw-r--r--include/asm-blackfin/elf.h127
-rw-r--r--include/asm-blackfin/emergency-restart.h6
-rw-r--r--include/asm-blackfin/entry.h56
-rw-r--r--include/asm-blackfin/errno.h6
-rw-r--r--include/asm-blackfin/fcntl.h13
-rw-r--r--include/asm-blackfin/flat.h58
-rw-r--r--include/asm-blackfin/futex.h6
-rw-r--r--include/asm-blackfin/gpio.h367
-rw-r--r--include/asm-blackfin/hardirq.h41
-rw-r--r--include/asm-blackfin/hw_irq.h6
-rw-r--r--include/asm-blackfin/ide.h32
-rw-r--r--include/asm-blackfin/io.h207
-rw-r--r--include/asm-blackfin/ioctl.h1
-rw-r--r--include/asm-blackfin/ioctls.h82
-rw-r--r--include/asm-blackfin/ipc.h1
-rw-r--r--include/asm-blackfin/ipcbuf.h30
-rw-r--r--include/asm-blackfin/irq.h70
-rw-r--r--include/asm-blackfin/irq_handler.h22
-rw-r--r--include/asm-blackfin/irq_regs.h1
-rw-r--r--include/asm-blackfin/kdebug.h1
-rw-r--r--include/asm-blackfin/kmap_types.h21
-rw-r--r--include/asm-blackfin/l1layout.h31
-rw-r--r--include/asm-blackfin/linkage.h7
-rw-r--r--include/asm-blackfin/local.h6
-rw-r--r--include/asm-blackfin/mach-bf533/anomaly.h175
-rw-r--r--include/asm-blackfin/mach-bf533/bf533.h306
-rw-r--r--include/asm-blackfin/mach-bf533/bfin_serial_5xx.h108
-rw-r--r--include/asm-blackfin/mach-bf533/blackfin.h45
-rw-r--r--include/asm-blackfin/mach-bf533/cdefBF532.h706
-rw-r--r--include/asm-blackfin/mach-bf533/defBF532.h1175
-rw-r--r--include/asm-blackfin/mach-bf533/dma.h54
-rw-r--r--include/asm-blackfin/mach-bf533/irq.h177
-rw-r--r--include/asm-blackfin/mach-bf533/mem_init.h316
-rw-r--r--include/asm-blackfin/mach-bf533/mem_map.h168
-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h120
-rw-r--r--include/asm-blackfin/mach-bf537/bf537.h287
-rw-r--r--include/asm-blackfin/mach-bf537/bfin_serial_5xx.h147
-rw-r--r--include/asm-blackfin/mach-bf537/blackfin.h430
-rw-r--r--include/asm-blackfin/mach-bf537/cdefBF534.h1823
-rw-r--r--include/asm-blackfin/mach-bf537/cdefBF537.h209
-rw-r--r--include/asm-blackfin/mach-bf537/defBF534.h2501
-rw-r--r--include/asm-blackfin/mach-bf537/defBF537.h404
-rw-r--r--include/asm-blackfin/mach-bf537/dma.h55
-rw-r--r--include/asm-blackfin/mach-bf537/irq.h219
-rw-r--r--include/asm-blackfin/mach-bf537/mem_init.h330
-rw-r--r--include/asm-blackfin/mach-bf537/mem_map.h175
-rw-r--r--include/asm-blackfin/mach-bf561/anomaly.h184
-rw-r--r--include/asm-blackfin/mach-bf561/bf561.h408
-rw-r--r--include/asm-blackfin/mach-bf561/bfin_serial_5xx.h108
-rw-r--r--include/asm-blackfin/mach-bf561/blackfin.h52
-rw-r--r--include/asm-blackfin/mach-bf561/cdefBF561.h1543
-rw-r--r--include/asm-blackfin/mach-bf561/defBF561.h1717
-rw-r--r--include/asm-blackfin/mach-bf561/dma.h35
-rw-r--r--include/asm-blackfin/mach-bf561/irq.h450
-rw-r--r--include/asm-blackfin/mach-bf561/mem_init.h322
-rw-r--r--include/asm-blackfin/mach-bf561/mem_map.h75
-rw-r--r--include/asm-blackfin/mach-common/cdef_LPBlackfin.h471
-rw-r--r--include/asm-blackfin/mach-common/context.S350
-rw-r--r--include/asm-blackfin/mach-common/def_LPBlackfin.h691
-rw-r--r--include/asm-blackfin/macros.h95
-rw-r--r--include/asm-blackfin/mem_map.h12
-rw-r--r--include/asm-blackfin/mman.h45
-rw-r--r--include/asm-blackfin/mmu.h30
-rw-r--r--include/asm-blackfin/mmu_context.h129
-rw-r--r--include/asm-blackfin/module.h19
-rw-r--r--include/asm-blackfin/msgbuf.h31
-rw-r--r--include/asm-blackfin/mutex.h9
-rw-r--r--include/asm-blackfin/namei.h19
-rw-r--r--include/asm-blackfin/page.h89
-rw-r--r--include/asm-blackfin/page_offset.h6
-rw-r--r--include/asm-blackfin/param.h22
-rw-r--r--include/asm-blackfin/pci.h148
-rw-r--r--include/asm-blackfin/percpu.h6
-rw-r--r--include/asm-blackfin/pgalloc.h8
-rw-r--r--include/asm-blackfin/pgtable.h96
-rw-r--r--include/asm-blackfin/poll.h24
-rw-r--r--include/asm-blackfin/posix_types.h65
-rw-r--r--include/asm-blackfin/processor.h130
-rw-r--r--include/asm-blackfin/ptrace.h166
-rw-r--r--include/asm-blackfin/resource.h6
-rw-r--r--include/asm-blackfin/scatterlist.h26
-rw-r--r--include/asm-blackfin/sections.h7
-rw-r--r--include/asm-blackfin/segment.h7
-rw-r--r--include/asm-blackfin/semaphore-helper.h82
-rw-r--r--include/asm-blackfin/semaphore.h106
-rw-r--r--include/asm-blackfin/sembuf.h25
-rw-r--r--include/asm-blackfin/setup.h17
-rw-r--r--include/asm-blackfin/shmbuf.h42
-rw-r--r--include/asm-blackfin/shmparam.h6
-rw-r--r--include/asm-blackfin/sigcontext.h55
-rw-r--r--include/asm-blackfin/siginfo.h35
-rw-r--r--include/asm-blackfin/signal.h160
-rw-r--r--include/asm-blackfin/socket.h53
-rw-r--r--include/asm-blackfin/sockios.h13
-rw-r--r--include/asm-blackfin/spinlock.h6
-rw-r--r--include/asm-blackfin/stat.h63
-rw-r--r--include/asm-blackfin/statfs.h6
-rw-r--r--include/asm-blackfin/string.h104
-rw-r--r--include/asm-blackfin/system.h250
-rw-r--r--include/asm-blackfin/termbits.h184
-rw-r--r--include/asm-blackfin/termios.h106
-rw-r--r--include/asm-blackfin/thread_info.h143
-rw-r--r--include/asm-blackfin/timex.h18
-rw-r--r--include/asm-blackfin/tlb.h16
-rw-r--r--include/asm-blackfin/tlbflush.h62
-rw-r--r--include/asm-blackfin/topology.h6
-rw-r--r--include/asm-blackfin/traps.h75
-rw-r--r--include/asm-blackfin/types.h66
-rw-r--r--include/asm-blackfin/uaccess.h271
-rw-r--r--include/asm-blackfin/ucontext.h17
-rw-r--r--include/asm-blackfin/unaligned.h6
-rw-r--r--include/asm-blackfin/unistd.h382
-rw-r--r--include/asm-blackfin/user.h89
141 files changed, 23301 insertions, 0 deletions
diff --git a/include/asm-blackfin/Kbuild b/include/asm-blackfin/Kbuild
new file mode 100644
index 000000000000..c68e1680da01
--- /dev/null
+++ b/include/asm-blackfin/Kbuild
@@ -0,0 +1 @@
include include/asm-generic/Kbuild.asm
diff --git a/include/asm-blackfin/a.out.h b/include/asm-blackfin/a.out.h
new file mode 100644
index 000000000000..d37a6849bf74
--- /dev/null
+++ b/include/asm-blackfin/a.out.h
@@ -0,0 +1,25 @@
1#ifndef __BFIN_A_OUT_H__
2#define __BFIN_A_OUT_H__
3
4struct exec {
5 unsigned long a_info; /* Use macros N_MAGIC, etc for access */
6 unsigned a_text; /* length of text, in bytes */
7 unsigned a_data; /* length of data, in bytes */
8 unsigned a_bss; /* length of uninitialized data area for file, in bytes */
9 unsigned a_syms; /* length of symbol table data in file, in bytes */
10 unsigned a_entry; /* start address */
11 unsigned a_trsize; /* length of relocation info for text, in bytes */
12 unsigned a_drsize; /* length of relocation info for data, in bytes */
13};
14
15#define N_TRSIZE(a) ((a).a_trsize)
16#define N_DRSIZE(a) ((a).a_drsize)
17#define N_SYMSIZE(a) ((a).a_syms)
18
19#ifdef __KERNEL__
20
21#define STACK_TOP TASK_SIZE
22
23#endif
24
25#endif /* __BFIN_A_OUT_H__ */
diff --git a/include/asm-blackfin/atomic.h b/include/asm-blackfin/atomic.h
new file mode 100644
index 000000000000..7cf508718605
--- /dev/null
+++ b/include/asm-blackfin/atomic.h
@@ -0,0 +1,144 @@
1#ifndef __ARCH_BLACKFIN_ATOMIC__
2#define __ARCH_BLACKFIN_ATOMIC__
3
4#include <asm/system.h> /* local_irq_XXX() */
5
6/*
7 * Atomic operations that C can't guarantee us. Useful for
8 * resource counting etc..
9 *
10 * Generally we do not concern about SMP BFIN systems, so we don't have
11 * to deal with that.
12 *
13 * Tony Kou (tonyko@lineo.ca) Lineo Inc. 2001
14 */
15
16typedef struct {
17 int counter;
18} atomic_t;
19#define ATOMIC_INIT(i) { (i) }
20
21#define atomic_read(v) ((v)->counter)
22#define atomic_set(v, i) (((v)->counter) = i)
23
24static __inline__ void atomic_add(int i, atomic_t * v)
25{
26 long flags;
27
28 local_irq_save(flags);
29 v->counter += i;
30 local_irq_restore(flags);
31}
32
33static __inline__ void atomic_sub(int i, atomic_t * v)
34{
35 long flags;
36
37 local_irq_save(flags);
38 v->counter -= i;
39 local_irq_restore(flags);
40
41}
42
43static inline int atomic_add_return(int i, atomic_t * v)
44{
45 int __temp = 0;
46 long flags;
47
48 local_irq_save(flags);
49 v->counter += i;
50 __temp = v->counter;
51 local_irq_restore(flags);
52
53
54 return __temp;
55}
56
57#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
58static inline int atomic_sub_return(int i, atomic_t * v)
59{
60 int __temp = 0;
61 long flags;
62
63 local_irq_save(flags);
64 v->counter -= i;
65 __temp = v->counter;
66 local_irq_restore(flags);
67
68 return __temp;
69}
70
71static __inline__ void atomic_inc(volatile atomic_t * v)
72{
73 long flags;
74
75 local_irq_save(flags);
76 v->counter++;
77 local_irq_restore(flags);
78}
79
80#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
81#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
82
83#define atomic_add_unless(v, a, u) \
84({ \
85 int c, old; \
86 c = atomic_read(v); \
87 while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
88 c = old; \
89 c != (u); \
90})
91#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
92
93static __inline__ void atomic_dec(volatile atomic_t * v)
94{
95 long flags;
96
97 local_irq_save(flags);
98 v->counter--;
99 local_irq_restore(flags);
100}
101
102static __inline__ void atomic_clear_mask(unsigned int mask, atomic_t * v)
103{
104 long flags;
105
106 local_irq_save(flags);
107 v->counter &= ~mask;
108 local_irq_restore(flags);
109}
110
111static __inline__ void atomic_set_mask(unsigned int mask, atomic_t * v)
112{
113 long flags;
114
115 local_irq_save(flags);
116 v->counter |= mask;
117 local_irq_restore(flags);
118}
119
120/* Atomic operations are already serializing */
121#define smp_mb__before_atomic_dec() barrier()
122#define smp_mb__after_atomic_dec() barrier()
123#define smp_mb__before_atomic_inc() barrier()
124#define smp_mb__after_atomic_inc() barrier()
125
126#define atomic_dec_return(v) atomic_sub_return(1,(v))
127#define atomic_inc_return(v) atomic_add_return(1,(v))
128
129/*
130 * atomic_inc_and_test - increment and test
131 * @v: pointer of type atomic_t
132 *
133 * Atomically increments @v by 1
134 * and returns true if the result is zero, or false for all
135 * other cases.
136 */
137#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
138
139#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
140#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
141
142#include <asm-generic/atomic.h>
143
144#endif /* __ARCH_BLACKFIN_ATOMIC __ */
diff --git a/include/asm-blackfin/auxvec.h b/include/asm-blackfin/auxvec.h
new file mode 100644
index 000000000000..215506cd87b7
--- /dev/null
+++ b/include/asm-blackfin/auxvec.h
@@ -0,0 +1,4 @@
1#ifndef __ASMBFIN_AUXVEC_H
2#define __ASMBFIN_AUXVEC_H
3
4#endif
diff --git a/include/asm-blackfin/bf5xx_timers.h b/include/asm-blackfin/bf5xx_timers.h
new file mode 100644
index 000000000000..86c770321b61
--- /dev/null
+++ b/include/asm-blackfin/bf5xx_timers.h
@@ -0,0 +1,209 @@
1/*
2 * include/asm/bf5xx_timers.h
3 *
4 * This file contains the major Data structures and constants
5 * used for General Purpose Timer Implementation in BF5xx
6 *
7 * Copyright (C) 2005 John DeHority
8 * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de)
9 *
10 */
11
12#ifndef _BLACKFIN_TIMERS_H_
13#define _BLACKFIN_TIMERS_H_
14
15#undef MAX_BLACKFIN_GPTIMERS
16/*
17 * BF537: 8 timers:
18 */
19#if defined(CONFIG_BF537)
20# define MAX_BLACKFIN_GPTIMERS 8
21# define TIMER0_GROUP_REG TIMER_ENABLE
22#endif
23/*
24 * BF561: 12 timers:
25 */
26#if defined(CONFIG_BF561)
27# define MAX_BLACKFIN_GPTIMERS 12
28# define TIMER0_GROUP_REG TMRS8_ENABLE
29# define TIMER8_GROUP_REG TMRS4_ENABLE
30#endif
31/*
32 * All others: 3 timers:
33 */
34#if !defined(MAX_BLACKFIN_GPTIMERS)
35# define MAX_BLACKFIN_GPTIMERS 3
36# define TIMER0_GROUP_REG TIMER_ENABLE
37#endif
38
39#define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1)
40#define BFIN_TIMER_OCTET(x) ((x) >> 3)
41
42/* used in masks for timer_enable() and timer_disable() */
43#define TIMER0bit 0x0001 /* 0001b */
44#define TIMER1bit 0x0002 /* 0010b */
45#define TIMER2bit 0x0004 /* 0100b */
46
47#if (MAX_BLACKFIN_GPTIMERS > 3)
48# define TIMER3bit 0x0008
49# define TIMER4bit 0x0010
50# define TIMER5bit 0x0020
51# define TIMER6bit 0x0040
52# define TIMER7bit 0x0080
53#endif
54
55#if (MAX_BLACKFIN_GPTIMERS > 8)
56# define TIMER8bit 0x0100
57# define TIMER9bit 0x0200
58# define TIMER10bit 0x0400
59# define TIMER11bit 0x0800
60#endif
61
62#define TIMER0_id 0
63#define TIMER1_id 1
64#define TIMER2_id 2
65
66#if (MAX_BLACKFIN_GPTIMERS > 3)
67# define TIMER3_id 3
68# define TIMER4_id 4
69# define TIMER5_id 5
70# define TIMER6_id 6
71# define TIMER7_id 7
72#endif
73
74#if (MAX_BLACKFIN_GPTIMERS > 8)
75# define TIMER8_id 8
76# define TIMER9_id 9
77# define TIMER10_id 10
78# define TIMER11_id 11
79#endif
80
81/* associated timers for ppi framesync: */
82
83#if defined(CONFIG_BF561)
84# define FS0_1_TIMER_ID TIMER8_id
85# define FS0_2_TIMER_ID TIMER9_id
86# define FS1_1_TIMER_ID TIMER10_id
87# define FS1_2_TIMER_ID TIMER11_id
88# define FS0_1_TIMER_BIT TIMER8bit
89# define FS0_2_TIMER_BIT TIMER9bit
90# define FS1_1_TIMER_BIT TIMER10bit
91# define FS1_2_TIMER_BIT TIMER11bit
92# undef FS1_TIMER_ID
93# undef FS2_TIMER_ID
94# undef FS1_TIMER_BIT
95# undef FS2_TIMER_BIT
96#else
97# define FS1_TIMER_ID TIMER0_id
98# define FS2_TIMER_ID TIMER1_id
99# define FS1_TIMER_BIT TIMER0bit
100# define FS2_TIMER_BIT TIMER1bit
101#endif
102
103/*
104** Timer Configuration Register Bits
105*/
106#define TIMER_ERR 0xC000
107#define TIMER_ERR_OVFL 0x4000
108#define TIMER_ERR_PROG_PER 0x8000
109#define TIMER_ERR_PROG_PW 0xC000
110#define TIMER_EMU_RUN 0x0200
111#define TIMER_TOGGLE_HI 0x0100
112#define TIMER_CLK_SEL 0x0080
113#define TIMER_OUT_DIS 0x0040
114#define TIMER_TIN_SEL 0x0020
115#define TIMER_IRQ_ENA 0x0010
116#define TIMER_PERIOD_CNT 0x0008
117#define TIMER_PULSE_HI 0x0004
118#define TIMER_MODE 0x0003
119#define TIMER_MODE_PWM 0x0001
120#define TIMER_MODE_WDTH 0x0002
121#define TIMER_MODE_EXT_CLK 0x0003
122
123/*
124** Timer Status Register Bits
125*/
126#define TIMER_STATUS_TIMIL0 0x0001
127#define TIMER_STATUS_TIMIL1 0x0002
128#define TIMER_STATUS_TIMIL2 0x0004
129#if (MAX_BLACKFIN_GPTIMERS > 3)
130# define TIMER_STATUS_TIMIL3 0x00000008
131# define TIMER_STATUS_TIMIL4 0x00010000
132# define TIMER_STATUS_TIMIL5 0x00020000
133# define TIMER_STATUS_TIMIL6 0x00040000
134# define TIMER_STATUS_TIMIL7 0x00080000
135# if (MAX_BLACKFIN_GPTIMERS > 8)
136# define TIMER_STATUS_TIMIL8 0x0001
137# define TIMER_STATUS_TIMIL9 0x0002
138# define TIMER_STATUS_TIMIL10 0x0004
139# define TIMER_STATUS_TIMIL11 0x0008
140# endif
141# define TIMER_STATUS_INTR 0x000F000F
142#else
143# define TIMER_STATUS_INTR 0x0007 /* any timer interrupt */
144#endif
145
146#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */
147#define TIMER_STATUS_TOVF1 0x0020
148#define TIMER_STATUS_TOVF2 0x0040
149#if (MAX_BLACKFIN_GPTIMERS > 3)
150# define TIMER_STATUS_TOVF3 0x00000080
151# define TIMER_STATUS_TOVF4 0x00100000
152# define TIMER_STATUS_TOVF5 0x00200000
153# define TIMER_STATUS_TOVF6 0x00400000
154# define TIMER_STATUS_TOVF7 0x00800000
155# if (MAX_BLACKFIN_GPTIMERS > 8)
156# define TIMER_STATUS_TOVF8 0x0010
157# define TIMER_STATUS_TOVF9 0x0020
158# define TIMER_STATUS_TOVF10 0x0040
159# define TIMER_STATUS_TOVF11 0x0080
160# endif
161# define TIMER_STATUS_OFLOW 0x00F000F0
162#else
163# define TIMER_STATUS_OFLOW 0x0070 /* any timer overflow */
164#endif
165
166/*
167** Timer Slave Enable Status : write 1 to clear
168*/
169#define TIMER_STATUS_TRUN0 0x1000
170#define TIMER_STATUS_TRUN1 0x2000
171#define TIMER_STATUS_TRUN2 0x4000
172#if (MAX_BLACKFIN_GPTIMERS > 3)
173# define TIMER_STATUS_TRUN3 0x00008000
174# define TIMER_STATUS_TRUN4 0x10000000
175# define TIMER_STATUS_TRUN5 0x20000000
176# define TIMER_STATUS_TRUN6 0x40000000
177# define TIMER_STATUS_TRUN7 0x80000000
178# define TIMER_STATUS_TRUN 0xF000F000
179# if (MAX_BLACKFIN_GPTIMERS > 8)
180# define TIMER_STATUS_TRUN8 0x1000
181# define TIMER_STATUS_TRUN9 0x2000
182# define TIMER_STATUS_TRUN10 0x4000
183# define TIMER_STATUS_TRUN11 0x8000
184# endif
185#else
186# define TIMER_STATUS_TRUN 0x7000
187#endif
188
189/*******************************************************************************
190* GP_TIMER API's
191*******************************************************************************/
192
193void set_gptimer_pwidth (int timer_id, int width);
194int get_gptimer_pwidth (int timer_id);
195void set_gptimer_period (int timer_id, int period);
196int get_gptimer_period (int timer_id);
197int get_gptimer_count (int timer_id);
198short get_gptimer_intr (int timer_id);
199void set_gptimer_config (int timer_id, short config);
200short get_gptimer_config (int timer_id);
201void set_gptimer_pulse_hi (int timer_id);
202void clear_gptimer_pulse_hi(int timer_id);
203void enable_gptimers (short mask);
204void disable_gptimers (short mask);
205short get_enabled_timers (void);
206int get_gptimer_status (int octet);
207void set_gptimer_status (int octet, int value);
208
209#endif
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
new file mode 100644
index 000000000000..e37f81609fc3
--- /dev/null
+++ b/include/asm-blackfin/bfin-global.h
@@ -0,0 +1,120 @@
1/*
2 * File: include/asm-blackfin/bfin-global.h
3 * Based on:
4 * Author: *
5 * Created:
6 * Description: Global extern defines for blackfin
7 *
8 * Modified:
9 * Copyright 2004-2006 Analog Devices Inc.
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, see the file COPYING, or write
25 * to the Free Software Foundation, Inc.,
26 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 */
28
29#ifndef _BFIN_GLOBAL_H_
30#define _BFIN_GLOBAL_H_
31
32#ifndef __ASSEMBLY__
33
34#include <asm-generic/sections.h>
35#include <asm/ptrace.h>
36#include <asm/user.h>
37#include <linux/linkage.h>
38#include <linux/types.h>
39
40#if defined(CONFIG_DMA_UNCACHED_2M)
41# define DMA_UNCACHED_REGION (2 * 1024 * 1024)
42#elif defined(CONFIG_DMA_UNCACHED_1M)
43# define DMA_UNCACHED_REGION (1024 * 1024)
44#else
45# define DMA_UNCACHED_REGION (0)
46#endif
47
48extern unsigned long get_cclk(void);
49extern unsigned long get_sclk(void);
50
51extern void dump_thread(struct pt_regs *regs, struct user *dump);
52extern void dump_bfin_regs(struct pt_regs *fp, void *retaddr);
53extern void dump_bfin_trace_buffer(void);
54
55extern int init_arch_irq(void);
56extern void bfin_reset(void);
57extern void _cplb_hdr(void);
58/* Blackfin cache functions */
59extern void bfin_icache_init(void);
60extern void bfin_dcache_init(void);
61extern int read_iloc(void);
62extern int bfin_console_init(void);
63extern asmlinkage void lower_to_irq14(void);
64extern void init_dma(void);
65extern void program_IAR(void);
66extern void evt14_softirq(void);
67extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
68extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type);
69
70extern void *l1_data_A_sram_alloc(size_t);
71extern void *l1_data_B_sram_alloc(size_t);
72extern void *l1_inst_sram_alloc(size_t);
73extern void *l1_data_sram_alloc(size_t);
74extern void *l1_data_sram_zalloc(size_t);
75extern int l1_data_A_sram_free(const void*);
76extern int l1_data_B_sram_free(const void*);
77extern int l1_inst_sram_free(const void*);
78extern int l1_data_sram_free(const void*);
79extern int sram_free(const void*);
80
81#define L1_INST_SRAM 0x00000001
82#define L1_DATA_A_SRAM 0x00000002
83#define L1_DATA_B_SRAM 0x00000004
84#define L1_DATA_SRAM 0x00000006
85extern void *sram_alloc_with_lsl(size_t, unsigned long);
86extern int sram_free_with_lsl(const void*);
87
88extern void led_on(int);
89extern void led_off(int);
90extern void led_toggle(int);
91extern void led_disp_num(int);
92extern void led_toggle_num(int);
93extern void init_leds(void);
94
95extern char *bfin_board_name __attribute__ ((weak));
96extern unsigned long wall_jiffies;
97extern unsigned long ipdt_table[];
98extern unsigned long dpdt_table[];
99extern unsigned long icplb_table[];
100extern unsigned long dcplb_table[];
101
102extern unsigned long ipdt_swapcount_table[];
103extern unsigned long dpdt_swapcount_table[];
104
105extern unsigned long table_start, table_end;
106
107extern struct file_operations dpmc_fops;
108extern char _start;
109extern unsigned long _ramstart, _ramend, _rambase;
110extern unsigned long memory_start, memory_end, physical_mem_end;
111extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
112 _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _ebss_b_l1[];
113
114#ifdef CONFIG_MTD_UCLINUX
115extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
116#endif
117
118#endif
119
120#endif /* _BLACKFIN_H_ */
diff --git a/include/asm-blackfin/bfin5xx_spi.h b/include/asm-blackfin/bfin5xx_spi.h
new file mode 100644
index 000000000000..95c1c952e7c1
--- /dev/null
+++ b/include/asm-blackfin/bfin5xx_spi.h
@@ -0,0 +1,170 @@
1/************************************************************
2*
3* Copyright (C) 2004, Analog Devices. All Rights Reserved
4*
5* FILE bfin5xx_spi.h
6* PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
7*
8*
9* DATE OF CREATION: March. 10th 2006
10*
11* SYNOPSIS:
12*
13* DESCRIPTION: header file for SPI controller driver for Blackfin5xx.
14**************************************************************
15
16* MODIFICATION HISTORY:
17* March 10, 2006 bfin5xx_spi.h Created. (Luke Yang)
18
19************************************************************/
20
21#ifndef _SPI_CHANNEL_H_
22#define _SPI_CHANNEL_H_
23
24#define SPI0_REGBASE 0xffc00500
25
26#define SPI_READ 0
27#define SPI_WRITE 1
28
29#define SPI_CTRL_OFF 0x0
30#define SPI_FLAG_OFF 0x4
31#define SPI_STAT_OFF 0x8
32#define SPI_TXBUFF_OFF 0xc
33#define SPI_RXBUFF_OFF 0x10
34#define SPI_BAUD_OFF 0x14
35#define SPI_SHAW_OFF 0x18
36
37#define CMD_SPI_OUT_ENABLE 1
38#define CMD_SPI_SET_BAUDRATE 2
39#define CMD_SPI_SET_POLAR 3
40#define CMD_SPI_SET_PHASE 4
41#define CMD_SPI_SET_MASTER 5
42#define CMD_SPI_SET_SENDOPT 6
43#define CMD_SPI_SET_RECVOPT 7
44#define CMD_SPI_SET_ORDER 8
45#define CMD_SPI_SET_LENGTH16 9
46#define CMD_SPI_GET_STAT 11
47#define CMD_SPI_GET_CFG 12
48#define CMD_SPI_SET_CSAVAIL 13
49#define CMD_SPI_SET_CSHIGH 14 /* CS unavail */
50#define CMD_SPI_SET_CSLOW 15 /* CS avail */
51#define CMD_SPI_MISO_ENABLE 16
52#define CMD_SPI_SET_CSENABLE 17
53#define CMD_SPI_SET_CSDISABLE 18
54
55#define CMD_SPI_SET_TRIGGER_MODE 19
56#define CMD_SPI_SET_TRIGGER_SENSE 20
57#define CMD_SPI_SET_TRIGGER_EDGE 21
58#define CMD_SPI_SET_TRIGGER_LEVEL 22
59
60#define CMD_SPI_SET_TIME_SPS 23
61#define CMD_SPI_SET_TIME_SAMPLES 24
62#define CMD_SPI_GET_SYSTEMCLOCK 25
63
64#define CMD_SPI_SET_WRITECONTINUOUS 26
65#define CMD_SPI_SET_SKFS 27
66
67#define CMD_SPI_GET_ALLCONFIG 32 /* For debug */
68
69#define SPI_DEFAULT_BARD 0x0100
70
71#define SPI0_IRQ_NUM IRQ_SPI
72#define SPI_ERR_TRIG -1
73
74#define BIT_CTL_ENABLE 0x4000
75#define BIT_CTL_OPENDRAIN 0x2000
76#define BIT_CTL_MASTER 0x1000
77#define BIT_CTL_POLAR 0x0800
78#define BIT_CTL_PHASE 0x0400
79#define BIT_CTL_BITORDER 0x0200
80#define BIT_CTL_WORDSIZE 0x0100
81#define BIT_CTL_MISOENABLE 0x0020
82#define BIT_CTL_RXMOD 0x0000
83#define BIT_CTL_TXMOD 0x0001
84#define BIT_CTL_TIMOD_DMA_TX 0x0003
85#define BIT_CTL_TIMOD_DMA_RX 0x0002
86#define BIT_CTL_SENDOPT 0x0004
87#define BIT_CTL_TIMOD 0x0003
88
89#define BIT_STAT_SPIF 0x0001
90#define BIT_STAT_MODF 0x0002
91#define BIT_STAT_TXE 0x0004
92#define BIT_STAT_TXS 0x0008
93#define BIT_STAT_RBSY 0x0010
94#define BIT_STAT_RXS 0x0020
95#define BIT_STAT_TXCOL 0x0040
96#define BIT_STAT_CLR 0xFFFF
97
98#define BIT_STU_SENDOVER 0x0001
99#define BIT_STU_RECVFULL 0x0020
100
101#define CFG_SPI_ENABLE 1
102#define CFG_SPI_DISABLE 0
103
104#define CFG_SPI_OUTENABLE 1
105#define CFG_SPI_OUTDISABLE 0
106
107#define CFG_SPI_ACTLOW 1
108#define CFG_SPI_ACTHIGH 0
109
110#define CFG_SPI_PHASESTART 1
111#define CFG_SPI_PHASEMID 0
112
113#define CFG_SPI_MASTER 1
114#define CFG_SPI_SLAVE 0
115
116#define CFG_SPI_SENELAST 0
117#define CFG_SPI_SENDZERO 1
118
119#define CFG_SPI_RCVFLUSH 1
120#define CFG_SPI_RCVDISCARD 0
121
122#define CFG_SPI_LSBFIRST 1
123#define CFG_SPI_MSBFIRST 0
124
125#define CFG_SPI_WORDSIZE16 1
126#define CFG_SPI_WORDSIZE8 0
127
128#define CFG_SPI_MISOENABLE 1
129#define CFG_SPI_MISODISABLE 0
130
131#define CFG_SPI_READ 0x00
132#define CFG_SPI_WRITE 0x01
133#define CFG_SPI_DMAREAD 0x02
134#define CFG_SPI_DMAWRITE 0x03
135
136#define CFG_SPI_CSCLEARALL 0
137#define CFG_SPI_CHIPSEL1 1
138#define CFG_SPI_CHIPSEL2 2
139#define CFG_SPI_CHIPSEL3 3
140#define CFG_SPI_CHIPSEL4 4
141#define CFG_SPI_CHIPSEL5 5
142#define CFG_SPI_CHIPSEL6 6
143#define CFG_SPI_CHIPSEL7 7
144
145#define CFG_SPI_CS1VALUE 1
146#define CFG_SPI_CS2VALUE 2
147#define CFG_SPI_CS3VALUE 3
148#define CFG_SPI_CS4VALUE 4
149#define CFG_SPI_CS5VALUE 5
150#define CFG_SPI_CS6VALUE 6
151#define CFG_SPI_CS7VALUE 7
152
153/* device.platform_data for SSP controller devices */
154struct bfin5xx_spi_master {
155 u16 num_chipselect;
156 u8 enable_dma;
157};
158
159/* spi_board_info.controller_data for SPI slave devices,
160 * copied to spi_device.platform_data ... mostly for dma tuning
161 */
162struct bfin5xx_spi_chip {
163 u16 ctl_reg;
164 u8 enable_dma;
165 u8 bits_per_word;
166 u8 cs_change_per_word;
167 u8 cs_chg_udelay;
168};
169
170#endif /* _SPI_CHANNEL_H_ */
diff --git a/include/asm-blackfin/bfin_simple_timer.h b/include/asm-blackfin/bfin_simple_timer.h
new file mode 100644
index 000000000000..fccbb595464a
--- /dev/null
+++ b/include/asm-blackfin/bfin_simple_timer.h
@@ -0,0 +1,13 @@
1#ifndef _bfin_simple_timer_h_
2#define _bfin_simple_timer_h_
3
4#include <linux/ioctl.h>
5
6#define BFIN_SIMPLE_TIMER_IOCTL_MAGIC 't'
7
8#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 2)
9#define BFIN_SIMPLE_TIMER_START _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6)
10#define BFIN_SIMPLE_TIMER_STOP _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8)
11#define BFIN_SIMPLE_TIMER_READ _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10)
12
13#endif
diff --git a/include/asm-blackfin/bfin_sport.h b/include/asm-blackfin/bfin_sport.h
new file mode 100644
index 000000000000..c76ed8def302
--- /dev/null
+++ b/include/asm-blackfin/bfin_sport.h
@@ -0,0 +1,175 @@
1/*
2 * File: include/asm-blackfin/bfin_sport.h
3 * Based on:
4 * Author: Roy Huang (roy.huang@analog.com)
5 *
6 * Created: Thu Aug. 24 2006
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __BFIN_SPORT_H__
31#define __BFIN_SPORT_H__
32
33#define SPORT_MAJOR 237
34#define SPORT_NR_DEVS 2
35
36/* Sport mode: it can be set to TDM, i2s or others */
37#define NORM_MODE 0x0
38#define TDM_MODE 0x1
39#define I2S_MODE 0x2
40
41/* Data format, normal, a-law or u-law */
42#define NORM_FORMAT 0x0
43#define ALAW_FORMAT 0x2
44#define ULAW_FORMAT 0x3
45struct sport_register;
46
47/* Function driver which use sport must initialize the structure */
48struct sport_config {
49 /*TDM (multichannels), I2S or other mode */
50 unsigned int mode:3;
51
52 /* if TDM mode is selected, channels must be set */
53 int channels; /* Must be in 8 units */
54 unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
55
56 /* I2S mode */
57 unsigned int right_first:1; /* Right stereo channel first */
58
59 /* In mormal mode, the following item need to be set */
60 unsigned int lsb_first:1; /* order of transmit or receive data */
61 unsigned int fsync:1; /* Frame sync required */
62 unsigned int data_indep:1; /* data independent frame sync generated */
63 unsigned int act_low:1; /* Active low TFS */
64 unsigned int late_fsync:1; /* Late frame sync */
65 unsigned int tckfe:1;
66 unsigned int sec_en:1; /* Secondary side enabled */
67
68 /* Choose clock source */
69 unsigned int int_clk:1; /* Internal or external clock */
70
71 /* If external clock is used, the following fields are ignored */
72 int serial_clk;
73 int fsync_clk;
74
75 unsigned int data_format:2; /*Normal, u-law or a-law */
76
77 int word_len; /* How length of the word in bits, 3-32 bits */
78 int dma_enabled;
79};
80
81struct sport_register {
82 unsigned short tcr1;
83 unsigned short reserved0;
84 unsigned short tcr2;
85 unsigned short reserved1;
86 unsigned short tclkdiv;
87 unsigned short reserved2;
88 unsigned short tfsdiv;
89 unsigned short reserved3;
90 unsigned long tx;
91 unsigned long reserved_l0;
92 unsigned long rx;
93 unsigned long reserved_l1;
94 unsigned short rcr1;
95 unsigned short reserved4;
96 unsigned short rcr2;
97 unsigned short reserved5;
98 unsigned short rclkdiv;
99 unsigned short reserved6;
100 unsigned short rfsdiv;
101 unsigned short reserved7;
102 unsigned short stat;
103 unsigned short reserved8;
104 unsigned short chnl;
105 unsigned short reserved9;
106 unsigned short mcmc1;
107 unsigned short reserved10;
108 unsigned short mcmc2;
109 unsigned short reserved11;
110 unsigned long mtcs0;
111 unsigned long mtcs1;
112 unsigned long mtcs2;
113 unsigned long mtcs3;
114 unsigned long mrcs0;
115 unsigned long mrcs1;
116 unsigned long mrcs2;
117 unsigned long mrcs3;
118};
119
120#define SPORT_IOC_MAGIC 'P'
121#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
122
123/* Test purpose */
124#define ENABLE_AD73311 _IOWR('P', 0x02, int)
125
126struct sport_dev {
127 struct cdev cdev; /* Char device structure */
128
129 int sport_num;
130
131 int dma_rx_chan;
132 int dma_tx_chan;
133
134 int rx_irq;
135 unsigned char *rx_buf; /* Buffer store the received data */
136 int rx_len; /* How many bytes will be received */
137 int rx_received; /* How many bytes has been received */
138
139 int tx_irq;
140 const unsigned char *tx_buf;
141 int tx_len;
142 int tx_sent;
143
144 int sport_err_irq;
145
146 struct mutex mutex; /* mutual exclusion semaphore */
147 struct task_struct *task;
148
149 wait_queue_head_t waitq;
150 int wait_con;
151 struct sport_register *regs;
152 struct sport_config config;
153};
154
155#define SPORT_TCR1 0
156#define SPORT_TCR2 1
157#define SPORT_TCLKDIV 2
158#define SPORT_TFSDIV 3
159#define SPORT_RCR1 8
160#define SPORT_RCR2 9
161#define SPORT_RCLKDIV 10
162#define SPORT_RFSDIV 11
163#define SPORT_CHANNEL 13
164#define SPORT_MCMC1 14
165#define SPORT_MCMC2 15
166#define SPORT_MTCS0 16
167#define SPORT_MTCS1 17
168#define SPORT_MTCS2 18
169#define SPORT_MTCS3 19
170#define SPORT_MRCS0 20
171#define SPORT_MRCS1 21
172#define SPORT_MRCS2 22
173#define SPORT_MRCS3 23
174
175#endif /*__BFIN_SPORT_H__*/
diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h
new file mode 100644
index 000000000000..27c2d0e48e1b
--- /dev/null
+++ b/include/asm-blackfin/bitops.h
@@ -0,0 +1,213 @@
1#ifndef _BLACKFIN_BITOPS_H
2#define _BLACKFIN_BITOPS_H
3
4/*
5 * Copyright 1992, Linus Torvalds.
6 */
7
8#include <linux/compiler.h>
9#include <asm/byteorder.h> /* swab32 */
10#include <asm/system.h> /* save_flags */
11
12#ifdef __KERNEL__
13
14#include <asm-generic/bitops/ffs.h>
15#include <asm-generic/bitops/__ffs.h>
16#include <asm-generic/bitops/sched.h>
17#include <asm-generic/bitops/ffz.h>
18
19static __inline__ void set_bit(int nr, volatile unsigned long *addr)
20{
21 int *a = (int *)addr;
22 int mask;
23 unsigned long flags;
24
25 a += nr >> 5;
26 mask = 1 << (nr & 0x1f);
27 local_irq_save(flags);
28 *a |= mask;
29 local_irq_restore(flags);
30}
31
32static __inline__ void __set_bit(int nr, volatile unsigned long *addr)
33{
34 int *a = (int *)addr;
35 int mask;
36
37 a += nr >> 5;
38 mask = 1 << (nr & 0x1f);
39 *a |= mask;
40}
41
42/*
43 * clear_bit() doesn't provide any barrier for the compiler.
44 */
45#define smp_mb__before_clear_bit() barrier()
46#define smp_mb__after_clear_bit() barrier()
47
48static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
49{
50 int *a = (int *)addr;
51 int mask;
52 unsigned long flags;
53 a += nr >> 5;
54 mask = 1 << (nr & 0x1f);
55 local_irq_save(flags);
56 *a &= ~mask;
57 local_irq_restore(flags);
58}
59
60static __inline__ void __clear_bit(int nr, volatile unsigned long *addr)
61{
62 int *a = (int *)addr;
63 int mask;
64
65 a += nr >> 5;
66 mask = 1 << (nr & 0x1f);
67 *a &= ~mask;
68}
69
70static __inline__ void change_bit(int nr, volatile unsigned long *addr)
71{
72 int mask, flags;
73 unsigned long *ADDR = (unsigned long *)addr;
74
75 ADDR += nr >> 5;
76 mask = 1 << (nr & 31);
77 local_irq_save(flags);
78 *ADDR ^= mask;
79 local_irq_restore(flags);
80}
81
82static __inline__ void __change_bit(int nr, volatile unsigned long *addr)
83{
84 int mask;
85 unsigned long *ADDR = (unsigned long *)addr;
86
87 ADDR += nr >> 5;
88 mask = 1 << (nr & 31);
89 *ADDR ^= mask;
90}
91
92static __inline__ int test_and_set_bit(int nr, void *addr)
93{
94 int mask, retval;
95 volatile unsigned int *a = (volatile unsigned int *)addr;
96 unsigned long flags;
97
98 a += nr >> 5;
99 mask = 1 << (nr & 0x1f);
100 local_irq_save(flags);
101 retval = (mask & *a) != 0;
102 *a |= mask;
103 local_irq_restore(flags);
104
105 return retval;
106}
107
108static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr)
109{
110 int mask, retval;
111 volatile unsigned int *a = (volatile unsigned int *)addr;
112
113 a += nr >> 5;
114 mask = 1 << (nr & 0x1f);
115 retval = (mask & *a) != 0;
116 *a |= mask;
117 return retval;
118}
119
120static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr)
121{
122 int mask, retval;
123 volatile unsigned int *a = (volatile unsigned int *)addr;
124 unsigned long flags;
125
126 a += nr >> 5;
127 mask = 1 << (nr & 0x1f);
128 local_irq_save(flags);
129 retval = (mask & *a) != 0;
130 *a &= ~mask;
131 local_irq_restore(flags);
132
133 return retval;
134}
135
136static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr)
137{
138 int mask, retval;
139 volatile unsigned int *a = (volatile unsigned int *)addr;
140
141 a += nr >> 5;
142 mask = 1 << (nr & 0x1f);
143 retval = (mask & *a) != 0;
144 *a &= ~mask;
145 return retval;
146}
147
148static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr)
149{
150 int mask, retval;
151 volatile unsigned int *a = (volatile unsigned int *)addr;
152 unsigned long flags;
153
154 a += nr >> 5;
155 mask = 1 << (nr & 0x1f);
156 local_irq_save(flags);
157 retval = (mask & *a) != 0;
158 *a ^= mask;
159 local_irq_restore(flags);
160 return retval;
161}
162
163static __inline__ int __test_and_change_bit(int nr,
164 volatile unsigned long *addr)
165{
166 int mask, retval;
167 volatile unsigned int *a = (volatile unsigned int *)addr;
168
169 a += nr >> 5;
170 mask = 1 << (nr & 0x1f);
171 retval = (mask & *a) != 0;
172 *a ^= mask;
173 return retval;
174}
175
176/*
177 * This routine doesn't need to be atomic.
178 */
179static __inline__ int __constant_test_bit(int nr, const void *addr)
180{
181 return ((1UL << (nr & 31)) &
182 (((const volatile unsigned int *)addr)[nr >> 5])) != 0;
183}
184
185static __inline__ int __test_bit(int nr, const void *addr)
186{
187 int *a = (int *)addr;
188 int mask;
189
190 a += nr >> 5;
191 mask = 1 << (nr & 0x1f);
192 return ((mask & *a) != 0);
193}
194
195#define test_bit(nr,addr) \
196(__builtin_constant_p(nr) ? \
197 __constant_test_bit((nr),(addr)) : \
198 __test_bit((nr),(addr)))
199
200#include <asm-generic/bitops/find.h>
201#include <asm-generic/bitops/hweight.h>
202
203#include <asm-generic/bitops/ext2-atomic.h>
204#include <asm-generic/bitops/ext2-non-atomic.h>
205
206#include <asm-generic/bitops/minix.h>
207
208#endif /* __KERNEL__ */
209
210#include <asm-generic/bitops/fls.h>
211#include <asm-generic/bitops/fls64.h>
212
213#endif /* _BLACKFIN_BITOPS_H */
diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h
new file mode 100644
index 000000000000..14e58de73973
--- /dev/null
+++ b/include/asm-blackfin/blackfin.h
@@ -0,0 +1,81 @@
1/*
2 * Common header file for blackfin family of processors.
3 *
4 */
5
6#ifndef _BLACKFIN_H_
7#define _BLACKFIN_H_
8
9#include <asm/macros.h>
10#include <asm/mach/blackfin.h>
11#include <asm/bfin-global.h>
12
13#ifndef __ASSEMBLY__
14
15/* SSYNC implementation for C file */
16#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
17static inline void SSYNC (void)
18{
19 int _tmp;
20 __asm__ __volatile__ ("cli %0;\n\t"
21 "nop;nop;\n\t"
22 "ssync;\n\t"
23 "sti %0;\n\t"
24 :"=d"(_tmp):);
25}
26#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
27static inline void SSYNC (void)
28{
29 int _tmp;
30 __asm__ __volatile__ ("cli %0;\n\t"
31 "ssync;\n\t"
32 "sti %0;\n\t"
33 :"=d"(_tmp):);
34}
35#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
36static inline void SSYNC (void)
37{
38 __builtin_bfin_ssync();
39}
40#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
41static inline void SSYNC (void)
42{
43 __asm__ __volatile__ ("ssync;\n\t");
44}
45#endif
46
47/* CSYNC implementation for C file */
48#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
49static inline void CSYNC (void)
50{
51 int _tmp;
52 __asm__ __volatile__ ("cli %0;\n\t"
53 "nop;nop;\n\t"
54 "csync;\n\t"
55 "sti %0;\n\t"
56 :"=d"(_tmp):);
57}
58#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
59static inline void CSYNC (void)
60{
61 int _tmp;
62 __asm__ __volatile__ ("cli %0;\n\t"
63 "csync;\n\t"
64 "sti %0;\n\t"
65 :"=d"(_tmp):);
66}
67#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
68static inline void CSYNC (void)
69{
70 __builtin_bfin_csync();
71}
72#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
73static inline void CSYNC (void)
74{
75 __asm__ __volatile__ ("csync;\n\t");
76}
77#endif
78
79#endif /* __ASSEMBLY__ */
80
81#endif /* _BLACKFIN_H_ */
diff --git a/include/asm-blackfin/bug.h b/include/asm-blackfin/bug.h
new file mode 100644
index 000000000000..41e53b29f167
--- /dev/null
+++ b/include/asm-blackfin/bug.h
@@ -0,0 +1,4 @@
1#ifndef _BLACKFIN_BUG_H
2#define _BLACKFIN_BUG_H
3#include <asm-generic/bug.h>
4#endif
diff --git a/include/asm-blackfin/bugs.h b/include/asm-blackfin/bugs.h
new file mode 100644
index 000000000000..9093c9c1fb81
--- /dev/null
+++ b/include/asm-blackfin/bugs.h
@@ -0,0 +1,16 @@
1/*
2 * include/asm-blackfin/bugs.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7/*
8 * This is included by init/main.c to check for architecture-dependent bugs.
9 *
10 * Needs:
11 * void check_bugs(void);
12 */
13
14static void check_bugs(void)
15{
16}
diff --git a/include/asm-blackfin/byteorder.h b/include/asm-blackfin/byteorder.h
new file mode 100644
index 000000000000..6a673d42da18
--- /dev/null
+++ b/include/asm-blackfin/byteorder.h
@@ -0,0 +1,48 @@
1#ifndef _BLACKFIN_BYTEORDER_H
2#define _BLACKFIN_BYTEORDER_H
3
4#include <asm/types.h>
5#include <linux/compiler.h>
6
7#ifdef __GNUC__
8
9static __inline__ __attribute_const__ __u32 ___arch__swahb32(__u32 xx)
10{
11 __u32 tmp;
12 __asm__("%1 = %0 >> 8 (V);\n\t"
13 "%0 = %0 << 8 (V);\n\t"
14 "%0 = %0 | %1;\n\t"
15 : "+d"(xx), "=&d"(tmp));
16 return xx;
17}
18
19static __inline__ __attribute_const__ __u32 ___arch__swahw32(__u32 xx)
20{
21 __u32 rv;
22 __asm__("%0 = PACK(%1.L, %1.H);\n\t": "=d"(rv): "d"(xx));
23 return rv;
24}
25
26#define __arch__swahb32(x) ___arch__swahb32(x)
27#define __arch__swahw32(x) ___arch__swahw32(x)
28#define __arch__swab32(x) ___arch__swahb32(___arch__swahw32(x))
29
30static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 xx)
31{
32 __u32 xw = xx;
33 __asm__("%0 <<= 8;\n %0.L = %0.L + %0.H (NS);\n": "+d"(xw));
34 return (__u16)xw;
35}
36
37#define __arch__swab16(x) ___arch__swab16(x)
38
39#endif
40
41#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
42# define __BYTEORDER_HAS_U64__
43# define __SWAB_64_THRU_32__
44#endif
45
46#include <linux/byteorder/little_endian.h>
47
48#endif /* _BLACKFIN_BYTEORDER_H */
diff --git a/include/asm-blackfin/cache.h b/include/asm-blackfin/cache.h
new file mode 100644
index 000000000000..023d72133b5a
--- /dev/null
+++ b/include/asm-blackfin/cache.h
@@ -0,0 +1,29 @@
1/*
2 * include/asm-blackfin/cache.h
3 */
4#ifndef __ARCH_BLACKFIN_CACHE_H
5#define __ARCH_BLACKFIN_CACHE_H
6
7/*
8 * Bytes per L1 cache line
9 * Blackfin loads 32 bytes for cache
10 */
11#define L1_CACHE_SHIFT 5
12#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
13#define SMP_CACHE_BYTES L1_CACHE_BYTES
14
15/*
16 * Put cacheline_aliged data to L1 data memory
17 */
18#ifdef CONFIG_CACHELINE_ALIGNED_L1
19#define __cacheline_aligned \
20 __attribute__((__aligned__(L1_CACHE_BYTES), \
21 __section__(".data_l1.cacheline_aligned")))
22#endif
23
24/*
25 * largest L1 which this arch supports
26 */
27#define L1_CACHE_SHIFT_MAX 5
28
29#endif
diff --git a/include/asm-blackfin/cacheflush.h b/include/asm-blackfin/cacheflush.h
new file mode 100644
index 000000000000..e5e000de3c36
--- /dev/null
+++ b/include/asm-blackfin/cacheflush.h
@@ -0,0 +1,90 @@
1/*
2 * File: include/asm-blackfin/cacheflush.h
3 * Based on: include/asm-m68knommu/cacheflush.h
4 * Author: LG Soft India
5 * Copyright (C) 2004 Analog Devices Inc.
6 * Created: Tue Sep 21 2004
7 * Description: Blackfin low-level cache routines adapted from the i386
8 * and PPC versions by Greg Ungerer (gerg@snapgear.com)
9 *
10 * Modified:
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2, or (at your option)
17 * any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; see the file COPYING.
26 * If not, write to the Free Software Foundation,
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 */
29
30#ifndef _BLACKFIN_CACHEFLUSH_H
31#define _BLACKFIN_CACHEFLUSH_H
32
33#include <asm/cplb.h>
34
35extern void blackfin_icache_dcache_flush_range(unsigned int, unsigned int);
36extern void blackfin_icache_flush_range(unsigned int, unsigned int);
37extern void blackfin_dcache_flush_range(unsigned int, unsigned int);
38extern void blackfin_dcache_invalidate_range(unsigned int, unsigned int);
39extern void blackfin_dflush_page(void *);
40
41#define flush_dcache_mmap_lock(mapping) do { } while (0)
42#define flush_dcache_mmap_unlock(mapping) do { } while (0)
43#define flush_cache_mm(mm) do { } while (0)
44#define flush_cache_range(vma, start, end) do { } while (0)
45#define flush_cache_page(vma, vmaddr) do { } while (0)
46#define flush_cache_vmap(start, end) do { } while (0)
47#define flush_cache_vunmap(start, end) do { } while (0)
48
49static inline void flush_icache_range(unsigned start, unsigned end)
50{
51#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_CACHE)
52
53# if defined(CONFIG_BLKFIN_WT)
54 blackfin_icache_flush_range((start), (end));
55# else
56 blackfin_icache_dcache_flush_range((start), (end));
57# endif
58
59#else
60
61# if defined(CONFIG_BLKFIN_CACHE)
62 blackfin_icache_flush_range((start), (end));
63# endif
64# if defined(CONFIG_BLKFIN_DCACHE)
65 blackfin_dcache_flush_range((start), (end));
66# endif
67
68#endif
69}
70
71#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
72do { memcpy(dst, src, len); \
73 flush_icache_range ((unsigned) (dst), (unsigned) (dst) + (len)); \
74} while (0)
75#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
76
77#if defined(CONFIG_BLKFIN_DCACHE)
78# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end))
79#else
80# define invalidate_dcache_range(start,end) do { } while (0)
81#endif
82#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_WB)
83# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
84# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
85#else
86# define flush_dcache_range(start,end) do { } while (0)
87# define flush_dcache_page(page) do { } while (0)
88#endif
89
90#endif /* _BLACKFIN_CACHEFLUSH_H */
diff --git a/include/asm-blackfin/checksum.h b/include/asm-blackfin/checksum.h
new file mode 100644
index 000000000000..2638f2586d2f
--- /dev/null
+++ b/include/asm-blackfin/checksum.h
@@ -0,0 +1,101 @@
1#ifndef _BFIN_CHECKSUM_H
2#define _BFIN_CHECKSUM_H
3
4/*
5 * MODIFIED FOR BFIN April 30, 2001 akbar.hussain@lineo.com
6 *
7 * computes the checksum of a memory block at buff, length len,
8 * and adds in "sum" (32-bit)
9 *
10 * returns a 32-bit number suitable for feeding into itself
11 * or csum_tcpudp_magic
12 *
13 * this function must be called with even lengths, except
14 * for the last fragment, which may be odd
15 *
16 * it's best to have buff aligned on a 32-bit boundary
17 */
18unsigned int csum_partial(const unsigned char *buff, int len, unsigned int sum);
19
20/*
21 * the same as csum_partial, but copies from src while it
22 * checksums
23 *
24 * here even more important to align src and dst on a 32-bit (or even
25 * better 64-bit) boundary
26 */
27
28unsigned int csum_partial_copy(const unsigned char *src, unsigned char *dst,
29 int len, int sum);
30
31/*
32 * the same as csum_partial_copy, but copies from user space.
33 *
34 * here even more important to align src and dst on a 32-bit (or even
35 * better 64-bit) boundary
36 */
37
38extern unsigned int csum_partial_copy_from_user(const unsigned char *src,
39 unsigned char *dst, int len,
40 int sum, int *csum_err);
41
42#define csum_partial_copy_nocheck(src, dst, len, sum) \
43 csum_partial_copy((src), (dst), (len), (sum))
44
45unsigned short ip_fast_csum(unsigned char *iph, unsigned int ihl);
46
47/*
48 * Fold a partial checksum
49 */
50
51static inline unsigned int csum_fold(unsigned int sum)
52{
53 while (sum >> 16)
54 sum = (sum & 0xffff) + (sum >> 16);
55 return ((~(sum << 16)) >> 16);
56}
57
58/*
59 * computes the checksum of the TCP/UDP pseudo-header
60 * returns a 16-bit checksum, already complemented
61 */
62
63static inline unsigned int
64csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr, unsigned short len,
65 unsigned short proto, unsigned int sum)
66{
67
68 __asm__ ("%0 = %0 + %1;\n\t"
69 "CC = AC0;\n\t"
70 "if !CC jump 4;\n\t"
71 "%0 = %0 + %4;\n\t"
72 "%0 = %0 + %2;\n\t"
73 "CC = AC0;\n\t"
74 "if !CC jump 4;\n\t"
75 "%0 = %0 + %4;\n\t"
76 "%0 = %0 + %3;\n\t"
77 "CC = AC0;\n\t"
78 "if !CC jump 4;\n\t"
79 "%0 = %0 + %4;\n\t"
80 "NOP;\n\t"
81 : "=d" (sum)
82 : "d" (daddr), "d" (saddr), "d" ((ntohs(len)<<16)+proto*256), "d" (1), "0"(sum));
83
84 return (sum);
85}
86
87static inline unsigned short int
88csum_tcpudp_magic(unsigned long saddr, unsigned long daddr, unsigned short len,
89 unsigned short proto, unsigned int sum)
90{
91 return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
92}
93
94/*
95 * this routine is used for miscellaneous IP-like checksums, mainly
96 * in icmp.c
97 */
98
99extern unsigned short ip_compute_csum(const unsigned char *buff, int len);
100
101#endif /* _BFIN_CHECKSUM_H */
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
new file mode 100644
index 000000000000..e0dd56bfa4c7
--- /dev/null
+++ b/include/asm-blackfin/cplb.h
@@ -0,0 +1,51 @@
1/************************************************************************
2 *
3 * cplb.h
4 *
5 * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
6 *
7 ************************************************************************/
8
9/* Defines necessary for cplb initialisation routines. */
10
11#ifndef _CPLB_H
12#define _CPLB_H
13
14# include <asm/blackfin.h>
15
16#define CPLB_ENABLE_ICACHE_P 0
17#define CPLB_ENABLE_DCACHE_P 1
18#define CPLB_ENABLE_DCACHE2_P 2
19#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
20#define CPLB_ENABLE_ICPLBS_P 4
21#define CPLB_ENABLE_DCPLBS_P 5
22
23#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
24#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
25#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
26#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
27#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
28#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
29#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
30 CPLB_ENABLE_ICPLBS | \
31 CPLB_ENABLE_DCPLBS
32
33#define CPLB_RELOADED 0x0000
34#define CPLB_NO_UNLOCKED 0x0001
35#define CPLB_NO_ADDR_MATCH 0x0002
36#define CPLB_PROT_VIOL 0x0003
37#define CPLB_UNKNOWN_ERR 0x0004
38
39#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
40#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
41
42#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
43
44#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
45#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
46#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
47#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
48#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
49#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
50
51#endif /* _CPLB_H */
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
new file mode 100644
index 000000000000..3bad2d1e6a8c
--- /dev/null
+++ b/include/asm-blackfin/cplbinit.h
@@ -0,0 +1,203 @@
1/*
2 * File: include/asm-blackfin/cplbinit.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <asm/blackfin.h>
31#include <asm/cplb.h>
32
33#define INITIAL_T 0x1
34#define SWITCH_T 0x2
35#define I_CPLB 0x4
36#define D_CPLB 0x8
37
38#define IN_KERNEL 1
39
40enum
41{ZERO_P, L1I_MEM, L1D_MEM, SDRAM_KERN , SDRAM_RAM_MTD, SDRAM_DMAZ, RES_MEM, ASYNC_MEM, L2_MEM};
42
43struct cplb_desc {
44 u32 start; /* start address */
45 u32 end; /* end address */
46 u32 psize; /* prefered size if any otherwise 1MB or 4MB*/
47 u16 attr;/* attributes */
48 u16 i_conf;/* I-CPLB DATA */
49 u16 d_conf;/* D-CPLB DATA */
50 u16 valid;/* valid */
51 const s8 name[30];/* name */
52};
53
54struct cplb_tab {
55 u_long *tab;
56 u16 pos;
57 u16 size;
58};
59
60u_long icplb_table[MAX_CPLBS+1];
61u_long dcplb_table[MAX_CPLBS+1];
62
63/* Till here we are discussing about the static memory management model.
64 * However, the operating envoronments commonly define more CPLB
65 * descriptors to cover the entire addressable memory than will fit into
66 * the available on-chip 16 CPLB MMRs. When this happens, the below table
67 * will be used which will hold all the potentially required CPLB descriptors
68 *
69 * This is how Page descriptor Table is implemented in uClinux/Blackfin.
70 */
71
72#ifdef CONFIG_CPLB_SWITCH_TAB_L1
73u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
74u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
75
76#ifdef CONFIG_CPLB_INFO
77u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
78u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
79#endif /* CONFIG_CPLB_INFO */
80
81#else
82
83u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
84u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
85
86#ifdef CONFIG_CPLB_INFO
87u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
88u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
89#endif /* CONFIG_CPLB_INFO */
90
91#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
92
93struct s_cplb {
94 struct cplb_tab init_i;
95 struct cplb_tab init_d;
96 struct cplb_tab switch_i;
97 struct cplb_tab switch_d;
98};
99
100#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
101static struct cplb_desc cplb_data[] = {
102 {
103 .start = 0,
104 .end = SIZE_4K,
105 .psize = SIZE_4K,
106 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
107 .i_conf = SDRAM_OOPS,
108 .d_conf = SDRAM_OOPS,
109#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
110 .valid = 1,
111#else
112 .valid = 0,
113#endif
114 .name = "ZERO Pointer Saveguard",
115 },
116 {
117 .start = L1_CODE_START,
118 .end = L1_CODE_START + L1_CODE_LENGTH,
119 .psize = SIZE_4M,
120 .attr = INITIAL_T | SWITCH_T | I_CPLB,
121 .i_conf = L1_IMEMORY,
122 .d_conf = 0,
123 .valid = 1,
124 .name = "L1 I-Memory",
125 },
126 {
127 .start = L1_DATA_A_START,
128 .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
129 .psize = SIZE_4M,
130 .attr = INITIAL_T | SWITCH_T | D_CPLB,
131 .i_conf = 0,
132 .d_conf = L1_DMEMORY,
133#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
134 .valid = 1,
135#else
136 .valid = 0,
137#endif
138 .name = "L1 D-Memory",
139 },
140 {
141 .start = 0,
142 .end = 0, /* dynamic */
143 .psize = 0,
144 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
145 .i_conf = SDRAM_IGENERIC,
146 .d_conf = SDRAM_DGENERIC,
147 .valid = 1,
148 .name = "SDRAM Kernel",
149 },
150 {
151 .start = 0, /* dynamic */
152 .end = 0, /* dynamic */
153 .psize = 0,
154 .attr = INITIAL_T | SWITCH_T | D_CPLB,
155 .i_conf = SDRAM_IGENERIC,
156 .d_conf = SDRAM_DNON_CHBL,
157 .valid = 1,
158 .name = "SDRAM RAM MTD",
159 },
160 {
161 .start = 0, /* dynamic */
162 .end = 0, /* dynamic */
163 .psize = SIZE_1M,
164 .attr = INITIAL_T | SWITCH_T | D_CPLB,
165 .d_conf = SDRAM_DNON_CHBL,
166 .valid = 1,//(DMA_UNCACHED_REGION > 0),
167 .name = "SDRAM Uncached DMA ZONE",
168 },
169 {
170 .start = 0, /* dynamic */
171 .end = 0, /* dynamic */
172 .psize = 0,
173 .attr = SWITCH_T | D_CPLB,
174 .i_conf = 0, /* dynamic */
175 .d_conf = 0, /* dynamic */
176 .valid = 1,
177 .name = "SDRAM Reserved Memory",
178 },
179 {
180 .start = ASYNC_BANK0_BASE,
181 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
182 .psize = 0,
183 .attr = SWITCH_T | D_CPLB,
184 .d_conf = SDRAM_EBIU,
185 .valid = 1,
186 .name = "ASYNC Memory",
187 },
188 {
189#if defined(CONFIG_BF561)
190 .start = L2_SRAM,
191 .end = L2_SRAM_END,
192 .psize = SIZE_1M,
193 .attr = SWITCH_T | D_CPLB,
194 .i_conf = L2_MEMORY,
195 .d_conf = L2_MEMORY,
196 .valid = 1,
197#else
198 .valid = 0,
199#endif
200 .name = "L2 Memory",
201 }
202};
203#endif
diff --git a/include/asm-blackfin/cpumask.h b/include/asm-blackfin/cpumask.h
new file mode 100644
index 000000000000..b20a8e9012cb
--- /dev/null
+++ b/include/asm-blackfin/cpumask.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_BLACKFIN_CPUMASK_H
2#define _ASM_BLACKFIN_CPUMASK_H
3
4#include <asm-generic/cpumask.h>
5
6#endif /* _ASM_BLACKFIN_CPUMASK_H */
diff --git a/include/asm-blackfin/cputime.h b/include/asm-blackfin/cputime.h
new file mode 100644
index 000000000000..2b19705f9885
--- /dev/null
+++ b/include/asm-blackfin/cputime.h
@@ -0,0 +1,6 @@
1#ifndef __BLACKFIN_CPUTIME_H
2#define __BLACKFIN_CPUTIME_H
3
4#include <asm-generic/cputime.h>
5
6#endif /* __BLACKFIN_CPUTIME_H */
diff --git a/include/asm-blackfin/current.h b/include/asm-blackfin/current.h
new file mode 100644
index 000000000000..31918d29122c
--- /dev/null
+++ b/include/asm-blackfin/current.h
@@ -0,0 +1,23 @@
1#ifndef _BLACKFIN_CURRENT_H
2#define _BLACKFIN_CURRENT_H
3/*
4 * current.h
5 * (C) Copyright 2000, Lineo, David McCullough <davidm@lineo.com>
6 *
7 * rather than dedicate a register (as the m68k source does), we
8 * just keep a global, we should probably just change it all to be
9 * current and lose _current_task.
10 */
11#include <linux/thread_info.h>
12
13struct task_struct;
14
15static inline struct task_struct *get_current(void) __attribute__ ((__const__));
16static inline struct task_struct *get_current(void)
17{
18 return (current_thread_info()->task);
19}
20
21#define current (get_current())
22
23#endif /* _BLACKFIN_CURRENT_H */
diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h
new file mode 100644
index 000000000000..52e7a10d7ff8
--- /dev/null
+++ b/include/asm-blackfin/delay.h
@@ -0,0 +1,44 @@
1#ifndef _BLACKFIN_DELAY_H
2#define _BLACKFIN_DELAY_H
3
4static inline void __delay(unsigned long loops)
5{
6
7/* FIXME: Currently the assembler doesn't recognize Loop Register Clobbers,
8 uncomment this as soon those are implemented */
9/*
10 __asm__ __volatile__ ( "\t LSETUP (1f,1f) LC0= %0\n\t"
11 "1:\t NOP;\n\t"
12 : :"a" (loops)
13 : "LT0","LB0","LC0");
14
15*/
16
17 __asm__ __volatile__("[--SP] = LC0;\n\t"
18 "[--SP] = LT0;\n\t"
19 "[--SP] = LB0;\n\t"
20 "LSETUP (1f,1f) LC0 = %0;\n\t"
21 "1:\t NOP;\n\t"
22 "LB0 = [SP++];\n\t"
23 "LT0 = [SP++];\n\t"
24 "LC0 = [SP++];\n"
25 :
26 :"a" (loops));
27}
28
29#include <linux/param.h> /* needed for HZ */
30
31/*
32 * Use only for very small delays ( < 1 msec). Should probably use a
33 * lookup table, really, as the multiplications take much too long with
34 * short delays. This is a "reasonable" implementation, though (and the
35 * first constant multiplications gets optimized away if the delay is
36 * a constant)
37 */
38static inline void udelay(unsigned long usecs)
39{
40 extern unsigned long loops_per_jiffy;
41 __delay(usecs * loops_per_jiffy / (1000000 / HZ));
42}
43
44#endif /* defined(_BLACKFIN_DELAY_H) */
diff --git a/include/asm-blackfin/device.h b/include/asm-blackfin/device.h
new file mode 100644
index 000000000000..d8f9872b0e2d
--- /dev/null
+++ b/include/asm-blackfin/device.h
@@ -0,0 +1,7 @@
1/*
2 * Arch specific extensions to struct device
3 *
4 * This file is released under the GPLv2
5 */
6#include <asm-generic/device.h>
7
diff --git a/include/asm-blackfin/div64.h b/include/asm-blackfin/div64.h
new file mode 100644
index 000000000000..6cd978cefb28
--- /dev/null
+++ b/include/asm-blackfin/div64.h
@@ -0,0 +1 @@
#include <asm-generic/div64.h>
diff --git a/include/asm-blackfin/dma-mapping.h b/include/asm-blackfin/dma-mapping.h
new file mode 100644
index 000000000000..7a77d7fe3a33
--- /dev/null
+++ b/include/asm-blackfin/dma-mapping.h
@@ -0,0 +1,66 @@
1#ifndef _BLACKFIN_DMA_MAPPING_H
2#define _BLACKFIN_DMA_MAPPING_H
3
4#include <asm/scatterlist.h>
5
6void dma_alloc_init(unsigned long start, unsigned long end);
7void *dma_alloc_coherent(struct device *dev, size_t size,
8 dma_addr_t *dma_handle, gfp_t gfp);
9void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
10 dma_addr_t dma_handle);
11
12/*
13 * Now for the API extensions over the pci_ one
14 */
15#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
16#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
17
18/*
19 * Map a single buffer of the indicated size for DMA in streaming mode.
20 * The 32-bit bus address to use is returned.
21 *
22 * Once the device is given the dma address, the device owns this memory
23 * until either pci_unmap_single or pci_dma_sync_single is performed.
24 */
25extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
26 enum dma_data_direction direction);
27
28/*
29 * Unmap a single streaming mode DMA translation. The dma_addr and size
30 * must match what was provided for in a previous pci_map_single call. All
31 * other usages are undefined.
32 *
33 * After this call, reads by the cpu to the buffer are guarenteed to see
34 * whatever the device wrote there.
35 */
36extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
37 enum dma_data_direction direction);
38
39/*
40 * Map a set of buffers described by scatterlist in streaming
41 * mode for DMA. This is the scather-gather version of the
42 * above pci_map_single interface. Here the scatter gather list
43 * elements are each tagged with the appropriate dma address
44 * and length. They are obtained via sg_dma_{address,length}(SG).
45 *
46 * NOTE: An implementation may be able to use a smaller number of
47 * DMA address/length pairs than there are SG table elements.
48 * (for example via virtual mapping capabilities)
49 * The routine returns the number of addr/length pairs actually
50 * used, at most nents.
51 *
52 * Device ownership issues as mentioned above for pci_map_single are
53 * the same here.
54 */
55extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
56 enum dma_data_direction direction);
57
58/*
59 * Unmap a set of streaming mode DMA translations.
60 * Again, cpu read rules concerning calls here are the same as for
61 * pci_unmap_single() above.
62 */
63extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
64 int nhwentries, enum dma_data_direction direction);
65
66#endif /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h
new file mode 100644
index 000000000000..be0d913e5516
--- /dev/null
+++ b/include/asm-blackfin/dma.h
@@ -0,0 +1,188 @@
1/*
2 * File: include/asm-blackfin/simple_bf533_dma.h
3 * Based on: none - original work
4 * Author: LG Soft India
5 * Copyright (C) 2004-2005 Analog Devices Inc.
6 * Created: Tue Sep 21 2004
7 * Description: This file contains the major Data structures and constants
8 * used for DMA Implementation in BF533
9 * Modified:
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING.
25 * If not, write to the Free Software Foundation,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29#ifndef _BLACKFIN_DMA_H_
30#define _BLACKFIN_DMA_H_
31
32#include <asm/io.h>
33#include <linux/slab.h>
34#include <asm/irq.h>
35#include <asm/signal.h>
36#include <asm/semaphore.h>
37
38#include <linux/kernel.h>
39#include <asm/mach/dma.h>
40#include <linux/mm.h>
41#include <linux/interrupt.h>
42#include <asm/blackfin.h>
43
44#define MAX_DMA_ADDRESS PAGE_OFFSET
45
46/*****************************************************************************
47* Generic DMA Declarations
48*
49****************************************************************************/
50enum dma_chan_status {
51 DMA_CHANNEL_FREE,
52 DMA_CHANNEL_REQUESTED,
53 DMA_CHANNEL_ENABLED,
54};
55
56/*-------------------------
57 * config reg bits value
58 *-------------------------*/
59#define DATA_SIZE_8 0
60#define DATA_SIZE_16 1
61#define DATA_SIZE_32 2
62
63#define DMA_FLOW_STOP 0
64#define DMA_FLOW_AUTO 1
65#define DMA_FLOW_ARRAY 4
66#define DMA_FLOW_SMALL 6
67#define DMA_FLOW_LARGE 7
68
69#define DIMENSION_LINEAR 0
70#define DIMENSION_2D 1
71
72#define DIR_READ 0
73#define DIR_WRITE 1
74
75#define INTR_DISABLE 0
76#define INTR_ON_BUF 2
77#define INTR_ON_ROW 3
78
79struct dmasg {
80 unsigned long next_desc_addr;
81 unsigned long start_addr;
82 unsigned short cfg;
83 unsigned short x_count;
84 short x_modify;
85 unsigned short y_count;
86 short y_modify;
87} __attribute__((packed));
88
89struct dma_register {
90 unsigned long next_desc_ptr; /* DMA Next Descriptor Pointer register */
91 unsigned long start_addr; /* DMA Start address register */
92
93 unsigned short cfg; /* DMA Configuration register */
94 unsigned short dummy1; /* DMA Configuration register */
95
96 unsigned long reserved;
97
98 unsigned short x_count; /* DMA x_count register */
99 unsigned short dummy2;
100
101 short x_modify; /* DMA x_modify register */
102 unsigned short dummy3;
103
104 unsigned short y_count; /* DMA y_count register */
105 unsigned short dummy4;
106
107 short y_modify; /* DMA y_modify register */
108 unsigned short dummy5;
109
110 unsigned long curr_desc_ptr; /* DMA Current Descriptor Pointer
111 register */
112 unsigned short curr_addr_ptr_lo; /* DMA Current Address Pointer
113 register */
114 unsigned short curr_addr_ptr_hi; /* DMA Current Address Pointer
115 register */
116 unsigned short irq_status; /* DMA irq status register */
117 unsigned short dummy6;
118
119 unsigned short peripheral_map; /* DMA peripheral map register */
120 unsigned short dummy7;
121
122 unsigned short curr_x_count; /* DMA Current x-count register */
123 unsigned short dummy8;
124
125 unsigned long reserved2;
126
127 unsigned short curr_y_count; /* DMA Current y-count register */
128 unsigned short dummy9;
129
130 unsigned long reserved3;
131
132};
133
134typedef irqreturn_t(*dma_interrupt_t) (int irq, void *dev_id);
135
136struct dma_channel {
137 struct mutex dmalock;
138 char *device_id;
139 enum dma_chan_status chan_status;
140 struct dma_register *regs;
141 struct dmasg *sg; /* large mode descriptor */
142 unsigned int ctrl_num; /* controller number */
143 dma_interrupt_t irq_callback;
144 void *data;
145 unsigned int dma_enable_flag;
146 unsigned int loopback_flag;
147};
148
149/*******************************************************************************
150* DMA API's
151*******************************************************************************/
152/* functions to set register mode */
153void set_dma_start_addr(unsigned int channel, unsigned long addr);
154void set_dma_next_desc_addr(unsigned int channel, unsigned long addr);
155void set_dma_x_count(unsigned int channel, unsigned short x_count);
156void set_dma_x_modify(unsigned int channel, short x_modify);
157void set_dma_y_count(unsigned int channel, unsigned short y_count);
158void set_dma_y_modify(unsigned int channel, short y_modify);
159void set_dma_config(unsigned int channel, unsigned short config);
160unsigned short set_bfin_dma_config(char direction, char flow_mode,
161 char intr_mode, char dma_mode, char width);
162
163/* get curr status for polling */
164unsigned short get_dma_curr_irqstat(unsigned int channel);
165unsigned short get_dma_curr_xcount(unsigned int channel);
166unsigned short get_dma_curr_ycount(unsigned int channel);
167
168/* set large DMA mode descriptor */
169void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg);
170
171/* check if current channel is in use */
172int dma_channel_active(unsigned int channel);
173
174/* common functions must be called in any mode */
175void free_dma(unsigned int channel);
176int dma_channel_active(unsigned int channel); /* check if a channel is in use */
177void disable_dma(unsigned int channel);
178void enable_dma(unsigned int channel);
179int request_dma(unsigned int channel, char *device_id);
180int set_dma_callback(unsigned int channel, dma_interrupt_t callback,
181 void *data);
182void dma_disable_irq(unsigned int channel);
183void dma_enable_irq(unsigned int channel);
184void clear_dma_irqstat(unsigned int channel);
185void *dma_memcpy(void *dest, const void *src, size_t count);
186void *safe_dma_memcpy(void *dest, const void *src, size_t count);
187
188#endif
diff --git a/include/asm-blackfin/dpmc.h b/include/asm-blackfin/dpmc.h
new file mode 100644
index 000000000000..f162edb23033
--- /dev/null
+++ b/include/asm-blackfin/dpmc.h
@@ -0,0 +1,70 @@
1/*
2 * include/asm-blackfin/dpmc.h - Miscellaneous IOCTL commands for Dynamic Power
3 * Management Controller Driver.
4 * Copyright (C) 2004 Analog Device Inc.
5 *
6 */
7#ifndef _BLACKFIN_DPMC_H_
8#define _BLACKFIN_DPMC_H_
9
10#define SLEEP_MODE 1
11#define DEEP_SLEEP_MODE 2
12#define ACTIVE_PLL_DISABLED 3
13#define FULLON_MODE 4
14#define ACTIVE_PLL_ENABLED 5
15#define HIBERNATE_MODE 6
16
17#define IOCTL_FULL_ON_MODE _IO('s', 0xA0)
18#define IOCTL_ACTIVE_MODE _IO('s', 0xA1)
19#define IOCTL_SLEEP_MODE _IO('s', 0xA2)
20#define IOCTL_DEEP_SLEEP_MODE _IO('s', 0xA3)
21#define IOCTL_HIBERNATE_MODE _IO('s', 0xA4)
22#define IOCTL_CHANGE_FREQUENCY _IOW('s', 0xA5, unsigned long)
23#define IOCTL_CHANGE_VOLTAGE _IOW('s', 0xA6, unsigned long)
24#define IOCTL_SET_CCLK _IOW('s', 0xA7, unsigned long)
25#define IOCTL_SET_SCLK _IOW('s', 0xA8, unsigned long)
26#define IOCTL_GET_PLLSTATUS _IOW('s', 0xA9, unsigned long)
27#define IOCTL_GET_CORECLOCK _IOW('s', 0xAA, unsigned long)
28#define IOCTL_GET_SYSTEMCLOCK _IOW('s', 0xAB, unsigned long)
29#define IOCTL_GET_VCO _IOW('s', 0xAC, unsigned long)
30#define IOCTL_DISABLE_WDOG_TIMER _IO('s', 0xAD)
31#define IOCTL_UNMASK_WDOG_WAKEUP_EVENT _IO('s',0xAE)
32#define IOCTL_PROGRAM_WDOG_TIMER _IOW('s',0xAF,unsigned long)
33#define IOCTL_CLEAR_WDOG_WAKEUP_EVENT _IO('s',0xB0)
34#define IOCTL_SLEEP_DEEPER_MODE _IO('s',0xB1)
35
36#define DPMC_MINOR 254
37
38#define ON 0
39#define OFF 1
40
41#ifdef __KERNEL__
42
43unsigned long calc_volt(void);
44int calc_vlev(int vlt);
45unsigned long change_voltage(unsigned long volt);
46int calc_msel(int vco_hz);
47unsigned long change_frequency(unsigned long vco_mhz);
48int set_pll_div(unsigned short sel, unsigned char flag);
49int get_vco(void);
50unsigned long change_system_clock(unsigned long clock);
51unsigned long change_core_clock(unsigned long clock);
52unsigned long get_pll_status(void);
53void change_baud(int baud);
54void fullon_mode(void);
55void active_mode(void);
56void sleep_mode(u32 sic_iwr);
57void deep_sleep(u32 sic_iwr);
58void hibernate_mode(u32 sic_iwr);
59void sleep_deeper(u32 sic_iwr);
60void program_wdog_timer(unsigned long);
61void unmask_wdog_wakeup_evt(void);
62void clear_wdog_wakeup_evt(void);
63void disable_wdog_timer(void);
64
65extern unsigned long get_cclk(void);
66extern unsigned long get_sclk(void);
67
68#endif /* __KERNEL__ */
69
70#endif /*_BLACKFIN_DPMC_H_*/
diff --git a/include/asm-blackfin/elf.h b/include/asm-blackfin/elf.h
new file mode 100644
index 000000000000..5264b5536a70
--- /dev/null
+++ b/include/asm-blackfin/elf.h
@@ -0,0 +1,127 @@
1/* Changes made by LG Soft Oct 2004*/
2
3#ifndef __ASMBFIN_ELF_H
4#define __ASMBFIN_ELF_H
5
6/*
7 * ELF register definitions..
8 */
9
10#include <asm/ptrace.h>
11#include <asm/user.h>
12
13/* Processor specific flags for the ELF header e_flags field. */
14#define EF_BFIN_PIC 0x00000001 /* -fpic */
15#define EF_BFIN_FDPIC 0x00000002 /* -mfdpic */
16#define EF_BFIN_CODE_IN_L1 0x00000010 /* --code-in-l1 */
17#define EF_BFIN_DATA_IN_L1 0x00000020 /* --data-in-l1 */
18
19typedef unsigned long elf_greg_t;
20
21#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
22typedef elf_greg_t elf_gregset_t[ELF_NGREG];
23
24typedef struct user_bfinfp_struct elf_fpregset_t;
25/*
26 * This is used to ensure we don't load something for the wrong architecture.
27 */
28#define elf_check_arch(x) ((x)->e_machine == EM_BLACKFIN)
29
30#define elf_check_fdpic(x) ((x)->e_flags & EF_BFIN_FDPIC /* && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS) */)
31#define elf_check_const_displacement(x) ((x)->e_flags & EF_BFIN_PIC)
32
33/* EM_BLACKFIN defined in linux/elf.h */
34
35/*
36 * These are used to set parameters in the core dumps.
37 */
38#define ELF_CLASS ELFCLASS32
39#define ELF_DATA ELFDATA2LSB
40#define ELF_ARCH EM_BLACKFIN
41
42#define ELF_PLAT_INIT(_r) _r->p1 = 0
43
44#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr) \
45do { \
46 _regs->r7 = 0; \
47 _regs->p0 = _exec_map_addr; \
48 _regs->p1 = _interp_map_addr; \
49 _regs->p2 = _dynamic_addr; \
50} while(0)
51
52#define USE_ELF_CORE_DUMP
53#define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC
54#define ELF_EXEC_PAGESIZE 4096
55
56#define R_unused0 0 /* relocation type 0 is not defined */
57#define R_pcrel5m2 1 /*LSETUP part a */
58#define R_unused1 2 /* relocation type 2 is not defined */
59#define R_pcrel10 3 /* type 3, if cc jump <target> */
60#define R_pcrel12_jump 4 /* type 4, jump <target> */
61#define R_rimm16 5 /* type 0x5, rN = <target> */
62#define R_luimm16 6 /* # 0x6, preg.l=<target> Load imm 16 to lower half */
63#define R_huimm16 7 /* # 0x7, preg.h=<target> Load imm 16 to upper half */
64#define R_pcrel12_jump_s 8 /* # 0x8 jump.s <target> */
65#define R_pcrel24_jump_x 9 /* # 0x9 jump.x <target> */
66#define R_pcrel24 10 /* # 0xa call <target> , not expandable */
67#define R_unusedb 11 /* # 0xb not generated */
68#define R_unusedc 12 /* # 0xc not used */
69#define R_pcrel24_jump_l 13 /*0xd jump.l <target> */
70#define R_pcrel24_call_x 14 /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */
71#define R_var_eq_symb 15 /* 0xf, linker should treat it same as 0x12 */
72#define R_byte_data 16 /* 0x10, .byte var = symbol */
73#define R_byte2_data 17 /* 0x11, .byte2 var = symbol */
74#define R_byte4_data 18 /* 0x12, .byte4 var = symbol and .var var=symbol */
75#define R_pcrel11 19 /* 0x13, lsetup part b */
76#define R_unused14 20 /* 0x14, undefined */
77#define R_unused15 21 /* not generated by VDSP 3.5 */
78
79/* arithmetic relocations */
80#define R_push 0xE0
81#define R_const 0xE1
82#define R_add 0xE2
83#define R_sub 0xE3
84#define R_mult 0xE4
85#define R_div 0xE5
86#define R_mod 0xE6
87#define R_lshift 0xE7
88#define R_rshift 0xE8
89#define R_and 0xE9
90#define R_or 0xEA
91#define R_xor 0xEB
92#define R_land 0xEC
93#define R_lor 0xED
94#define R_len 0xEE
95#define R_neg 0xEF
96#define R_comp 0xF0
97#define R_page 0xF1
98#define R_hwpage 0xF2
99#define R_addr 0xF3
100
101/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
102 use of this is to invoke "./ld.so someprog" to test out a new version of
103 the loader. We need to make sure that it is out of the way of the program
104 that it will "exec", and that there is sufficient room for the brk. */
105
106#define ELF_ET_DYN_BASE 0xD0000000UL
107
108#define ELF_CORE_COPY_REGS(pr_reg, regs) \
109 memcpy((char *) &pr_reg, (char *)regs, \
110 sizeof(struct pt_regs));
111
112/* This yields a mask that user programs can use to figure out what
113 instruction set this cpu supports. */
114
115#define ELF_HWCAP (0)
116
117/* This yields a string that ld.so will use to load implementation
118 specific libraries for optimization. This is more specific in
119 intent than poking at uname or /proc/cpuinfo. */
120
121#define ELF_PLATFORM (NULL)
122
123#ifdef __KERNEL__
124#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
125#endif
126
127#endif
diff --git a/include/asm-blackfin/emergency-restart.h b/include/asm-blackfin/emergency-restart.h
new file mode 100644
index 000000000000..27f6c785d103
--- /dev/null
+++ b/include/asm-blackfin/emergency-restart.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_EMERGENCY_RESTART_H
2#define _ASM_EMERGENCY_RESTART_H
3
4#include <asm-generic/emergency-restart.h>
5
6#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h
new file mode 100644
index 000000000000..562c6d3a3232
--- /dev/null
+++ b/include/asm-blackfin/entry.h
@@ -0,0 +1,56 @@
1#ifndef __BFIN_ENTRY_H
2#define __BFIN_ENTRY_H
3
4#include <asm/setup.h>
5#include <asm/page.h>
6
7#ifdef __ASSEMBLY__
8
9#define LFLUSH_I_AND_D 0x00000808
10#define LSIGTRAP 5
11
12/* process bits for task_struct.flags */
13#define PF_TRACESYS_OFF 3
14#define PF_TRACESYS_BIT 5
15#define PF_PTRACED_OFF 3
16#define PF_PTRACED_BIT 4
17#define PF_DTRACE_OFF 1
18#define PF_DTRACE_BIT 5
19
20/* This one is used for exceptions, emulation, and NMI. It doesn't push
21 RETI and doesn't do cli. */
22#define SAVE_ALL_SYS save_context_no_interrupts
23/* This is used for all normal interrupts. It saves a minimum of registers
24 to the stack, loads the IRQ number, and jumps to common code. */
25#define INTERRUPT_ENTRY(N) \
26 [--sp] = SYSCFG; \
27 \
28 [--sp] = P0; /*orig_p0*/ \
29 [--sp] = R0; /*orig_r0*/ \
30 [--sp] = (R7:0,P5:0); \
31 R0 = (N); \
32 jump __common_int_entry;
33
34/* For timer interrupts, we need to save IPEND, since the user_mode
35 macro accesses it to determine where to account time. */
36#define TIMER_INTERRUPT_ENTRY(N) \
37 [--sp] = SYSCFG; \
38 \
39 [--sp] = P0; /*orig_p0*/ \
40 [--sp] = R0; /*orig_r0*/ \
41 [--sp] = (R7:0,P5:0); \
42 p0.l = lo(IPEND); \
43 p0.h = hi(IPEND); \
44 r1 = [p0]; \
45 R0 = (N); \
46 jump __common_int_entry;
47
48/* This one pushes RETI without using CLI. Interrupts are enabled. */
49#define SAVE_CONTEXT_SYSCALL save_context_syscall
50#define SAVE_CONTEXT save_context_with_interrupts
51
52#define RESTORE_ALL_SYS restore_context_no_interrupts
53#define RESTORE_CONTEXT restore_context_with_interrupts
54
55#endif /* __ASSEMBLY__ */
56#endif /* __BFIN_ENTRY_H */
diff --git a/include/asm-blackfin/errno.h b/include/asm-blackfin/errno.h
new file mode 100644
index 000000000000..164e4f39bb57
--- /dev/null
+++ b/include/asm-blackfin/errno.h
@@ -0,0 +1,6 @@
1#ifndef _BFIN_ERRNO_H
2#define _BFIN_ERRNO_H
3
4#include<asm-generic/errno.h>
5
6#endif /* _BFIN_ERRNO_H */
diff --git a/include/asm-blackfin/fcntl.h b/include/asm-blackfin/fcntl.h
new file mode 100644
index 000000000000..9c4037127857
--- /dev/null
+++ b/include/asm-blackfin/fcntl.h
@@ -0,0 +1,13 @@
1#ifndef _BFIN_FCNTL_H
2#define _BFIN_FCNTL_H
3
4/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
5 located on an ext2 file system */
6#define O_DIRECTORY 040000 /* must be a directory */
7#define O_NOFOLLOW 0100000 /* don't follow links */
8#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */
9#define O_LARGEFILE 0400000
10
11#include <asm-generic/fcntl.h>
12
13#endif
diff --git a/include/asm-blackfin/flat.h b/include/asm-blackfin/flat.h
new file mode 100644
index 000000000000..e70074e05f4e
--- /dev/null
+++ b/include/asm-blackfin/flat.h
@@ -0,0 +1,58 @@
1/*
2 * include/asm-blackfin/flat.h -- uClinux flat-format executables
3 *
4 * Copyright (C) 2003,
5 *
6 */
7
8#ifndef __BLACKFIN_FLAT_H__
9#define __BLACKFIN_FLAT_H__
10
11#include <asm/unaligned.h>
12
13#define flat_stack_align(sp) /* nothing needed */
14#define flat_argvp_envp_on_stack() 0
15#define flat_old_ram_flag(flags) (flags)
16
17extern unsigned long bfin_get_addr_from_rp (unsigned long *ptr,
18 unsigned long relval,
19 unsigned long flags,
20 unsigned long *persistent);
21
22extern void bfin_put_addr_at_rp(unsigned long *ptr, unsigned long addr,
23 unsigned long relval);
24
25/* The amount by which a relocation can exceed the program image limits
26 without being regarded as an error. */
27
28#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
29
30#define flat_get_addr_from_rp(rp, relval, flags, persistent) \
31 bfin_get_addr_from_rp(rp, relval, flags, persistent)
32#define flat_put_addr_at_rp(rp, val, relval) \
33 bfin_put_addr_at_rp(rp, val, relval)
34
35/* Convert a relocation entry into an address. */
36static inline unsigned long
37flat_get_relocate_addr (unsigned long relval)
38{
39 return relval & 0x03ffffff; /* Mask out top 6 bits */
40}
41
42static inline int flat_set_persistent(unsigned long relval,
43 unsigned long *persistent)
44{
45 int type = (relval >> 26) & 7;
46 if (type == 3) {
47 *persistent = relval << 16;
48 return 1;
49 }
50 return 0;
51}
52
53static inline int flat_addr_absolute(unsigned long relval)
54{
55 return (relval & (1 << 29)) != 0;
56}
57
58#endif /* __BLACKFIN_FLAT_H__ */
diff --git a/include/asm-blackfin/futex.h b/include/asm-blackfin/futex.h
new file mode 100644
index 000000000000..6a332a9f099c
--- /dev/null
+++ b/include/asm-blackfin/futex.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_FUTEX_H
2#define _ASM_FUTEX_H
3
4#include <asm-generic/futex.h>
5
6#endif
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
new file mode 100644
index 000000000000..d16fe3cd6135
--- /dev/null
+++ b/include/asm-blackfin/gpio.h
@@ -0,0 +1,367 @@
1/*
2 * File: arch/blackfin/kernel/bfin_gpio.h
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30/*
31* Number BF537/6/4 BF561 BF533/2/1
32*
33* GPIO_0 PF0 PF0 PF0
34* GPIO_1 PF1 PF1 PF1
35* GPIO_2 PF2 PF2 PF2
36* GPIO_3 PF3 PF3 PF3
37* GPIO_4 PF4 PF4 PF4
38* GPIO_5 PF5 PF5 PF5
39* GPIO_6 PF6 PF6 PF6
40* GPIO_7 PF7 PF7 PF7
41* GPIO_8 PF8 PF8 PF8
42* GPIO_9 PF9 PF9 PF9
43* GPIO_10 PF10 PF10 PF10
44* GPIO_11 PF11 PF11 PF11
45* GPIO_12 PF12 PF12 PF12
46* GPIO_13 PF13 PF13 PF13
47* GPIO_14 PF14 PF14 PF14
48* GPIO_15 PF15 PF15 PF15
49* GPIO_16 PG0 PF16
50* GPIO_17 PG1 PF17
51* GPIO_18 PG2 PF18
52* GPIO_19 PG3 PF19
53* GPIO_20 PG4 PF20
54* GPIO_21 PG5 PF21
55* GPIO_22 PG6 PF22
56* GPIO_23 PG7 PF23
57* GPIO_24 PG8 PF24
58* GPIO_25 PG9 PF25
59* GPIO_26 PG10 PF26
60* GPIO_27 PG11 PF27
61* GPIO_28 PG12 PF28
62* GPIO_29 PG13 PF29
63* GPIO_30 PG14 PF30
64* GPIO_31 PG15 PF31
65* GPIO_32 PH0 PF32
66* GPIO_33 PH1 PF33
67* GPIO_34 PH2 PF34
68* GPIO_35 PH3 PF35
69* GPIO_36 PH4 PF36
70* GPIO_37 PH5 PF37
71* GPIO_38 PH6 PF38
72* GPIO_39 PH7 PF39
73* GPIO_40 PH8 PF40
74* GPIO_41 PH9 PF41
75* GPIO_42 PH10 PF42
76* GPIO_43 PH11 PF43
77* GPIO_44 PH12 PF44
78* GPIO_45 PH13 PF45
79* GPIO_46 PH14 PF46
80* GPIO_47 PH15 PF47
81*/
82
83#ifndef __ARCH_BLACKFIN_GPIO_H__
84#define __ARCH_BLACKFIN_GPIO_H__
85
86#define gpio_bank(x) ((x) >> 4)
87#define gpio_bit(x) (1<<((x) & 0xF))
88#define gpio_sub_n(x) ((x) & 0xF)
89
90#define GPIO_BANKSIZE 16
91
92#define GPIO_0 0
93#define GPIO_1 1
94#define GPIO_2 2
95#define GPIO_3 3
96#define GPIO_4 4
97#define GPIO_5 5
98#define GPIO_6 6
99#define GPIO_7 7
100#define GPIO_8 8
101#define GPIO_9 9
102#define GPIO_10 10
103#define GPIO_11 11
104#define GPIO_12 12
105#define GPIO_13 13
106#define GPIO_14 14
107#define GPIO_15 15
108#define GPIO_16 16
109#define GPIO_17 17
110#define GPIO_18 18
111#define GPIO_19 19
112#define GPIO_20 20
113#define GPIO_21 21
114#define GPIO_22 22
115#define GPIO_23 23
116#define GPIO_24 24
117#define GPIO_25 25
118#define GPIO_26 26
119#define GPIO_27 27
120#define GPIO_28 28
121#define GPIO_29 29
122#define GPIO_30 30
123#define GPIO_31 31
124#define GPIO_32 32
125#define GPIO_33 33
126#define GPIO_34 34
127#define GPIO_35 35
128#define GPIO_36 36
129#define GPIO_37 37
130#define GPIO_38 38
131#define GPIO_39 39
132#define GPIO_40 40
133#define GPIO_41 41
134#define GPIO_42 42
135#define GPIO_43 43
136#define GPIO_44 44
137#define GPIO_45 45
138#define GPIO_46 46
139#define GPIO_47 47
140
141
142#define PERIPHERAL_USAGE 1
143#define GPIO_USAGE 0
144
145#ifdef BF533_FAMILY
146#define MAX_BLACKFIN_GPIOS 16
147#endif
148
149#ifdef BF537_FAMILY
150#define MAX_BLACKFIN_GPIOS 48
151#define PORT_F 0
152#define PORT_G 1
153#define PORT_H 2
154#define PORT_J 3
155
156#define GPIO_PF0 0
157#define GPIO_PF1 1
158#define GPIO_PF2 2
159#define GPIO_PF3 3
160#define GPIO_PF4 4
161#define GPIO_PF5 5
162#define GPIO_PF6 6
163#define GPIO_PF7 7
164#define GPIO_PF8 8
165#define GPIO_PF9 9
166#define GPIO_PF10 10
167#define GPIO_PF11 11
168#define GPIO_PF12 12
169#define GPIO_PF13 13
170#define GPIO_PF14 14
171#define GPIO_PF15 15
172#define GPIO_PG0 16
173#define GPIO_PG1 17
174#define GPIO_PG2 18
175#define GPIO_PG3 19
176#define GPIO_PG4 20
177#define GPIO_PG5 21
178#define GPIO_PG6 22
179#define GPIO_PG7 23
180#define GPIO_PG8 24
181#define GPIO_PG9 25
182#define GPIO_PG10 26
183#define GPIO_PG11 27
184#define GPIO_PG12 28
185#define GPIO_PG13 29
186#define GPIO_PG14 30
187#define GPIO_PG15 31
188#define GPIO_PH0 32
189#define GPIO_PH1 33
190#define GPIO_PH2 34
191#define GPIO_PH3 35
192#define GPIO_PH4 36
193#define GPIO_PH5 37
194#define GPIO_PH6 38
195#define GPIO_PH7 39
196#define GPIO_PH8 40
197#define GPIO_PH9 41
198#define GPIO_PH10 42
199#define GPIO_PH11 43
200#define GPIO_PH12 44
201#define GPIO_PH13 45
202#define GPIO_PH14 46
203#define GPIO_PH15 47
204
205#endif
206
207#ifdef BF561_FAMILY
208#define MAX_BLACKFIN_GPIOS 48
209#define PORT_FIO0 0
210#define PORT_FIO1 1
211#define PORT_FIO2 2
212#endif
213
214#ifndef __ASSEMBLY__
215
216/***********************************************************
217*
218* FUNCTIONS: Blackfin General Purpose Ports Access Functions
219*
220* INPUTS/OUTPUTS:
221* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
222*
223*
224* DESCRIPTION: These functions abstract direct register access
225* to Blackfin processor General Purpose
226* Ports Regsiters
227*
228* CAUTION: These functions do not belong to the GPIO Driver API
229*************************************************************
230* MODIFICATION HISTORY :
231**************************************************************/
232
233void set_gpio_dir(unsigned short, unsigned short);
234void set_gpio_inen(unsigned short, unsigned short);
235void set_gpio_polar(unsigned short, unsigned short);
236void set_gpio_edge(unsigned short, unsigned short);
237void set_gpio_both(unsigned short, unsigned short);
238void set_gpio_data(unsigned short, unsigned short);
239void set_gpio_maska(unsigned short, unsigned short);
240void set_gpio_maskb(unsigned short, unsigned short);
241void set_gpio_toggle(unsigned short);
242void set_gpiop_dir(unsigned short, unsigned short);
243void set_gpiop_inen(unsigned short, unsigned short);
244void set_gpiop_polar(unsigned short, unsigned short);
245void set_gpiop_edge(unsigned short, unsigned short);
246void set_gpiop_both(unsigned short, unsigned short);
247void set_gpiop_data(unsigned short, unsigned short);
248void set_gpiop_maska(unsigned short, unsigned short);
249void set_gpiop_maskb(unsigned short, unsigned short);
250unsigned short get_gpio_dir(unsigned short);
251unsigned short get_gpio_inen(unsigned short);
252unsigned short get_gpio_polar(unsigned short);
253unsigned short get_gpio_edge(unsigned short);
254unsigned short get_gpio_both(unsigned short);
255unsigned short get_gpio_maska(unsigned short);
256unsigned short get_gpio_maskb(unsigned short);
257unsigned short get_gpio_data(unsigned short);
258unsigned short get_gpiop_dir(unsigned short);
259unsigned short get_gpiop_inen(unsigned short);
260unsigned short get_gpiop_polar(unsigned short);
261unsigned short get_gpiop_edge(unsigned short);
262unsigned short get_gpiop_both(unsigned short);
263unsigned short get_gpiop_maska(unsigned short);
264unsigned short get_gpiop_maskb(unsigned short);
265unsigned short get_gpiop_data(unsigned short);
266
267struct gpio_port_t {
268 unsigned short data;
269 unsigned short dummy1;
270 unsigned short data_clear;
271 unsigned short dummy2;
272 unsigned short data_set;
273 unsigned short dummy3;
274 unsigned short toggle;
275 unsigned short dummy4;
276 unsigned short maska;
277 unsigned short dummy5;
278 unsigned short maska_clear;
279 unsigned short dummy6;
280 unsigned short maska_set;
281 unsigned short dummy7;
282 unsigned short maska_toggle;
283 unsigned short dummy8;
284 unsigned short maskb;
285 unsigned short dummy9;
286 unsigned short maskb_clear;
287 unsigned short dummy10;
288 unsigned short maskb_set;
289 unsigned short dummy11;
290 unsigned short maskb_toggle;
291 unsigned short dummy12;
292 unsigned short dir;
293 unsigned short dummy13;
294 unsigned short polar;
295 unsigned short dummy14;
296 unsigned short edge;
297 unsigned short dummy15;
298 unsigned short both;
299 unsigned short dummy16;
300 unsigned short inen;
301};
302
303#ifdef CONFIG_PM
304#define PM_WAKE_RISING 0x1
305#define PM_WAKE_FALLING 0x2
306#define PM_WAKE_HIGH 0x4
307#define PM_WAKE_LOW 0x8
308#define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING)
309
310int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type);
311void gpio_pm_wakeup_free(unsigned short gpio);
312unsigned int gpio_pm_setup(void);
313void gpio_pm_restore(void);
314
315struct gpio_port_s {
316 unsigned short data;
317 unsigned short data_clear;
318 unsigned short data_set;
319 unsigned short toggle;
320 unsigned short maska;
321 unsigned short maska_clear;
322 unsigned short maska_set;
323 unsigned short maska_toggle;
324 unsigned short maskb;
325 unsigned short maskb_clear;
326 unsigned short maskb_set;
327 unsigned short maskb_toggle;
328 unsigned short dir;
329 unsigned short polar;
330 unsigned short edge;
331 unsigned short both;
332 unsigned short inen;
333
334 unsigned short fer;
335};
336#endif /*CONFIG_PM*/
337
338/***********************************************************
339*
340* FUNCTIONS: Blackfin GPIO Driver
341*
342* INPUTS/OUTPUTS:
343* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
344*
345*
346* DESCRIPTION: Blackfin GPIO Driver API
347*
348* CAUTION:
349*************************************************************
350* MODIFICATION HISTORY :
351**************************************************************/
352
353int gpio_request(unsigned short, const char *);
354void gpio_free(unsigned short);
355
356void gpio_set_value(unsigned short gpio, unsigned short arg);
357unsigned short gpio_get_value(unsigned short gpio);
358
359#define gpio_get_value(gpio) get_gpio_data(gpio)
360#define gpio_set_value(gpio, value) set_gpio_data(gpio, value)
361
362void gpio_direction_input(unsigned short gpio);
363void gpio_direction_output(unsigned short gpio);
364
365#endif /* __ASSEMBLY__ */
366
367#endif /* __ARCH_BLACKFIN_GPIO_H__ */
diff --git a/include/asm-blackfin/hardirq.h b/include/asm-blackfin/hardirq.h
new file mode 100644
index 000000000000..0cab0d35badc
--- /dev/null
+++ b/include/asm-blackfin/hardirq.h
@@ -0,0 +1,41 @@
1#ifndef __BFIN_HARDIRQ_H
2#define __BFIN_HARDIRQ_H
3
4#include <linux/cache.h>
5#include <linux/threads.h>
6#include <asm/irq.h>
7
8typedef struct {
9 unsigned int __softirq_pending;
10 unsigned int __syscall_count;
11 struct task_struct *__ksoftirqd_task;
12} ____cacheline_aligned irq_cpustat_t;
13
14#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
15
16/*
17 * We put the hardirq and softirq counter into the preemption
18 * counter. The bitmask has the following meaning:
19 *
20 * - bits 0-7 are the preemption count (max preemption depth: 256)
21 * - bits 8-15 are the softirq count (max # of softirqs: 256)
22 * - bits 16-23 are the hardirq count (max # of hardirqs: 256)
23 *
24 * - ( bit 26 is the PREEMPT_ACTIVE flag. )
25 *
26 * PREEMPT_MASK: 0x000000ff
27 * HARDIRQ_MASK: 0x0000ff00
28 * SOFTIRQ_MASK: 0x00ff0000
29 */
30
31#define HARDIRQ_BITS 8
32
33#ifdef NR_IRQS
34# if (1 << HARDIRQ_BITS) < NR_IRQS
35# error HARDIRQ_BITS is too low!
36# endif
37#endif
38
39#define __ARCH_IRQ_EXIT_IRQS_DISABLED 1
40
41#endif
diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h
new file mode 100644
index 000000000000..5b51eaec012c
--- /dev/null
+++ b/include/asm-blackfin/hw_irq.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_BFIN_HW_IRQ_H
2#define __ASM_BFIN_HW_IRQ_H
3
4/* Dummy include. */
5
6#endif
diff --git a/include/asm-blackfin/ide.h b/include/asm-blackfin/ide.h
new file mode 100644
index 000000000000..41b2db46a168
--- /dev/null
+++ b/include/asm-blackfin/ide.h
@@ -0,0 +1,32 @@
1/****************************************************************************/
2
3/*
4 * linux/include/asm-blackfin/ide.h
5 *
6 * Copyright (C) 1994-1996 Linus Torvalds & authors
7 * Copyright (C) 2001 Lineo Inc., davidm@snapgear.com
8 * Copyright (C) 2002 Greg Ungerer (gerg@snapgear.com)
9 * Copyright (C) 2002 Yoshinori Sato (ysato@users.sourceforge.jp)
10 * Copyright (C) 2005 Hennerich Michael (hennerich@blackfin.uclinux.org)
11 */
12
13/****************************************************************************/
14#ifndef _BLACKFIN_IDE_H
15#define _BLACKFIN_IDE_H
16/****************************************************************************/
17#ifdef __KERNEL__
18/****************************************************************************/
19
20#define MAX_HWIFS 1
21
22/* Legacy ... BLK_DEV_IDECS */
23#define IDE_ARCH_OBSOLETE_INIT
24#define ide_default_io_ctl(base) ((base) + 0x206) /* obsolete */
25
26
27#include <asm-generic/ide_iops.h>
28
29/****************************************************************************/
30#endif /* __KERNEL__ */
31#endif /* _BLACKFIN_IDE_H */
32/****************************************************************************/
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
new file mode 100644
index 000000000000..7e6995e80d97
--- /dev/null
+++ b/include/asm-blackfin/io.h
@@ -0,0 +1,207 @@
1#ifndef _BFIN_IO_H
2#define _BFIN_IO_H
3
4#ifdef __KERNEL__
5
6#ifndef __ASSEMBLY__
7#include <linux/types.h>
8#endif
9#include <linux/compiler.h>
10
11/*
12 * These are for ISA/PCI shared memory _only_ and should never be used
13 * on any other type of memory, including Zorro memory. They are meant to
14 * access the bus in the bus byte order which is little-endian!.
15 *
16 * readX/writeX() are used to access memory mapped devices. On some
17 * architectures the memory mapped IO stuff needs to be accessed
18 * differently. On the bfin architecture, we just read/write the
19 * memory location directly.
20 */
21#ifndef __ASSEMBLY__
22
23static inline unsigned char readb(void __iomem *addr)
24{
25 unsigned int val;
26 int tmp;
27
28 __asm__ __volatile__ ("cli %1;\n\t"
29 "NOP; NOP; SSYNC;\n\t"
30 "%0 = b [%2] (z);\n\t"
31 "sti %1;\n\t"
32 : "=d"(val), "=d"(tmp): "a"(addr)
33 );
34
35 return (unsigned char) val;
36}
37
38static inline unsigned short readw(void __iomem *addr)
39{
40 unsigned int val;
41 int tmp;
42
43 __asm__ __volatile__ ("cli %1;\n\t"
44 "NOP; NOP; SSYNC;\n\t"
45 "%0 = w [%2] (z);\n\t"
46 "sti %1;\n\t"
47 : "=d"(val), "=d"(tmp): "a"(addr)
48 );
49
50 return (unsigned short) val;
51}
52
53static inline unsigned int readl(void __iomem *addr)
54{
55 unsigned int val;
56 int tmp;
57
58 __asm__ __volatile__ ("cli %1;\n\t"
59 "NOP; NOP; SSYNC;\n\t"
60 "%0 = [%2];\n\t"
61 "sti %1;\n\t"
62 : "=d"(val), "=d"(tmp): "a"(addr)
63 );
64 return val;
65}
66
67#endif /* __ASSEMBLY__ */
68
69#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
70#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
71#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
72
73#define __raw_readb readb
74#define __raw_readw readw
75#define __raw_readl readl
76#define __raw_writeb writeb
77#define __raw_writew writew
78#define __raw_writel writel
79#define memset_io(a,b,c) memset((void *)(a),(b),(c))
80#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
81#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
82
83#define inb(addr) readb(addr)
84#define inw(addr) readw(addr)
85#define inl(addr) readl(addr)
86#define outb(x,addr) ((void) writeb(x,addr))
87#define outw(x,addr) ((void) writew(x,addr))
88#define outl(x,addr) ((void) writel(x,addr))
89
90#define inb_p(addr) inb(addr)
91#define inw_p(addr) inw(addr)
92#define inl_p(addr) inl(addr)
93#define outb_p(x,addr) outb(x,addr)
94#define outw_p(x,addr) outw(x,addr)
95#define outl_p(x,addr) outl(x,addr)
96
97#define ioread8_rep(a,d,c) insb(a,d,c)
98#define ioread16_rep(a,d,c) insw(a,d,c)
99#define ioread32_rep(a,d,c) insl(a,d,c)
100#define iowrite8_rep(a,s,c) outsb(a,s,c)
101#define iowrite16_rep(a,s,c) outsw(a,s,c)
102#define iowrite32_rep(a,s,c) outsl(a,s,c)
103
104#define ioread8(X) readb(X)
105#define ioread16(X) readw(X)
106#define ioread32(X) readl(X)
107#define iowrite8(val,X) writeb(val,X)
108#define iowrite16(val,X) writew(val,X)
109#define iowrite32(val,X) writel(val,X)
110
111#define IO_SPACE_LIMIT 0xffffffff
112
113/* Values for nocacheflag and cmode */
114#define IOMAP_NOCACHE_SER 1
115
116#ifndef __ASSEMBLY__
117
118extern void outsb(void __iomem *port, const void *addr, unsigned long count);
119extern void outsw(void __iomem *port, const void *addr, unsigned long count);
120extern void outsl(void __iomem *port, const void *addr, unsigned long count);
121
122extern void insb(const void __iomem *port, void *addr, unsigned long count);
123extern void insw(const void __iomem *port, void *addr, unsigned long count);
124extern void insl(const void __iomem *port, void *addr, unsigned long count);
125
126/*
127 * Map some physical address range into the kernel address space.
128 */
129static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
130 int cacheflag)
131{
132 return (void __iomem *)physaddr;
133}
134
135/*
136 * Unmap a ioremap()ed region again
137 */
138static inline void iounmap(void *addr)
139{
140}
141
142/*
143 * __iounmap unmaps nearly everything, so be careful
144 * it doesn't free currently pointer/page tables anymore but it
145 * wans't used anyway and might be added later.
146 */
147static inline void __iounmap(void *addr, unsigned long size)
148{
149}
150
151/*
152 * Set new cache mode for some kernel address space.
153 * The caller must push data for that range itself, if such data may already
154 * be in the cache.
155 */
156static inline void kernel_set_cachemode(void *addr, unsigned long size,
157 int cmode)
158{
159}
160
161static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
162{
163 return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
164}
165static inline void __iomem *ioremap_nocache(unsigned long physaddr,
166 unsigned long size)
167{
168 return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
169}
170
171extern void blkfin_inv_cache_all(void);
172
173#endif
174
175#define ioport_map(port, nr) ((void __iomem*)(port))
176#define ioport_unmap(addr)
177
178#define dma_cache_inv(_start,_size) do { blkfin_inv_cache_all();} while (0)
179#define dma_cache_wback(_start,_size) do { } while (0)
180#define dma_cache_wback_inv(_start,_size) do { blkfin_inv_cache_all();} while (0)
181
182/* Pages to physical address... */
183#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
184#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT)
185
186#define mm_ptov(vaddr) ((void *) (vaddr))
187#define mm_vtop(vaddr) ((unsigned long) (vaddr))
188#define phys_to_virt(vaddr) ((void *) (vaddr))
189#define virt_to_phys(vaddr) ((unsigned long) (vaddr))
190
191#define virt_to_bus virt_to_phys
192#define bus_to_virt phys_to_virt
193
194/*
195 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
196 * access
197 */
198#define xlate_dev_mem_ptr(p) __va(p)
199
200/*
201 * Convert a virtual cached pointer to an uncached pointer
202 */
203#define xlate_dev_kmem_ptr(p) p
204
205#endif /* __KERNEL__ */
206
207#endif /* _BFIN_IO_H */
diff --git a/include/asm-blackfin/ioctl.h b/include/asm-blackfin/ioctl.h
new file mode 100644
index 000000000000..b279fe06dfe5
--- /dev/null
+++ b/include/asm-blackfin/ioctl.h
@@ -0,0 +1 @@
#include <asm-generic/ioctl.h>
diff --git a/include/asm-blackfin/ioctls.h b/include/asm-blackfin/ioctls.h
new file mode 100644
index 000000000000..8356204151db
--- /dev/null
+++ b/include/asm-blackfin/ioctls.h
@@ -0,0 +1,82 @@
1#ifndef __ARCH_BFIN_IOCTLS_H__
2#define __ARCH_BFIN_IOCTLS_H__
3
4#include <asm/ioctl.h>
5
6/* 0x54 is just a magic number to make these relatively unique ('T') */
7
8#define TCGETS 0x5401
9#define TCSETS 0x5402
10#define TCSETSW 0x5403
11#define TCSETSF 0x5404
12#define TCGETA 0x5405
13#define TCSETA 0x5406
14#define TCSETAW 0x5407
15#define TCSETAF 0x5408
16#define TCSBRK 0x5409
17#define TCXONC 0x540A
18#define TCFLSH 0x540B
19#define TIOCEXCL 0x540C
20#define TIOCNXCL 0x540D
21#define TIOCSCTTY 0x540E
22#define TIOCGPGRP 0x540F
23#define TIOCSPGRP 0x5410
24#define TIOCOUTQ 0x5411
25#define TIOCSTI 0x5412
26#define TIOCGWINSZ 0x5413
27#define TIOCSWINSZ 0x5414
28#define TIOCMGET 0x5415
29#define TIOCMBIS 0x5416
30#define TIOCMBIC 0x5417
31#define TIOCMSET 0x5418
32#define TIOCGSOFTCAR 0x5419
33#define TIOCSSOFTCAR 0x541A
34#define FIONREAD 0x541B
35#define TIOCINQ FIONREAD
36#define TIOCLINUX 0x541C
37#define TIOCCONS 0x541D
38#define TIOCGSERIAL 0x541E
39#define TIOCSSERIAL 0x541F
40#define TIOCPKT 0x5420
41#define FIONBIO 0x5421
42#define TIOCNOTTY 0x5422
43#define TIOCSETD 0x5423
44#define TIOCGETD 0x5424
45#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
46#define TIOCTTYGSTRUCT 0x5426 /* For debugging only */
47#define TIOCSBRK 0x5427 /* BSD compatibility */
48#define TIOCCBRK 0x5428 /* BSD compatibility */
49#define TIOCGSID 0x5429 /* Return the session ID of FD */
50#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
51#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
52
53#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */
54#define FIOCLEX 0x5451
55#define FIOASYNC 0x5452
56#define TIOCSERCONFIG 0x5453
57#define TIOCSERGWILD 0x5454
58#define TIOCSERSWILD 0x5455
59#define TIOCGLCKTRMIOS 0x5456
60#define TIOCSLCKTRMIOS 0x5457
61#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
62#define TIOCSERGETLSR 0x5459 /* Get line status register */
63#define TIOCSERGETMULTI 0x545A /* Get multiport config */
64#define TIOCSERSETMULTI 0x545B /* Set multiport config */
65
66#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
67#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
68
69#define FIOQSIZE 0x545E
70
71/* Used for packet mode */
72#define TIOCPKT_DATA 0
73#define TIOCPKT_FLUSHREAD 1
74#define TIOCPKT_FLUSHWRITE 2
75#define TIOCPKT_STOP 4
76#define TIOCPKT_START 8
77#define TIOCPKT_NOSTOP 16
78#define TIOCPKT_DOSTOP 32
79
80#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
81
82#endif /* __ARCH_BFIN_IOCTLS_H__ */
diff --git a/include/asm-blackfin/ipc.h b/include/asm-blackfin/ipc.h
new file mode 100644
index 000000000000..a46e3d9c2a3f
--- /dev/null
+++ b/include/asm-blackfin/ipc.h
@@ -0,0 +1 @@
#include <asm-generic/ipc.h>
diff --git a/include/asm-blackfin/ipcbuf.h b/include/asm-blackfin/ipcbuf.h
new file mode 100644
index 000000000000..8f0899cdf4d2
--- /dev/null
+++ b/include/asm-blackfin/ipcbuf.h
@@ -0,0 +1,30 @@
1/* Changes origined from m68k version. Lineo Inc. May 2001 */
2
3#ifndef __BFIN_IPCBUF_H__
4#define __BFIN_IPCBUF_H__
5
6/*
7 * The user_ipc_perm structure for m68k architecture.
8 * Note extra padding because this structure is passed back and forth
9 * between kernel and user space.
10 *
11 * Pad space is left for:
12 * - 32-bit mode_t and seq
13 * - 2 miscellaneous 32-bit values
14 */
15
16struct ipc64_perm {
17 __kernel_key_t key;
18 __kernel_uid32_t uid;
19 __kernel_gid32_t gid;
20 __kernel_uid32_t cuid;
21 __kernel_gid32_t cgid;
22 __kernel_mode_t mode;
23 unsigned short __pad1;
24 unsigned short seq;
25 unsigned short __pad2;
26 unsigned long __unused1;
27 unsigned long __unused2;
28};
29
30#endif /* __BFIN_IPCBUF_H__ */
diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h
new file mode 100644
index 000000000000..65480dab244e
--- /dev/null
+++ b/include/asm-blackfin/irq.h
@@ -0,0 +1,70 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file COPYING in the main directory of this archive
4 * for more details.
5 *
6 * Changed by HuTao Apr18, 2003
7 *
8 * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
9 * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
10 * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
11 *
12 * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
13 * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
14 * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
15 */
16
17#ifndef _BFIN_IRQ_H_
18#define _BFIN_IRQ_H_
19
20#include <asm/mach/irq.h>
21#include <asm/ptrace.h>
22
23/*******************************************************************************
24 ***** INTRODUCTION ***********
25 * On the Blackfin, the interrupt structure allows remmapping of the hardware
26 * levels.
27 * - I'm going to assume that the H/W level is going to stay at the default
28 * settings. If someone wants to go through and abstart this out, feel free
29 * to mod the interrupt numbering scheme.
30 * - I'm abstracting the interrupts so that uClinux does not know anything
31 * about the H/W levels. If you want to change the H/W AND keep the abstracted
32 * levels that uClinux sees, you should be able to do most of it here.
33 * - I've left the "abstract" numbering sparce in case someone wants to pull the
34 * interrupts apart (just the TX/RX for the various devices)
35 *******************************************************************************/
36
37/* SYS_IRQS and NR_IRQS are defined in <asm/mach-bf5xx/irq.h>*/
38
39/*
40 * Machine specific interrupt sources.
41 *
42 * Adding an interrupt service routine for a source with this bit
43 * set indicates a special machine specific interrupt source.
44 * The machine specific files define these sources.
45 *
46 * The IRQ_MACHSPEC bit is now gone - the only thing it did was to
47 * introduce unnecessary overhead.
48 *
49 * All interrupt handling is actually machine specific so it is better
50 * to use function pointers, as used by the Sparc port, and select the
51 * interrupt handling functions when initializing the kernel. This way
52 * we save some unnecessary overhead at run-time.
53 * 01/11/97 - Jes
54 */
55
56extern void ack_bad_irq(unsigned int irq);
57
58static __inline__ int irq_canonicalize(int irq)
59{
60 return irq;
61}
62
63/* count of spurious interrupts */
64/* extern volatile unsigned int num_spurious; */
65
66#ifndef NO_IRQ
67#define NO_IRQ ((unsigned int)(-1))
68#endif
69
70#endif /* _BFIN_IRQ_H_ */
diff --git a/include/asm-blackfin/irq_handler.h b/include/asm-blackfin/irq_handler.h
new file mode 100644
index 000000000000..d830f0a49a1c
--- /dev/null
+++ b/include/asm-blackfin/irq_handler.h
@@ -0,0 +1,22 @@
1#ifndef _IRQ_HANDLER_H
2#define _IRQ_HANDLER_H
3
4/* BASE LEVEL interrupt handler routines */
5asmlinkage void evt_emulation(void);
6asmlinkage void evt_exception(void);
7asmlinkage void trap(void);
8asmlinkage void evt_ivhw(void);
9asmlinkage void evt_timer(void);
10asmlinkage void evt_evt2(void);
11asmlinkage void evt_evt7(void);
12asmlinkage void evt_evt8(void);
13asmlinkage void evt_evt9(void);
14asmlinkage void evt_evt10(void);
15asmlinkage void evt_evt11(void);
16asmlinkage void evt_evt12(void);
17asmlinkage void evt_evt13(void);
18asmlinkage void evt_soft_int1(void);
19asmlinkage void evt_system_call(void);
20asmlinkage void init_exception_buff(void);
21
22#endif
diff --git a/include/asm-blackfin/irq_regs.h b/include/asm-blackfin/irq_regs.h
new file mode 100644
index 000000000000..3dd9c0b70270
--- /dev/null
+++ b/include/asm-blackfin/irq_regs.h
@@ -0,0 +1 @@
#include <asm-generic/irq_regs.h>
diff --git a/include/asm-blackfin/kdebug.h b/include/asm-blackfin/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-blackfin/kdebug.h
@@ -0,0 +1 @@
#include <asm-generic/kdebug.h>
diff --git a/include/asm-blackfin/kmap_types.h b/include/asm-blackfin/kmap_types.h
new file mode 100644
index 000000000000..e215f7104974
--- /dev/null
+++ b/include/asm-blackfin/kmap_types.h
@@ -0,0 +1,21 @@
1#ifndef _ASM_KMAP_TYPES_H
2#define _ASM_KMAP_TYPES_H
3
4enum km_type {
5 KM_BOUNCE_READ,
6 KM_SKB_SUNRPC_DATA,
7 KM_SKB_DATA_SOFTIRQ,
8 KM_USER0,
9 KM_USER1,
10 KM_BIO_SRC_IRQ,
11 KM_BIO_DST_IRQ,
12 KM_PTE0,
13 KM_PTE1,
14 KM_IRQ0,
15 KM_IRQ1,
16 KM_SOFTIRQ0,
17 KM_SOFTIRQ1,
18 KM_TYPE_NR
19};
20
21#endif
diff --git a/include/asm-blackfin/l1layout.h b/include/asm-blackfin/l1layout.h
new file mode 100644
index 000000000000..c13ded777828
--- /dev/null
+++ b/include/asm-blackfin/l1layout.h
@@ -0,0 +1,31 @@
1/*
2 * l1layout.h
3 * Defines a layout of L1 scratchpad memory that userspace can rely on.
4 */
5
6#ifndef _L1LAYOUT_H_
7#define _L1LAYOUT_H_
8
9#include <asm/blackfin.h>
10
11#ifndef __ASSEMBLY__
12
13/* Data that is "mapped" into the process VM at the start of the L1 scratch
14 memory, so that each process can access it at a fixed address. Used for
15 stack checking. */
16struct l1_scratch_task_info
17{
18 /* Points to the start of the stack. */
19 void *stack_start;
20 /* Not updated by the kernel; a user process can modify this to
21 keep track of the lowest address of the stack pointer during its
22 runtime. */
23 void *lowest_sp;
24};
25
26/* A pointer to the structure in memory. */
27#define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)L1_SCRATCH_START)
28
29#endif
30
31#endif
diff --git a/include/asm-blackfin/linkage.h b/include/asm-blackfin/linkage.h
new file mode 100644
index 000000000000..5a822bb790f7
--- /dev/null
+++ b/include/asm-blackfin/linkage.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_LINKAGE_H
2#define __ASM_LINKAGE_H
3
4#define __ALIGN .align 4
5#define __ALIGN_STR ".align 4"
6
7#endif
diff --git a/include/asm-blackfin/local.h b/include/asm-blackfin/local.h
new file mode 100644
index 000000000000..75afffbc6421
--- /dev/null
+++ b/include/asm-blackfin/local.h
@@ -0,0 +1,6 @@
1#ifndef __BLACKFIN_LOCAL_H
2#define __BLACKFIN_LOCAL_H
3
4#include <asm-generic/local.h>
5
6#endif /* __BLACKFIN_LOCAL_H */
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
new file mode 100644
index 000000000000..a84d3909345e
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -0,0 +1,175 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/anomaly.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31/* This file shoule be up to date with:
32 * - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List
33 * - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List
34 * - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List
35 */
36
37#ifndef _MACH_ANOMALY_H_
38#define _MACH_ANOMALY_H_
39
40/* We do not support 0.1 or 0.2 silicon - sorry */
41#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2))
42#error Kernel will not work on BF533 Version 0.1 or 0.2
43#endif
44
45/* Issues that are common to 0.5, 0.4, and 0.3 silicon */
46#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
47#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
48 slot1 and store of a P register in slot 2 is not
49 supported */
50#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
51 every corresponding match */
52#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
53 Channel DMA stops */
54#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
55 registers. */
56#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
57 upper bits*/
58#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
59#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
60 syncs */
61#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
62 functional */
63#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
64 state */
65#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
66#define ANOMALY_05000272 /* Certain data cache write through modes fail for
67 VDDint <=0.9V */
68#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
69#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
70 an edge is detected may clear interrupt */
71#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
72 DMA system instability */
73#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
74 not restored */
75#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
76 control */
77#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
78 killed in a particular stage*/
79#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
80 registers are interrupted */
81#define ANOMALY_05000311 /* Erroneous flag pin operations under specific sequences*/
82
83#endif
84
85/* These issues only occur on 0.3 or 0.4 BF533 */
86#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
87#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
88 updated at the same time. */
89#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
90 Cache Fill can be corrupted after or during
91 Instruction DMA if certain core stalls exist */
92#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
93 Purpose TX or RX modes */
94#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
95 preceding memory read */
96#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
97 inactive channels in certain conditions */
98#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
99 situation */
100#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
101#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
102#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
103 data*/
104#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
105 Differences in certain Conditions */
106#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
107#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
108 hardware reset */
109#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
110 IDLE around a Change of Control causes
111 unpredictable results */
112#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
113 shadow of a conditional branch */
114#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
115 errors */
116#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
117#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
118 interrupt not functional */
119#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
120 loops may cause the instruction fetch unit to
121 malfunction */
122#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
123 the ICPLB Data registers differ */
124#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
125#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
126#define ANOMALY_05000262 /* Stores to data cache may be lost */
127#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
128#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
129 instruction will cause an infinite stall in the
130 second to last instruction in a hardware loop */
131#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
132 SPORT external receive and transmit clocks. */
133#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
134 internal voltage regulator (VDDint) to increase. */
135#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
136 internal voltage regulator (VDDint) to decrease */
137#endif
138
139/* These issues are only on 0.4 silicon */
140#if (defined(CONFIG_BF_REV_0_4))
141#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
142#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
143 (TDM) */
144#endif
145
146/* These issues are only on 0.3 silicon */
147#if defined(CONFIG_BF_REV_0_3)
148#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
149 External Frame Syncs */
150#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
151 Instruction or Data Fetches, or by Fetches at the
152 boundary of reserved memory space */
153#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
154 when polarity setting is changed */
155#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
156 corruption */
157#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
158 fix */
159#define ANOMALY_05000201 /* Receive frame sync not ignored during active
160 frames in sport MCM */
161#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
162 stopping */
163#if defined(CONFIG_BF533)
164#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
165 allocate cache lines on reads only mode */
166#endif /* CONFIG_BF533 */
167#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
168#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
169 instructions */
170#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
171 Sync Transmit Mode */
172#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
173#endif
174
175#endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf533/bf533.h b/include/asm-blackfin/mach-bf533/bf533.h
new file mode 100644
index 000000000000..185fc1284858
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/bf533.h
@@ -0,0 +1,306 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/bf533.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF533_H__
31#define __MACH_BF533_H__
32
33#define SUPPORTED_REVID 2
34
35#define OFFSET_(x) ((x) & 0x0000FFFF)
36
37/*some misc defines*/
38#define IMASK_IVG15 0x8000
39#define IMASK_IVG14 0x4000
40#define IMASK_IVG13 0x2000
41#define IMASK_IVG12 0x1000
42
43#define IMASK_IVG11 0x0800
44#define IMASK_IVG10 0x0400
45#define IMASK_IVG9 0x0200
46#define IMASK_IVG8 0x0100
47
48#define IMASK_IVG7 0x0080
49#define IMASK_IVGTMR 0x0040
50#define IMASK_IVGHW 0x0020
51
52/***************************/
53
54
55#define BLKFIN_DSUBBANKS 4
56#define BLKFIN_DWAYS 2
57#define BLKFIN_DLINES 64
58#define BLKFIN_ISUBBANKS 4
59#define BLKFIN_IWAYS 4
60#define BLKFIN_ILINES 32
61
62#define WAY0_L 0x1
63#define WAY1_L 0x2
64#define WAY01_L 0x3
65#define WAY2_L 0x4
66#define WAY02_L 0x5
67#define WAY12_L 0x6
68#define WAY012_L 0x7
69
70#define WAY3_L 0x8
71#define WAY03_L 0x9
72#define WAY13_L 0xA
73#define WAY013_L 0xB
74
75#define WAY32_L 0xC
76#define WAY320_L 0xD
77#define WAY321_L 0xE
78#define WAYALL_L 0xF
79
80#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
81
82/* IAR0 BIT FIELDS*/
83#define RTC_ERROR_BIT 0x0FFFFFFF
84#define UART_ERROR_BIT 0xF0FFFFFF
85#define SPORT1_ERROR_BIT 0xFF0FFFFF
86#define SPI_ERROR_BIT 0xFFF0FFFF
87#define SPORT0_ERROR_BIT 0xFFFF0FFF
88#define PPI_ERROR_BIT 0xFFFFF0FF
89#define DMA_ERROR_BIT 0xFFFFFF0F
90#define PLLWAKE_ERROR_BIT 0xFFFFFFFF
91
92/* IAR1 BIT FIELDS*/
93#define DMA7_UARTTX_BIT 0x0FFFFFFF
94#define DMA6_UARTRX_BIT 0xF0FFFFFF
95#define DMA5_SPI_BIT 0xFF0FFFFF
96#define DMA4_SPORT1TX_BIT 0xFFF0FFFF
97#define DMA3_SPORT1RX_BIT 0xFFFF0FFF
98#define DMA2_SPORT0TX_BIT 0xFFFFF0FF
99#define DMA1_SPORT0RX_BIT 0xFFFFFF0F
100#define DMA0_PPI_BIT 0xFFFFFFFF
101
102/* IAR2 BIT FIELDS*/
103#define WDTIMER_BIT 0x0FFFFFFF
104#define MEMDMA1_BIT 0xF0FFFFFF
105#define MEMDMA0_BIT 0xFF0FFFFF
106#define PFB_BIT 0xFFF0FFFF
107#define PFA_BIT 0xFFFF0FFF
108#define TIMER2_BIT 0xFFFFF0FF
109#define TIMER1_BIT 0xFFFFFF0F
110#define TIMER0_BIT 0xFFFFFFFF
111
112/********************************* EBIU Settings ************************************/
113#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
114#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
115
116#ifdef CONFIG_C_AMBEN_ALL
117#define V_AMBEN AMBEN_ALL
118#endif
119#ifdef CONFIG_C_AMBEN
120#define V_AMBEN 0x0
121#endif
122#ifdef CONFIG_C_AMBEN_B0
123#define V_AMBEN AMBEN_B0
124#endif
125#ifdef CONFIG_C_AMBEN_B0_B1
126#define V_AMBEN AMBEN_B0_B1
127#endif
128#ifdef CONFIG_C_AMBEN_B0_B1_B2
129#define V_AMBEN AMBEN_B0_B1_B2
130#endif
131#ifdef CONFIG_C_AMCKEN
132#define V_AMCKEN AMCKEN
133#else
134#define V_AMCKEN 0x0
135#endif
136#ifdef CONFIG_C_CDPRIO
137#define V_CDPRIO 0x100
138#else
139#define V_CDPRIO 0x0
140#endif
141
142#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
143
144#define MAX_VC 650000000
145#define MIN_VC 50000000
146
147#ifdef CONFIG_BFIN_KERNEL_CLOCK
148/********************************PLL Settings **************************************/
149#if (CONFIG_VCO_MULT < 0)
150#error "VCO Multiplier is less than 0. Please select a different value"
151#endif
152
153#if (CONFIG_VCO_MULT == 0)
154#error "VCO Multiplier should be greater than 0. Please select a different value"
155#endif
156
157#if (CONFIG_VCO_MULT > 64)
158#error "VCO Multiplier is more than 64. Please select a different value"
159#endif
160
161#ifndef CONFIG_CLKIN_HALF
162#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
163#else
164#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
165#endif
166
167#ifndef CONFIG_PLL_BYPASS
168#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
169#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
170#else
171#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
172#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
173#endif
174
175#if (CONFIG_SCLK_DIV < 1)
176#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
177#endif
178
179#if (CONFIG_SCLK_DIV > 15)
180#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
181#endif
182
183#if (CONFIG_CCLK_DIV != 1)
184#if (CONFIG_CCLK_DIV != 2)
185#if (CONFIG_CCLK_DIV != 4)
186#if (CONFIG_CCLK_DIV != 8)
187#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
188#endif
189#endif
190#endif
191#endif
192
193#if (CONFIG_VCO_HZ > MAX_VC)
194#error "VCO selected is more than maximum value. Please change the VCO multipler"
195#endif
196
197#if (CONFIG_SCLK_HZ > 133000000)
198#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
199#endif
200
201#if (CONFIG_SCLK_HZ < 27000000)
202#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
203#endif
204
205#if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ)
206#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
207#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
208#error "Please select sclk less than cclk"
209#endif
210#endif
211#endif
212
213#if (CONFIG_CCLK_DIV == 1)
214#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
215#endif
216#if (CONFIG_CCLK_DIV == 2)
217#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
218#endif
219#if (CONFIG_CCLK_DIV == 4)
220#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
221#endif
222#if (CONFIG_CCLK_DIV == 8)
223#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
224#endif
225#ifndef CONFIG_CCLK_ACT_DIV
226#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
227#endif
228
229#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1)
230#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
231#endif
232
233#endif /* CONFIG_BFIN_KERNEL_CLOCK */
234
235#ifdef CONFIG_BF533
236#define CPU "BF533"
237#define CPUID 0x027a5000
238#endif
239#ifdef CONFIG_BF532
240#define CPU "BF532"
241#define CPUID 0x0275A000
242#endif
243#ifdef CONFIG_BF531
244#define CPU "BF531"
245#define CPUID 0x027a5000
246#endif
247#ifndef CPU
248#define CPU "UNKNOWN"
249#define CPUID 0x0
250#endif
251
252#if (CONFIG_MEM_SIZE % 4)
253#error "SDRAM mem size must be multible of 4MB"
254#endif
255
256#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
257#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
258#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
259#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
260
261/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
262
263#define ANOMALY_05000158_WORKAROUND 0x200
264#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
265#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
266 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
267#else /*Write Through */
268#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \
269 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
270#endif
271
272#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
273#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
274#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
275#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
276
277#define SIZE_1K 0x00000400 /* 1K */
278#define SIZE_4K 0x00001000 /* 4K */
279#define SIZE_1M 0x00100000 /* 1M */
280#define SIZE_4M 0x00400000 /* 4M */
281
282#define MAX_CPLBS (16 * 2)
283
284/*
285* Number of required data CPLB switchtable entries
286* MEMSIZE / 4 (we mostly install 4M page size CPLBs
287* approx 16 for smaller 1MB page size CPLBs for allignment purposes
288* 1 for L1 Data Memory
289* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
290* 1 for ASYNC Memory
291*/
292
293
294#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
295
296/*
297* Number of required instruction CPLB switchtable entries
298* MEMSIZE / 4 (we mostly install 4M page size CPLBs
299* approx 12 for smaller 1MB page size CPLBs for allignment purposes
300* 1 for L1 Instruction Memory
301* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
302*/
303
304#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
305
306#endif /* __MACH_BF533_H__ */
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
new file mode 100644
index 000000000000..23bf76aa3451
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -0,0 +1,108 @@
1#include <linux/serial.h>
2#include <asm/dma.h>
3
4#define NR_PORTS 1
5
6#define OFFSET_THR 0x00 /* Transmit Holding register */
7#define OFFSET_RBR 0x00 /* Receive Buffer register */
8#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
9#define OFFSET_IER 0x04 /* Interrupt Enable Register */
10#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
11#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
12#define OFFSET_LCR 0x0C /* Line Control Register */
13#define OFFSET_MCR 0x10 /* Modem Control Register */
14#define OFFSET_LSR 0x14 /* Line Status Register */
15#define OFFSET_MSR 0x18 /* Modem Status Register */
16#define OFFSET_SCR 0x1C /* SCR Scratch Register */
17#define OFFSET_GCTL 0x24 /* Global Control Register */
18
19#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
20#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
21#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
22#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
23#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
24#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
25#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
27
28#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
29#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
30#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
31#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
32#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
33#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
34
35#ifdef CONFIG_BFIN_UART0_CTSRTS
36# define CONFIG_SERIAL_BFIN_CTSRTS
37# ifndef CONFIG_UART0_CTS_PIN
38# define CONFIG_UART0_CTS_PIN -1
39# endif
40# ifndef CONFIG_UART0_RTS_PIN
41# define CONFIG_UART0_RTS_PIN -1
42# endif
43#endif
44
45struct bfin_serial_port {
46 struct uart_port port;
47 unsigned int old_status;
48#ifdef CONFIG_SERIAL_BFIN_DMA
49 int tx_done;
50 int tx_count;
51 struct circ_buf rx_dma_buf;
52 struct timer_list rx_dma_timer;
53 int rx_dma_nrows;
54 unsigned int tx_dma_channel;
55 unsigned int rx_dma_channel;
56 struct work_struct tx_dma_workqueue;
57#else
58 struct work_struct cts_workqueue;
59#endif
60#ifdef CONFIG_SERIAL_BFIN_CTSRTS
61 int cts_pin;
62 int rts_pin;
63#endif
64};
65
66struct bfin_serial_port bfin_serial_ports[NR_PORTS];
67struct bfin_serial_res {
68 unsigned long uart_base_addr;
69 int uart_irq;
70#ifdef CONFIG_SERIAL_BFIN_DMA
71 unsigned int uart_tx_dma_channel;
72 unsigned int uart_rx_dma_channel;
73#endif
74#ifdef CONFIG_SERIAL_BFIN_CTSRTS
75 int uart_cts_pin;
76 int uart_rts_pin;
77#endif
78};
79
80struct bfin_serial_res bfin_serial_resource[] = {
81 0xFFC00400,
82 IRQ_UART_RX,
83#ifdef CONFIG_SERIAL_BFIN_DMA
84 CH_UART_TX,
85 CH_UART_RX,
86#endif
87#ifdef CONFIG_BFIN_UART0_CTSRTS
88 CONFIG_UART0_CTS_PIN,
89 CONFIG_UART0_RTS_PIN,
90#endif
91};
92
93
94int nr_ports = NR_PORTS;
95static void bfin_serial_hw_init(struct bfin_serial_port *uart)
96{
97
98#ifdef CONFIG_SERIAL_BFIN_CTSRTS
99 if (uart->cts_pin >= 0) {
100 gpio_request(uart->cts_pin, NULL);
101 gpio_direction_input(uart->cts_pin);
102 }
103 if (uart->rts_pin >= 0) {
104 gpio_request(uart->rts_pin, NULL);
105 gpio_direction_input(uart->rts_pin);
106 }
107#endif
108}
diff --git a/include/asm-blackfin/mach-bf533/blackfin.h b/include/asm-blackfin/mach-bf533/blackfin.h
new file mode 100644
index 000000000000..e4384491e972
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/blackfin.h
@@ -0,0 +1,45 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _MACH_BLACKFIN_H_
32#define _MACH_BLACKFIN_H_
33
34#define BF533_FAMILY
35
36#include "bf533.h"
37#include "mem_map.h"
38#include "defBF532.h"
39#include "anomaly.h"
40
41#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
42#include "cdefBF532.h"
43#endif
44
45#endif /* _MACH_BLACKFIN_H_ */
diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h
new file mode 100644
index 000000000000..1d7c494ceb64
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/cdefBF532.h
@@ -0,0 +1,706 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/cdefBF532.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF532_H
32#define _CDEF_BF532_H
33/*
34#if !defined(__ADSPLPBLACKFIN__)
35#warning cdefBF532.h should only be included for 532 compatible chips.
36#endif
37*/
38/*include all Core registers and bit definitions*/
39#include "defBF532.h"
40
41/*include core specific register pointer definitions*/
42#include <asm/mach-common/cdef_LPBlackfin.h>
43
44#include <asm/system.h>
45
46/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
47#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
48#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val)
49#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
50#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
51#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
52#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
53#define bfin_read_CHIPID() bfin_read32(CHIPID)
54#define bfin_read_SWRST() bfin_read16(SWRST)
55#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
56#define bfin_read_SYSCR() bfin_read16(SYSCR)
57#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
58#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
59#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
60#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
61/* Writing to VR_CTL initiates a PLL relock sequence. */
62static __inline__ void bfin_write_VR_CTL(unsigned int val)
63{
64 unsigned long flags, iwr;
65
66 bfin_write16(VR_CTL, val);
67 __builtin_bfin_ssync();
68 /* Enable the PLL Wakeup bit in SIC IWR */
69 iwr = bfin_read32(SIC_IWR);
70 /* Only allow PPL Wakeup) */
71 bfin_write32(SIC_IWR, IWR_ENABLE(0));
72 local_irq_save(flags);
73 asm("IDLE;");
74 local_irq_restore(flags);
75 bfin_write32(SIC_IWR, iwr);
76}
77
78/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
79#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
80#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
81#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
82#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
83#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
84#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
85#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
86#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
87#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
88#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
89#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
90#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
91#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
92#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
93
94/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
95#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
96#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
97#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
98#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
99#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
100#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
101
102/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
103#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
104#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
105#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
106#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
107#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
108#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
109#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
110#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
111#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
112#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
113#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
114#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
115#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
116#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
117
118/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
119#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
120#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val)
121#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
122#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C,val)
123#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
124#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S,val)
125#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C)
126#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val)
127#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S)
128#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val)
129#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C)
130#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val)
131#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S)
132#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val)
133#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR)
134#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val)
135#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE)
136#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val)
137#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH)
138#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val)
139#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN)
140#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val)
141#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
142#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D,val)
143#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
144#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T,val)
145#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D)
146#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val)
147#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T)
148#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val)
149#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D)
150#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val)
151#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
152#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
153
154/* DMA Traffic controls */
155#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
156#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
157#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
158#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
159#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
160#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
161#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
162#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
163
164/* DMA Controller */
165#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
166#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
167#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
168#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
169#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
170#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
171#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
172#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
173#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
174#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
175#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
176#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
177#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
178#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
179#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
180#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
181#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
182#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
183#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
184#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
185#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
186#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
187#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
188#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
189#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
190#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
191
192#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
193#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
194#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
195#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
196#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
197#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
198#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
199#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
200#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
201#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
202#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
203#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
204#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
205#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
206#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
207#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
208#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
209#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
210#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
211#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
212#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
213#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
214#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
215#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
216#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
217#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
218
219#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
220#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
221#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
222#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
223#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
224#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
225#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
226#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
227#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
228#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
229#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
230#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
231#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
232#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
233#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
234#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
235#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
236#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
237#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
238#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
239#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
240#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
241#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
242#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
243#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
244#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
245
246#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
247#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
248#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
249#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
250#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
251#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
252#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
253#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
254#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
255#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
256#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
257#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
258#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
259#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
260#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
261#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
262#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
263#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
264#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
265#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
266#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
267#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
268#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
269#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
270#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
271#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
272
273#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
274#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
275#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
276#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
277#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
278#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
279#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
280#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
281#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
282#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
283#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
284#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
285#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
286#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
287#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
288#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
289#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
290#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
291#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
292#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
293#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
294#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
295#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
296#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
297#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
298#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
299
300#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
301#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
302#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
303#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
304#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
305#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
306#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
307#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
308#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
309#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
310#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
311#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
312#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
313#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
314#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
315#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
316#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
317#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
318#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
319#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
320#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
321#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
322#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
323#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
324#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
325#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
326
327#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
328#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
329#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
330#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
331#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
332#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
333#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
334#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
335#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
336#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
337#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
338#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
339#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
340#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
341#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
342#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
343#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
344#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
345#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
346#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
347#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
348#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
349#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
350#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
351#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
352#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
353
354#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
355#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
356#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
357#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
358#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
359#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
360#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
361#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
362#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
363#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
364#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
365#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
366#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
367#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
368#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
369#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
370#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
371#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
372#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
373#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
374#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
375#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
376#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
377#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
378#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
379#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
380
381#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
382#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
383#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
384#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
385#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
386#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
387#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
388#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
389#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
390#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
391#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
392#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
393#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
394#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
395#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
396#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
397#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
398#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
399#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
400#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
401#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
402#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
403#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
404#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
405#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
406#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
407
408#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
409#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
410#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
411#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
412#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
413#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
414#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
415#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
416#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
417#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
418#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
419#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
420#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
421#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
422#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
423#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
424#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
425#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
426#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
427#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
428#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
429#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
430#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
431#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
432#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
433#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
434
435#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
436#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
437#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
438#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
439#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
440#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
441#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
442#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
443#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
444#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
445#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
446#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
447#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
448#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
449#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
450#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
451#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
452#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
453#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
454#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
455#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
456#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
457#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
458#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
459#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
460#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
461
462#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
463#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
464#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
465#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
466#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
467#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
468#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
469#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
470#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
471#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
472#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
473#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
474#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
475#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
476#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
477#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
478#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
479#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
480#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
481#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
482#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
483#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
484#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
485#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
486#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
487#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
488
489/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
490#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
491#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
492#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
493#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
494#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
495#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
496
497/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
498#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
499#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
500#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
501#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
502#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
503#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
504#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
505#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
506
507/* UART Controller */
508#define bfin_read_UART_THR() bfin_read16(UART_THR)
509#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
510#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
511#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
512#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
513#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
514#define bfin_read_UART_IER() bfin_read16(UART_IER)
515#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
516#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
517#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
518#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
519#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
520#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
521#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
522#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
523#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
524#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
525#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
526/*
527#define UART_MSR
528*/
529#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
530#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
531#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
532#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
533
534/* SPI Controller */
535#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
536#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
537#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
538#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
539#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
540#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
541#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
542#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
543#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
544#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
545#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
546#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
547#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
548#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
549
550/* TIMER 0, 1, 2 Registers */
551#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
552#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
553#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
554#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
555#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
556#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
557#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
558#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
559
560#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
561#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
562#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
563#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
564#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
565#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
566#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
567#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
568
569#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
570#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
571#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
572#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
573#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
574#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
575#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
576#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
577
578#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
579#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
580#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
581#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
582#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
583#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val)
584
585/* SPORT0 Controller */
586#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
587#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
588#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
589#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
590#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
591#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
592#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
593#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
594#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
595#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
596#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
597#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
598#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
599#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
600#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
601#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
602#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
603#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
604#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
605#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
606#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
607#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
608#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
609#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
610#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
611#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
612#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
613#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
614#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
615#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
616#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
617#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
618#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
619#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
620#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
621#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
622#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
623#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
624#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
625#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
626#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
627#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
628#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
629#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
630#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
631#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
632#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
633#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
634#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
635#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
636#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
637#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
638
639/* SPORT1 Controller */
640#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
641#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
642#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
643#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
644#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
645#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
646#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
647#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
648#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
649#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
650#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
651#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
652#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
653#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
654#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
655#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
656#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
657#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
658#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
659#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
660#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
661#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
662#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
663#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
664#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
665#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
666#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
667#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
668#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
669#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
670#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
671#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
672#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
673#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
674#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
675#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
676#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
677#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
678#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
679#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
680#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
681#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
682#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
683#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
684#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
685#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
686#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
687#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
688#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
689#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
690#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
691#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
692
693/* Parallel Peripheral Interface (PPI) */
694#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
695#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
696#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
697#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
698#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS()
699#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
700#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
701#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
702#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
703#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
704#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
705
706#endif /* _CDEF_BF532_H */
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
new file mode 100644
index 000000000000..b240a082aa09
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -0,0 +1,1175 @@
1/************************************************************************
2 *
3 * This file is subject to the terms and conditions of the GNU Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Non-GPL License also available as part of VisualDSP++
8 * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
9 *
10 * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
11 *
12 * This file under source code control, please send bugs or changes to:
13 * dsptools.support@analog.com
14 *
15 ************************************************************************/
16/*
17 * File: include/asm-blackfin/mach-bf533/defBF532.h
18 * Based on:
19 * Author:
20 *
21 * Created:
22 * Description:
23 *
24 * Rev:
25 *
26 * Modified:
27 *
28 * Bugs: Enter bugs at http://blackfin.uclinux.org/
29 *
30 * This program is free software; you can redistribute it and/or modify
31 * it under the terms of the GNU General Public License as published by
32 * the Free Software Foundation; either version 2, or (at your option)
33 * any later version.
34 *
35 * This program is distributed in the hope that it will be useful,
36 * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 * GNU General Public License for more details.
39 *
40 * You should have received a copy of the GNU General Public License
41 * along with this program; see the file COPYING.
42 * If not, write to the Free Software Foundation,
43 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
44 */
45/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
46
47#ifndef _DEF_BF532_H
48#define _DEF_BF532_H
49/*
50#if !defined(__ADSPLPBLACKFIN__)
51#warning defBF532.h should only be included for 532 compatible chips
52#endif
53*/
54/* include all Core registers and bit definitions */
55#include <asm/mach-common/def_LPBlackfin.h>
56
57/*********************************************************************************** */
58/* System MMR Register Map */
59/*********************************************************************************** */
60/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
61
62#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
63#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
64#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
65#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
66#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
67#define CHIPID 0xFFC00014 /* Chip ID Register */
68#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
69#define SYSCR 0xFFC00104 /* System Configuration registe */
70
71/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
72#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
73#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
74#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
75#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
76#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
77#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
78#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
79
80/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
81#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
82#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
83#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
84
85/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
86#define RTC_STAT 0xFFC00300 /* RTC Status Register */
87#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
88#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
89#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
90#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
91#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
92#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
93
94/* UART Controller (0xFFC00400 - 0xFFC004FF) */
95#define UART_THR 0xFFC00400 /* Transmit Holding register */
96#define UART_RBR 0xFFC00400 /* Receive Buffer register */
97#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
98#define UART_IER 0xFFC00404 /* Interrupt Enable Register */
99#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
100#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */
101#define UART_LCR 0xFFC0040C /* Line Control Register */
102#define UART_MCR 0xFFC00410 /* Modem Control Register */
103#define UART_LSR 0xFFC00414 /* Line Status Register */
104#if 0
105#define UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
106#endif
107#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
108#define UART_GCTL 0xFFC00424 /* Global Control Register */
109
110/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
111#define SPI_CTL 0xFFC00500 /* SPI Control Register */
112#define SPI_FLG 0xFFC00504 /* SPI Flag register */
113#define SPI_STAT 0xFFC00508 /* SPI Status register */
114#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
115#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
116#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
117#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
118
119/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
120
121#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
122#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
123#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
124#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
125
126#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
127#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
128#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
129#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
130
131#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
132#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
133#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
134#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
135
136#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
137#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
138#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
139
140/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
141
142#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
143#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
144#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
145#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
146#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
147#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
148#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
149#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
150#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
151#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
152#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
153#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
154#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
155#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
156#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
157#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
158#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
159
160/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
161#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
162#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
163#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
164#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
165#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
166#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
167#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
168#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
169#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
170#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
171#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
172#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
173#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
174#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
175#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
176#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
177#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
178#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
179#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
180#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
181#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
182#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
183
184/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
185#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
186#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
187#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
188#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
189#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
190#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
191#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
192#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
193#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
194#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
195#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
196#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
197#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
198#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
199#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
200#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
201#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
202#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
203#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
204#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
205#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
206#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
207
208/* Asynchronous Memory Controller - External Bus Interface Unit */
209#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
210#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
211#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
212
213/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
214
215#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
216#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
217#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
218#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
219
220/* DMA Traffic controls */
221#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
222#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
223#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
224#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
225
226/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
227#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
228#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
229#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
230#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
231#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
232#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
233#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
234#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
235#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
236#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
237#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
238#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
239#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
240
241#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
242#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
243#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
244#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
245#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
246#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
247#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
248#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
249#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
250#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
251#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
252#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
253#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
254
255#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
256#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
257#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
258#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
259#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
260#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
261#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
262#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
263#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
264#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
265#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
266#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
267#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
268
269#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
270#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
271#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
272#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
273#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
274#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
275#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
276#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
277#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
278#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
279#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
280#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
281#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
282
283#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
284#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
285#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
286#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
287#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
288#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
289#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
290#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
291#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
292#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
293#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
294#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
295#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
296
297#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
298#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
299#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
300#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
301#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
302#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
303#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
304#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
305#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
306#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
307#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
308#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
309#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
310
311#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
312#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
313#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
314#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
315#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
316#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
317#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
318#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
319#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
320#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
321#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
322#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
323#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
324
325#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
326#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
327#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
328#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
329#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
330#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
331#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
332#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
333#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
334#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
335#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
336#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
337#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
338
339#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
340#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
341#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */
342#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */
343#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */
344#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */
345#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */
346#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
347#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */
348#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */
349#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */
350#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
351#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */
352
353#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */
354#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
355#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */
356#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */
357#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */
358#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */
359#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */
360#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
361#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */
362#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */
363#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */
364#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
365#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */
366
367#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */
368#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
369#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */
370#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */
371#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */
372#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */
373#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */
374#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
375#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */
376#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */
377#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */
378#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
379#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */
380
381#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */
382#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
383#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */
384#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */
385#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */
386#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */
387#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */
388#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
389#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */
390#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */
391#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */
392#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */
393#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */
394
395/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
396
397#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
398#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
399#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
400#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
401#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
402
403/*********************************************************************************** */
404/* System MMR Register Bits */
405/******************************************************************************* */
406
407/* ********************* PLL AND RESET MASKS ************************ */
408
409/* PLL_CTL Masks */
410#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */
411#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */
412#define PLL_OFF 0x00000002 /* Shut off PLL clocks */
413#define STOPCK_OFF 0x00000008 /* Core clock off */
414#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */
415#define BYPASS 0x00000100 /* Bypass the PLL */
416
417/* PLL_DIV Masks */
418
419#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
420
421#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
422#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
423#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
424#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
425
426/* PLL_STAT Masks */
427#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
428#define FULL_ON 0x0002 /* Processor In Full On Mode */
429#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
430#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
431
432/* CHIPID Masks */
433#define CHIPID_VERSION 0xF0000000
434#define CHIPID_FAMILY 0x0FFFF000
435#define CHIPID_MANUFACTURE 0x00000FFE
436
437/* SWRST Mask */
438#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */
439
440/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
441
442 /* SIC_IAR0 Masks */
443
444#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
445#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
446#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
447#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
448#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
449#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
450#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
451#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
452
453/* SIC_IAR1 Masks */
454
455#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
456#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
457#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
458#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
459#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
460#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
461#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
462#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
463
464/* SIC_IAR2 Masks */
465#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
466#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
467#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
468#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
469#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
470#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
471#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
472#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
473
474/* SIC_IMASK Masks */
475#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
476#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
477#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
478#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
479
480/* SIC_IWR Masks */
481#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
482#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
483#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
484#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
485
486/* ********* WATCHDOG TIMER MASKS ********************8 */
487
488/* Watchdog Timer WDOG_CTL Register */
489#define ICTL(x) ((x<<1) & 0x0006)
490#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */
491#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */
492#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */
493#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */
494
495#define TMR_EN 0x0000
496#define TMR_DIS 0x0AD0
497#define TRO 0x8000
498
499#define ICTL_P0 0x01
500#define ICTL_P1 0x02
501#define TRO_P 0x0F
502
503/* ***************************** UART CONTROLLER MASKS ********************** */
504
505/* UART_LCR Register */
506
507#define DLAB 0x80
508#define SB 0x40
509#define STP 0x20
510#define EPS 0x10
511#define PEN 0x08
512#define STB 0x04
513#define WLS(x) ((x-5) & 0x03)
514
515#define DLAB_P 0x07
516#define SB_P 0x06
517#define STP_P 0x05
518#define EPS_P 0x04
519#define PEN_P 0x03
520#define STB_P 0x02
521#define WLS_P1 0x01
522#define WLS_P0 0x00
523
524/* UART_MCR Register */
525#define LOOP_ENA 0x10
526#define LOOP_ENA_P 0x04
527
528/* UART_LSR Register */
529#define TEMT 0x40
530#define THRE 0x20
531#define BI 0x10
532#define FE 0x08
533#define PE 0x04
534#define OE 0x02
535#define DR 0x01
536
537#define TEMP_P 0x06
538#define THRE_P 0x05
539#define BI_P 0x04
540#define FE_P 0x03
541#define PE_P 0x02
542#define OE_P 0x01
543#define DR_P 0x00
544
545/* UART_IER Register */
546#define ELSI 0x04
547#define ETBEI 0x02
548#define ERBFI 0x01
549
550#define ELSI_P 0x02
551#define ETBEI_P 0x01
552#define ERBFI_P 0x00
553
554/* UART_IIR Register */
555#define STATUS(x) ((x << 1) & 0x06)
556#define NINT 0x01
557#define STATUS_P1 0x02
558#define STATUS_P0 0x01
559#define NINT_P 0x00
560#define IIR_TX_READY 0x02 /* UART_THR empty */
561#define IIR_RX_READY 0x04 /* Receive data ready */
562#define IIR_LINE_CHANGE 0x06 /* Receive line status */
563#define IIR_STATUS 0x06
564
565/* UART_GCTL Register */
566#define FFE 0x20
567#define FPE 0x10
568#define RPOLC 0x08
569#define TPOLC 0x04
570#define IREN 0x02
571#define UCEN 0x01
572
573#define FFE_P 0x05
574#define FPE_P 0x04
575#define RPOLC_P 0x03
576#define TPOLC_P 0x02
577#define IREN_P 0x01
578#define UCEN_P 0x00
579
580/* ********** SERIAL PORT MASKS ********************** */
581
582/* SPORTx_TCR1 Masks */
583#define TSPEN 0x0001 /* TX enable */
584#define ITCLK 0x0002 /* Internal TX Clock Select */
585#define TDTYPE 0x000C /* TX Data Formatting Select */
586#define TLSBIT 0x0010 /* TX Bit Order */
587#define ITFS 0x0200 /* Internal TX Frame Sync Select */
588#define TFSR 0x0400 /* TX Frame Sync Required Select */
589#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
590#define LTFS 0x1000 /* Low TX Frame Sync Select */
591#define LATFS 0x2000 /* Late TX Frame Sync Select */
592#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
593
594/* SPORTx_TCR2 Masks */
595#define SLEN 0x001F /*TX Word Length */
596#define TXSE 0x0100 /*TX Secondary Enable */
597#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
598#define TRFST 0x0400 /*TX Right-First Data Order */
599
600/* SPORTx_RCR1 Masks */
601#define RSPEN 0x0001 /* RX enable */
602#define IRCLK 0x0002 /* Internal RX Clock Select */
603#define RDTYPE 0x000C /* RX Data Formatting Select */
604#define RULAW 0x0008 /* u-Law enable */
605#define RALAW 0x000C /* A-Law enable */
606#define RLSBIT 0x0010 /* RX Bit Order */
607#define IRFS 0x0200 /* Internal RX Frame Sync Select */
608#define RFSR 0x0400 /* RX Frame Sync Required Select */
609#define LRFS 0x1000 /* Low RX Frame Sync Select */
610#define LARFS 0x2000 /* Late RX Frame Sync Select */
611#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
612
613/* SPORTx_RCR2 Masks */
614#define SLEN 0x001F /*RX Word Length */
615#define RXSE 0x0100 /*RX Secondary Enable */
616#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
617#define RRFST 0x0400 /*Right-First Data Order */
618
619/*SPORTx_STAT Masks */
620#define RXNE 0x0001 /*RX FIFO Not Empty Status */
621#define RUVF 0x0002 /*RX Underflow Status */
622#define ROVF 0x0004 /*RX Overflow Status */
623#define TXF 0x0008 /*TX FIFO Full Status */
624#define TUVF 0x0010 /*TX Underflow Status */
625#define TOVF 0x0020 /*TX Overflow Status */
626#define TXHRE 0x0040 /*TX Hold Register Empty */
627
628/*SPORTx_MCMC1 Masks */
629#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
630#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
631
632/*SPORTx_MCMC2 Masks */
633#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
634#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
635#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
636#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
637#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
638#define MFD 0x0000F000 /*Multichannel Frame Delay */
639
640/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
641
642/* PPI_CONTROL Masks */
643#define PORT_EN 0x00000001 /* PPI Port Enable */
644#define PORT_DIR 0x00000002 /* PPI Port Direction */
645#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
646#define PORT_CFG 0x00000030 /* PPI Port Configuration */
647#define FLD_SEL 0x00000040 /* PPI Active Field Select */
648#define PACK_EN 0x00000080 /* PPI Packing Mode */
649#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
650#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
651#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
652#define DLENGTH 0x00003800 /* PPI Data Length */
653#define DLEN_8 0x0000 /* Data Length = 8 Bits */
654#define DLEN_10 0x0800 /* Data Length = 10 Bits */
655#define DLEN_11 0x1000 /* Data Length = 11 Bits */
656#define DLEN_12 0x1800 /* Data Length = 12 Bits */
657#define DLEN_13 0x2000 /* Data Length = 13 Bits */
658#define DLEN_14 0x2800 /* Data Length = 14 Bits */
659#define DLEN_15 0x3000 /* Data Length = 15 Bits */
660#define DLEN_16 0x3800 /* Data Length = 16 Bits */
661#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
662#define POL 0x0000C000 /* PPI Signal Polarities */
663
664/* PPI_STATUS Masks */
665#define FLD 0x00000400 /* Field Indicator */
666#define FT_ERR 0x00000800 /* Frame Track Error */
667#define OVR 0x00001000 /* FIFO Overflow Error */
668#define UNDR 0x00002000 /* FIFO Underrun Error */
669#define ERR_DET 0x00004000 /* Error Detected Indicator */
670#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
671
672/* ********** DMA CONTROLLER MASKS *********************8 */
673
674/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */
675#define DMAEN 0x00000001 /* Channel Enable */
676#define WNR 0x00000002 /* Channel Direction (W/R*) */
677#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
678#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
679#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
680#define DMA2D 0x00000010 /* 2D/1D* Mode */
681#define RESTART 0x00000020 /* Restart */
682#define DI_SEL 0x00000040 /* Data Interrupt Select */
683#define DI_EN 0x00000080 /* Data Interrupt Enable */
684#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
685#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
686#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
687#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
688#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
689#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
690#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
691#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
692#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
693#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
694#define NDSIZE 0x00000900 /* Next Descriptor Size */
695#define DMAFLOW 0x00007000 /* Flow Control */
696#define DMAFLOW_STOP 0x0000 /* Stop Mode */
697#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
698#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
699#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
700#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
701
702#define DMAEN_P 0 /* Channel Enable */
703#define WNR_P 1 /* Channel Direction (W/R*) */
704#define DMA2D_P 4 /* 2D/1D* Mode */
705#define RESTART_P 5 /* Restart */
706#define DI_SEL_P 6 /* Data Interrupt Select */
707#define DI_EN_P 7 /* Data Interrupt Enable */
708
709/*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
710
711#define DMA_DONE 0x00000001 /* DMA Done Indicator */
712#define DMA_ERR 0x00000002 /* DMA Error Indicator */
713#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
714#define DMA_RUN 0x00000008 /* DMA Running Indicator */
715
716#define DMA_DONE_P 0 /* DMA Done Indicator */
717#define DMA_ERR_P 1 /* DMA Error Indicator */
718#define DFETCH_P 2 /* Descriptor Fetch Indicator */
719#define DMA_RUN_P 3 /* DMA Running Indicator */
720
721/*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
722
723#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
724#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
725#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
726#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
727#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
728#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
729#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
730#define PMAP 0x00007000 /* DMA Peripheral Map Field */
731
732/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
733
734/* PWM Timer bit definitions */
735
736/* TIMER_ENABLE Register */
737#define TIMEN0 0x0001
738#define TIMEN1 0x0002
739#define TIMEN2 0x0004
740
741#define TIMEN0_P 0x00
742#define TIMEN1_P 0x01
743#define TIMEN2_P 0x02
744
745/* TIMER_DISABLE Register */
746#define TIMDIS0 0x0001
747#define TIMDIS1 0x0002
748#define TIMDIS2 0x0004
749
750#define TIMDIS0_P 0x00
751#define TIMDIS1_P 0x01
752#define TIMDIS2_P 0x02
753
754/* TIMER_STATUS Register */
755#define TIMIL0 0x0001
756#define TIMIL1 0x0002
757#define TIMIL2 0x0004
758#define TOVL_ERR0 0x0010
759#define TOVL_ERR1 0x0020
760#define TOVL_ERR2 0x0040
761#define TRUN0 0x1000
762#define TRUN1 0x2000
763#define TRUN2 0x4000
764
765#define TIMIL0_P 0x00
766#define TIMIL1_P 0x01
767#define TIMIL2_P 0x02
768#define TOVL_ERR0_P 0x04
769#define TOVL_ERR1_P 0x05
770#define TOVL_ERR2_P 0x06
771#define TRUN0_P 0x0C
772#define TRUN1_P 0x0D
773#define TRUN2_P 0x0E
774
775/* TIMERx_CONFIG Registers */
776#define PWM_OUT 0x0001
777#define WDTH_CAP 0x0002
778#define EXT_CLK 0x0003
779#define PULSE_HI 0x0004
780#define PERIOD_CNT 0x0008
781#define IRQ_ENA 0x0010
782#define TIN_SEL 0x0020
783#define OUT_DIS 0x0040
784#define CLK_SEL 0x0080
785#define TOGGLE_HI 0x0100
786#define EMU_RUN 0x0200
787#define ERR_TYP(x) ((x & 0x03) << 14)
788
789#define TMODE_P0 0x00
790#define TMODE_P1 0x01
791#define PULSE_HI_P 0x02
792#define PERIOD_CNT_P 0x03
793#define IRQ_ENA_P 0x04
794#define TIN_SEL_P 0x05
795#define OUT_DIS_P 0x06
796#define CLK_SEL_P 0x07
797#define TOGGLE_HI_P 0x08
798#define EMU_RUN_P 0x09
799#define ERR_TYP_P0 0x0E
800#define ERR_TYP_P1 0x0F
801
802/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
803
804/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
805#define PF0 0x0001
806#define PF1 0x0002
807#define PF2 0x0004
808#define PF3 0x0008
809#define PF4 0x0010
810#define PF5 0x0020
811#define PF6 0x0040
812#define PF7 0x0080
813#define PF8 0x0100
814#define PF9 0x0200
815#define PF10 0x0400
816#define PF11 0x0800
817#define PF12 0x1000
818#define PF13 0x2000
819#define PF14 0x4000
820#define PF15 0x8000
821
822/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
823#define PF0_P 0
824#define PF1_P 1
825#define PF2_P 2
826#define PF3_P 3
827#define PF4_P 4
828#define PF5_P 5
829#define PF6_P 6
830#define PF7_P 7
831#define PF8_P 8
832#define PF9_P 9
833#define PF10_P 10
834#define PF11_P 11
835#define PF12_P 12
836#define PF13_P 13
837#define PF14_P 14
838#define PF15_P 15
839
840/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
841
842/* SPI_CTL Masks */
843#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
844#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
845#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
846#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
847#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
848#define SPI_LEN 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
849#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
850#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
851#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
852#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
853#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
854#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
855
856/* SPI_FLG Masks */
857#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
858#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
859#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
860#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
861#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
862#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
863#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
864#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
865#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
866#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
867#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
868#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
869#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
870#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
871
872/* SPI_FLG Bit Positions */
873#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
874#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
875#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
876#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
877#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
878#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
879#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
880#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
881#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
882#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
883#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
884#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
885#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
886#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
887
888/* SPI_STAT Masks */
889#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
890#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
891#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
892#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
893#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
894#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
895#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
896
897/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
898
899/* AMGCTL Masks */
900#define AMCKEN 0x00000001 /* Enable CLKOUT */
901#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
902#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
903#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
904#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
905
906/* AMGCTL Bit Positions */
907#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
908#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
909#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
910#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
911
912/* AMBCTL0 Masks */
913#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
914#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
915#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
916#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
917#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
918#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
919#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
920#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
921#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
922#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
923#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
924#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
925#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
926#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
927#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
928#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
929#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
930#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
931#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
932#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
933#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
934#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
935#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
936#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
937#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
938#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
939#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
940#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
941#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
942#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
943#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
944#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
945#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
946#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
947#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
948#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
949#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
950#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
951#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
952#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
953#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
954#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
955#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
956#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
957#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
958#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
959#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
960#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
961#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
962#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
963#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
964#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
965#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
966#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
967#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
968#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
969#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
970#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
971#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
972#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
973#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
974#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
975#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
976#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
977#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
978#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
979#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
980#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
981#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
982#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
983#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
984#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
985#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
986#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
987#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
988#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
989#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
990#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
991#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
992#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
993#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
994#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
995#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
996#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
997#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
998#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
999#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
1000#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
1001
1002/* AMBCTL1 Masks */
1003#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
1004#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
1005#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
1006#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
1007#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
1008#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
1009#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1010#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1011#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1012#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1013#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1014#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1015#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1016#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1017#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
1018#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
1019#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
1020#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
1021#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
1022#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
1023#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
1024#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
1025#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
1026#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
1027#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
1028#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
1029#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
1030#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
1031#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
1032#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
1033#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
1034#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
1035#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
1036#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
1037#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
1038#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
1039#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
1040#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
1041#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
1042#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
1043#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
1044#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
1045#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
1046#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
1047#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
1048#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
1049#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
1050#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
1051#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
1052#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
1053#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1054#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1055#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1056#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1057#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1058#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1059#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1060#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1061#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
1062#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
1063#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
1064#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
1065#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
1066#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
1067#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
1068#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
1069#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
1070#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
1071#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
1072#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
1073#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
1074#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
1075#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
1076#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
1077#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
1078#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
1079#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
1080#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
1081#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
1082#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
1083#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
1084#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
1085#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
1086#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
1087#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
1088#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
1089#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
1090#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
1091
1092/* ********************** SDRAM CONTROLLER MASKS *************************** */
1093
1094/* SDGCTL Masks */
1095#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
1096#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
1097#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
1098#define PFE 0x00000010 /* Enable SDRAM prefetch */
1099#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
1100#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1101#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1102#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1103#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1104#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1105#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1106#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1107#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1108#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1109#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1110#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1111#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1112#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1113#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1114#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1115#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1116#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1117#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1118#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1119#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1120#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1121#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1122#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1123#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1124#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1125#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1126#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1127#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1128#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1129#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1130#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1131#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1132#define PUPSD 0x00200000 /*Power-up start delay */
1133#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
1134#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
1135#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
1136#define EBUFE 0x02000000 /* Enable external buffering timing */
1137#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
1138#define EMREN 0x10000000 /* Extended mode register enable */
1139#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
1140#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
1141
1142/* EBIU_SDBCTL Masks */
1143#define EBE 0x00000001 /* Enable SDRAM external bank */
1144#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1145#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
1146#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
1147#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
1148#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1149#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
1150#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
1151#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
1152
1153/* EBIU_SDSTAT Masks */
1154#define SDCI 0x00000001 /* SDRAM controller is idle */
1155#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
1156#define SDPUA 0x00000004 /* SDRAM power up active */
1157#define SDRS 0x00000008 /* SDRAM is in reset state */
1158#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1159#define BGSTAT 0x00000020 /* Bus granted */
1160
1161/*VR_CTL Masks*/
1162#define WAKE 0x100
1163#define VLEV_6 0x60
1164#define VLEV_7 0x70
1165#define VLEV_8 0x80
1166#define VLEV_9 0x90
1167#define VLEV_10 0xA0
1168#define VLEV_11 0xB0
1169#define VLEV_12 0xC0
1170#define VLEV_13 0xD0
1171#define VLEV_14 0xE0
1172#define VLEV_15 0xF0
1173#define FREQ_3 0x03
1174
1175#endif /* _DEF_BF532_H */
diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h
new file mode 100644
index 000000000000..bd9d5e94307d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/dma.h
@@ -0,0 +1,54 @@
1/*****************************************************************************
2*
3* BF-533/2/1 Specific Declarations
4*
5****************************************************************************/
6/*
7 * File: include/asm-blackfin/mach-bf533/dma.h
8 * Based on:
9 * Author:
10 *
11 * Created:
12 * Description:
13 *
14 * Rev:
15 *
16 * Modified:
17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING.
32 * If not, write to the Free Software Foundation,
33 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 */
35
36#ifndef _MACH_DMA_H_
37#define _MACH_DMA_H_
38
39#define MAX_BLACKFIN_DMA_CHANNEL 12
40
41#define CH_PPI 0
42#define CH_SPORT0_RX 1
43#define CH_SPORT0_TX 2
44#define CH_SPORT1_RX 3
45#define CH_SPORT1_TX 4
46#define CH_SPI 5
47#define CH_UART_RX 6
48#define CH_UART_TX 7
49#define CH_MEM_STREAM0_DEST 8 /* TX */
50#define CH_MEM_STREAM0_SRC 9 /* RX */
51#define CH_MEM_STREAM1_DEST 10 /* TX */
52#define CH_MEM_STREAM1_SRC 11 /* RX */
53
54#endif
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
new file mode 100644
index 000000000000..9879e68e315c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/irq.h
@@ -0,0 +1,177 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/defBF532.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _BF533_IRQ_H_
32#define _BF533_IRQ_H_
33
34/*
35 * Interrupt source definitions
36 Event Source Core Event Name
37Core Emulation **
38 Events (highest priority) EMU 0
39 Reset RST 1
40 NMI NMI 2
41 Exception EVX 3
42 Reserved -- 4
43 Hardware Error IVHW 5
44 Core Timer IVTMR 6 *
45 PLL Wakeup Interrupt IVG7 7
46 DMA Error (generic) IVG7 8
47 PPI Error Interrupt IVG7 9
48 SPORT0 Error Interrupt IVG7 10
49 SPORT1 Error Interrupt IVG7 11
50 SPI Error Interrupt IVG7 12
51 UART Error Interrupt IVG7 13
52 RTC Interrupt IVG8 14
53 DMA0 Interrupt (PPI) IVG8 15
54 DMA1 (SPORT0 RX) IVG9 16
55 DMA2 (SPORT0 TX) IVG9 17
56 DMA3 (SPORT1 RX) IVG9 18
57 DMA4 (SPORT1 TX) IVG9 19
58 DMA5 (PPI) IVG10 20
59 DMA6 (UART RX) IVG10 21
60 DMA7 (UART TX) IVG10 22
61 Timer0 IVG11 23
62 Timer1 IVG11 24
63 Timer2 IVG11 25
64 PF Interrupt A IVG12 26
65 PF Interrupt B IVG12 27
66 DMA8/9 Interrupt IVG13 28
67 DMA10/11 Interrupt IVG13 29
68 Watchdog Timer IVG13 30
69 Software Interrupt 1 IVG14 31
70 Software Interrupt 2 --
71 (lowest priority) IVG15 32 *
72 */
73#define SYS_IRQS 32
74#define NR_PERI_INTS 24
75
76/* The ABSTRACT IRQ definitions */
77/** the first seven of the following are fixed, the rest you change if you need to **/
78#define IRQ_EMU 0 /*Emulation */
79#define IRQ_RST 1 /*reset */
80#define IRQ_NMI 2 /*Non Maskable */
81#define IRQ_EVX 3 /*Exception */
82#define IRQ_UNUSED 4 /*- unused interrupt*/
83#define IRQ_HWERR 5 /*Hardware Error */
84#define IRQ_CORETMR 6 /*Core timer */
85
86#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
87#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
88#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */
89#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */
90#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */
91#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */
92#define IRQ_UART_ERROR 13 /*UART Error Interrupt */
93#define IRQ_RTC 14 /*RTC Interrupt */
94#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */
95#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */
96#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
97#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
98#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
99#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
100#define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */
101#define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */
102#define IRQ_TMR0 23 /*Timer 0 */
103#define IRQ_TMR1 24 /*Timer 1 */
104#define IRQ_TMR2 25 /*Timer 2 */
105#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */
106#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */
107#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */
108#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */
109#define IRQ_WATCH 30 /*Watch Dog Timer */
110
111#define IRQ_SW_INT1 31 /*Software Int 1 */
112#define IRQ_SW_INT2 32 /*Software Int 2 (reserved for SYSCALL) */
113
114#define IRQ_PF0 33
115#define IRQ_PF1 34
116#define IRQ_PF2 35
117#define IRQ_PF3 36
118#define IRQ_PF4 37
119#define IRQ_PF5 38
120#define IRQ_PF6 39
121#define IRQ_PF7 40
122#define IRQ_PF8 41
123#define IRQ_PF9 42
124#define IRQ_PF10 43
125#define IRQ_PF11 44
126#define IRQ_PF12 45
127#define IRQ_PF13 46
128#define IRQ_PF14 47
129#define IRQ_PF15 48
130
131#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
132#define NR_IRQS (IRQ_PF15+1)
133#else
134#define NR_IRQS SYS_IRQS
135#endif
136
137#define IVG7 7
138#define IVG8 8
139#define IVG9 9
140#define IVG10 10
141#define IVG11 11
142#define IVG12 12
143#define IVG13 13
144#define IVG14 14
145#define IVG15 15
146
147/* IAR0 BIT FIELDS*/
148#define RTC_ERROR_POS 28
149#define UART_ERROR_POS 24
150#define SPORT1_ERROR_POS 20
151#define SPI_ERROR_POS 16
152#define SPORT0_ERROR_POS 12
153#define PPI_ERROR_POS 8
154#define DMA_ERROR_POS 4
155#define PLLWAKE_ERROR_POS 0
156
157/* IAR1 BIT FIELDS*/
158#define DMA7_UARTTX_POS 28
159#define DMA6_UARTRX_POS 24
160#define DMA5_SPI_POS 20
161#define DMA4_SPORT1TX_POS 16
162#define DMA3_SPORT1RX_POS 12
163#define DMA2_SPORT0TX_POS 8
164#define DMA1_SPORT0RX_POS 4
165#define DMA0_PPI_POS 0
166
167/* IAR2 BIT FIELDS*/
168#define WDTIMER_POS 28
169#define MEMDMA1_POS 24
170#define MEMDMA0_POS 20
171#define PFB_POS 16
172#define PFA_POS 12
173#define TIMER2_POS 8
174#define TIMER1_POS 4
175#define TIMER0_POS 0
176
177#endif /* _BF533_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf533/mem_init.h b/include/asm-blackfin/mach-bf533/mem_init.h
new file mode 100644
index 000000000000..1620dae5254d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/mem_init.h
@@ -0,0 +1,316 @@
1/*
2 * File: include/asm-blackfin/mach-bf533/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD)
33#if (CONFIG_SCLK_HZ > 119402985)
34#define SDRAM_tRP TRP_2
35#define SDRAM_tRP_num 2
36#define SDRAM_tRAS TRAS_7
37#define SDRAM_tRAS_num 7
38#define SDRAM_tRCD TRCD_2
39#define SDRAM_tWR TWR_2
40#endif
41#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
42#define SDRAM_tRP TRP_2
43#define SDRAM_tRP_num 2
44#define SDRAM_tRAS TRAS_6
45#define SDRAM_tRAS_num 6
46#define SDRAM_tRCD TRCD_2
47#define SDRAM_tWR TWR_2
48#endif
49#if (CONFIG_SCLK_HZ > 8955223) && (CONFIG_SCLK_HZ <= 104477612)
50#define SDRAM_tRP TRP_2
51#define SDRAM_tRP_num 2
52#define SDRAM_tRAS TRAS_5
53#define SDRAM_tRAS_num 5
54#define SDRAM_tRCD TRCD_2
55#define SDRAM_tWR TWR_2
56#endif
57#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
58#define SDRAM_tRP TRP_2
59#define SDRAM_tRP_num 2
60#define SDRAM_tRAS TRAS_4
61#define SDRAM_tRAS_num 4
62#define SDRAM_tRCD TRCD_2
63#define SDRAM_tWR TWR_2
64#endif
65#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
66#define SDRAM_tRP TRP_2
67#define SDRAM_tRP_num 2
68#define SDRAM_tRAS TRAS_3
69#define SDRAM_tRAS_num 3
70#define SDRAM_tRCD TRCD_2
71#define SDRAM_tWR TWR_2
72#endif
73#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
74#define SDRAM_tRP TRP_1
75#define SDRAM_tRP_num 1
76#define SDRAM_tRAS TRAS_4
77#define SDRAM_tRAS_num 3
78#define SDRAM_tRCD TRCD_1
79#define SDRAM_tWR TWR_2
80#endif
81#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
82#define SDRAM_tRP TRP_1
83#define SDRAM_tRP_num 1
84#define SDRAM_tRAS TRAS_3
85#define SDRAM_tRAS_num 3
86#define SDRAM_tRCD TRCD_1
87#define SDRAM_tWR TWR_2
88#endif
89#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
90#define SDRAM_tRP TRP_1
91#define SDRAM_tRP_num 1
92#define SDRAM_tRAS TRAS_2
93#define SDRAM_tRAS_num 2
94#define SDRAM_tRCD TRCD_1
95#define SDRAM_tWR TWR_2
96#endif
97#if (CONFIG_SCLK_HZ <= 29850746)
98#define SDRAM_tRP TRP_1
99#define SDRAM_tRP_num 1
100#define SDRAM_tRAS TRAS_1
101#define SDRAM_tRAS_num 1
102#define SDRAM_tRCD TRCD_1
103#define SDRAM_tWR TWR_2
104#endif
105#endif
106
107#if (CONFIG_MEM_MT48LC16M16A2TG_75)
108 /*SDRAM INFORMATION: */
109#define SDRAM_Tref 64 /* Refresh period in milliseconds */
110#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
111#define SDRAM_CL CL_3
112#endif
113
114#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
115 /*SDRAM INFORMATION: */
116#define SDRAM_Tref 64 /* Refresh period in milliseconds */
117#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
118#define SDRAM_CL CL_3
119#endif
120
121#if (CONFIG_MEM_GENERIC_BOARD)
122 /*SDRAM INFORMATION: Modify this for your board */
123#define SDRAM_Tref 64 /* Refresh period in milliseconds */
124#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
125#define SDRAM_CL CL_3
126#endif
127
128#if (CONFIG_MEM_SIZE == 128)
129#define SDRAM_SIZE EBSZ_128
130#endif
131#if (CONFIG_MEM_SIZE == 64)
132#define SDRAM_SIZE EBSZ_64
133#endif
134#if (CONFIG_MEM_SIZE == 32)
135#define SDRAM_SIZE EBSZ_32
136#endif
137#if (CONFIG_MEM_SIZE == 16)
138#define SDRAM_SIZE EBSZ_16
139#endif
140#if (CONFIG_MEM_ADD_WIDTH == 11)
141#define SDRAM_WIDTH EBCAW_11
142#endif
143#if (CONFIG_MEM_ADD_WIDTH == 10)
144#define SDRAM_WIDTH EBCAW_10
145#endif
146#if (CONFIG_MEM_ADD_WIDTH == 9)
147#define SDRAM_WIDTH EBCAW_9
148#endif
149#if (CONFIG_MEM_ADD_WIDTH == 8)
150#define SDRAM_WIDTH EBCAW_8
151#endif
152
153#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
154
155/* Equation from section 17 (p17-46) of BF533 HRM */
156#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
157
158/* Enable SCLK Out */
159#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
160
161#if defined CONFIG_CLKIN_HALF
162#define CLKIN_HALF 1
163#else
164#define CLKIN_HALF 0
165#endif
166
167#if defined CONFIG_PLL_BYPASS
168#define PLL_BYPASS 1
169#else
170#define PLL_BYPASS 0
171#endif
172
173/***************************************Currently Not Being Used *********************************/
174#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
175#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
176#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
177#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
178#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
179
180#if (flash_EBIU_AMBCTL_TT > 3)
181#define flash_EBIU_AMBCTL0_TT B0TT_4
182#endif
183#if (flash_EBIU_AMBCTL_TT == 3)
184#define flash_EBIU_AMBCTL0_TT B0TT_3
185#endif
186#if (flash_EBIU_AMBCTL_TT == 2)
187#define flash_EBIU_AMBCTL0_TT B0TT_2
188#endif
189#if (flash_EBIU_AMBCTL_TT < 2)
190#define flash_EBIU_AMBCTL0_TT B0TT_1
191#endif
192
193#if (flash_EBIU_AMBCTL_ST > 3)
194#define flash_EBIU_AMBCTL0_ST B0ST_4
195#endif
196#if (flash_EBIU_AMBCTL_ST == 3)
197#define flash_EBIU_AMBCTL0_ST B0ST_3
198#endif
199#if (flash_EBIU_AMBCTL_ST == 2)
200#define flash_EBIU_AMBCTL0_ST B0ST_2
201#endif
202#if (flash_EBIU_AMBCTL_ST < 2)
203#define flash_EBIU_AMBCTL0_ST B0ST_1
204#endif
205
206#if (flash_EBIU_AMBCTL_HT > 2)
207#define flash_EBIU_AMBCTL0_HT B0HT_3
208#endif
209#if (flash_EBIU_AMBCTL_HT == 2)
210#define flash_EBIU_AMBCTL0_HT B0HT_2
211#endif
212#if (flash_EBIU_AMBCTL_HT == 1)
213#define flash_EBIU_AMBCTL0_HT B0HT_1
214#endif
215#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
216#define flash_EBIU_AMBCTL0_HT B0HT_0
217#endif
218#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
219#define flash_EBIU_AMBCTL0_HT B0HT_1
220#endif
221
222#if (flash_EBIU_AMBCTL_WAT > 14)
223#define flash_EBIU_AMBCTL0_WAT B0WAT_15
224#endif
225#if (flash_EBIU_AMBCTL_WAT == 14)
226#define flash_EBIU_AMBCTL0_WAT B0WAT_14
227#endif
228#if (flash_EBIU_AMBCTL_WAT == 13)
229#define flash_EBIU_AMBCTL0_WAT B0WAT_13
230#endif
231#if (flash_EBIU_AMBCTL_WAT == 12)
232#define flash_EBIU_AMBCTL0_WAT B0WAT_12
233#endif
234#if (flash_EBIU_AMBCTL_WAT == 11)
235#define flash_EBIU_AMBCTL0_WAT B0WAT_11
236#endif
237#if (flash_EBIU_AMBCTL_WAT == 10)
238#define flash_EBIU_AMBCTL0_WAT B0WAT_10
239#endif
240#if (flash_EBIU_AMBCTL_WAT == 9)
241#define flash_EBIU_AMBCTL0_WAT B0WAT_9
242#endif
243#if (flash_EBIU_AMBCTL_WAT == 8)
244#define flash_EBIU_AMBCTL0_WAT B0WAT_8
245#endif
246#if (flash_EBIU_AMBCTL_WAT == 7)
247#define flash_EBIU_AMBCTL0_WAT B0WAT_7
248#endif
249#if (flash_EBIU_AMBCTL_WAT == 6)
250#define flash_EBIU_AMBCTL0_WAT B0WAT_6
251#endif
252#if (flash_EBIU_AMBCTL_WAT == 5)
253#define flash_EBIU_AMBCTL0_WAT B0WAT_5
254#endif
255#if (flash_EBIU_AMBCTL_WAT == 4)
256#define flash_EBIU_AMBCTL0_WAT B0WAT_4
257#endif
258#if (flash_EBIU_AMBCTL_WAT == 3)
259#define flash_EBIU_AMBCTL0_WAT B0WAT_3
260#endif
261#if (flash_EBIU_AMBCTL_WAT == 2)
262#define flash_EBIU_AMBCTL0_WAT B0WAT_2
263#endif
264#if (flash_EBIU_AMBCTL_WAT == 1)
265#define flash_EBIU_AMBCTL0_WAT B0WAT_1
266#endif
267
268#if (flash_EBIU_AMBCTL_RAT > 14)
269#define flash_EBIU_AMBCTL0_RAT B0RAT_15
270#endif
271#if (flash_EBIU_AMBCTL_RAT == 14)
272#define flash_EBIU_AMBCTL0_RAT B0RAT_14
273#endif
274#if (flash_EBIU_AMBCTL_RAT == 13)
275#define flash_EBIU_AMBCTL0_RAT B0RAT_13
276#endif
277#if (flash_EBIU_AMBCTL_RAT == 12)
278#define flash_EBIU_AMBCTL0_RAT B0RAT_12
279#endif
280#if (flash_EBIU_AMBCTL_RAT == 11)
281#define flash_EBIU_AMBCTL0_RAT B0RAT_11
282#endif
283#if (flash_EBIU_AMBCTL_RAT == 10)
284#define flash_EBIU_AMBCTL0_RAT B0RAT_10
285#endif
286#if (flash_EBIU_AMBCTL_RAT == 9)
287#define flash_EBIU_AMBCTL0_RAT B0RAT_9
288#endif
289#if (flash_EBIU_AMBCTL_RAT == 8)
290#define flash_EBIU_AMBCTL0_RAT B0RAT_8
291#endif
292#if (flash_EBIU_AMBCTL_RAT == 7)
293#define flash_EBIU_AMBCTL0_RAT B0RAT_7
294#endif
295#if (flash_EBIU_AMBCTL_RAT == 6)
296#define flash_EBIU_AMBCTL0_RAT B0RAT_6
297#endif
298#if (flash_EBIU_AMBCTL_RAT == 5)
299#define flash_EBIU_AMBCTL0_RAT B0RAT_5
300#endif
301#if (flash_EBIU_AMBCTL_RAT == 4)
302#define flash_EBIU_AMBCTL0_RAT B0RAT_4
303#endif
304#if (flash_EBIU_AMBCTL_RAT == 3)
305#define flash_EBIU_AMBCTL0_RAT B0RAT_3
306#endif
307#if (flash_EBIU_AMBCTL_RAT == 2)
308#define flash_EBIU_AMBCTL0_RAT B0RAT_2
309#endif
310#if (flash_EBIU_AMBCTL_RAT == 1)
311#define flash_EBIU_AMBCTL0_RAT B0RAT_1
312#endif
313
314#define flash_EBIU_AMBCTL0 \
315 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
316 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h
new file mode 100644
index 000000000000..e84baa3e939d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/mem_map.h
@@ -0,0 +1,168 @@
1
2/*
3 * File: include/asm-blackfin/mach-bf533/mem_map.h
4 * Based on:
5 * Author:
6 *
7 * Created:
8 * Description:
9 *
10 * Rev:
11 *
12 * Modified:
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _MEM_MAP_533_H_
33#define _MEM_MAP_533_H_
34
35#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
36#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
37
38/* Async Memory Banks */
39#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
40#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
41#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
42#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
43#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
44#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
45#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
46#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
47
48/* Boot ROM Memory */
49
50#define BOOT_ROM_START 0xEF000000
51
52/* Level 1 Memory */
53
54#ifdef CONFIG_BLKFIN_CACHE
55#define BLKFIN_ICACHESIZE (16*1024)
56#else
57#define BLKFIN_ICACHESIZE (0*1024)
58#endif
59
60/* Memory Map for ADSP-BF533 processors */
61
62#ifdef CONFIG_BF533
63#define L1_CODE_START 0xFFA00000
64#define L1_DATA_A_START 0xFF800000
65#define L1_DATA_B_START 0xFF900000
66
67#ifdef CONFIG_BLKFIN_CACHE
68#define L1_CODE_LENGTH (0x14000 - 0x4000)
69#else
70#define L1_CODE_LENGTH 0x14000
71#endif
72
73#ifdef CONFIG_BLKFIN_DCACHE
74
75#ifdef CONFIG_BLKFIN_DCACHE_BANKA
76#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
77#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
78#define L1_DATA_B_LENGTH 0x8000
79#define BLKFIN_DCACHESIZE (16*1024)
80#define BLKFIN_DSUPBANKS 1
81#else
82#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
83#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
84#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
85#define BLKFIN_DCACHESIZE (32*1024)
86#define BLKFIN_DSUPBANKS 2
87#endif
88
89#else
90#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
91#define L1_DATA_A_LENGTH 0x8000
92#define L1_DATA_B_LENGTH 0x8000
93#define BLKFIN_DCACHESIZE (0*1024)
94#define BLKFIN_DSUPBANKS 0
95#endif /*CONFIG_BLKFIN_DCACHE*/
96#endif
97
98/* Memory Map for ADSP-BF532 processors */
99
100#ifdef CONFIG_BF532
101#define L1_CODE_START 0xFFA08000
102#define L1_DATA_A_START 0xFF804000
103#define L1_DATA_B_START 0xFF904000
104
105#ifdef CONFIG_BLKFIN_CACHE
106#define L1_CODE_LENGTH (0xC000 - 0x4000)
107#else
108#define L1_CODE_LENGTH 0xC000
109#endif
110
111#ifdef CONFIG_BLKFIN_DCACHE
112
113#ifdef CONFIG_BLKFIN_DCACHE_BANKA
114#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
115#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
116#define L1_DATA_B_LENGTH 0x4000
117#define BLKFIN_DCACHESIZE (16*1024)
118#define BLKFIN_DSUPBANKS 1
119
120#else
121#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
122#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
123#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
124#define BLKFIN_DCACHESIZE (32*1024)
125#define BLKFIN_DSUPBANKS 2
126#endif
127
128#else
129#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
130#define L1_DATA_A_LENGTH 0x4000
131#define L1_DATA_B_LENGTH 0x4000
132#define BLKFIN_DCACHESIZE (0*1024)
133#define BLKFIN_DSUPBANKS 0
134#endif /*CONFIG_BLKFIN_DCACHE*/
135#endif
136
137/* Memory Map for ADSP-BF531 processors */
138
139#ifdef CONFIG_BF531
140#define L1_CODE_START 0xFFA08000
141#define L1_DATA_A_START 0xFF804000
142#define L1_DATA_B_START 0xFF904000
143#define L1_CODE_LENGTH 0x4000
144#define L1_DATA_B_LENGTH 0x0000
145
146
147#ifdef CONFIG_BLKFIN_DCACHE
148#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
149#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
150#define BLKFIN_DCACHESIZE (16*1024)
151#define BLKFIN_DSUPBANKS 1
152#else
153#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
154#define L1_DATA_A_LENGTH 0x4000
155#define BLKFIN_DCACHESIZE (0*1024)
156#define BLKFIN_DSUPBANKS 0
157#endif
158
159#endif
160
161/* Scratch Pad Memory */
162
163#if defined(CONFIG_BF533) || defined(CONFIG_BF532) || defined(CONFIG_BF531)
164#define L1_SCRATCH_START 0xFFB00000
165#define L1_SCRATCH_LENGTH 0x1000
166#endif
167
168#endif /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
new file mode 100644
index 000000000000..7f040f5ba018
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -0,0 +1,120 @@
1
2/*
3 * File: include/asm-blackfin/mach-bf537/anomaly.h
4 * Based on:
5 * Author:
6 *
7 * Created:
8 * Description:
9 *
10 * Rev:
11 *
12 * Modified:
13 *
14 *
15 * Bugs: Enter bugs at http://blackfin.uclinux.org/
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; see the file COPYING.
29 * If not, write to the Free Software Foundation,
30 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 */
32
33/* This file shoule be up to date with:
34 * - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List
35 * - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List
36 * - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List
37 */
38
39#ifndef _MACH_ANOMALY_H_
40#define _MACH_ANOMALY_H_
41
42/* We do not support 0.1 silicon - sorry */
43#if (defined(CONFIG_BF_REV_0_1))
44#error Kernel will not work on BF537/6/4 Version 0.1
45#endif
46
47#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2))
48#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
49 slot1 and store of a P register in slot 2 is not
50 supported */
51#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
52 Channel DMA stops */
53#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
54 registers. */
55#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
56 upper bits*/
57#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
58 syncs */
59#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
60#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
61 Changed */
62#endif
63#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
64 SPORT external receive and transmit clocks. */
65#define ANOMALY_05000272 /* Certain data cache write through modes fail for
66 VDDint <=0.9V */
67#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
68#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
69 an edge is detected may clear interrupt */
70#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
71 not restored */
72#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
73 control */
74#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
75 killed in a particular stage*/
76#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
77 registers are interrupted */
78#endif
79
80#if defined(CONFIG_BF_REV_0_2)
81#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
82 IDLE around a Change of Control causes
83 unpredictable results */
84#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
85 (TDM) */
86#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
87#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
88#endif
89#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
90#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
91 interrupt not functional */
92#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
93#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
94#endif
95#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
96 loops may cause the instruction fetch unit to
97 malfunction */
98#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
99 the ICPLB Data registers differ */
100#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
101#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
102#define ANOMALY_05000262 /* Stores to data cache may be lost */
103#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
104#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
105 instruction will cause an infinite stall in the
106 second to last instruction in a hardware loop */
107#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
108 and non-zero DEB_TRAFFIC_PERIOD value */
109#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
110 internal voltage regulator (VDDint) to decrease */
111#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
112 an edge is detected may clear interrupt */
113#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
114 DMA system instability */
115#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
116 Atmel Dataflash devices */
117
118#endif /* CONFIG_BF_REV_0_2 */
119
120#endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf537/bf537.h b/include/asm-blackfin/mach-bf537/bf537.h
new file mode 100644
index 000000000000..b8924cd7730c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/bf537.h
@@ -0,0 +1,287 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/bf537.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF537
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF537_H__
31#define __MACH_BF537_H__
32
33#define SUPPORTED_REVID 2
34
35/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
36
37#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */
38#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */
39#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
40#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
41#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */
42#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */
43#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
44
45#define OFFSET_(x) ((x) & 0x0000FFFF)
46
47/*some misc defines*/
48#define IMASK_IVG15 0x8000
49#define IMASK_IVG14 0x4000
50#define IMASK_IVG13 0x2000
51#define IMASK_IVG12 0x1000
52
53#define IMASK_IVG11 0x0800
54#define IMASK_IVG10 0x0400
55#define IMASK_IVG9 0x0200
56#define IMASK_IVG8 0x0100
57
58#define IMASK_IVG7 0x0080
59#define IMASK_IVGTMR 0x0040
60#define IMASK_IVGHW 0x0020
61
62/***************************/
63
64
65#define BLKFIN_DSUBBANKS 4
66#define BLKFIN_DWAYS 2
67#define BLKFIN_DLINES 64
68#define BLKFIN_ISUBBANKS 4
69#define BLKFIN_IWAYS 4
70#define BLKFIN_ILINES 32
71
72#define WAY0_L 0x1
73#define WAY1_L 0x2
74#define WAY01_L 0x3
75#define WAY2_L 0x4
76#define WAY02_L 0x5
77#define WAY12_L 0x6
78#define WAY012_L 0x7
79
80#define WAY3_L 0x8
81#define WAY03_L 0x9
82#define WAY13_L 0xA
83#define WAY013_L 0xB
84
85#define WAY32_L 0xC
86#define WAY320_L 0xD
87#define WAY321_L 0xE
88#define WAYALL_L 0xF
89
90#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
91
92/********************************* EBIU Settings ************************************/
93#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
94#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
95
96#ifdef CONFIG_C_AMBEN_ALL
97#define V_AMBEN AMBEN_ALL
98#endif
99#ifdef CONFIG_C_AMBEN
100#define V_AMBEN 0x0
101#endif
102#ifdef CONFIG_C_AMBEN_B0
103#define V_AMBEN AMBEN_B0
104#endif
105#ifdef CONFIG_C_AMBEN_B0_B1
106#define V_AMBEN AMBEN_B0_B1
107#endif
108#ifdef CONFIG_C_AMBEN_B0_B1_B2
109#define V_AMBEN AMBEN_B0_B1_B2
110#endif
111#ifdef CONFIG_C_AMCKEN
112#define V_AMCKEN AMCKEN
113#else
114#define V_AMCKEN 0x0
115#endif
116#ifdef CONFIG_C_CDPRIO
117#define V_CDPRIO 0x100
118#else
119#define V_CDPRIO 0x0
120#endif
121
122#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
123
124#define MAX_VC 650000000
125#define MIN_VC 50000000
126
127/********************************PLL Settings **************************************/
128#ifdef CONFIG_BFIN_KERNEL_CLOCK
129#if (CONFIG_VCO_MULT < 0)
130#error "VCO Multiplier is less than 0. Please select a different value"
131#endif
132
133#if (CONFIG_VCO_MULT == 0)
134#error "VCO Multiplier should be greater than 0. Please select a different value"
135#endif
136
137#if (CONFIG_VCO_MULT > 64)
138#error "VCO Multiplier is more than 64. Please select a different value"
139#endif
140
141#ifndef CONFIG_CLKIN_HALF
142#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
143#else
144#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
145#endif
146
147#ifndef CONFIG_PLL_BYPASS
148#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
149#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
150#else
151#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
152#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
153#endif
154
155#if (CONFIG_SCLK_DIV < 1)
156#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
157#endif
158
159#if (CONFIG_SCLK_DIV > 15)
160#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
161#endif
162
163#if (CONFIG_CCLK_DIV != 1)
164#if (CONFIG_CCLK_DIV != 2)
165#if (CONFIG_CCLK_DIV != 4)
166#if (CONFIG_CCLK_DIV != 8)
167#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
168#endif
169#endif
170#endif
171#endif
172
173#if (CONFIG_VCO_HZ > MAX_VC)
174#error "VCO selected is more than maximum value. Please change the VCO multipler"
175#endif
176
177#if (CONFIG_SCLK_HZ > 133000000)
178#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
179#endif
180
181#if (CONFIG_SCLK_HZ < 27000000)
182#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
183#endif
184
185#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
186#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
187#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
188#error "Please select sclk less than cclk"
189#endif
190#endif
191#endif
192
193#if (CONFIG_CCLK_DIV == 1)
194#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
195#endif
196#if (CONFIG_CCLK_DIV == 2)
197#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
198#endif
199#if (CONFIG_CCLK_DIV == 4)
200#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
201#endif
202#if (CONFIG_CCLK_DIV == 8)
203#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
204#endif
205#ifndef CONFIG_CCLK_ACT_DIV
206#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
207#endif
208
209#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1)
210#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
211#endif
212
213#endif /* CONFIG_BFIN_KERNEL_CLOCK */
214
215#ifdef CONFIG_BF537
216#define CPU "BF537"
217#define CPUID 0x027c8000
218#endif
219#ifdef CONFIG_BF536
220#define CPU "BF536"
221#define CPUID 0x027c8000
222#endif
223#ifdef CONFIG_BF534
224#define CPU "BF534"
225#define CPUID 0x027c6000
226#endif
227#ifndef CPU
228#define CPU "UNKNOWN"
229#define CPUID 0x0
230#endif
231
232#if (CONFIG_MEM_SIZE % 4)
233#error "SDRAM mem size must be multible of 4MB"
234#endif
235
236#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
237#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
238#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
239#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
240
241/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
242
243#define ANOMALY_05000158_WORKAROUND 0x200
244#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
245#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
246 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
247#else /*Write Through */
248#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
249 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
250#endif
251
252
253#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
254#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
255#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
256#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
257
258#define SIZE_1K 0x00000400 /* 1K */
259#define SIZE_4K 0x00001000 /* 4K */
260#define SIZE_1M 0x00100000 /* 1M */
261#define SIZE_4M 0x00400000 /* 4M */
262
263#define MAX_CPLBS (16 * 2)
264
265/*
266* Number of required data CPLB switchtable entries
267* MEMSIZE / 4 (we mostly install 4M page size CPLBs
268* approx 16 for smaller 1MB page size CPLBs for allignment purposes
269* 1 for L1 Data Memory
270* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
271* 1 for ASYNC Memory
272*/
273
274
275#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
276
277/*
278* Number of required instruction CPLB switchtable entries
279* MEMSIZE / 4 (we mostly install 4M page size CPLBs
280* approx 12 for smaller 1MB page size CPLBs for allignment purposes
281* 1 for L1 Instruction Memory
282* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
283*/
284
285#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
286
287#endif /* __MACH_BF537_H__ */
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
new file mode 100644
index 000000000000..8f5d9c4d8d5b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
@@ -0,0 +1,147 @@
1#include <linux/serial.h>
2#include <asm/dma.h>
3
4#define NR_PORTS 2
5
6#define OFFSET_THR 0x00 /* Transmit Holding register */
7#define OFFSET_RBR 0x00 /* Receive Buffer register */
8#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
9#define OFFSET_IER 0x04 /* Interrupt Enable Register */
10#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
11#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
12#define OFFSET_LCR 0x0C /* Line Control Register */
13#define OFFSET_MCR 0x10 /* Modem Control Register */
14#define OFFSET_LSR 0x14 /* Line Status Register */
15#define OFFSET_MSR 0x18 /* Modem Status Register */
16#define OFFSET_SCR 0x1C /* SCR Scratch Register */
17#define OFFSET_GCTL 0x24 /* Global Control Register */
18
19#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
20#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
21#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
22#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
23#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
24#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
25#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
27
28#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
29#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
30#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
31#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
32#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
33#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
34
35#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
36# define CONFIG_SERIAL_BFIN_CTSRTS
37
38# ifndef CONFIG_UART0_CTS_PIN
39# define CONFIG_UART0_CTS_PIN -1
40# endif
41
42# ifndef CONFIG_UART0_RTS_PIN
43# define CONFIG_UART0_RTS_PIN -1
44# endif
45
46# ifndef CONFIG_UART1_CTS_PIN
47# define CONFIG_UART1_CTS_PIN -1
48# endif
49
50# ifndef CONFIG_UART1_RTS_PIN
51# define CONFIG_UART1_RTS_PIN -1
52# endif
53#endif
54/*
55 * The pin configuration is different from schematic
56 */
57struct bfin_serial_port {
58 struct uart_port port;
59 unsigned int old_status;
60#ifdef CONFIG_SERIAL_BFIN_DMA
61 int tx_done;
62 int tx_count;
63 struct circ_buf rx_dma_buf;
64 struct timer_list rx_dma_timer;
65 int rx_dma_nrows;
66 unsigned int tx_dma_channel;
67 unsigned int rx_dma_channel;
68 struct work_struct tx_dma_workqueue;
69#else
70 struct work_struct cts_workqueue;
71#endif
72#ifdef CONFIG_SERIAL_BFIN_CTSRTS
73 int cts_pin;
74 int rts_pin;
75#endif
76};
77
78struct bfin_serial_port bfin_serial_ports[NR_PORTS];
79struct bfin_serial_res {
80 unsigned long uart_base_addr;
81 int uart_irq;
82#ifdef CONFIG_SERIAL_BFIN_DMA
83 unsigned int uart_tx_dma_channel;
84 unsigned int uart_rx_dma_channel;
85#endif
86#ifdef CONFIG_SERIAL_BFIN_CTSRTS
87 int uart_cts_pin;
88 int uart_rts_pin;
89#endif
90};
91
92struct bfin_serial_res bfin_serial_resource[] = {
93#ifdef CONFIG_SERIAL_BFIN_UART0
94 {
95 0xFFC00400,
96 IRQ_UART0_RX,
97#ifdef CONFIG_SERIAL_BFIN_DMA
98 CH_UART0_TX,
99 CH_UART0_RX,
100#endif
101#ifdef CONFIG_BFIN_UART0_CTSRTS
102 CONFIG_UART0_CTS_PIN,
103 CONFIG_UART0_RTS_PIN,
104#endif
105 },
106#endif
107#ifdef CONFIG_SERIAL_BFIN_UART1
108 {
109 0xFFC02000,
110 IRQ_UART1_RX,
111#ifdef CONFIG_SERIAL_BFIN_DMA
112 CH_UART1_TX,
113 CH_UART1_RX,
114#endif
115#ifdef CONFIG_BFIN_UART1_CTSRTS
116 CONFIG_UART1_CTS_PIN,
117 CONFIG_UART1_RTS_PIN,
118#endif
119 },
120#endif
121};
122
123int nr_ports = ARRAY_SIZE(bfin_serial_resource);
124
125static void bfin_serial_hw_init(struct bfin_serial_port *uart)
126{
127 unsigned short val;
128 val = bfin_read16(BFIN_PORT_MUX);
129 val &= ~(PFDE | PFTE);
130 bfin_write16(BFIN_PORT_MUX, val);
131
132 val = bfin_read16(PORTF_FER);
133 val |= 0xF;
134 bfin_write16(PORTF_FER, val);
135
136#ifdef CONFIG_SERIAL_BFIN_CTSRTS
137 if (uart->cts_pin >= 0) {
138 gpio_request(uart->cts_pin, NULL);
139 gpio_direction_input(uart->cts_pin);
140 }
141
142 if (uart->rts_pin >= 0) {
143 gpio_request(uart->rts_pin, NULL);
144 gpio_direction_output(uart->rts_pin);
145 }
146#endif
147}
diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h
new file mode 100644
index 000000000000..bbd97051ec9c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/blackfin.h
@@ -0,0 +1,430 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _MACH_BLACKFIN_H_
33#define _MACH_BLACKFIN_H_
34
35#define BF537_FAMILY
36
37#include "bf537.h"
38#include "mem_map.h"
39#include "defBF534.h"
40#include "anomaly.h"
41
42#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
43#include "defBF537.h"
44#endif
45
46#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
47#include "cdefBF534.h"
48
49/* UART 0*/
50#define bfin_read_UART_THR() bfin_read_UART0_THR()
51#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
52#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
53#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
54#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
55#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
56#define bfin_read_UART_IER() bfin_read_UART0_IER()
57#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
58#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
59#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
60#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
61#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
62#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
63#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
64#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
65#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
66#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
67#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
68#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
69#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
70#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
71#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
72
73#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
74#include "cdefBF537.h"
75#endif
76#endif
77
78/* MAP used DEFINES from BF533 to BF537 - so we don't need to change them in the driver, kernel, etc. */
79
80/* UART_IIR Register */
81#define STATUS(x) ((x << 1) & 0x06)
82#define STATUS_P1 0x02
83#define STATUS_P0 0x01
84
85/* UART 0*/
86
87/* DMA Channnel */
88#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
89#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
90#define CH_UART_RX CH_UART0_RX
91#define bfin_read_CH_UART_TX() bfin_read_CH_UART0_TX()
92#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART0_TX(val)
93#define CH_UART_TX CH_UART0_TX
94
95/* System Interrupt Controller */
96#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART0_RX()
97#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART0_RX(val)
98#define IRQ_UART_RX IRQ_UART0_RX
99#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART0_TX()
100#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART0_TX(val)
101#define IRQ_UART_TX IRQ_UART0_TX
102#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART0_ERROR()
103#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART0_ERROR(val)
104#define IRQ_UART_ERROR IRQ_UART0_ERROR
105
106/* MMR Registers*/
107#define bfin_read_UART_THR() bfin_read_UART0_THR()
108#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
109#define UART_THR UART0_THR
110#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
111#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
112#define UART_RBR UART0_RBR
113#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
114#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
115#define UART_DLL UART0_DLL
116#define bfin_read_UART_IER() bfin_read_UART0_IER()
117#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
118#define UART_IER UART0_IER
119#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
120#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
121#define UART_DLH UART0_DLH
122#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
123#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
124#define UART_IIR UART0_IIR
125#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
126#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
127#define UART_LCR UART0_LCR
128#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
129#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
130#define UART_MCR UART0_MCR
131#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
132#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
133#define UART_LSR UART0_LSR
134#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
135#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
136#define UART_SCR UART0_SCR
137#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
138#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
139#define UART_GCTL UART0_GCTL
140
141/* DPMC*/
142#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
143#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
144#define STOPCK_OFF STOPCK
145
146/* FIO USE PORT F*/
147#ifdef CONFIG_BF537_PORT_F
148#define bfin_read_PORT_FER() bfin_read_PORTF_FER()
149#define bfin_write_PORT_FER(val) bfin_write_PORTF_FER(val)
150#define bfin_read_FIO_FLAG_D() bfin_read_PORTFIO()
151#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTFIO(val)
152#define bfin_read_FIO_FLAG_C() bfin_read_PORTFIO_CLEAR()
153#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTFIO_CLEAR(val)
154#define bfin_read_FIO_FLAG_S() bfin_read_PORTFIO_SET()
155#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTFIO_SET(val)
156#define bfin_read_FIO_FLAG_T() bfin_read_PORTFIO_TOGGLE()
157#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTFIO_TOGGLE(val)
158#define bfin_read_FIO_MASKA_D() bfin_read_PORTFIO_MASKA()
159#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTFIO_MASKA(val)
160#define bfin_read_FIO_MASKA_C() bfin_read_PORTFIO_MASKA_CLEAR()
161#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTFIO_MASKA_CLEAR(val)
162#define bfin_read_FIO_MASKA_S() bfin_read_PORTFIO_MASKA_SET()
163#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTFIO_MASKA_SET(val)
164#define bfin_read_FIO_MASKA_T() bfin_read_PORTFIO_MASKA_TOGGLE()
165#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTFIO_MASKA_TOGGLE(val)
166#define bfin_read_FIO_MASKB_D() bfin_read_PORTFIO_MASKB()
167#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTFIO_MASKB(val)
168#define bfin_read_FIO_MASKB_C() bfin_read_PORTFIO_MASKB_CLEAR()
169#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTFIO_MASKB_CLEAR(val)
170#define bfin_read_FIO_MASKB_S() bfin_read_PORTFIO_MASKB_SET()
171#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTFIO_MASKB_SET(val)
172#define bfin_read_FIO_MASKB_T() bfin_read_PORTFIO_MASKB_TOGGLE()
173#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTFIO_MASKB_TOGGLE(val)
174#define bfin_read_FIO_DIR() bfin_read_PORTFIO_DIR()
175#define bfin_write_FIO_DIR(val) bfin_write_PORTFIO_DIR(val)
176#define bfin_read_FIO_POLAR() bfin_read_PORTFIO_POLAR()
177#define bfin_write_FIO_POLAR(val) bfin_write_PORTFIO_POLAR(val)
178#define bfin_read_FIO_EDGE() bfin_read_PORTFIO_EDGE()
179#define bfin_write_FIO_EDGE(val) bfin_write_PORTFIO_EDGE(val)
180#define bfin_read_FIO_BOTH() bfin_read_PORTFIO_BOTH()
181#define bfin_write_FIO_BOTH(val) bfin_write_PORTFIO_BOTH(val)
182#define bfin_read_FIO_INEN() bfin_read_PORTFIO_INEN()
183#define bfin_write_FIO_INEN(val) bfin_write_PORTFIO_INEN(val)
184
185#define bfin_read_FIO_FLAG_D() bfin_read_PORTFIO()
186#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTFIO(val)
187#define FIO_FLAG_D PORTFIO
188#define bfin_read_FIO_FLAG_C() bfin_read_PORTFIO_CLEAR()
189#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTFIO_CLEAR(val)
190#define FIO_FLAG_C PORTFIO_CLEAR
191#define bfin_read_FIO_FLAG_S() bfin_read_PORTFIO_SET()
192#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTFIO_SET(val)
193#define FIO_FLAG_S PORTFIO_SET
194#define bfin_read_FIO_FLAG_T() bfin_read_PORTFIO_TOGGLE()
195#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTFIO_TOGGLE(val)
196#define FIO_FLAG_T PORTFIO_TOGGLE
197#define bfin_read_FIO_MASKA_D() bfin_read_PORTFIO_MASKA()
198#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTFIO_MASKA(val)
199#define FIO_MASKA_D PORTFIO_MASKA
200#define bfin_read_FIO_MASKA_C() bfin_read_PORTFIO_MASKA_CLEAR()
201#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTFIO_MASKA_CLEAR(val)
202#define FIO_MASKA_C PORTFIO_MASKA_CLEAR
203#define bfin_read_FIO_MASKA_S() bfin_read_PORTFIO_MASKA_SET()
204#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTFIO_MASKA_SET(val)
205#define FIO_MASKA_S PORTFIO_MASKA_SET
206#define bfin_read_FIO_MASKA_T() bfin_read_PORTFIO_MASKA_TOGGLE()
207#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTFIO_MASKA_TOGGLE(val)
208#define FIO_MASKA_T PORTFIO_MASKA_TOGGLE
209#define bfin_read_FIO_MASKB_D() bfin_read_PORTFIO_MASKB()
210#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTFIO_MASKB(val)
211#define FIO_MASKB_D PORTFIO_MASKB
212#define bfin_read_FIO_MASKB_C() bfin_read_PORTFIO_MASKB_CLEAR()
213#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTFIO_MASKB_CLEAR(val)
214#define FIO_MASKB_C PORTFIO_MASKB_CLEAR
215#define bfin_read_FIO_MASKB_S() bfin_read_PORTFIO_MASKB_SET()
216#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTFIO_MASKB_SET(val)
217#define FIO_MASKB_S PORTFIO_MASKB_SET
218#define bfin_read_FIO_MASKB_T() bfin_read_PORTFIO_MASKB_TOGGLE()
219#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTFIO_MASKB_TOGGLE(val)
220#define FIO_MASKB_T PORTFIO_MASKB_TOGGLE
221#define bfin_read_FIO_DIR() bfin_read_PORTFIO_DIR()
222#define bfin_write_FIO_DIR(val) bfin_write_PORTFIO_DIR(val)
223#define FIO_DIR PORTFIO_DIR
224#define bfin_read_FIO_POLAR() bfin_read_PORTFIO_POLAR()
225#define bfin_write_FIO_POLAR(val) bfin_write_PORTFIO_POLAR(val)
226#define FIO_POLAR PORTFIO_POLAR
227#define bfin_read_FIO_EDGE() bfin_read_PORTFIO_EDGE()
228#define bfin_write_FIO_EDGE(val) bfin_write_PORTFIO_EDGE(val)
229#define FIO_EDGE PORTFIO_EDGE
230#define bfin_read_FIO_BOTH() bfin_read_PORTFIO_BOTH()
231#define bfin_write_FIO_BOTH(val) bfin_write_PORTFIO_BOTH(val)
232#define FIO_BOTH PORTFIO_BOTH
233#define bfin_read_FIO_INEN() bfin_read_PORTFIO_INEN()
234#define bfin_write_FIO_INEN(val) bfin_write_PORTFIO_INEN(val)
235#define FIO_INEN PORTFIO_INEN
236#endif
237
238/* FIO USE PORT G*/
239#ifdef CONFIG_BF537_PORT_G
240#define bfin_read_PORT_FER() bfin_read_PORTG_FER()
241#define bfin_write_PORT_FER(val) bfin_write_PORTG_FER(val)
242#define bfin_read_FIO_FLAG_D() bfin_read_PORTGIO()
243#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTGIO(val)
244#define bfin_read_FIO_FLAG_C() bfin_read_PORTGIO_CLEAR()
245#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTGIO_CLEAR(val)
246#define bfin_read_FIO_FLAG_S() bfin_read_PORTGIO_SET()
247#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTGIO_SET(val)
248#define bfin_read_FIO_FLAG_T() bfin_read_PORTGIO_TOGGLE()
249#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTGIO_TOGGLE(val)
250#define bfin_read_FIO_MASKA_D() bfin_read_PORTGIO_MASKA()
251#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTGIO_MASKA(val)
252#define bfin_read_FIO_MASKA_C() bfin_read_PORTGIO_MASKA_CLEAR()
253#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTGIO_MASKA_CLEAR(val)
254#define bfin_read_FIO_MASKA_S() bfin_read_PORTGIO_MASKA_SET()
255#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTGIO_MASKA_SET(val)
256#define bfin_read_FIO_MASKA_T() bfin_read_PORTGIO_MASKA_TOGGLE()
257#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTGIO_MASKA_TOGGLE(val)
258#define bfin_read_FIO_MASKB_D() bfin_read_PORTGIO_MASKB()
259#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTGIO_MASKB(val)
260#define bfin_read_FIO_MASKB_C() bfin_read_PORTGIO_MASKB_CLEAR()
261#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTGIO_MASKB_CLEAR(val)
262#define bfin_read_FIO_MASKB_S() bfin_read_PORTGIO_MASKB_SET()
263#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTGIO_MASKB_SET(val)
264#define bfin_read_FIO_MASKB_T() bfin_read_PORTGIO_MASKB_TOGGLE()
265#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTGIO_MASKB_TOGGLE(val)
266#define bfin_read_FIO_DIR() bfin_read_PORTGIO_DIR()
267#define bfin_write_FIO_DIR(val) bfin_write_PORTGIO_DIR(val)
268#define bfin_read_FIO_POLAR() bfin_read_PORTGIO_POLAR()
269#define bfin_write_FIO_POLAR(val) bfin_write_PORTGIO_POLAR(val)
270#define bfin_read_FIO_EDGE() bfin_read_PORTGIO_EDGE()
271#define bfin_write_FIO_EDGE(val) bfin_write_PORTGIO_EDGE(val)
272#define bfin_read_FIO_BOTH() bfin_read_PORTGIO_BOTH()
273#define bfin_write_FIO_BOTH(val) bfin_write_PORTGIO_BOTH(val)
274#define bfin_read_FIO_INEN() bfin_read_PORTGIO_INEN()
275#define bfin_write_FIO_INEN(val) bfin_write_PORTGIO_INEN(val)
276
277#define bfin_read_FIO_FLAG_D() bfin_read_PORTGIO()
278#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTGIO(val)
279#define FIO_FLAG_D PORTGIO
280#define bfin_read_FIO_FLAG_C() bfin_read_PORTGIO_CLEAR()
281#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTGIO_CLEAR(val)
282#define FIO_FLAG_C PORTGIO_CLEAR
283#define bfin_read_FIO_FLAG_S() bfin_read_PORTGIO_SET()
284#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTGIO_SET(val)
285#define FIO_FLAG_S PORTGIO_SET
286#define bfin_read_FIO_FLAG_T() bfin_read_PORTGIO_TOGGLE()
287#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTGIO_TOGGLE(val)
288#define FIO_FLAG_T PORTGIO_TOGGLE
289#define bfin_read_FIO_MASKA_D() bfin_read_PORTGIO_MASKA()
290#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTGIO_MASKA(val)
291#define FIO_MASKA_D PORTGIO_MASKA
292#define bfin_read_FIO_MASKA_C() bfin_read_PORTGIO_MASKA_CLEAR()
293#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTGIO_MASKA_CLEAR(val)
294#define FIO_MASKA_C PORTGIO_MASKA_CLEAR
295#define bfin_read_FIO_MASKA_S() bfin_read_PORTGIO_MASKA_SET()
296#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTGIO_MASKA_SET(val)
297#define FIO_MASKA_S PORTGIO_MASKA_SET
298#define bfin_read_FIO_MASKA_T() bfin_read_PORTGIO_MASKA_TOGGLE()
299#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTGIO_MASKA_TOGGLE(val)
300#define FIO_MASKA_T PORTGIO_MASKA_TOGGLE
301#define bfin_read_FIO_MASKB_D() bfin_read_PORTGIO_MASKB()
302#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTGIO_MASKB(val)
303#define FIO_MASKB_D PORTGIO_MASKB
304#define bfin_read_FIO_MASKB_C() bfin_read_PORTGIO_MASKB_CLEAR()
305#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTGIO_MASKB_CLEAR(val)
306#define FIO_MASKB_C PORTGIO_MASKB_CLEAR
307#define bfin_read_FIO_MASKB_S() bfin_read_PORTGIO_MASKB_SET()
308#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTGIO_MASKB_SET(val)
309#define FIO_MASKB_S PORTGIO_MASKB_SET
310#define bfin_read_FIO_MASKB_T() bfin_read_PORTGIO_MASKB_TOGGLE()
311#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTGIO_MASKB_TOGGLE(val)
312#define FIO_MASKB_T PORTGIO_MASKB_TOGGLE
313#define bfin_read_FIO_DIR() bfin_read_PORTGIO_DIR()
314#define bfin_write_FIO_DIR(val) bfin_write_PORTGIO_DIR(val)
315#define FIO_DIR PORTGIO_DIR
316#define bfin_read_FIO_POLAR() bfin_read_PORTGIO_POLAR()
317#define bfin_write_FIO_POLAR(val) bfin_write_PORTGIO_POLAR(val)
318#define FIO_POLAR PORTGIO_POLAR
319#define bfin_read_FIO_EDGE() bfin_read_PORTGIO_EDGE()
320#define bfin_write_FIO_EDGE(val) bfin_write_PORTGIO_EDGE(val)
321#define FIO_EDGE PORTGIO_EDGE
322#define bfin_read_FIO_BOTH() bfin_read_PORTGIO_BOTH()
323#define bfin_write_FIO_BOTH(val) bfin_write_PORTGIO_BOTH(val)
324#define FIO_BOTH PORTGIO_BOTH
325#define bfin_read_FIO_INEN() bfin_read_PORTGIO_INEN()
326#define bfin_write_FIO_INEN(val) bfin_write_PORTGIO_INEN(val)
327#define FIO_INEN PORTGIO_INEN
328
329#endif
330
331/* FIO USE PORT H*/
332#ifdef CONFIG_BF537_PORT_H
333#define bfin_read_PORT_FER() bfin_read_PORTH_FER()
334#define bfin_write_PORT_FER(val) bfin_write_PORTH_FER(val)
335#define bfin_read_FIO_FLAG_D() bfin_read_PORTHIO()
336#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTHIO(val)
337#define bfin_read_FIO_FLAG_C() bfin_read_PORTHIO_CLEAR()
338#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTHIO_CLEAR(val)
339#define bfin_read_FIO_FLAG_S() bfin_read_PORTHIO_SET()
340#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTHIO_SET(val)
341#define bfin_read_FIO_FLAG_T() bfin_read_PORTHIO_TOGGLE()
342#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTHIO_TOGGLE(val)
343#define bfin_read_FIO_MASKA_D() bfin_read_PORTHIO_MASKA()
344#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTHIO_MASKA(val)
345#define bfin_read_FIO_MASKA_C() bfin_read_PORTHIO_MASKA_CLEAR()
346#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTHIO_MASKA_CLEAR(val)
347#define bfin_read_FIO_MASKA_S() bfin_read_PORTHIO_MASKA_SET()
348#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTHIO_MASKA_SET(val)
349#define bfin_read_FIO_MASKA_T() bfin_read_PORTHIO_MASKA_TOGGLE()
350#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTHIO_MASKA_TOGGLE(val)
351#define bfin_read_FIO_MASKB_D() bfin_read_PORTHIO_MASKB()
352#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTHIO_MASKB(val)
353#define bfin_read_FIO_MASKB_C() bfin_read_PORTHIO_MASKB_CLEAR()
354#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTHIO_MASKB_CLEAR(val)
355#define bfin_read_FIO_MASKB_S() bfin_read_PORTHIO_MASKB_SET()
356#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTHIO_MASKB_SET(val)
357#define bfin_read_FIO_MASKB_T() bfin_read_PORTHIO_MASKB_TOGGLE()
358#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTHIO_MASKB_TOGGLE(val)
359#define bfin_read_FIO_DIR() bfin_read_PORTHIO_DIR()
360#define bfin_write_FIO_DIR(val) bfin_write_PORTHIO_DIR(val)
361#define bfin_read_FIO_POLAR() bfin_read_PORTHIO_POLAR()
362#define bfin_write_FIO_POLAR(val) bfin_write_PORTHIO_POLAR(val)
363#define bfin_read_FIO_EDGE() bfin_read_PORTHIO_EDGE()
364#define bfin_write_FIO_EDGE(val) bfin_write_PORTHIO_EDGE(val)
365#define bfin_read_FIO_BOTH() bfin_read_PORTHIO_BOTH()
366#define bfin_write_FIO_BOTH(val) bfin_write_PORTHIO_BOTH(val)
367#define bfin_read_FIO_INEN() bfin_read_PORTHIO_INEN()
368#define bfin_write_FIO_INEN(val) bfin_write_PORTHIO_INEN(val)
369
370#define bfin_read_FIO_FLAG_D() bfin_read_PORTHIO()
371#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTHIO(val)
372#define FIO_FLAG_D PORTHIO
373#define bfin_read_FIO_FLAG_C() bfin_read_PORTHIO_CLEAR()
374#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTHIO_CLEAR(val)
375#define FIO_FLAG_C PORTHIO_CLEAR
376#define bfin_read_FIO_FLAG_S() bfin_read_PORTHIO_SET()
377#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTHIO_SET(val)
378#define FIO_FLAG_S PORTHIO_SET
379#define bfin_read_FIO_FLAG_T() bfin_read_PORTHIO_TOGGLE()
380#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTHIO_TOGGLE(val)
381#define FIO_FLAG_T PORTHIO_TOGGLE
382#define bfin_read_FIO_MASKA_D() bfin_read_PORTHIO_MASKA()
383#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTHIO_MASKA(val)
384#define FIO_MASKA_D PORTHIO_MASKA
385#define bfin_read_FIO_MASKA_C() bfin_read_PORTHIO_MASKA_CLEAR()
386#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTHIO_MASKA_CLEAR(val)
387#define FIO_MASKA_C PORTHIO_MASKA_CLEAR
388#define bfin_read_FIO_MASKA_S() bfin_read_PORTHIO_MASKA_SET()
389#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTHIO_MASKA_SET(val)
390#define FIO_MASKA_S PORTHIO_MASKA_SET
391#define bfin_read_FIO_MASKA_T() bfin_read_PORTHIO_MASKA_TOGGLE()
392#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTHIO_MASKA_TOGGLE(val)
393#define FIO_MASKA_T PORTHIO_MASKA_TOGGLE
394#define bfin_read_FIO_MASKB_D() bfin_read_PORTHIO_MASKB()
395#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTHIO_MASKB(val)
396#define FIO_MASKB_D PORTHIO_MASKB
397#define bfin_read_FIO_MASKB_C() bfin_read_PORTHIO_MASKB_CLEAR()
398#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTHIO_MASKB_CLEAR(val)
399#define FIO_MASKB_C PORTHIO_MASKB_CLEAR
400#define bfin_read_FIO_MASKB_S() bfin_read_PORTHIO_MASKB_SET()
401#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTHIO_MASKB_SET(val)
402#define FIO_MASKB_S PORTHIO_MASKB_SET
403#define bfin_read_FIO_MASKB_T() bfin_read_PORTHIO_MASKB_TOGGLE()
404#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTHIO_MASKB_TOGGLE(val)
405#define FIO_MASKB_T PORTHIO_MASKB_TOGGLE
406#define bfin_read_FIO_DIR() bfin_read_PORTHIO_DIR()
407#define bfin_write_FIO_DIR(val) bfin_write_PORTHIO_DIR(val)
408#define FIO_DIR PORTHIO_DIR
409#define bfin_read_FIO_POLAR() bfin_read_PORTHIO_POLAR()
410#define bfin_write_FIO_POLAR(val) bfin_write_PORTHIO_POLAR(val)
411#define FIO_POLAR PORTHIO_POLAR
412#define bfin_read_FIO_EDGE() bfin_read_PORTHIO_EDGE()
413#define bfin_write_FIO_EDGE(val) bfin_write_PORTHIO_EDGE(val)
414#define FIO_EDGE PORTHIO_EDGE
415#define bfin_read_FIO_BOTH() bfin_read_PORTHIO_BOTH()
416#define bfin_write_FIO_BOTH(val) bfin_write_PORTHIO_BOTH(val)
417#define FIO_BOTH PORTHIO_BOTH
418#define bfin_read_FIO_INEN() bfin_read_PORTHIO_INEN()
419#define bfin_write_FIO_INEN(val) bfin_write_PORTHIO_INEN(val)
420#define FIO_INEN PORTHIO_INEN
421
422#endif
423
424/* PLL_DIV Masks */
425#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
426#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
427#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
428#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
429
430#endif
diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h
new file mode 100644
index 000000000000..7b658c175f85
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/cdefBF534.h
@@ -0,0 +1,1823 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/cdefbf534.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF534_H
33#define _CDEF_BF534_H
34
35/* Include all Core registers and bit definitions */
36#include "defBF534.h"
37
38/* Include core specific register pointer definitions */
39#include <asm/mach-common/cdef_LPBlackfin.h>
40
41#include <asm/system.h>
42
43/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
44#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
45#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val)
46#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
47#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
48#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
49/* Writing to VR_CTL initiates a PLL relock sequence. */
50static __inline__ void bfin_write_VR_CTL(unsigned int val)
51{
52 unsigned long flags, iwr;
53
54 bfin_write16(VR_CTL, val);
55 __builtin_bfin_ssync();
56 /* Enable the PLL Wakeup bit in SIC IWR */
57 iwr = bfin_read32(SIC_IWR);
58 /* Only allow PPL Wakeup) */
59 bfin_write32(SIC_IWR, IWR_ENABLE(0));
60 local_irq_save(flags);
61 asm("IDLE;");
62 local_irq_restore(flags);
63 bfin_write32(SIC_IWR, iwr);
64}
65#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
66#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
67#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
68#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
69#define bfin_read_CHIPID() bfin_read32(CHIPID)
70
71/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
72#define bfin_read_SWRST() bfin_read16(SWRST)
73#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
74#define bfin_read_SYSCR() bfin_read16(SYSCR)
75#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
76#define pSIC_RVECT ((void * volatile *)SIC_RVECT)
77#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
78#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val)
79#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
80#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
81#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
82#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
83#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
84#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
85#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
86#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
87#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
88#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
89#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
90#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
91#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
92#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
93
94/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
95#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
96#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
97#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
98#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
99#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
100#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
101
102/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
103#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
104#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
105#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
106#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
107#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
108#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
109#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
110#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
111#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
112#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
113#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
114#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
115#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
116#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
117
118/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
119#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
120#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR,val)
121#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
122#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR,val)
123#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
124#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL,val)
125#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
126#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER,val)
127#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
128#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH,val)
129#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
130#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR,val)
131#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
132#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR,val)
133#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
134#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR,val)
135#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
136#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR,val)
137#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
138#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR,val)
139#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
140#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR,val)
141#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
142#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL,val)
143
144/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
145#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
146#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
147#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
148#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
149#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
150#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
151#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
152#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
153#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
154#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
155#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
156#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
157#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
158#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
159
160/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
161#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
162#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
163#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
164#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
165#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
166#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
167#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
168#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
169
170#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
171#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
172#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
173#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
174#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
175#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
176#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
177#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
178
179#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
180#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
181#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
182#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
183#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
184#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
185#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
186#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
187
188#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
189#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
190#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
191#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
192#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
193#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
194#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
195#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
196
197#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
198#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
199#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
200#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
201#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
202#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
203#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
204#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
205
206#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
207#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
208#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
209#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
210#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
211#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
212#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
213#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
214
215#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
216#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
217#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
218#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
219#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
220#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
221#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
222#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
223
224#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
225#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
226#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
227#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
228#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
229#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
230#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
231#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
232
233#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
234#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
235#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
236#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
237#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
238#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS,val)
239
240/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
241#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
242#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO,val)
243#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
244#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR,val)
245#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
246#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET,val)
247#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
248#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE,val)
249#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
250#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA,val)
251#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
252#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR,val)
253#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
254#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET,val)
255#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
256#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE,val)
257#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
258#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB,val)
259#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
260#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR,val)
261#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
262#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET,val)
263#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
264#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE,val)
265#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
266#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR,val)
267#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
268#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR,val)
269#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
270#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE,val)
271#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
272#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH,val)
273#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
274#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN,val)
275
276/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
277#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
278#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
279#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
280#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
281#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
282#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
283#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
284#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
285#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
286#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
287#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
288#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
289#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
290#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
291#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
292#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
293#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
294#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
295#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
296#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
297#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
298#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
299#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
300#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
301#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
302#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
303#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
304#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
305#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
306#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
307#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
308#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
309#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
310#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
311#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
312#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
313#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
314#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
315#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
316#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
317#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
318#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
319#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
320#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
321#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
322#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
323#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
324#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
325#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
326#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
327#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
328#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
329
330/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
331#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
332#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
333#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
334#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
335#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
336#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
337#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
338#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
339#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
340#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
341#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
342#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
343#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
344#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
345#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
346#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
347#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
348#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
349#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
350#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
351#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
352#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
353#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
354#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
355#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
356#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
357#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
358#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
359#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
360#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
361#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
362#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
363#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
364#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
365#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
366#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
367#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
368#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
369#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
370#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
371#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
372#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
373#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
374#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
375#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
376#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
377#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
378#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
379#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
380#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
381#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
382#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
383
384/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
385#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
386#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
387#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
388#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
389#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
390#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
391#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
392#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
393#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
394#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
395#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
396#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
397#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
398#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
399
400/* DMA Traffic Control Registers */
401#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER)
402#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
403#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
404#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT)
405#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
406#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
407
408/* DMA Controller */
409#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
410#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
411#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
412#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
413#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
414#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
415#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
416#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
417#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
418#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
419#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
420#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
421#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
422#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
423#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
424#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
425#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
426#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
427#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
428#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
429#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
430#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
431#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
432#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
433#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
434#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
435
436#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
437#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
438#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
439#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
440#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
441#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
442#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
443#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
444#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
445#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
446#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
447#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
448#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
449#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
450#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
451#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
452#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
453#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
454#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
455#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
456#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
457#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
458#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
459#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
460#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
461#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
462
463#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
464#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
465#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
466#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
467#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
468#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
469#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
470#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
471#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
472#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
473#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
474#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
475#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
476#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
477#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
478#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
479#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
480#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
481#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
482#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
483#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
484#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
485#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
486#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
487#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
488#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
489
490#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
491#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
492#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
493#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
494#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
495#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
496#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
497#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
498#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
499#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
500#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
501#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
502#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
503#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
504#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
505#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
506#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
507#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
508#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
509#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
510#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
511#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
512#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
513#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
514#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
515#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
516
517#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
518#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
519#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
520#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
521#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
522#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
523#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
524#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
525#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
526#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
527#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
528#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
529#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
530#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
531#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
532#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
533#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
534#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
535#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
536#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
537#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
538#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
539#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
540#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
541#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
542#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
543
544#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
545#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
546#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
547#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
548#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
549#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
550#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
551#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
552#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
553#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
554#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
555#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
556#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
557#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
558#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
559#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
560#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
561#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
562#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
563#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
564#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
565#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
566#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
567#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
568#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
569#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
570
571#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
572#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
573#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
574#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
575#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
576#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
577#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
578#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
579#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
580#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
581#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
582#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
583#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
584#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
585#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
586#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
587#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
588#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
589#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
590#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
591#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
592#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
593#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
594#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
595#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
596#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
597
598#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
599#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
600#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
601#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
602#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
603#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
604#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
605#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
606#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
607#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
608#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
609#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
610#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
611#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
612#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
613#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
614#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
615#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
616#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
617#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
618#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
619#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
620#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
621#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
622#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
623#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
624
625#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
626#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG,val)
627#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
628#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR,val)
629#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
630#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR,val)
631#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
632#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT,val)
633#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
634#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT,val)
635#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
636#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY,val)
637#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
638#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY,val)
639#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
640#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR,val)
641#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
642#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR,val)
643#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
644#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT,val)
645#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
646#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT,val)
647#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
648#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS,val)
649#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
650#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP,val)
651
652#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
653#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG,val)
654#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
655#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR,val)
656#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
657#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR,val)
658#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
659#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT,val)
660#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
661#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT,val)
662#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
663#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY,val)
664#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
665#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY,val)
666#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
667#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR,val)
668#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
669#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR,val)
670#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
671#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT,val)
672#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
673#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT,val)
674#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
675#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS,val)
676#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
677#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP,val)
678
679#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
680#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG,val)
681#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
682#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR,val)
683#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
684#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR,val)
685#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
686#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT,val)
687#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
688#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT,val)
689#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
690#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY,val)
691#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
692#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY,val)
693#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
694#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR,val)
695#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
696#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR,val)
697#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
698#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT,val)
699#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
700#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT,val)
701#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
702#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS,val)
703#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
704#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP,val)
705
706#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
707#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG,val)
708#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
709#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR,val)
710#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
711#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR,val)
712#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
713#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT,val)
714#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
715#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT,val)
716#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
717#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY,val)
718#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
719#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY,val)
720#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
721#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR,val)
722#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
723#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR,val)
724#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
725#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT,val)
726#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
727#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT,val)
728#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
729#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS,val)
730#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
731#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP,val)
732
733#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
734#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
735#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
736#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
737#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
738#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
739#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
740#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
741#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
742#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
743#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
744#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
745#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
746#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
747#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
748#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
749#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
750#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
751#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
752#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
753#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
754#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
755#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
756#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
757#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
758#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
759
760#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
761#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
762#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
763#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
764#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
765#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
766#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
767#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
768#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
769#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
770#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
771#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
772#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
773#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
774#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
775#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
776#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
777#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
778#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
779#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
780#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
781#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
782#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
783#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
784#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
785#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
786
787#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
788#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
789#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
790#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
791#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
792#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
793#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
794#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
795#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
796#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
797#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
798#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
799#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
800#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
801#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
802#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
803#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
804#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
805#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
806#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
807#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
808#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
809#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
810#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
811#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
812#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
813
814#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
815#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
816#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
817#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
818#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
819#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
820#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
821#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
822#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
823#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
824#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
825#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
826#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
827#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
828#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
829#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
830#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
831#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
832#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
833#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
834#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
835#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
836#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
837#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
838#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
839#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
840
841/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
842#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
843#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
844#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
845#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
846#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
847#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
848#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
849#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
850#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
851#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
852#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
853
854/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
855#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
856#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val)
857#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
858#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL,val)
859#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
860#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL,val)
861#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
862#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT,val)
863#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
864#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR,val)
865#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
866#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL,val)
867#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
868#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT,val)
869#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
870#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR,val)
871#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
872#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT,val)
873#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
874#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK,val)
875#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
876#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL,val)
877#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
878#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT,val)
879#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
880#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8,val)
881#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
882#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16,val)
883#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
884#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8,val)
885#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
886#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16,val)
887
888/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
889#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
890#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO,val)
891#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
892#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR,val)
893#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
894#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET,val)
895#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
896#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE,val)
897#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
898#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA,val)
899#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
900#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR,val)
901#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
902#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET,val)
903#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
904#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE,val)
905#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
906#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB,val)
907#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
908#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR,val)
909#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
910#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET,val)
911#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
912#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE,val)
913#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
914#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR,val)
915#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
916#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR,val)
917#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
918#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE,val)
919#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
920#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH,val)
921#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
922#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN,val)
923
924/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
925#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
926#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO,val)
927#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
928#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR,val)
929#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
930#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET,val)
931#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
932#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE,val)
933#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
934#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA,val)
935#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
936#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR,val)
937#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
938#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET,val)
939#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
940#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE,val)
941#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
942#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB,val)
943#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
944#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR,val)
945#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
946#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET,val)
947#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
948#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE,val)
949#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
950#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR,val)
951#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
952#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR,val)
953#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
954#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE,val)
955#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
956#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH,val)
957#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
958#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN,val)
959
960/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
961#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
962#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR,val)
963#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
964#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR,val)
965#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
966#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL,val)
967#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
968#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER,val)
969#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
970#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH,val)
971#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
972#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR,val)
973#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
974#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR,val)
975#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
976#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR,val)
977#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
978#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR,val)
979#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
980#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR,val)
981#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
982#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR,val)
983#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
984#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL,val)
985
986/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
987/* For Mailboxes 0-15 */
988#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
989#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1,val)
990#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
991#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1,val)
992#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
993#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1,val)
994#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
995#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1,val)
996#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
997#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1,val)
998#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
999#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1,val)
1000#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
1001#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1,val)
1002#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
1003#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1,val)
1004#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
1005#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1,val)
1006#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
1007#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1,val)
1008#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
1009#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1,val)
1010#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
1011#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1,val)
1012#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
1013#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1,val)
1014
1015/* For Mailboxes 16-31 */
1016#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
1017#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2,val)
1018#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
1019#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2,val)
1020#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
1021#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2,val)
1022#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
1023#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2,val)
1024#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
1025#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2,val)
1026#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
1027#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2,val)
1028#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
1029#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2,val)
1030#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
1031#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2,val)
1032#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
1033#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2,val)
1034#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
1035#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2,val)
1036#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
1037#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2,val)
1038#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
1039#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2,val)
1040#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
1041#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2,val)
1042
1043#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
1044#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK,val)
1045#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
1046#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING,val)
1047#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
1048#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG,val)
1049#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
1050#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS,val)
1051#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
1052#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC,val)
1053#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
1054#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS,val)
1055#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
1056#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM,val)
1057#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
1058#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF,val)
1059#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
1060#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL,val)
1061#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
1062#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR,val)
1063#define bfin_read_CAN_SFCMVER() bfin_read16(CAN_SFCMVER)
1064#define bfin_write_CAN_SFCMVER(val) bfin_write16(CAN_SFCMVER,val)
1065#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
1066#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD,val)
1067#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
1068#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR,val)
1069#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
1070#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR,val)
1071#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
1072#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG,val)
1073#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
1074#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT,val)
1075#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
1076#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val)
1077#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
1078#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val)
1079#define bfin_read_CAN_SFCMVER2() bfin_read16(CAN_SFCMVER2)
1080#define bfin_write_CAN_SFCMVER2(val) bfin_write16(CAN_SFCMVER2,val)
1081
1082/* Mailbox Acceptance Masks */
1083#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
1084#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L,val)
1085#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
1086#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H,val)
1087#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
1088#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L,val)
1089#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
1090#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H,val)
1091#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
1092#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L,val)
1093#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
1094#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H,val)
1095#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
1096#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L,val)
1097#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
1098#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H,val)
1099#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
1100#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L,val)
1101#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
1102#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H,val)
1103#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
1104#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L,val)
1105#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
1106#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H,val)
1107#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
1108#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L,val)
1109#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
1110#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H,val)
1111#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
1112#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L,val)
1113#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
1114#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H,val)
1115#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
1116#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L,val)
1117#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
1118#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H,val)
1119#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
1120#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L,val)
1121#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
1122#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H,val)
1123#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
1124#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L,val)
1125#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
1126#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H,val)
1127#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
1128#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L,val)
1129#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
1130#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H,val)
1131#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
1132#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L,val)
1133#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
1134#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H,val)
1135#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
1136#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L,val)
1137#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
1138#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H,val)
1139#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
1140#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L,val)
1141#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
1142#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H,val)
1143#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
1144#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L,val)
1145#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
1146#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H,val)
1147
1148#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
1149#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L,val)
1150#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
1151#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H,val)
1152#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
1153#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L,val)
1154#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
1155#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H,val)
1156#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
1157#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L,val)
1158#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
1159#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H,val)
1160#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
1161#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L,val)
1162#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
1163#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H,val)
1164#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
1165#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L,val)
1166#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
1167#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H,val)
1168#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
1169#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L,val)
1170#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
1171#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H,val)
1172#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
1173#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L,val)
1174#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
1175#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H,val)
1176#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
1177#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L,val)
1178#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
1179#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H,val)
1180#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
1181#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L,val)
1182#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
1183#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H,val)
1184#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
1185#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L,val)
1186#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
1187#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H,val)
1188#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
1189#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L,val)
1190#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
1191#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H,val)
1192#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
1193#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L,val)
1194#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
1195#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H,val)
1196#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
1197#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L,val)
1198#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
1199#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H,val)
1200#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
1201#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L,val)
1202#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
1203#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H,val)
1204#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
1205#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L,val)
1206#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
1207#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H,val)
1208#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
1209#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L,val)
1210#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
1211#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H,val)
1212
1213/* CAN Acceptance Mask Area Macros */
1214#define bfin_read_CAN_AM_L(x)() bfin_read16(CAN_AM_L(x))
1215#define bfin_write_CAN_AM_L(x)(val) bfin_write16(CAN_AM_L(x),val)
1216#define bfin_read_CAN_AM_H(x)() bfin_read16(CAN_AM_H(x))
1217#define bfin_write_CAN_AM_H(x)(val) bfin_write16(CAN_AM_H(x),val)
1218
1219/* Mailbox Registers */
1220#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
1221#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1,val)
1222#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
1223#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0,val)
1224#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
1225#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP,val)
1226#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
1227#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH,val)
1228#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
1229#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3,val)
1230#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
1231#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2,val)
1232#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
1233#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1,val)
1234#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
1235#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0,val)
1236
1237#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
1238#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1,val)
1239#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
1240#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0,val)
1241#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
1242#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP,val)
1243#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
1244#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH,val)
1245#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
1246#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3,val)
1247#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
1248#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2,val)
1249#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
1250#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1,val)
1251#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
1252#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0,val)
1253
1254#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
1255#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1,val)
1256#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
1257#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0,val)
1258#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
1259#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP,val)
1260#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
1261#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH,val)
1262#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
1263#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3,val)
1264#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
1265#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2,val)
1266#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
1267#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1,val)
1268#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
1269#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0,val)
1270
1271#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
1272#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1,val)
1273#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
1274#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0,val)
1275#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
1276#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP,val)
1277#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
1278#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH,val)
1279#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
1280#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3,val)
1281#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
1282#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2,val)
1283#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
1284#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1,val)
1285#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
1286#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0,val)
1287
1288#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
1289#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1,val)
1290#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
1291#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0,val)
1292#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
1293#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP,val)
1294#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
1295#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH,val)
1296#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
1297#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3,val)
1298#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
1299#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2,val)
1300#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
1301#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1,val)
1302#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
1303#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0,val)
1304
1305#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
1306#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1,val)
1307#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
1308#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0,val)
1309#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
1310#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP,val)
1311#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
1312#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH,val)
1313#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
1314#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3,val)
1315#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
1316#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2,val)
1317#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
1318#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1,val)
1319#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
1320#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0,val)
1321
1322#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
1323#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1,val)
1324#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
1325#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0,val)
1326#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
1327#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP,val)
1328#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
1329#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH,val)
1330#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
1331#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3,val)
1332#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
1333#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2,val)
1334#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
1335#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1,val)
1336#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
1337#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0,val)
1338
1339#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
1340#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1,val)
1341#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
1342#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0,val)
1343#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
1344#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP,val)
1345#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
1346#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH,val)
1347#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
1348#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3,val)
1349#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
1350#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2,val)
1351#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
1352#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1,val)
1353#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
1354#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0,val)
1355
1356#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
1357#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1,val)
1358#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
1359#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0,val)
1360#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
1361#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP,val)
1362#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
1363#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH,val)
1364#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
1365#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3,val)
1366#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
1367#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2,val)
1368#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
1369#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1,val)
1370#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
1371#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0,val)
1372
1373#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
1374#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1,val)
1375#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
1376#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0,val)
1377#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
1378#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP,val)
1379#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
1380#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH,val)
1381#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
1382#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3,val)
1383#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
1384#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2,val)
1385#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
1386#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1,val)
1387#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
1388#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0,val)
1389
1390#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
1391#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1,val)
1392#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
1393#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0,val)
1394#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
1395#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP,val)
1396#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
1397#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH,val)
1398#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
1399#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3,val)
1400#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
1401#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2,val)
1402#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
1403#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1,val)
1404#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
1405#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0,val)
1406
1407#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
1408#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1,val)
1409#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
1410#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0,val)
1411#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
1412#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP,val)
1413#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
1414#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH,val)
1415#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
1416#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3,val)
1417#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
1418#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2,val)
1419#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
1420#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1,val)
1421#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
1422#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0,val)
1423
1424#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
1425#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1,val)
1426#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
1427#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0,val)
1428#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
1429#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP,val)
1430#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
1431#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH,val)
1432#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
1433#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3,val)
1434#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
1435#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2,val)
1436#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
1437#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1,val)
1438#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
1439#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0,val)
1440
1441#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
1442#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1,val)
1443#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
1444#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0,val)
1445#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
1446#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP,val)
1447#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
1448#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH,val)
1449#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
1450#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3,val)
1451#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
1452#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2,val)
1453#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
1454#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1,val)
1455#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
1456#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0,val)
1457
1458#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
1459#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1,val)
1460#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
1461#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0,val)
1462#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
1463#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP,val)
1464#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
1465#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH,val)
1466#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
1467#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3,val)
1468#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
1469#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2,val)
1470#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
1471#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1,val)
1472#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
1473#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0,val)
1474
1475#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
1476#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1,val)
1477#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
1478#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0,val)
1479#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
1480#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP,val)
1481#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
1482#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH,val)
1483#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
1484#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3,val)
1485#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
1486#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2,val)
1487#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
1488#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1,val)
1489#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
1490#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0,val)
1491
1492#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
1493#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1,val)
1494#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
1495#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0,val)
1496#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
1497#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP,val)
1498#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
1499#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH,val)
1500#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
1501#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3,val)
1502#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
1503#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2,val)
1504#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
1505#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1,val)
1506#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
1507#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0,val)
1508
1509#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
1510#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1,val)
1511#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
1512#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0,val)
1513#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
1514#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP,val)
1515#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
1516#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH,val)
1517#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
1518#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3,val)
1519#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
1520#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2,val)
1521#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
1522#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1,val)
1523#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
1524#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0,val)
1525
1526#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
1527#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1,val)
1528#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
1529#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0,val)
1530#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
1531#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP,val)
1532#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
1533#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH,val)
1534#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
1535#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3,val)
1536#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
1537#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2,val)
1538#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
1539#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1,val)
1540#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
1541#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0,val)
1542
1543#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
1544#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1,val)
1545#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
1546#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0,val)
1547#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
1548#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP,val)
1549#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
1550#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH,val)
1551#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
1552#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3,val)
1553#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
1554#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2,val)
1555#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
1556#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1,val)
1557#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
1558#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0,val)
1559
1560#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
1561#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1,val)
1562#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
1563#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0,val)
1564#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
1565#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP,val)
1566#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
1567#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH,val)
1568#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
1569#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3,val)
1570#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
1571#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2,val)
1572#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
1573#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1,val)
1574#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
1575#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0,val)
1576
1577#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
1578#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1,val)
1579#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
1580#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0,val)
1581#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
1582#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP,val)
1583#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
1584#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH,val)
1585#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
1586#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3,val)
1587#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
1588#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2,val)
1589#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
1590#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1,val)
1591#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
1592#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0,val)
1593
1594#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
1595#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1,val)
1596#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
1597#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0,val)
1598#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
1599#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP,val)
1600#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
1601#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH,val)
1602#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
1603#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3,val)
1604#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
1605#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2,val)
1606#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
1607#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1,val)
1608#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
1609#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0,val)
1610
1611#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
1612#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1,val)
1613#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
1614#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0,val)
1615#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
1616#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP,val)
1617#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
1618#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH,val)
1619#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
1620#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3,val)
1621#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
1622#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2,val)
1623#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
1624#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1,val)
1625#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
1626#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0,val)
1627
1628#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
1629#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1,val)
1630#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
1631#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0,val)
1632#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
1633#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP,val)
1634#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
1635#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH,val)
1636#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
1637#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3,val)
1638#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
1639#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2,val)
1640#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
1641#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1,val)
1642#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
1643#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0,val)
1644
1645#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
1646#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1,val)
1647#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
1648#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0,val)
1649#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
1650#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP,val)
1651#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
1652#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH,val)
1653#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
1654#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3,val)
1655#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
1656#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2,val)
1657#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
1658#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1,val)
1659#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
1660#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0,val)
1661
1662#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
1663#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1,val)
1664#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
1665#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0,val)
1666#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
1667#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP,val)
1668#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
1669#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH,val)
1670#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
1671#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3,val)
1672#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
1673#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2,val)
1674#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
1675#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1,val)
1676#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
1677#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0,val)
1678
1679#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
1680#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1,val)
1681#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
1682#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0,val)
1683#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
1684#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP,val)
1685#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
1686#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH,val)
1687#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
1688#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3,val)
1689#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
1690#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2,val)
1691#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
1692#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1,val)
1693#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
1694#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0,val)
1695
1696#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
1697#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1,val)
1698#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
1699#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0,val)
1700#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
1701#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP,val)
1702#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
1703#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH,val)
1704#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
1705#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3,val)
1706#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
1707#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2,val)
1708#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
1709#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1,val)
1710#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
1711#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0,val)
1712
1713#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
1714#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1,val)
1715#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
1716#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0,val)
1717#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
1718#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP,val)
1719#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
1720#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH,val)
1721#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
1722#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3,val)
1723#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
1724#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2,val)
1725#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
1726#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1,val)
1727#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
1728#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0,val)
1729
1730#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
1731#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1,val)
1732#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
1733#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0,val)
1734#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
1735#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP,val)
1736#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
1737#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH,val)
1738#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
1739#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3,val)
1740#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
1741#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2,val)
1742#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
1743#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1,val)
1744#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
1745#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0,val)
1746
1747#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
1748#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1,val)
1749#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
1750#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0,val)
1751#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
1752#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP,val)
1753#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
1754#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH,val)
1755#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
1756#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3,val)
1757#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
1758#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2,val)
1759#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
1760#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1,val)
1761#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
1762#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0,val)
1763
1764/* CAN Mailbox Area Macros */
1765#define bfin_read_CAN_MB_ID1(x)() bfin_read16(CAN_MB_ID1(x))
1766#define bfin_write_CAN_MB_ID1(x)(val) bfin_write16(CAN_MB_ID1(x),val)
1767#define bfin_read_CAN_MB_ID0(x)() bfin_read16(CAN_MB_ID0(x))
1768#define bfin_write_CAN_MB_ID0(x)(val) bfin_write16(CAN_MB_ID0(x),val)
1769#define bfin_read_CAN_MB_TIMESTAMP(x)() bfin_read16(CAN_MB_TIMESTAMP(x))
1770#define bfin_write_CAN_MB_TIMESTAMP(x)(val) bfin_write16(CAN_MB_TIMESTAMP(x),val)
1771#define bfin_read_CAN_MB_LENGTH(x)() bfin_read16(CAN_MB_LENGTH(x))
1772#define bfin_write_CAN_MB_LENGTH(x)(val) bfin_write16(CAN_MB_LENGTH(x),val)
1773#define bfin_read_CAN_MB_DATA3(x)() bfin_read16(CAN_MB_DATA3(x))
1774#define bfin_write_CAN_MB_DATA3(x)(val) bfin_write16(CAN_MB_DATA3(x),val)
1775#define bfin_read_CAN_MB_DATA2(x)() bfin_read16(CAN_MB_DATA2(x))
1776#define bfin_write_CAN_MB_DATA2(x)(val) bfin_write16(CAN_MB_DATA2(x),val)
1777#define bfin_read_CAN_MB_DATA1(x)() bfin_read16(CAN_MB_DATA1(x))
1778#define bfin_write_CAN_MB_DATA1(x)(val) bfin_write16(CAN_MB_DATA1(x),val)
1779#define bfin_read_CAN_MB_DATA0(x)() bfin_read16(CAN_MB_DATA0(x))
1780#define bfin_write_CAN_MB_DATA0(x)(val) bfin_write16(CAN_MB_DATA0(x),val)
1781
1782/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
1783#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
1784#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER,val)
1785#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
1786#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER,val)
1787#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
1788#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER,val)
1789#define bfin_read_PORT_MUX() bfin_read16(BFIN_PORT_MUX)
1790#define bfin_write_PORT_MUX(val) bfin_write16(BFIN_PORT_MUX,val)
1791
1792/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
1793#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1794#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL,val)
1795#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1796#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT,val)
1797#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1798#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT,val)
1799#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1800#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT,val)
1801#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1802#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW,val)
1803#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1804#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT,val)
1805#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1806#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT,val)
1807
1808#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1809#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL,val)
1810#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1811#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT,val)
1812#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1813#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT,val)
1814#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1815#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT,val)
1816#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1817#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW,val)
1818#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1819#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT,val)
1820#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1821#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
1822
1823#endif /* _CDEF_BF534_H */
diff --git a/include/asm-blackfin/mach-bf537/cdefBF537.h b/include/asm-blackfin/mach-bf537/cdefBF537.h
new file mode 100644
index 000000000000..932a1b6b5d14
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/cdefBF537.h
@@ -0,0 +1,209 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/cdefBF537.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 * System MMR Register Map
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF537_H
33#define _CDEF_BF537_H
34
35/* Include MMRs Common to BF534 */
36#include "cdefBF534.h"
37
38/* Include all Core registers and bit definitions */
39#include "defBF537.h"
40
41/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
42/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
43#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE)
44#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
45#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE,val)
46#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
47#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO,val)
48#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
49#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI,val)
50#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
51#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO,val)
52#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
53#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI,val)
54#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
55#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD,val)
56#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
57#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT,val)
58#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
59#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC,val)
60#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
61#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1,val)
62#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
63#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2,val)
64#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
65#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL,val)
66#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
67#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0,val)
68#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
69#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1,val)
70#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
71#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2,val)
72#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
73#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3,val)
74#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
75#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD,val)
76#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
77#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF,val)
78#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
79#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0,val)
80#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
81#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1,val)
82
83#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL)
84#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
85#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL,val)
86#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
87#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT,val)
88#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
89#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT,val)
90#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
91#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY,val)
92#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
93#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE,val)
94#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
95#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT,val)
96#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
97#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY,val)
98#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
99#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE,val)
100
101#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
102#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL,val)
103#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
104#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS,val)
105#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
106#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE,val)
107#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
108#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS,val)
109#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
110#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE,val)
111
112#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
113#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK,val)
114#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
115#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS,val)
116#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
117#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN,val)
118#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
119#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET,val)
120#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
121#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF,val)
122#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
123#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST,val)
124#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
125#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI,val)
126#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
127#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD,val)
128#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
129#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI,val)
130#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
131#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO,val)
132#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
133#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG,val)
134#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
135#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL,val)
136#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
137#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE,val)
138#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
139#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE,val)
140#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
141#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM,val)
142#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
143#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT,val)
144#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
145#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED,val)
146#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
147#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT,val)
148#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
149#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64,val)
150#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128)
151#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
152#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128,val)
153#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
154#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256,val)
155#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
156#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512,val)
157#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
158#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024,val)
159#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
160#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024,val)
161
162#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
163#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK,val)
164#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
165#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL,val)
166#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
167#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL,val)
168#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
169#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET,val)
170#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
171#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER,val)
172#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
173#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL,val)
174#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
175#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL,val)
176#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
177#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND,val)
178#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
179#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR,val)
180#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
181#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST,val)
182#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
183#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI,val)
184#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
185#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD,val)
186#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
187#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR,val)
188#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
189#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL,val)
190#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
191#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM,val)
192#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
193#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT,val)
194#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
195#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64,val)
196#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
197#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128,val)
198#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
199#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256,val)
200#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
201#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512,val)
202#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
203#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024,val)
204#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
205#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024,val)
206#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
207#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT,val)
208
209#endif /* _CDEF_BF537_H */
diff --git a/include/asm-blackfin/mach-bf537/defBF534.h b/include/asm-blackfin/mach-bf537/defBF534.h
new file mode 100644
index 000000000000..e605e9709004
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/defBF534.h
@@ -0,0 +1,2501 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/cdefBF537.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF534_H
32#define _DEF_BF534_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37/************************************************************************************
38** System MMR Register Map
39*************************************************************************************/
40/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
41#define PLL_CTL 0xFFC00000 /* PLL Control Register */
42#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
43#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
44#define PLL_STAT 0xFFC0000C /* PLL Status Register */
45#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
46#define CHIPID 0xFFC00014 /* Chip ID Register */
47
48/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
49#define SWRST 0xFFC00100 /* Software Reset Register */
50#define SYSCR 0xFFC00104 /* System Configuration Register */
51#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
52#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
53#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
54#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
55#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
56#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
57#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
58#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
59
60/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
61#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
62#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
63#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
64
65/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
66#define RTC_STAT 0xFFC00300 /* RTC Status Register */
67#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
68#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
69#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
70#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
71#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
72#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
73
74/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
75#define UART0_THR 0xFFC00400 /* Transmit Holding register */
76#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
77#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
78#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
79#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
80#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
81#define UART0_LCR 0xFFC0040C /* Line Control Register */
82#define UART0_MCR 0xFFC00410 /* Modem Control Register */
83#define UART0_LSR 0xFFC00414 /* Line Status Register */
84#define UART0_MSR 0xFFC00418 /* Modem Status Register */
85#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
86#define UART0_GCTL 0xFFC00424 /* Global Control Register */
87
88/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
89#define SPI_CTL 0xFFC00500 /* SPI Control Register */
90#define SPI_FLG 0xFFC00504 /* SPI Flag register */
91#define SPI_STAT 0xFFC00508 /* SPI Status register */
92#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
93#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
94#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
95#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
96
97/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
98#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
99#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
100#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
101#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
102
103#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
104#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
105#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
106#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
107
108#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
109#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
110#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
111#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
112
113#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
114#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
115#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
116#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
117
118#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
119#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
120#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
121#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
122
123#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
124#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
125#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
126#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
127
128#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
129#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
130#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
131#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
132
133#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
134#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
135#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
136#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
137
138#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
139#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
140#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
141
142/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
143#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
144#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
145#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
146#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
147#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
148#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
149#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
150#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
151#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
152#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
153#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
154#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
155#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
156#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
157#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
158#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
159#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
160
161/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
162#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
163#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
164#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
165#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
166#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
167#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
168#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
169#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
170#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
171#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
172#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
173#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
174#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
175#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
176#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
177#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
178#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
179#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
180#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
181#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
182#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
183#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
184
185/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
186#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
187#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
188#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
189#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
190#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
191#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
192#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
193#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
194#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
195#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
196#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
197#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
198#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
199#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
200#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
201#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
202#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
203#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
204#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
205#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
206#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
207#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
208
209/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
210#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
211#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
212#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
213#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
214#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
215#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
216#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
217
218/* DMA Traffic Control Registers */
219#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
220#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
221
222/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
223#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
224#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
225#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
226#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
227#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
228#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
229#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
230#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
231#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
232#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
233#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
234#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
235#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
236
237#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
238#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
239#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
240#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
241#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
242#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
243#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
244#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
245#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
246#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
247#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
248#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
249#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
250
251#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
252#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
253#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
254#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
255#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
256#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
257#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
258#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
259#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
260#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
261#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
262#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
263#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
264
265#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
266#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
267#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
268#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
269#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
270#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
271#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
272#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
273#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
274#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
275#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
276#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
277#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
278
279#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
280#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
281#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
282#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
283#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
284#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
285#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
286#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
287#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
288#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
289#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
290#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
291#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
292
293#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
294#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
295#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
296#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
297#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
298#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
299#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
300#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
301#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
302#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
303#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
304#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
305#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
306
307#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
308#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
309#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
310#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
311#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
312#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
313#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
314#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
315#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
316#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
317#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
318#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
319#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
320
321#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
322#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
323#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
324#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
325#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
326#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
327#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
328#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
329#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
330#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
331#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
332#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
333#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
334
335#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
336#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
337#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
338#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
339#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
340#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
341#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
342#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
343#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
344#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
345#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
346#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
347#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
348
349#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
350#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
351#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
352#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
353#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
354#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
355#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
356#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
357#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
358#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
359#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
360#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
361#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
362
363#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
364#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
365#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
366#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
367#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
368#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
369#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
370#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
371#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
372#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
373#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
374#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
375#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
376
377#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
378#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
379#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
380#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
381#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
382#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
383#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
384#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
385#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
386#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
387#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
388#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
389#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
390
391#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
392#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
393#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
394#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
395#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
396#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
397#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
398#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
399#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
400#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
401#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
402#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
403#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
404
405#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
406#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
407#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
408#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
409#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
410#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
411#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
412#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
413#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
414#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
415#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
416#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
417#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
418
419#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
420#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
421#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
422#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
423#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
424#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
425#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
426#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
427#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
428#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
429#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
430#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
431#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
432
433#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
434#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
435#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
436#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
437#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
438#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
439#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
440#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
441#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
442#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
443#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
444#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
445#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
446
447/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
448#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
449#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
450#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
451#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
452#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
453
454/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
455#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
456#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
457#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
458#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
459#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
460#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
461#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
462#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
463#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
464#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
465#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
466#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
467#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
468#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
469#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
470#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
471
472/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
473#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
474#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
475#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
476#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
477#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
478#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
479#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
480#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
481#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
482#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
483#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
484#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
485#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
486#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
487#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
488#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
489#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
490
491/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
492#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
493#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
494#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
495#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
496#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
497#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
498#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
499#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
500#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
501#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
502#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
503#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
504#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
505#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
506#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
507#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
508#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
509
510/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
511#define UART1_THR 0xFFC02000 /* Transmit Holding register */
512#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
513#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
514#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
515#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
516#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
517#define UART1_LCR 0xFFC0200C /* Line Control Register */
518#define UART1_MCR 0xFFC02010 /* Modem Control Register */
519#define UART1_LSR 0xFFC02014 /* Line Status Register */
520#define UART1_MSR 0xFFC02018 /* Modem Status Register */
521#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
522#define UART1_GCTL 0xFFC02024 /* Global Control Register */
523
524/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
525/* For Mailboxes 0-15 */
526#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
527#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
528#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
529#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
530#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
531#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
532#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
533#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
534#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
535#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
536#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
537#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
538#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */
539
540/* For Mailboxes 16-31 */
541#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
542#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
543#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
544#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
545#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
546#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
547#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
548#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
549#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
550#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
551#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
552#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
553#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */
554
555/* CAN Configuration, Control, and Status Registers */
556#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
557#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
558#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
559#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
560#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
561#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
562#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
563#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
564#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
565#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
566#define CAN_SFCMVER 0xFFC02AA8 /* Version Code Register */
567#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
568#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
569#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
570#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
571#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
572#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
573#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
574
575/* Mailbox Acceptance Masks */
576#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
577#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
578#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
579#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
580#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
581#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
582#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
583#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
584#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
585#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
586#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
587#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
588#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
589#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
590#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
591#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
592#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
593#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
594#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
595#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
596#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
597#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
598#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
599#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
600#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
601#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
602#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
603#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
604#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
605#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
606#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
607#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
608
609#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
610#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
611#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
612#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
613#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
614#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
615#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
616#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
617#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
618#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
619#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
620#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
621#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
622#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
623#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
624#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
625#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
626#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
627#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
628#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
629#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
630#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
631#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
632#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
633#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
634#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
635#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
636#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
637#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
638#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
639#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
640#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
641
642/* CAN Acceptance Mask Macros */
643#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
644#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
645
646/* Mailbox Registers */
647#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
648#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
649#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
650#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
651#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
652#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
653#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
654#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
655
656#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
657#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
658#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
659#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
660#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
661#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
662#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
663#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
664
665#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
666#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
667#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
668#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
669#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
670#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
671#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
672#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
673
674#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
675#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
676#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
677#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
678#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
679#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
680#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
681#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
682
683#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
684#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
685#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
686#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
687#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
688#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
689#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
690#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
691
692#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
693#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
694#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
695#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
696#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
697#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
698#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
699#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
700
701#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
702#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
703#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
704#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
705#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
706#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
707#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
708#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
709
710#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
711#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
712#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
713#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
714#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
715#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
716#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
717#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
718
719#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
720#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
721#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
722#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
723#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
724#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
725#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
726#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
727
728#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
729#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
730#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
731#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
732#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
733#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
734#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
735#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
736
737#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
738#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
739#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
740#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
741#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
742#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
743#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
744#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
745
746#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
747#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
748#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
749#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
750#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
751#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
752#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
753#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
754
755#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
756#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
757#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
758#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
759#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
760#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
761#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
762#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
763
764#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
765#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
766#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
767#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
768#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
769#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
770#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
771#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
772
773#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
774#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
775#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
776#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
777#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
778#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
779#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
780#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
781
782#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
783#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
784#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
785#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
786#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
787#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
788#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
789#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
790
791#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
792#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
793#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
794#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
795#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
796#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
797#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
798#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
799
800#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
801#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
802#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
803#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
804#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
805#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
806#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
807#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
808
809#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
810#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
811#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
812#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
813#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
814#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
815#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
816#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
817
818#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
819#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
820#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
821#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
822#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
823#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
824#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
825#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
826
827#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
828#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
829#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
830#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
831#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
832#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
833#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
834#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
835
836#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
837#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
838#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
839#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
840#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
841#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
842#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
843#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
844
845#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
846#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
847#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
848#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
849#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
850#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
851#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
852#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
853
854#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
855#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
856#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
857#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
858#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
859#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
860#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
861#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
862
863#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
864#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
865#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
866#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
867#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
868#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
869#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
870#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
871
872#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
873#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
874#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
875#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
876#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
877#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
878#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
879#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
880
881#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
882#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
883#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
884#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
885#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
886#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
887#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
888#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
889
890#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
891#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
892#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
893#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
894#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
895#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
896#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
897#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
898
899#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
900#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
901#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
902#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
903#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
904#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
905#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
906#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
907
908#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
909#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
910#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
911#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
912#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
913#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
914#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
915#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
916
917#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
918#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
919#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
920#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
921#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
922#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
923#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
924#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
925
926#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
927#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
928#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
929#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
930#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
931#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
932#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
933#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
934
935/* CAN Mailbox Area Macros */
936#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
937#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
938#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
939#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
940#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
941#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
942#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
943#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
944
945/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
946#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
947#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
948#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
949#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
950
951/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
952#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
953#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
954#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
955#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
956#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
957#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
958#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
959
960#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
961#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
962#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
963#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
964#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
965#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
966#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
967
968/***********************************************************************************
969** System MMR Register Bits And Macros
970**
971** Disclaimer: All macros are intended to make C and Assembly code more readable.
972** Use these macros carefully, as any that do left shifts for field
973** depositing will result in the lower order bits being destroyed. Any
974** macro that shifts left to properly position the bit-field should be
975** used as part of an OR to initialize a register and NOT as a dynamic
976** modifier UNLESS the lower order bits are saved and ORed back in when
977** the macro is used.
978*************************************************************************************/
979/*
980** ********************* PLL AND RESET MASKS ****************************************/
981/* PLL_CTL Masks */
982#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
983#define PLL_OFF 0x0002 /* PLL Not Powered */
984#define STOPCK 0x0008 /* Core Clock Off */
985#define PDWN 0x0020 /* Enter Deep Sleep Mode */
986#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
987#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
988#define BYPASS 0x0100 /* Bypass the PLL */
989#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
990/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
991#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
992
993/* PLL_DIV Masks */
994#define SSEL 0x000F /* System Select */
995#define CSEL 0x0030 /* Core Select */
996#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
997#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
998#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
999#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
1000/* PLL_DIV Macros */
1001#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
1002
1003/* VR_CTL Masks */
1004#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
1005#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
1006#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
1007#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
1008#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
1009
1010#define GAIN 0x000C /* Voltage Level Gain */
1011#define GAIN_5 0x0000 /* GAIN = 5 */
1012#define GAIN_10 0x0004 /* GAIN = 10 */
1013#define GAIN_20 0x0008 /* GAIN = 20 */
1014#define GAIN_50 0x000C /* GAIN = 50 */
1015
1016#define VLEV 0x00F0 /* Internal Voltage Level */
1017#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
1018#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
1019#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
1020#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
1021#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
1022#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
1023#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
1024#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
1025#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
1026#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
1027
1028#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
1029#define PHYWE 0x0200 /* Enable PHY Wakeup From Hibernate */
1030#define CANWE 0x0400 /* Enable CAN Wakeup From Hibernate */
1031#define PHYCLKOE 0x4000 /* PHY Clock Output Enable */
1032#define CKELOW 0x8000 /* Enable Drive CKE Low During Reset */
1033
1034/* PLL_STAT Masks */
1035#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
1036#define FULL_ON 0x0002 /* Processor In Full On Mode */
1037#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
1038#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
1039
1040/* CHIPID Masks */
1041#define CHIPID_VERSION 0xF0000000
1042#define CHIPID_FAMILY 0x0FFFF000
1043#define CHIPID_MANUFACTURE 0x00000FFE
1044
1045/* SWRST Masks */
1046#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
1047#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
1048#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
1049#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
1050#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
1051
1052/* SYSCR Masks */
1053#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
1054#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
1055
1056/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
1057
1058/* SIC_IAR0 Macros */
1059#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
1060#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
1061#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
1062#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
1063#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
1064#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
1065#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
1066#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
1067
1068/* SIC_IAR1 Macros */
1069#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
1070#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
1071#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
1072#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
1073#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
1074#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
1075#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
1076#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
1077
1078/* SIC_IAR2 Macros */
1079#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
1080#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
1081#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
1082#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
1083#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
1084#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
1085#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
1086#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
1087
1088/* SIC_IAR3 Macros */
1089#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
1090#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
1091#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
1092#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
1093#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
1094#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
1095#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
1096#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
1097
1098/* SIC_IMASK Masks */
1099#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
1100#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
1101#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
1102#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
1103
1104/* SIC_IWR Masks */
1105#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
1106#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
1107#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1108#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1109
1110/* *************** WATCHDOG TIMER MASKS *******************************************/
1111/* WDOG_CTL Masks */
1112#define WDOG_RESET 0x0000 /* Generate Reset Event */
1113#define WDOG_NMI 0x0002 /* Generate Non-Maskable Interrupt (NMI) Event */
1114#define WDOG_GPI 0x0004 /* Generate General Purpose (GP) Interrupt */
1115#define WDOG_NONE 0x0006 /* Disable Watchdog Timer Interrupts */
1116#define TMR_EN 0x0FF0 /* Watchdog Counter Enable */
1117#define TMR_DIS 0x0AD0 /* Watchdog Counter Disable */
1118#define TRO 0x8000 /* Watchdog Expired */
1119
1120/* ************** UART CONTROLLER MASKS *************************/
1121/* UARTx_LCR Masks */
1122#define WLS(x) ((((x)&0x3)-5) & 0x03) /* Word Length Select */
1123#define STB 0x04 /* Stop Bits */
1124#define PEN 0x08 /* Parity Enable */
1125#define EPS 0x10 /* Even Parity Select */
1126#define STP 0x20 /* Stick Parity */
1127#define SB 0x40 /* Set Break */
1128#define DLAB 0x80 /* Divisor Latch Access */
1129
1130/* UARTx_MCR Mask */
1131#define LOOP 0x10 /* Loopback Mode Enable */
1132
1133/* UARTx_LSR Masks */
1134#define DR 0x01 /* Data Ready */
1135#define OE 0x02 /* Overrun Error */
1136#define PE 0x04 /* Parity Error */
1137#define FE 0x08 /* Framing Error */
1138#define BI 0x10 /* Break Interrupt */
1139#define THRE 0x20 /* THR Empty */
1140#define TEMT 0x40 /* TSR and UART_THR Empty */
1141
1142/* UARTx_IER Masks */
1143#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
1144#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
1145#define ELSI 0x04 /* Enable RX Status Interrupt */
1146
1147/* UARTx_IIR Masks */
1148#define NINT 0x01 /* Pending Interrupt */
1149#define IIR_TX_READY 0x02 /* UART_THR empty */
1150#define IIR_RX_READY 0x04 /* Receive data ready */
1151#define IIR_LINE_CHANGE 0x06 /* Receive line status */
1152#define IIR_STATUS 0x06
1153
1154/* UARTx_GCTL Masks */
1155#define UCEN 0x01 /* Enable UARTx Clocks */
1156#define IREN 0x02 /* Enable IrDA Mode */
1157#define TPOLC 0x04 /* IrDA TX Polarity Change */
1158#define RPOLC 0x08 /* IrDA RX Polarity Change */
1159#define FPE 0x10 /* Force Parity Error On Transmit */
1160#define FFE 0x20 /* Force Framing Error On Transmit */
1161
1162/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
1163/* SPI_CTL Masks */
1164#define TIMOD 0x0003 /* Transfer Initiate Mode */
1165#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
1166#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
1167#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
1168#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
1169#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
1170#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
1171#define PSSE 0x0010 /* Slave-Select Input Enable */
1172#define EMISO 0x0020 /* Enable MISO As Output */
1173#define SPI_SIZE 0x0100 /* Size of Words (16/8* Bits) */
1174#define LSBF 0x0200 /* LSB First */
1175#define CPHA 0x0400 /* Clock Phase */
1176#define CPOL 0x0800 /* Clock Polarity */
1177#define MSTR 0x1000 /* Master/Slave* */
1178#define WOM 0x2000 /* Write Open Drain Master */
1179#define SPE 0x4000 /* SPI Enable */
1180
1181/* SPI_FLG Masks */
1182#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
1183#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
1184#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
1185#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
1186#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
1187#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
1188#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
1189#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
1190#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
1191#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
1192#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
1193#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
1194#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
1195#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
1196
1197/* SPI_STAT Masks */
1198#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
1199#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
1200#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
1201#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
1202#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
1203#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
1204#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
1205
1206/* **************** GENERAL PURPOSE TIMER MASKS **********************/
1207/* TIMER_ENABLE Masks */
1208#define TIMEN0 0x0001 /* Enable Timer 0 */
1209#define TIMEN1 0x0002 /* Enable Timer 1 */
1210#define TIMEN2 0x0004 /* Enable Timer 2 */
1211#define TIMEN3 0x0008 /* Enable Timer 3 */
1212#define TIMEN4 0x0010 /* Enable Timer 4 */
1213#define TIMEN5 0x0020 /* Enable Timer 5 */
1214#define TIMEN6 0x0040 /* Enable Timer 6 */
1215#define TIMEN7 0x0080 /* Enable Timer 7 */
1216
1217/* TIMER_DISABLE Masks */
1218#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
1219#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
1220#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
1221#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
1222#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
1223#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
1224#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
1225#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
1226
1227/* TIMER_STATUS Masks */
1228#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
1229#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
1230#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
1231#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
1232#define TOVL_ERR0 0x00000010 /* Timer 0 Counter Overflow */
1233#define TOVL_ERR1 0x00000020 /* Timer 1 Counter Overflow */
1234#define TOVL_ERR2 0x00000040 /* Timer 2 Counter Overflow */
1235#define TOVL_ERR3 0x00000080 /* Timer 3 Counter Overflow */
1236#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
1237#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
1238#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
1239#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
1240#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
1241#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
1242#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
1243#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
1244#define TOVL_ERR4 0x00100000 /* Timer 4 Counter Overflow */
1245#define TOVL_ERR5 0x00200000 /* Timer 5 Counter Overflow */
1246#define TOVL_ERR6 0x00400000 /* Timer 6 Counter Overflow */
1247#define TOVL_ERR7 0x00800000 /* Timer 7 Counter Overflow */
1248#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
1249#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
1250#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
1251#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
1252
1253/* TIMERx_CONFIG Masks */
1254#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
1255#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
1256#define EXT_CLK 0x0003 /* External Clock Mode */
1257#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
1258#define PERIOD_CNT 0x0008 /* Period Count */
1259#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
1260#define TIN_SEL 0x0020 /* Timer Input Select */
1261#define OUT_DIS 0x0040 /* Output Pad Disable */
1262#define CLK_SEL 0x0080 /* Timer Clock Select */
1263#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
1264#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1265#define ERR_TYP 0xC000 /* Error Type */
1266
1267/* ****************** GPIO PORTS F, G, H MASKS ***********************/
1268/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1269/* Port F Masks */
1270#define PF0 0x0001
1271#define PF1 0x0002
1272#define PF2 0x0004
1273#define PF3 0x0008
1274#define PF4 0x0010
1275#define PF5 0x0020
1276#define PF6 0x0040
1277#define PF7 0x0080
1278#define PF8 0x0100
1279#define PF9 0x0200
1280#define PF10 0x0400
1281#define PF11 0x0800
1282#define PF12 0x1000
1283#define PF13 0x2000
1284#define PF14 0x4000
1285#define PF15 0x8000
1286
1287/* Port G Masks */
1288#define PG0 0x0001
1289#define PG1 0x0002
1290#define PG2 0x0004
1291#define PG3 0x0008
1292#define PG4 0x0010
1293#define PG5 0x0020
1294#define PG6 0x0040
1295#define PG7 0x0080
1296#define PG8 0x0100
1297#define PG9 0x0200
1298#define PG10 0x0400
1299#define PG11 0x0800
1300#define PG12 0x1000
1301#define PG13 0x2000
1302#define PG14 0x4000
1303#define PG15 0x8000
1304
1305/* Port H Masks */
1306#define PH0 0x0001
1307#define PH1 0x0002
1308#define PH2 0x0004
1309#define PH3 0x0008
1310#define PH4 0x0010
1311#define PH5 0x0020
1312#define PH6 0x0040
1313#define PH7 0x0080
1314#define PH8 0x0100
1315#define PH9 0x0200
1316#define PH10 0x0400
1317#define PH11 0x0800
1318#define PH12 0x1000
1319#define PH13 0x2000
1320#define PH14 0x4000
1321#define PH15 0x8000
1322
1323/* ******************* SERIAL PORT MASKS **************************************/
1324/* SPORTx_TCR1 Masks */
1325#define TSPEN 0x0001 /* Transmit Enable */
1326#define ITCLK 0x0002 /* Internal Transmit Clock Select */
1327#define DTYPE_NORM 0x0004 /* Data Format Normal */
1328#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1329#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1330#define TLSBIT 0x0010 /* Transmit Bit Order */
1331#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
1332#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
1333#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
1334#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
1335#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
1336#define TCKFE 0x4000 /* Clock Falling Edge Select */
1337
1338/* SPORTx_TCR2 Masks and Macro */
1339#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
1340#define TXSE 0x0100 /* TX Secondary Enable */
1341#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
1342#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
1343
1344/* SPORTx_RCR1 Masks */
1345#define RSPEN 0x0001 /* Receive Enable */
1346#define IRCLK 0x0002 /* Internal Receive Clock Select */
1347#define DTYPE_NORM 0x0004 /* Data Format Normal */
1348#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1349#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1350#define RLSBIT 0x0010 /* Receive Bit Order */
1351#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
1352#define RFSR 0x0400 /* Receive Frame Sync Required Select */
1353#define LRFS 0x1000 /* Low Receive Frame Sync Select */
1354#define LARFS 0x2000 /* Late Receive Frame Sync Select */
1355#define RCKFE 0x4000 /* Clock Falling Edge Select */
1356
1357/* SPORTx_RCR2 Masks */
1358#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
1359#define RXSE 0x0100 /* RX Secondary Enable */
1360#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
1361#define RRFST 0x0400 /* Right-First Data Order */
1362
1363/* SPORTx_STAT Masks */
1364#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
1365#define RUVF 0x0002 /* Sticky Receive Underflow Status */
1366#define ROVF 0x0004 /* Sticky Receive Overflow Status */
1367#define TXF 0x0008 /* Transmit FIFO Full Status */
1368#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
1369#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
1370#define TXHRE 0x0040 /* Transmit Hold Register Empty */
1371
1372/* SPORTx_MCMC1 Macros */
1373#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1374
1375/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
1376#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1377
1378/* SPORTx_MCMC2 Masks */
1379#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1380#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1381#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1382#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
1383#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
1384#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
1385#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
1386#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1387#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1388#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1389#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1390#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1391#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1392#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1393#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1394#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1395#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1396#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1397#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1398#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1399#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1400#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1401#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1402
1403/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1404/* EBIU_AMGCTL Masks */
1405#define AMCKEN 0x0001 /* Enable CLKOUT */
1406#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1407#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1408#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1409#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1410#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1411
1412/* EBIU_AMBCTL0 Masks */
1413#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
1414#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
1415#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
1416#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
1417#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
1418#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
1419#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
1420#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
1421#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
1422#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
1423#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1424#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1425#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1426#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1427#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
1428#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
1429#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
1430#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
1431#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
1432#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
1433#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
1434#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
1435#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
1436#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
1437#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
1438#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
1439#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
1440#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
1441#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
1442#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
1443#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
1444#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
1445#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
1446#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
1447#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
1448#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
1449#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
1450#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
1451#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
1452#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
1453#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
1454#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
1455#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
1456#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
1457
1458#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
1459#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
1460#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
1461#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
1462#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
1463#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
1464#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
1465#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
1466#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
1467#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
1468#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1469#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1470#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1471#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1472#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
1473#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
1474#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
1475#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
1476#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
1477#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
1478#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
1479#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
1480#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
1481#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
1482#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
1483#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
1484#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
1485#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
1486#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
1487#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
1488#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
1489#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
1490#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
1491#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
1492#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
1493#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
1494#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
1495#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
1496#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
1497#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
1498#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
1499#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
1500#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
1501#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
1502
1503/* EBIU_AMBCTL1 Masks */
1504#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
1505#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
1506#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
1507#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
1508#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
1509#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
1510#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
1511#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
1512#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
1513#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
1514#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1515#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1516#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1517#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1518#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
1519#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
1520#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
1521#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
1522#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1523#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1524#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1525#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1526#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1527#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1528#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1529#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1530#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1531#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1532#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1533#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1534#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1535#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1536#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1537#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1538#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1539#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1540#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1541#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1542#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1543#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1544#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1545#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1546#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1547#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1548
1549#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
1550#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
1551#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
1552#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1553#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1554#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1555#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
1556#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1557#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1558#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1559#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1560#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1561#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1562#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1563#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
1564#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1565#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1566#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1567#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1568#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1569#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1570#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1571#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1572#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1573#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1574#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1575#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1576#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1577#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1578#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
1579#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1580#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1581#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1582#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1583#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1584#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1585#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1586#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1587#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1588#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1589#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1590#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1591#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1592#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1593
1594/* ********************** SDRAM CONTROLLER MASKS **********************************************/
1595/* EBIU_SDGCTL Masks */
1596#define SCTLE 0x00000001 /* Enable SDRAM Signals */
1597#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
1598#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
1599#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1600#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1601#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1602#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1603#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1604#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1605#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1606#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1607#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1608#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1609#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1610#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1611#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1612#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1613#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1614#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1615#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1616#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1617#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1618#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1619#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1620#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1621#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1622#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1623#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1624#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1625#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1626#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1627#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1628#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1629#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1630#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1631#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1632#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1633#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1634#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1635#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1636#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1637#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1638#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1639#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1640#define EMREN 0x10000000 /* Extended Mode Register Enable */
1641#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1642#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1643
1644/* EBIU_SDBCTL Masks */
1645#define EBE 0x0001 /* Enable SDRAM External Bank */
1646#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1647#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1648#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1649#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1650#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1651#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1652#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1653#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1654
1655/* EBIU_SDSTAT Masks */
1656#define SDCI 0x0001 /* SDRAM Controller Idle */
1657#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1658#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1659#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1660#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1661#define BGSTAT 0x0020 /* Bus Grant Status */
1662
1663/* ************************** DMA CONTROLLER MASKS ********************************/
1664/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1665#define DMAEN 0x0001 /* DMA Channel Enable */
1666#define WNR 0x0002 /* Channel Direction (W/R*) */
1667#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1668#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1669#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1670#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1671#define RESTART 0x0020 /* DMA Buffer Clear */
1672#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1673#define DI_EN 0x0080 /* Data Interrupt Enable */
1674#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1675#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1676#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1677#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1678#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1679#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1680#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1681#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1682#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1683#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1684#define NDSIZE 0x0900 /* Next Descriptor Size */
1685
1686#define DMAFLOW 0x7000 /* Flow Control */
1687#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1688#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1689#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1690#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1691#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1692
1693/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1694#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1695#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1696#define PMAP_PPI 0x0000 /* PPI Port DMA */
1697#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1698#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1699#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1700#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1701#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1702#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1703#define PMAP_SPI 0x7000 /* SPI Port DMA */
1704#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1705#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1706#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1707#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1708
1709/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1710#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1711#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1712#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1713#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1714
1715/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1716/* PPI_CONTROL Masks */
1717#define PORT_EN 0x0001 /* PPI Port Enable */
1718#define PORT_DIR 0x0002 /* PPI Port Direction */
1719#define XFR_TYPE 0x000C /* PPI Transfer Type */
1720#define PORT_CFG 0x0030 /* PPI Port Configuration */
1721#define FLD_SEL 0x0040 /* PPI Active Field Select */
1722#define PACK_EN 0x0080 /* PPI Packing Mode */
1723#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1724#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1725#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1726#define DLENGTH 0x3800 /* PPI Data Length */
1727#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1728#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1729#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1730#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1731#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1732#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1733#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1734#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1735#define POLC 0x4000 /* PPI Clock Polarity */
1736#define POLS 0x8000 /* PPI Frame Sync Polarity */
1737
1738/* PPI_STATUS Masks */
1739#define FLD 0x0400 /* Field Indicator */
1740#define FT_ERR 0x0800 /* Frame Track Error */
1741#define OVR 0x1000 /* FIFO Overflow Error */
1742#define UNDR 0x2000 /* FIFO Underrun Error */
1743#define ERR_DET 0x4000 /* Error Detected Indicator */
1744#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1745
1746/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1747/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1748#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1749#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1750
1751/* TWI_PRESCALE Masks */
1752#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1753#define TWI_ENA 0x0080 /* TWI Enable */
1754#define SCCB 0x0200 /* SCCB Compatibility Enable */
1755
1756/* TWI_SLAVE_CTRL Masks */
1757#define SEN 0x0001 /* Slave Enable */
1758#define SADD_LEN 0x0002 /* Slave Address Length */
1759#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1760#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1761#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1762
1763/* TWI_SLAVE_STAT Masks */
1764#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1765#define GCALL 0x0002 /* General Call Indicator */
1766
1767/* TWI_MASTER_CTRL Masks */
1768#define MEN 0x0001 /* Master Mode Enable */
1769#define MADD_LEN 0x0002 /* Master Address Length */
1770#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1771#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1772#define STOP 0x0010 /* Issue Stop Condition */
1773#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1774#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1775#define SDAOVR 0x4000 /* Serial Data Override */
1776#define SCLOVR 0x8000 /* Serial Clock Override */
1777
1778/* TWI_MASTER_STAT Masks */
1779#define MPROG 0x0001 /* Master Transfer In Progress */
1780#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1781#define ANAK 0x0004 /* Address Not Acknowledged */
1782#define DNAK 0x0008 /* Data Not Acknowledged */
1783#define BUFRDERR 0x0010 /* Buffer Read Error */
1784#define BUFWRERR 0x0020 /* Buffer Write Error */
1785#define SDASEN 0x0040 /* Serial Data Sense */
1786#define SCLSEN 0x0080 /* Serial Clock Sense */
1787#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1788
1789/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1790#define SINIT 0x0001 /* Slave Transfer Initiated */
1791#define SCOMP 0x0002 /* Slave Transfer Complete */
1792#define SERR 0x0004 /* Slave Transfer Error */
1793#define SOVF 0x0008 /* Slave Overflow */
1794#define MCOMP 0x0010 /* Master Transfer Complete */
1795#define MERR 0x0020 /* Master Transfer Error */
1796#define XMTSERV 0x0040 /* Transmit FIFO Service */
1797#define RCVSERV 0x0080 /* Receive FIFO Service */
1798
1799/* TWI_FIFO_CTRL Masks */
1800#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1801#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1802#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1803#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1804
1805/* TWI_FIFO_STAT Masks */
1806#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1807#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1808#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1809#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1810
1811#define RCVSTAT 0x000C /* Receive FIFO Status */
1812#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1813#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1814#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1815
1816/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
1817/* CAN_CONTROL Masks */
1818#define SRS 0x0001 /* Software Reset */
1819#define DNM 0x0002 /* Device Net Mode */
1820#define ABO 0x0004 /* Auto-Bus On Enable */
1821#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */
1822#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
1823#define SMR 0x0020 /* Sleep Mode Request */
1824#define CSR 0x0040 /* CAN Suspend Mode Request */
1825#define CCR 0x0080 /* CAN Configuration Mode Request */
1826
1827/* CAN_STATUS Masks */
1828#define WT 0x0001 /* TX Warning Flag */
1829#define WR 0x0002 /* RX Warning Flag */
1830#define EP 0x0004 /* Error Passive Mode */
1831#define EBO 0x0008 /* Error Bus Off Mode */
1832#define SMA 0x0020 /* Sleep Mode Acknowledge */
1833#define CSA 0x0040 /* Suspend Mode Acknowledge */
1834#define CCA 0x0080 /* Configuration Mode Acknowledge */
1835#define MBPTR 0x1F00 /* Mailbox Pointer */
1836#define TRM 0x4000 /* Transmit Mode */
1837#define REC 0x8000 /* Receive Mode */
1838
1839/* CAN_CLOCK Masks */
1840#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
1841
1842/* CAN_TIMING Masks */
1843#define TSEG1 0x000F /* Time Segment 1 */
1844#define TSEG2 0x0070 /* Time Segment 2 */
1845#define SAM 0x0080 /* Sampling */
1846#define SJW 0x0300 /* Synchronization Jump Width */
1847
1848/* CAN_DEBUG Masks */
1849#define DEC 0x0001 /* Disable CAN Error Counters */
1850#define DRI 0x0002 /* Disable CAN RX Input */
1851#define DTO 0x0004 /* Disable CAN TX Output */
1852#define DIL 0x0008 /* Disable CAN Internal Loop */
1853#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
1854#define MRB 0x0020 /* Mode Read Back Enable */
1855#define CDE 0x8000 /* CAN Debug Enable */
1856
1857/* CAN_CEC Masks */
1858#define RXECNT 0x00FF /* Receive Error Counter */
1859#define TXECNT 0xFF00 /* Transmit Error Counter */
1860
1861/* CAN_INTR Masks */
1862#define MBRIF 0x0001 /* Mailbox Receive Interrupt */
1863#define MBTIF 0x0002 /* Mailbox Transmit Interrupt */
1864#define GIRQ 0x0004 /* Global Interrupt */
1865#define SMACK 0x0008 /* Sleep Mode Acknowledge */
1866#define CANTX 0x0040 /* CAN TX Bus Value */
1867#define CANRX 0x0080 /* CAN RX Bus Value */
1868
1869/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
1870#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
1871#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
1872#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
1873#define BASEID 0x1FFC /* Base Identifier */
1874#define IDE 0x2000 /* Identifier Extension */
1875#define RTR 0x4000 /* Remote Frame Transmission Request */
1876#define AME 0x8000 /* Acceptance Mask Enable */
1877
1878/* CAN_MBxx_TIMESTAMP Masks */
1879#define TSV 0xFFFF /* Timestamp */
1880
1881/* CAN_MBxx_LENGTH Masks */
1882#define DLC 0x000F /* Data Length Code */
1883
1884/* CAN_AMxxH and CAN_AMxxL Masks */
1885#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
1886#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
1887#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
1888#define BASEID 0x1FFC /* Base Identifier */
1889#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
1890#define FMD 0x4000 /* Full Mask Data Field Enable */
1891#define FDF 0x8000 /* Filter On Data Field Enable */
1892
1893/* CAN_MC1 Masks */
1894#define MC0 0x0001 /* Enable Mailbox 0 */
1895#define MC1 0x0002 /* Enable Mailbox 1 */
1896#define MC2 0x0004 /* Enable Mailbox 2 */
1897#define MC3 0x0008 /* Enable Mailbox 3 */
1898#define MC4 0x0010 /* Enable Mailbox 4 */
1899#define MC5 0x0020 /* Enable Mailbox 5 */
1900#define MC6 0x0040 /* Enable Mailbox 6 */
1901#define MC7 0x0080 /* Enable Mailbox 7 */
1902#define MC8 0x0100 /* Enable Mailbox 8 */
1903#define MC9 0x0200 /* Enable Mailbox 9 */
1904#define MC10 0x0400 /* Enable Mailbox 10 */
1905#define MC11 0x0800 /* Enable Mailbox 11 */
1906#define MC12 0x1000 /* Enable Mailbox 12 */
1907#define MC13 0x2000 /* Enable Mailbox 13 */
1908#define MC14 0x4000 /* Enable Mailbox 14 */
1909#define MC15 0x8000 /* Enable Mailbox 15 */
1910
1911/* CAN_MC2 Masks */
1912#define MC16 0x0001 /* Enable Mailbox 16 */
1913#define MC17 0x0002 /* Enable Mailbox 17 */
1914#define MC18 0x0004 /* Enable Mailbox 18 */
1915#define MC19 0x0008 /* Enable Mailbox 19 */
1916#define MC20 0x0010 /* Enable Mailbox 20 */
1917#define MC21 0x0020 /* Enable Mailbox 21 */
1918#define MC22 0x0040 /* Enable Mailbox 22 */
1919#define MC23 0x0080 /* Enable Mailbox 23 */
1920#define MC24 0x0100 /* Enable Mailbox 24 */
1921#define MC25 0x0200 /* Enable Mailbox 25 */
1922#define MC26 0x0400 /* Enable Mailbox 26 */
1923#define MC27 0x0800 /* Enable Mailbox 27 */
1924#define MC28 0x1000 /* Enable Mailbox 28 */
1925#define MC29 0x2000 /* Enable Mailbox 29 */
1926#define MC30 0x4000 /* Enable Mailbox 30 */
1927#define MC31 0x8000 /* Enable Mailbox 31 */
1928
1929/* CAN_MD1 Masks */
1930#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
1931#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
1932#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
1933#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
1934#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
1935#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
1936#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
1937#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
1938#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
1939#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
1940#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
1941#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
1942#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
1943#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
1944#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
1945#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
1946
1947/* CAN_MD2 Masks */
1948#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
1949#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
1950#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
1951#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
1952#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
1953#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
1954#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
1955#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
1956#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
1957#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
1958#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
1959#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
1960#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
1961#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
1962#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
1963#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
1964
1965/* CAN_RMP1 Masks */
1966#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
1967#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
1968#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
1969#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
1970#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
1971#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
1972#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
1973#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
1974#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
1975#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
1976#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
1977#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
1978#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
1979#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
1980#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
1981#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
1982
1983/* CAN_RMP2 Masks */
1984#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
1985#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
1986#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
1987#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
1988#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
1989#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
1990#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
1991#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
1992#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
1993#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
1994#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
1995#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
1996#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
1997#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
1998#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
1999#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
2000
2001/* CAN_RML1 Masks */
2002#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
2003#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
2004#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
2005#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
2006#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
2007#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
2008#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
2009#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
2010#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
2011#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
2012#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
2013#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
2014#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
2015#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
2016#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
2017#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
2018
2019/* CAN_RML2 Masks */
2020#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
2021#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
2022#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
2023#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
2024#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
2025#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
2026#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
2027#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
2028#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
2029#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
2030#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
2031#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
2032#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
2033#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
2034#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
2035#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
2036
2037/* CAN_OPSS1 Masks */
2038#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
2039#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
2040#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
2041#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
2042#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
2043#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
2044#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
2045#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
2046#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
2047#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
2048#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
2049#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
2050#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
2051#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
2052#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
2053#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
2054
2055/* CAN_OPSS2 Masks */
2056#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
2057#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
2058#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
2059#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
2060#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
2061#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
2062#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
2063#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
2064#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
2065#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
2066#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
2067#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
2068#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
2069#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
2070#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
2071#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
2072
2073/* CAN_TRR1 Masks */
2074#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
2075#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
2076#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
2077#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
2078#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
2079#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
2080#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
2081#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
2082#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
2083#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
2084#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
2085#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
2086#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
2087#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
2088#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
2089#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
2090
2091/* CAN_TRR2 Masks */
2092#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
2093#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
2094#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
2095#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
2096#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
2097#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
2098#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
2099#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
2100#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
2101#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
2102#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
2103#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
2104#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
2105#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
2106#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
2107#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
2108
2109/* CAN_TRS1 Masks */
2110#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
2111#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
2112#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
2113#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
2114#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
2115#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
2116#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
2117#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
2118#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
2119#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
2120#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
2121#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
2122#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
2123#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
2124#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
2125#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
2126
2127/* CAN_TRS2 Masks */
2128#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
2129#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
2130#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
2131#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
2132#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
2133#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
2134#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
2135#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
2136#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
2137#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
2138#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
2139#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
2140#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
2141#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
2142#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
2143#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
2144
2145/* CAN_AA1 Masks */
2146#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
2147#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
2148#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
2149#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
2150#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
2151#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
2152#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
2153#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
2154#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
2155#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
2156#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
2157#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
2158#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
2159#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
2160#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
2161#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
2162
2163/* CAN_AA2 Masks */
2164#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
2165#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
2166#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
2167#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
2168#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
2169#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
2170#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
2171#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
2172#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
2173#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
2174#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
2175#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
2176#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
2177#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
2178#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
2179#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
2180
2181/* CAN_TA1 Masks */
2182#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
2183#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
2184#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
2185#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
2186#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
2187#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
2188#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
2189#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
2190#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
2191#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
2192#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
2193#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
2194#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
2195#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
2196#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
2197#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
2198
2199/* CAN_TA2 Masks */
2200#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
2201#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
2202#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
2203#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
2204#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
2205#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
2206#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
2207#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
2208#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
2209#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
2210#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
2211#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
2212#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
2213#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
2214#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
2215#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
2216
2217/* CAN_MBTD Masks */
2218#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
2219#define TDA 0x0040 /* Temporary Disable Acknowledge */
2220#define TDR 0x0080 /* Temporary Disable Request */
2221
2222/* CAN_RFH1 Masks */
2223#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
2224#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
2225#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
2226#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
2227#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
2228#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
2229#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
2230#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
2231#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
2232#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
2233#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
2234#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
2235#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
2236#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
2237#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
2238#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
2239
2240/* CAN_RFH2 Masks */
2241#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
2242#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
2243#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
2244#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
2245#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
2246#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
2247#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
2248#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
2249#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
2250#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
2251#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
2252#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
2253#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
2254#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
2255#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
2256#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
2257
2258/* CAN_MBTIF1 Masks */
2259#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
2260#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
2261#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
2262#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
2263#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
2264#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
2265#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
2266#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
2267#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
2268#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
2269#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
2270#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
2271#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
2272#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
2273#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
2274#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
2275
2276/* CAN_MBTIF2 Masks */
2277#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
2278#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
2279#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
2280#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
2281#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
2282#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
2283#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
2284#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
2285#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
2286#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
2287#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
2288#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
2289#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
2290#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
2291#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
2292#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
2293
2294/* CAN_MBRIF1 Masks */
2295#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
2296#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
2297#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
2298#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
2299#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
2300#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
2301#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
2302#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
2303#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
2304#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
2305#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
2306#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
2307#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
2308#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
2309#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
2310#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
2311
2312/* CAN_MBRIF2 Masks */
2313#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
2314#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
2315#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
2316#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
2317#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
2318#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
2319#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
2320#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
2321#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
2322#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
2323#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
2324#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
2325#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
2326#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
2327#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
2328#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
2329
2330/* CAN_MBIM1 Masks */
2331#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
2332#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
2333#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
2334#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
2335#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
2336#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
2337#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
2338#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
2339#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
2340#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
2341#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
2342#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
2343#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
2344#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
2345#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
2346#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
2347
2348/* CAN_MBIM2 Masks */
2349#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
2350#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
2351#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
2352#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
2353#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
2354#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
2355#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
2356#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
2357#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
2358#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
2359#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
2360#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
2361#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
2362#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
2363#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
2364#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
2365
2366/* CAN_GIM Masks */
2367#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
2368#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
2369#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
2370#define BOIM 0x0008 /* Enable Bus Off Interrupt */
2371#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
2372#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
2373#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
2374#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
2375#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
2376#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
2377#define ADIM 0x0400 /* Enable Access Denied Interrupt */
2378
2379/* CAN_GIS Masks */
2380#define EWTIS 0x0001 /* TX Error Count IRQ Status */
2381#define EWRIS 0x0002 /* RX Error Count IRQ Status */
2382#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
2383#define BOIS 0x0008 /* Bus Off IRQ Status */
2384#define WUIS 0x0010 /* Wake-Up IRQ Status */
2385#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
2386#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
2387#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
2388#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
2389#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
2390#define ADIS 0x0400 /* Access Denied IRQ Status */
2391
2392/* CAN_GIF Masks */
2393#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
2394#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
2395#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
2396#define BOIF 0x0008 /* Bus Off IRQ Flag */
2397#define WUIF 0x0010 /* Wake-Up IRQ Flag */
2398#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
2399#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
2400#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
2401#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
2402#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
2403#define ADIF 0x0400 /* Access Denied IRQ Flag */
2404
2405/* CAN_UCCNF Masks */
2406#define UCCNF 0x000F /* Universal Counter Mode */
2407#define UC_STAMP 0x0001 /* Timestamp Mode */
2408#define UC_WDOG 0x0002 /* Watchdog Mode */
2409#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
2410#define UC_ERROR 0x0006 /* CAN Error Frame Count */
2411#define UC_OVER 0x0007 /* CAN Overload Frame Count */
2412#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
2413#define UC_AA 0x0009 /* TX Abort Count */
2414#define UC_TA 0x000A /* TX Successful Count */
2415#define UC_REJECT 0x000B /* RX Message Rejected Count */
2416#define UC_RML 0x000C /* RX Message Lost Count */
2417#define UC_RX 0x000D /* Total Successful RX Messages Count */
2418#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
2419#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
2420#define UCRC 0x0020 /* Universal Counter Reload/Clear */
2421#define UCCT 0x0040 /* Universal Counter CAN Trigger */
2422#define UCE 0x0080 /* Universal Counter Enable */
2423
2424/* CAN_ESR Masks */
2425#define ACKE 0x0004 /* Acknowledge Error */
2426#define SER 0x0008 /* Stuff Error */
2427#define CRCE 0x0010 /* CRC Error */
2428#define SA0 0x0020 /* Stuck At Dominant Error */
2429#define BEF 0x0040 /* Bit Error Flag */
2430#define FER 0x0080 /* Form Error Flag */
2431
2432/* CAN_EWR Masks */
2433#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
2434#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
2435
2436/* ******************* PIN CONTROL REGISTER MASKS ************************/
2437/* PORT_MUX Masks */
2438#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
2439#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
2440#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
2441
2442#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
2443#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
2444#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
2445#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
2446
2447#define PFDE 0x0008 /* Port F DMA Request Enable */
2448#define PGDE_UART 0x0000 /* Enable UART0 RX/TX */
2449#define PGDE_DMA 0x0008 /* Enable DMAR1:0 */
2450
2451#define PFTE 0x0010 /* Port F Timer Enable */
2452#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
2453#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
2454
2455#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
2456#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
2457#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
2458
2459#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
2460#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
2461#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
2462
2463#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
2464#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
2465#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
2466
2467#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
2468#define PFFE_TIMER 0x0000 /* Enable TMR2 */
2469#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
2470
2471#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
2472#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
2473#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
2474
2475#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
2476#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
2477#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
2478
2479#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
2480#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
2481#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
2482
2483/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
2484/* HDMAx_CTL Masks */
2485#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
2486#define REP 0x0002 /* HDMA Request Polarity */
2487#define UTE 0x0004 /* Urgency Threshold Enable */
2488#define OIE 0x0010 /* Overflow Interrupt Enable */
2489#define BDIE 0x0020 /* Block Done Interrupt Enable */
2490#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
2491#define DRQ 0x0300 /* HDMA Request Type */
2492#define DRQ_NONE 0x0000 /* No Request */
2493#define DRQ_SINGLE 0x0100 /* Channels Request Single */
2494#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
2495#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
2496#define RBC 0x1000 /* Reload BCNT With IBCNT */
2497#define PS 0x2000 /* HDMA Pin Status */
2498#define OI 0x4000 /* Overflow Interrupt Generated */
2499#define BDI 0x8000 /* Block Done Interrupt Generated */
2500
2501#endif /* _DEF_BF534_H */
diff --git a/include/asm-blackfin/mach-bf537/defBF537.h b/include/asm-blackfin/mach-bf537/defBF537.h
new file mode 100644
index 000000000000..26f9c02eb73c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/defBF537.h
@@ -0,0 +1,404 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/defbf537.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _DEF_BF537_H
33#define _DEF_BF537_H
34
35/*include all Core registers and bit definitions*/
36#include "defBF537.h"
37
38/*include core specific register pointer definitions*/
39#include <asm/mach-common/cdef_LPBlackfin.h>
40
41/************************************************************************************
42** Define EMAC Section Unique to BF536/BF537
43*************************************************************************************/
44
45/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
46#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
47#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
48#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
49#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
50#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
51#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
52#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
53#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
54#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
55#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
56#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
57#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
58#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
59#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
60#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
61#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
62#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
63#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
64#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
65
66#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
67#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
68#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
69#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
70#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
71#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
72#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
73#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
74
75#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
76#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
77#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
78#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
79#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
80
81#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
82#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
83#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
84#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
85#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
86#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
87#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
88#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
89#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
90#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
91#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
92#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
93#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
94#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
95#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
96#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
97#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
98#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
99#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
100#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
101#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
102#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
103#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
104#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
105
106#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
107#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
108#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
109#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
110#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
111#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
112#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
113#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
114#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
115#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
116#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
117#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
118#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
119#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
120#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
121#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
122#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
123#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
124#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
125#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
126#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
127#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
128#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
129
130/* Listing for IEEE-Supported Count Registers */
131#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
132#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
133#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
134#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
135#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
136#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
137#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
138#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
139#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
140#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
141#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
142#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
143#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
144#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
145#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
146#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
147#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
148#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
149#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
150#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */
151#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
152#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
153#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
154#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
155
156#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
157#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
158#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
159#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
160#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
161#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
162#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
163#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
164#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
165#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
166#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
167#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
168#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
169#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
170#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
171#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
172#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
173#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
174#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
175#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
176#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
177#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
178#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
179
180/***********************************************************************************
181** System MMR Register Bits And Macros
182**
183** Disclaimer: All macros are intended to make C and Assembly code more readable.
184** Use these macros carefully, as any that do left shifts for field
185** depositing will result in the lower order bits being destroyed. Any
186** macro that shifts left to properly position the bit-field should be
187** used as part of an OR to initialize a register and NOT as a dynamic
188** modifier UNLESS the lower order bits are saved and ORed back in when
189** the macro is used.
190*************************************************************************************/
191/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
192/* EMAC_OPMODE Masks */
193#define RE 0x00000001 /* Receiver Enable */
194#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
195#define HU 0x00000010 /* Hash Filter Unicast Address */
196#define HM 0x00000020 /* Hash Filter Multicast Address */
197#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
198#define PR 0x00000080 /* Promiscuous Mode Enable */
199#define IFE 0x00000100 /* Inverse Filtering Enable */
200#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
201#define PBF 0x00000400 /* Pass Bad Frames Enable */
202#define PSF 0x00000800 /* Pass Short Frames Enable */
203#define RAF 0x00001000 /* Receive-All Mode */
204#define TE 0x00010000 /* Transmitter Enable */
205#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
206#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
207#define DC 0x00080000 /* Deferral Check */
208#define BOLMT 0x00300000 /* Back-Off Limit */
209#define BOLMT_10 0x00000000 /* 10-bit range */
210#define BOLMT_8 0x00100000 /* 8-bit range */
211#define BOLMT_4 0x00200000 /* 4-bit range */
212#define BOLMT_1 0x00300000 /* 1-bit range */
213#define DRTY 0x00400000 /* Disable TX Retry On Collision */
214#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
215#define RMII 0x01000000 /* RMII/MII* Mode */
216#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
217#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
218#define LB 0x08000000 /* Internal Loopback Enable */
219#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
220
221/* EMAC_STAADD Masks */
222#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
223#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
224#define STADISPRE 0x00000004 /* Disable Preamble Generation */
225#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
226#define REGAD 0x000007C0 /* STA Register Address */
227#define PHYAD 0x0000F800 /* PHY Device Address */
228
229#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
230#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
231
232/* EMAC_STADAT Mask */
233#define STADATA 0x0000FFFF /* Station Management Data */
234
235/* EMAC_FLC Masks */
236#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
237#define FLCE 0x00000002 /* Flow Control Enable */
238#define PCF 0x00000004 /* Pass Control Frames */
239#define BKPRSEN 0x00000008 /* Enable Backpressure */
240#define FLCPAUSE 0xFFFF0000 /* Pause Time */
241
242#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
243
244/* EMAC_WKUP_CTL Masks */
245#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
246#define MPKE 0x00000002 /* Magic Packet Enable */
247#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
248#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
249#define MPKS 0x00000020 /* Magic Packet Received Status */
250#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
251
252/* EMAC_WKUP_FFCMD Masks */
253#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
254#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
255#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
256#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
257#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
258#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
259#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
260#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
261
262/* EMAC_WKUP_FFOFF Masks */
263#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
264#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
265#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
266#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
267
268#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
269#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
270#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
271#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
272/* Set ALL Offsets */
273#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
274
275/* EMAC_WKUP_FFCRC0 Masks */
276#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
277#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
278
279#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
280#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
281
282/* EMAC_WKUP_FFCRC1 Masks */
283#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
284#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
285
286#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
287#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
288
289/* EMAC_SYSCTL Masks */
290#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
291#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
292#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
293#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
294
295#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
296
297/* EMAC_SYSTAT Masks */
298#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
299#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
300#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
301#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
302#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
303#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
304#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
305#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
306
307/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
308#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
309#define RX_COMP 0x00001000 /* RX Frame Complete */
310#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
311#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
312#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
313#define RX_CRC 0x00010000 /* RX Frame CRC Error */
314#define RX_LEN 0x00020000 /* RX Frame Length Error */
315#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
316#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
317#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
318#define RX_PHY 0x00200000 /* RX Frame PHY Error */
319#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
320#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
321#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
322#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
323#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
324#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
325#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
326#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
327#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
328#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
329
330/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
331#define TX_COMP 0x00000001 /* TX Frame Complete */
332#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
333#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
334#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
335#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
336#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
337#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
338#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
339#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
340#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
341#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
342#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
343#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
344#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
345#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
346
347/* EMAC_MMC_CTL Masks */
348#define RSTC 0x00000001 /* Reset All Counters */
349#define CROLL 0x00000002 /* Counter Roll-Over Enable */
350#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
351#define MMCE 0x00000008 /* Enable MMC Counter Operation */
352
353/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
354#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
355#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
356#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
357#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
358#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
359#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
360#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
361#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
362#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
363#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
364#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
365#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
366#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
367#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
368#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
369#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
370#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
371#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
372#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
373#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
374#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
375#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
376#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
377#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
378
379/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
380#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
381#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
382#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
383#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
384#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
385#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
386#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
387#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
388#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
389#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
390#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
391#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
392#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
393#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
394#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
395#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
396#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
397#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
398#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
399#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
400#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
401#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
402#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
403
404#endif /* _DEF_BF537_H */
diff --git a/include/asm-blackfin/mach-bf537/dma.h b/include/asm-blackfin/mach-bf537/dma.h
new file mode 100644
index 000000000000..7a964040870a
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/dma.h
@@ -0,0 +1,55 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/dma.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _MACH_DMA_H_
33#define _MACH_DMA_H_
34
35#define MAX_BLACKFIN_DMA_CHANNEL 16
36
37#define CH_PPI 0
38#define CH_EMAC_RX 1
39#define CH_EMAC_TX 2
40#define CH_SPORT0_RX 3
41#define CH_SPORT0_TX 4
42#define CH_SPORT1_RX 5
43#define CH_SPORT1_TX 6
44#define CH_SPI 7
45#define CH_UART0_RX 8
46#define CH_UART0_TX 9
47#define CH_UART1_RX 10
48#define CH_UART1_TX 11
49
50#define CH_MEM_STREAM0_DEST 12 /* TX */
51#define CH_MEM_STREAM0_SRC 13 /* RX */
52#define CH_MEM_STREAM1_DEST 14 /* TX */
53#define CH_MEM_STREAM1_SRC 15 /* RX */
54
55#endif
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
new file mode 100644
index 000000000000..8af2a832ef6b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -0,0 +1,219 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/irq.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _BF537_IRQ_H_
33#define _BF537_IRQ_H_
34
35/*
36 * Interrupt source definitions
37 Event Source Core Event Name
38Core Emulation **
39 Events (highest priority) EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47.....
48
49 Software Interrupt 1 IVG14 31
50 Software Interrupt 2 --
51 (lowest priority) IVG15 32 *
52 */
53
54#define SYS_IRQS 41
55#define NR_PERI_INTS 32
56
57/* The ABSTRACT IRQ definitions */
58/** the first seven of the following are fixed, the rest you change if you need to **/
59#define IRQ_EMU 0 /*Emulation */
60#define IRQ_RST 1 /*reset */
61#define IRQ_NMI 2 /*Non Maskable */
62#define IRQ_EVX 3 /*Exception */
63#define IRQ_UNUSED 4 /*- unused interrupt*/
64#define IRQ_HWERR 5 /*Hardware Error */
65#define IRQ_CORETMR 6 /*Core timer */
66
67#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
68#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
69#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */
70#define IRQ_RTC 10 /*RTC Interrupt */
71#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */
72#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */
73#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */
74#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */
75#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */
76#define IRQ_TWI 16 /*TWI Interrupt */
77#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */
78#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */
79#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */
80#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */
81#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */
82#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */
83#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */
84#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */
85#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */
86#define IRQ_TMR0 26 /*Timer 0 */
87#define IRQ_TMR1 27 /*Timer 1 */
88#define IRQ_TMR2 28 /*Timer 2 */
89#define IRQ_TMR3 29 /*Timer 3 */
90#define IRQ_TMR4 30 /*Timer 4 */
91#define IRQ_TMR5 31 /*Timer 5 */
92#define IRQ_TMR6 32 /*Timer 6 */
93#define IRQ_TMR7 33 /*Timer 7 */
94#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
95#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
96#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
97#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
98#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
99#define IRQ_WATCH 38 /*Watch Dog Timer */
100#define IRQ_SW_INT1 40 /*Software Int 1 */
101#define IRQ_SW_INT2 41 /*Software Int 2 (reserved for SYSCALL) */
102
103#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
104#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
105#define IRQ_MAC_ERROR 44 /*PPI Error Interrupt */
106#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */
107#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */
108#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */
109#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */
110#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */
111
112#define IRQ_PF0 50
113#define IRQ_PF1 51
114#define IRQ_PF2 52
115#define IRQ_PF3 53
116#define IRQ_PF4 54
117#define IRQ_PF5 55
118#define IRQ_PF6 56
119#define IRQ_PF7 57
120#define IRQ_PF8 58
121#define IRQ_PF9 59
122#define IRQ_PF10 60
123#define IRQ_PF11 61
124#define IRQ_PF12 62
125#define IRQ_PF13 63
126#define IRQ_PF14 64
127#define IRQ_PF15 65
128
129#define IRQ_PG0 66
130#define IRQ_PG1 67
131#define IRQ_PG2 68
132#define IRQ_PG3 69
133#define IRQ_PG4 70
134#define IRQ_PG5 71
135#define IRQ_PG6 72
136#define IRQ_PG7 73
137#define IRQ_PG8 74
138#define IRQ_PG9 75
139#define IRQ_PG10 76
140#define IRQ_PG11 77
141#define IRQ_PG12 78
142#define IRQ_PG13 79
143#define IRQ_PG14 80
144#define IRQ_PG15 81
145
146#define IRQ_PH0 82
147#define IRQ_PH1 83
148#define IRQ_PH2 84
149#define IRQ_PH3 85
150#define IRQ_PH4 86
151#define IRQ_PH5 87
152#define IRQ_PH6 88
153#define IRQ_PH7 89
154#define IRQ_PH8 90
155#define IRQ_PH9 91
156#define IRQ_PH10 92
157#define IRQ_PH11 93
158#define IRQ_PH12 94
159#define IRQ_PH13 95
160#define IRQ_PH14 96
161#define IRQ_PH15 97
162
163#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
164#define NR_IRQS (IRQ_PH15+1)
165#else
166#define NR_IRQS (IRQ_UART1_ERROR+1)
167#endif
168
169#define IVG7 7
170#define IVG8 8
171#define IVG9 9
172#define IVG10 10
173#define IVG11 11
174#define IVG12 12
175#define IVG13 13
176#define IVG14 14
177#define IVG15 15
178
179/* IAR0 BIT FIELDS*/
180#define IRQ_PLL_WAKEUP_POS 0
181#define IRQ_DMA_ERROR_POS 4
182#define IRQ_ERROR_POS 8
183#define IRQ_RTC_POS 12
184#define IRQ_PPI_POS 16
185#define IRQ_SPORT0_RX_POS 20
186#define IRQ_SPORT0_TX_POS 24
187#define IRQ_SPORT1_RX_POS 28
188
189/* IAR1 BIT FIELDS*/
190#define IRQ_SPORT1_TX_POS 0
191#define IRQ_TWI_POS 4
192#define IRQ_SPI_POS 8
193#define IRQ_UART0_RX_POS 12
194#define IRQ_UART0_TX_POS 16
195#define IRQ_UART1_RX_POS 20
196#define IRQ_UART1_TX_POS 24
197#define IRQ_CAN_RX_POS 28
198
199/* IAR2 BIT FIELDS*/
200#define IRQ_CAN_TX_POS 0
201#define IRQ_MAC_RX_POS 4
202#define IRQ_MAC_TX_POS 8
203#define IRQ_TMR0_POS 12
204#define IRQ_TMR1_POS 16
205#define IRQ_TMR2_POS 20
206#define IRQ_TMR3_POS 24
207#define IRQ_TMR4_POS 28
208
209/* IAR3 BIT FIELDS*/
210#define IRQ_TMR5_POS 0
211#define IRQ_TMR6_POS 4
212#define IRQ_TMR7_POS 8
213#define IRQ_PROG_INTA_POS 12
214#define IRQ_PORTG_INTB_POS 16
215#define IRQ_MEM_DMA0_POS 20
216#define IRQ_MEM_DMA1_POS 24
217#define IRQ_WATCH_POS 28
218
219#endif /* _BF537_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf537/mem_init.h b/include/asm-blackfin/mach-bf537/mem_init.h
new file mode 100644
index 000000000000..9ad979d416c6
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/mem_init.h
@@ -0,0 +1,330 @@
1/*
2 * File: include/asm-blackfin/mach-bf537/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75)
33#if (CONFIG_SCLK_HZ > 119402985)
34#define SDRAM_tRP TRP_2
35#define SDRAM_tRP_num 2
36#define SDRAM_tRAS TRAS_7
37#define SDRAM_tRAS_num 7
38#define SDRAM_tRCD TRCD_2
39#define SDRAM_tWR TWR_2
40#endif
41#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
42#define SDRAM_tRP TRP_2
43#define SDRAM_tRP_num 2
44#define SDRAM_tRAS TRAS_6
45#define SDRAM_tRAS_num 6
46#define SDRAM_tRCD TRCD_2
47#define SDRAM_tWR TWR_2
48#endif
49#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
50#define SDRAM_tRP TRP_2
51#define SDRAM_tRP_num 2
52#define SDRAM_tRAS TRAS_5
53#define SDRAM_tRAS_num 5
54#define SDRAM_tRCD TRCD_2
55#define SDRAM_tWR TWR_2
56#endif
57#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
58#define SDRAM_tRP TRP_2
59#define SDRAM_tRP_num 2
60#define SDRAM_tRAS TRAS_4
61#define SDRAM_tRAS_num 4
62#define SDRAM_tRCD TRCD_2
63#define SDRAM_tWR TWR_2
64#endif
65#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
66#define SDRAM_tRP TRP_2
67#define SDRAM_tRP_num 2
68#define SDRAM_tRAS TRAS_3
69#define SDRAM_tRAS_num 3
70#define SDRAM_tRCD TRCD_2
71#define SDRAM_tWR TWR_2
72#endif
73#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
74#define SDRAM_tRP TRP_1
75#define SDRAM_tRP_num 1
76#define SDRAM_tRAS TRAS_4
77#define SDRAM_tRAS_num 3
78#define SDRAM_tRCD TRCD_1
79#define SDRAM_tWR TWR_2
80#endif
81#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
82#define SDRAM_tRP TRP_1
83#define SDRAM_tRP_num 1
84#define SDRAM_tRAS TRAS_3
85#define SDRAM_tRAS_num 3
86#define SDRAM_tRCD TRCD_1
87#define SDRAM_tWR TWR_2
88#endif
89#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
90#define SDRAM_tRP TRP_1
91#define SDRAM_tRP_num 1
92#define SDRAM_tRAS TRAS_2
93#define SDRAM_tRAS_num 2
94#define SDRAM_tRCD TRCD_1
95#define SDRAM_tWR TWR_2
96#endif
97#if (CONFIG_SCLK_HZ <= 29850746)
98#define SDRAM_tRP TRP_1
99#define SDRAM_tRP_num 1
100#define SDRAM_tRAS TRAS_1
101#define SDRAM_tRAS_num 1
102#define SDRAM_tRCD TRCD_1
103#define SDRAM_tWR TWR_2
104#endif
105#endif
106
107#if (CONFIG_MEM_MT48LC16M16A2TG_75)
108 /*SDRAM INFORMATION: */
109#define SDRAM_Tref 64 /* Refresh period in milliseconds */
110#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
111#define SDRAM_CL CL_3
112#endif
113
114#if (CONFIG_MEM_MT48LC16M8A2TG_75)
115 /*SDRAM INFORMATION: */
116#define SDRAM_Tref 64 /* Refresh period in milliseconds */
117#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
118#define SDRAM_CL CL_3
119#endif
120
121#if (CONFIG_MEM_MT48LC32M8A2_75)
122 /*SDRAM INFORMATION: */
123#define SDRAM_Tref 64 /* Refresh period in milliseconds */
124#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
125#define SDRAM_CL CL_3
126#endif
127
128#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
129 /*SDRAM INFORMATION: */
130#define SDRAM_Tref 64 /* Refresh period in milliseconds */
131#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
132#define SDRAM_CL CL_3
133#endif
134
135#if (CONFIG_MEM_GENERIC_BOARD)
136 /*SDRAM INFORMATION: Modify this for your board */
137#define SDRAM_Tref 64 /* Refresh period in milliseconds */
138#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
139#define SDRAM_CL CL_3
140#endif
141
142#if (CONFIG_MEM_SIZE == 128)
143#define SDRAM_SIZE EBSZ_128
144#endif
145#if (CONFIG_MEM_SIZE == 64)
146#define SDRAM_SIZE EBSZ_64
147#endif
148#if (CONFIG_MEM_SIZE == 32)
149#define SDRAM_SIZE EBSZ_32
150#endif
151#if (CONFIG_MEM_SIZE == 16)
152#define SDRAM_SIZE EBSZ_16
153#endif
154#if (CONFIG_MEM_ADD_WIDTH == 11)
155#define SDRAM_WIDTH EBCAW_11
156#endif
157#if (CONFIG_MEM_ADD_WIDTH == 10)
158#define SDRAM_WIDTH EBCAW_10
159#endif
160#if (CONFIG_MEM_ADD_WIDTH == 9)
161#define SDRAM_WIDTH EBCAW_9
162#endif
163#if (CONFIG_MEM_ADD_WIDTH == 8)
164#define SDRAM_WIDTH EBCAW_8
165#endif
166
167#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
168
169/* Equation from section 17 (p17-46) of BF533 HRM */
170#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
171
172/* Enable SCLK Out */
173#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
174
175#if defined CONFIG_CLKIN_HALF
176#define CLKIN_HALF 1
177#else
178#define CLKIN_HALF 0
179#endif
180
181#if defined CONFIG_PLL_BYPASS
182#define PLL_BYPASS 1
183#else
184#define PLL_BYPASS 0
185#endif
186
187/***************************************Currently Not Being Used *********************************/
188#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
189#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
190#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
191#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
192#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
193
194#if (flash_EBIU_AMBCTL_TT > 3)
195#define flash_EBIU_AMBCTL0_TT B0TT_4
196#endif
197#if (flash_EBIU_AMBCTL_TT == 3)
198#define flash_EBIU_AMBCTL0_TT B0TT_3
199#endif
200#if (flash_EBIU_AMBCTL_TT == 2)
201#define flash_EBIU_AMBCTL0_TT B0TT_2
202#endif
203#if (flash_EBIU_AMBCTL_TT < 2)
204#define flash_EBIU_AMBCTL0_TT B0TT_1
205#endif
206
207#if (flash_EBIU_AMBCTL_ST > 3)
208#define flash_EBIU_AMBCTL0_ST B0ST_4
209#endif
210#if (flash_EBIU_AMBCTL_ST == 3)
211#define flash_EBIU_AMBCTL0_ST B0ST_3
212#endif
213#if (flash_EBIU_AMBCTL_ST == 2)
214#define flash_EBIU_AMBCTL0_ST B0ST_2
215#endif
216#if (flash_EBIU_AMBCTL_ST < 2)
217#define flash_EBIU_AMBCTL0_ST B0ST_1
218#endif
219
220#if (flash_EBIU_AMBCTL_HT > 2)
221#define flash_EBIU_AMBCTL0_HT B0HT_3
222#endif
223#if (flash_EBIU_AMBCTL_HT == 2)
224#define flash_EBIU_AMBCTL0_HT B0HT_2
225#endif
226#if (flash_EBIU_AMBCTL_HT == 1)
227#define flash_EBIU_AMBCTL0_HT B0HT_1
228#endif
229#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
230#define flash_EBIU_AMBCTL0_HT B0HT_0
231#endif
232#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
233#define flash_EBIU_AMBCTL0_HT B0HT_1
234#endif
235
236#if (flash_EBIU_AMBCTL_WAT > 14)
237#define flash_EBIU_AMBCTL0_WAT B0WAT_15
238#endif
239#if (flash_EBIU_AMBCTL_WAT == 14)
240#define flash_EBIU_AMBCTL0_WAT B0WAT_14
241#endif
242#if (flash_EBIU_AMBCTL_WAT == 13)
243#define flash_EBIU_AMBCTL0_WAT B0WAT_13
244#endif
245#if (flash_EBIU_AMBCTL_WAT == 12)
246#define flash_EBIU_AMBCTL0_WAT B0WAT_12
247#endif
248#if (flash_EBIU_AMBCTL_WAT == 11)
249#define flash_EBIU_AMBCTL0_WAT B0WAT_11
250#endif
251#if (flash_EBIU_AMBCTL_WAT == 10)
252#define flash_EBIU_AMBCTL0_WAT B0WAT_10
253#endif
254#if (flash_EBIU_AMBCTL_WAT == 9)
255#define flash_EBIU_AMBCTL0_WAT B0WAT_9
256#endif
257#if (flash_EBIU_AMBCTL_WAT == 8)
258#define flash_EBIU_AMBCTL0_WAT B0WAT_8
259#endif
260#if (flash_EBIU_AMBCTL_WAT == 7)
261#define flash_EBIU_AMBCTL0_WAT B0WAT_7
262#endif
263#if (flash_EBIU_AMBCTL_WAT == 6)
264#define flash_EBIU_AMBCTL0_WAT B0WAT_6
265#endif
266#if (flash_EBIU_AMBCTL_WAT == 5)
267#define flash_EBIU_AMBCTL0_WAT B0WAT_5
268#endif
269#if (flash_EBIU_AMBCTL_WAT == 4)
270#define flash_EBIU_AMBCTL0_WAT B0WAT_4
271#endif
272#if (flash_EBIU_AMBCTL_WAT == 3)
273#define flash_EBIU_AMBCTL0_WAT B0WAT_3
274#endif
275#if (flash_EBIU_AMBCTL_WAT == 2)
276#define flash_EBIU_AMBCTL0_WAT B0WAT_2
277#endif
278#if (flash_EBIU_AMBCTL_WAT == 1)
279#define flash_EBIU_AMBCTL0_WAT B0WAT_1
280#endif
281
282#if (flash_EBIU_AMBCTL_RAT > 14)
283#define flash_EBIU_AMBCTL0_RAT B0RAT_15
284#endif
285#if (flash_EBIU_AMBCTL_RAT == 14)
286#define flash_EBIU_AMBCTL0_RAT B0RAT_14
287#endif
288#if (flash_EBIU_AMBCTL_RAT == 13)
289#define flash_EBIU_AMBCTL0_RAT B0RAT_13
290#endif
291#if (flash_EBIU_AMBCTL_RAT == 12)
292#define flash_EBIU_AMBCTL0_RAT B0RAT_12
293#endif
294#if (flash_EBIU_AMBCTL_RAT == 11)
295#define flash_EBIU_AMBCTL0_RAT B0RAT_11
296#endif
297#if (flash_EBIU_AMBCTL_RAT == 10)
298#define flash_EBIU_AMBCTL0_RAT B0RAT_10
299#endif
300#if (flash_EBIU_AMBCTL_RAT == 9)
301#define flash_EBIU_AMBCTL0_RAT B0RAT_9
302#endif
303#if (flash_EBIU_AMBCTL_RAT == 8)
304#define flash_EBIU_AMBCTL0_RAT B0RAT_8
305#endif
306#if (flash_EBIU_AMBCTL_RAT == 7)
307#define flash_EBIU_AMBCTL0_RAT B0RAT_7
308#endif
309#if (flash_EBIU_AMBCTL_RAT == 6)
310#define flash_EBIU_AMBCTL0_RAT B0RAT_6
311#endif
312#if (flash_EBIU_AMBCTL_RAT == 5)
313#define flash_EBIU_AMBCTL0_RAT B0RAT_5
314#endif
315#if (flash_EBIU_AMBCTL_RAT == 4)
316#define flash_EBIU_AMBCTL0_RAT B0RAT_4
317#endif
318#if (flash_EBIU_AMBCTL_RAT == 3)
319#define flash_EBIU_AMBCTL0_RAT B0RAT_3
320#endif
321#if (flash_EBIU_AMBCTL_RAT == 2)
322#define flash_EBIU_AMBCTL0_RAT B0RAT_2
323#endif
324#if (flash_EBIU_AMBCTL_RAT == 1)
325#define flash_EBIU_AMBCTL0_RAT B0RAT_1
326#endif
327
328#define flash_EBIU_AMBCTL0 \
329 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
330 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h
new file mode 100644
index 000000000000..2a808c1202bf
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/mem_map.h
@@ -0,0 +1,175 @@
1/*
2 * file: include/asm-blackfin/mach-bf537/mem_map.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * Memory MAP Common header file for blackfin BF537/6/4 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */
30
31#ifndef _MEM_MAP_537_H_
32#define _MEM_MAP_537_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
40#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
42#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50
51/* Level 1 Memory */
52
53/* Memory Map for ADSP-BF537 processors */
54
55#ifdef CONFIG_BLKFIN_CACHE
56#define BLKFIN_ICACHESIZE (16*1024)
57#else
58#define BLKFIN_ICACHESIZE (0*1024)
59#endif
60
61
62#ifdef CONFIG_BF537
63#define L1_CODE_START 0xFFA00000
64#define L1_DATA_A_START 0xFF800000
65#define L1_DATA_B_START 0xFF900000
66
67#define L1_CODE_LENGTH 0xC000
68
69#ifdef CONFIG_BLKFIN_DCACHE
70
71#ifdef CONFIG_BLKFIN_DCACHE_BANKA
72#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
73#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
74#define L1_DATA_B_LENGTH 0x8000
75#define BLKFIN_DCACHESIZE (16*1024)
76#define BLKFIN_DSUPBANKS 1
77#else
78#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
79#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
80#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
81#define BLKFIN_DCACHESIZE (32*1024)
82#define BLKFIN_DSUPBANKS 2
83#endif
84
85#else
86#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
87#define L1_DATA_A_LENGTH 0x8000
88#define L1_DATA_B_LENGTH 0x8000
89#define BLKFIN_DCACHESIZE (0*1024)
90#define BLKFIN_DSUPBANKS 0
91#endif /*CONFIG_BLKFIN_DCACHE*/
92
93#endif /*CONFIG_BF537*/
94
95/* Memory Map for ADSP-BF536 processors */
96
97#ifdef CONFIG_BF536
98#define L1_CODE_START 0xFFA00000
99#define L1_DATA_A_START 0xFF804000
100#define L1_DATA_B_START 0xFF904000
101
102#define L1_CODE_LENGTH 0xC000
103
104
105#ifdef CONFIG_BLKFIN_DCACHE
106
107#ifdef CONFIG_BLKFIN_DCACHE_BANKA
108#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
109#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
110#define L1_DATA_B_LENGTH 0x4000
111#define BLKFIN_DCACHESIZE (16*1024)
112#define BLKFIN_DSUPBANKS 1
113
114#else
115#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
116#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
117#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
118#define BLKFIN_DCACHESIZE (32*1024)
119#define BLKFIN_DSUPBANKS 2
120#endif
121
122#else
123#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
124#define L1_DATA_A_LENGTH 0x4000
125#define L1_DATA_B_LENGTH 0x4000
126#define BLKFIN_DCACHESIZE (0*1024)
127#define BLKFIN_DSUPBANKS 0
128#endif /*CONFIG_BLKFIN_DCACHE*/
129
130#endif
131
132/* Memory Map for ADSP-BF534 processors */
133
134#ifdef CONFIG_BF534
135#define L1_CODE_START 0xFFA00000
136#define L1_DATA_A_START 0xFF800000
137#define L1_DATA_B_START 0xFF900000
138
139#define L1_CODE_LENGTH 0xC000
140
141#ifdef CONFIG_BLKFIN_DCACHE
142
143#ifdef CONFIG_BLKFIN_DCACHE_BANKA
144#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
145#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
146#define L1_DATA_B_LENGTH 0x8000
147#define BLKFIN_DCACHESIZE (16*1024)
148#define BLKFIN_DSUPBANKS 1
149
150#else
151#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
152#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
153#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
154#define BLKFIN_DCACHESIZE (32*1024)
155#define BLKFIN_DSUPBANKS 2
156#endif
157
158#else
159#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
160#define L1_DATA_A_LENGTH 0x8000
161#define L1_DATA_B_LENGTH 0x8000
162#define BLKFIN_DCACHESIZE (0*1024)
163#define BLKFIN_DSUPBANKS 0
164#endif /*CONFIG_BLKFIN_DCACHE*/
165
166#endif
167
168/* Scratch Pad Memory */
169
170#if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
171#define L1_SCRATCH_START 0xFFB00000
172#define L1_SCRATCH_LENGTH 0x1000
173#endif
174
175#endif /* _MEM_MAP_537_H_ */
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
new file mode 100644
index 000000000000..f5b32d66517d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -0,0 +1,184 @@
1
2/*
3 * File: include/asm-blackfin/mach-bf561/anomaly.h
4 * Based on:
5 * Author:
6 *
7 * Created:
8 * Description:
9 *
10 * Rev:
11 *
12 * Modified:
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32/* This file shoule be up to date with:
33 * - Revision L, 10Aug2006; ADSP-BF561 Silicon Anomaly List
34 */
35
36#ifndef _MACH_ANOMALY_H_
37#define _MACH_ANOMALY_H_
38
39/* We do not support 0.1 or 0.4 silicon - sorry */
40#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || defined(CONFIG_BF_REV_0_4))
41#error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4
42#endif
43
44/* Issues that are common to 0.5 and 0.3 silicon */
45#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3))
46#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
47 slot1 and store of a P register in slot 2 is not
48 supported */
49#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
50 updated at the same time. */
51#define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned
52 memory locations */
53#define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR
54 registers */
55#define ANOMALY_05000127 /* Signbits instruction not functional under certain
56 conditions */
57#define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */
58#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
59 upper bits */
60#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
61#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
62 syncs */
63#define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz
64 and higher devices */
65#define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */
66#define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */
67#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
68 functional */
69#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
70 shadow of a conditional branch */
71#define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop
72 may cause bad instruction fetches */
73#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
74 external SPORT TX and RX clocks */
75#define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */
76#define ANOMALY_05000269 /* High I/O activity causes output voltage of internal
77 voltage regulator (VDDint) to increase */
78#define ANOMALY_05000270 /* High I/O activity causes output voltage of internal
79 voltage regulator (VDDint) to decrease */
80#define ANOMALY_05000272 /* Certain data cache write through modes fail for
81 VDDint <=0.9V */
82#define ANOMALY_05000274 /* Data cache write back to external synchronous memory
83 may be lost */
84#define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */
85#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
86 registers are interrupted */
87
88#endif /* (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */
89
90#if (defined(CONFIG_BF_REV_0_5))
91#define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT
92 mode with external clock */
93#define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to
94 using IMDMA */
95#endif
96
97#if (defined(CONFIG_BF_REV_0_3))
98#define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input)
99 Mode with 0 Frame Syncs */
100#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
101#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through
102 cache data writes */
103#define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */
104#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
105#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
106#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
107 accumulator saturation */
108#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
109 Purpose TX or RX modes */
110#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
111 registers */
112#define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with
113 External Frame Syncs */
114#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
115#define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits
116 (not a meaningful mode) */
117#define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer
118 Placement in Memory */
119#define ANOMALY_05000189 /* False Protection Exception */
120#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
121 when polarity setting is changed */
122#define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data
123 corruption */
124#define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding
125 memory read */
126#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
127 fix */
128#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
129 inactive channels in certain conditions */
130#define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG
131 situation */
132#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
133 allocate cache lines on reads only mode */
134#define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA
135 stopping */
136#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
137#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
138 instructions */
139#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
140#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
141 state */
142#define ANOMALY_05000220 /* Data Corruption with Cached External Memory and
143 Non-Cached On-Chip L2 Memory */
144#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
145#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
146 data */
147#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
148 Differences in certain Conditions */
149#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
150#define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in
151 multichannel mode */
152#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
153 hardware reset */
154#define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of
155 Control causes failures */
156#define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */
157#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
158 (TDM) mode in certain conditions */
159#define ANOMALY_05000251 /* Exception not generated for MMR accesses in
160 reserved region */
161#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
162#define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12
163 of the ICPLB Data registers differ */
164#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
165#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
166#define ANOMALY_05000262 /* Stores to data cache may be lost */
167#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB
168 exception */
169#define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second
170 to last instruction in hardware loop */
171#define ANOMALY_05000276 /* Timing requirements change for External Frame
172 Sync PPI Modes with non-zero PPI_DELAY */
173#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
174 DMA system instability */
175#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
176 not restored */
177#define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed
178 in a particular stage */
179#define ANOMALY_05000287 /* A read will receive incorrect data under certain
180 conditions */
181#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
182#endif
183
184#endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
new file mode 100644
index 000000000000..96a5d3a47e45
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/bf561.h
@@ -0,0 +1,408 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/bf561.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF561_H__
31#define __MACH_BF561_H__
32
33#define SUPPORTED_REVID 0x3
34
35#define OFFSET_(x) ((x) & 0x0000FFFF)
36#define L1_ISRAM 0xFFA00000
37#define L1_ISRAM_END 0xFFA04000
38#define DATA_BANKA_SRAM 0xFF800000
39#define DATA_BANKA_SRAM_END 0xFF804000
40#define DATA_BANKB_SRAM 0xFF900000
41#define DATA_BANKB_SRAM_END 0xFF904000
42#define L1_DSRAMA 0xFF800000
43#define L1_DSRAMA_END 0xFF804000
44#define L1_DSRAMB 0xFF900000
45#define L1_DSRAMB_END 0xFF904000
46#define L2_SRAM 0xFEB00000
47#define L2_SRAM_END 0xFEB20000
48#define AMB_FLASH 0x20000000
49#define AMB_FLASH_END 0x21000000
50#define AMB_FLASH_LENGTH 0x01000000
51#define L1_ISRAM_LENGTH 0x4000
52#define L1_DSRAMA_LENGTH 0x4000
53#define L1_DSRAMB_LENGTH 0x4000
54#define L2_SRAM_LENGTH 0x20000
55
56/*some misc defines*/
57#define IMASK_IVG15 0x8000
58#define IMASK_IVG14 0x4000
59#define IMASK_IVG13 0x2000
60#define IMASK_IVG12 0x1000
61
62#define IMASK_IVG11 0x0800
63#define IMASK_IVG10 0x0400
64#define IMASK_IVG9 0x0200
65#define IMASK_IVG8 0x0100
66
67#define IMASK_IVG7 0x0080
68#define IMASK_IVGTMR 0x0040
69#define IMASK_IVGHW 0x0020
70
71/***************************
72 * Blackfin Cache setup
73 */
74
75
76#define BLKFIN_ISUBBANKS 4
77#define BLKFIN_IWAYS 4
78#define BLKFIN_ILINES 32
79
80#define BLKFIN_DSUBBANKS 4
81#define BLKFIN_DWAYS 2
82#define BLKFIN_DLINES 64
83
84#define WAY0_L 0x1
85#define WAY1_L 0x2
86#define WAY01_L 0x3
87#define WAY2_L 0x4
88#define WAY02_L 0x5
89#define WAY12_L 0x6
90#define WAY012_L 0x7
91
92#define WAY3_L 0x8
93#define WAY03_L 0x9
94#define WAY13_L 0xA
95#define WAY013_L 0xB
96
97#define WAY32_L 0xC
98#define WAY320_L 0xD
99#define WAY321_L 0xE
100#define WAYALL_L 0xF
101
102#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
103
104/* IAR0 BIT FIELDS */
105#define PLL_WAKEUP_BIT 0xFFFFFFFF
106#define DMA1_ERROR_BIT 0xFFFFFF0F
107#define DMA2_ERROR_BIT 0xFFFFF0FF
108#define IMDMA_ERROR_BIT 0xFFFF0FFF
109#define PPI1_ERROR_BIT 0xFFF0FFFF
110#define PPI2_ERROR_BIT 0xFF0FFFFF
111#define SPORT0_ERROR_BIT 0xF0FFFFFF
112#define SPORT1_ERROR_BIT 0x0FFFFFFF
113/* IAR1 BIT FIELDS */
114#define SPI_ERROR_BIT 0xFFFFFFFF
115#define UART_ERROR_BIT 0xFFFFFF0F
116#define RESERVED_ERROR_BIT 0xFFFFF0FF
117#define DMA1_0_BIT 0xFFFF0FFF
118#define DMA1_1_BIT 0xFFF0FFFF
119#define DMA1_2_BIT 0xFF0FFFFF
120#define DMA1_3_BIT 0xF0FFFFFF
121#define DMA1_4_BIT 0x0FFFFFFF
122/* IAR2 BIT FIELDS */
123#define DMA1_5_BIT 0xFFFFFFFF
124#define DMA1_6_BIT 0xFFFFFF0F
125#define DMA1_7_BIT 0xFFFFF0FF
126#define DMA1_8_BIT 0xFFFF0FFF
127#define DMA1_9_BIT 0xFFF0FFFF
128#define DMA1_10_BIT 0xFF0FFFFF
129#define DMA1_11_BIT 0xF0FFFFFF
130#define DMA2_0_BIT 0x0FFFFFFF
131/* IAR3 BIT FIELDS */
132#define DMA2_1_BIT 0xFFFFFFFF
133#define DMA2_2_BIT 0xFFFFFF0F
134#define DMA2_3_BIT 0xFFFFF0FF
135#define DMA2_4_BIT 0xFFFF0FFF
136#define DMA2_5_BIT 0xFFF0FFFF
137#define DMA2_6_BIT 0xFF0FFFFF
138#define DMA2_7_BIT 0xF0FFFFFF
139#define DMA2_8_BIT 0x0FFFFFFF
140/* IAR4 BIT FIELDS */
141#define DMA2_9_BIT 0xFFFFFFFF
142#define DMA2_10_BIT 0xFFFFFF0F
143#define DMA2_11_BIT 0xFFFFF0FF
144#define TIMER0_BIT 0xFFFF0FFF
145#define TIMER1_BIT 0xFFF0FFFF
146#define TIMER2_BIT 0xFF0FFFFF
147#define TIMER3_BIT 0xF0FFFFFF
148#define TIMER4_BIT 0x0FFFFFFF
149/* IAR5 BIT FIELDS */
150#define TIMER5_BIT 0xFFFFFFFF
151#define TIMER6_BIT 0xFFFFFF0F
152#define TIMER7_BIT 0xFFFFF0FF
153#define TIMER8_BIT 0xFFFF0FFF
154#define TIMER9_BIT 0xFFF0FFFF
155#define TIMER10_BIT 0xFF0FFFFF
156#define TIMER11_BIT 0xF0FFFFFF
157#define PROG0_INTA_BIT 0x0FFFFFFF
158/* IAR6 BIT FIELDS */
159#define PROG0_INTB_BIT 0xFFFFFFFF
160#define PROG1_INTA_BIT 0xFFFFFF0F
161#define PROG1_INTB_BIT 0xFFFFF0FF
162#define PROG2_INTA_BIT 0xFFFF0FFF
163#define PROG2_INTB_BIT 0xFFF0FFFF
164#define DMA1_WRRD0_BIT 0xFF0FFFFF
165#define DMA1_WRRD1_BIT 0xF0FFFFFF
166#define DMA2_WRRD0_BIT 0x0FFFFFFF
167/* IAR7 BIT FIELDS */
168#define DMA2_WRRD1_BIT 0xFFFFFFFF
169#define IMDMA_WRRD0_BIT 0xFFFFFF0F
170#define IMDMA_WRRD1_BIT 0xFFFFF0FF
171#define WATCH_BIT 0xFFFF0FFF
172#define RESERVED_1_BIT 0xFFF0FFFF
173#define RESERVED_2_BIT 0xFF0FFFFF
174#define SUPPLE_0_BIT 0xF0FFFFFF
175#define SUPPLE_1_BIT 0x0FFFFFFF
176
177/* Miscellaneous Values */
178
179/****************************** EBIU Settings ********************************/
180#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
181#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
182
183#if defined(CONFIG_C_AMBEN_ALL)
184#define V_AMBEN AMBEN_ALL
185#elif defined(CONFIG_C_AMBEN)
186#define V_AMBEN 0x0
187#elif defined(CONFIG_C_AMBEN_B0)
188#define V_AMBEN AMBEN_B0
189#elif defined(CONFIG_C_AMBEN_B0_B1)
190#define V_AMBEN AMBEN_B0_B1
191#elif defined(CONFIG_C_AMBEN_B0_B1_B2)
192#define V_AMBEN AMBEN_B0_B1_B2
193#endif
194
195#ifdef CONFIG_C_AMCKEN
196#define V_AMCKEN AMCKEN
197#else
198#define V_AMCKEN 0x0
199#endif
200
201#ifdef CONFIG_C_B0PEN
202#define V_B0PEN 0x10
203#else
204#define V_B0PEN 0x00
205#endif
206
207#ifdef CONFIG_C_B1PEN
208#define V_B1PEN 0x20
209#else
210#define V_B1PEN 0x00
211#endif
212
213#ifdef CONFIG_C_B2PEN
214#define V_B2PEN 0x40
215#else
216#define V_B2PEN 0x00
217#endif
218
219#ifdef CONFIG_C_B3PEN
220#define V_B3PEN 0x80
221#else
222#define V_B3PEN 0x00
223#endif
224
225#ifdef CONFIG_C_CDPRIO
226#define V_CDPRIO 0x100
227#else
228#define V_CDPRIO 0x0
229#endif
230
231#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
232
233#define MAX_VC 600000000
234#define MIN_VC 50000000
235
236/******************************* PLL Settings ********************************/
237#ifdef CONFIG_BFIN_KERNEL_CLOCK
238#if (CONFIG_VCO_MULT < 0)
239#error "VCO Multiplier is less than 0. Please select a different value"
240#endif
241
242#if (CONFIG_VCO_MULT == 0)
243#error "VCO Multiplier should be greater than 0. Please select a different value"
244#endif
245
246#ifndef CONFIG_CLKIN_HALF
247#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
248#else
249#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
250#endif
251
252#ifndef CONFIG_PLL_BYPASS
253#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
254#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
255#else
256#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
257#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
258#endif
259
260#if (CONFIG_SCLK_DIV < 1)
261#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
262#endif
263
264#if (CONFIG_SCLK_DIV > 15)
265#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
266#endif
267
268#if (CONFIG_CCLK_DIV != 1)
269#if (CONFIG_CCLK_DIV != 2)
270#if (CONFIG_CCLK_DIV != 4)
271#if (CONFIG_CCLK_DIV != 8)
272#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
273#endif
274#endif
275#endif
276#endif
277
278#if (CONFIG_VCO_HZ > MAX_VC)
279#error "VCO selected is more than maximum value. Please change the VCO multipler"
280#endif
281
282#if (CONFIG_SCLK_HZ > 133000000)
283#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
284#endif
285
286#if (CONFIG_SCLK_HZ < 27000000)
287#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
288#endif
289
290#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
291#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
292#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
293#error "Please select sclk less than cclk"
294#endif
295#endif
296#endif
297
298#if (CONFIG_CCLK_DIV == 1)
299#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
300#endif
301#if (CONFIG_CCLK_DIV == 2)
302#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
303#endif
304#if (CONFIG_CCLK_DIV == 4)
305#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
306#endif
307#if (CONFIG_CCLK_DIV == 8)
308#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
309#endif
310#ifndef CONFIG_CCLK_ACT_DIV
311#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
312#endif
313
314#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1)
315#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
316#endif
317
318#endif /* CONFIG_BFIN_KERNEL_CLOCK */
319
320#ifdef CONFIG_BF561
321#define CPU "BF561"
322#define CPUID 0x027bb000
323#endif
324#ifndef CPU
325#define CPU "UNKNOWN"
326#define CPUID 0x0
327#endif
328
329#if (CONFIG_MEM_SIZE % 4)
330#error "SDRAM memory size must be a multiple of 4MB!"
331#endif
332#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
333#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
334#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
335#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
336
337/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
338
339#define ANOMALY_05000158_WORKAROUND 0x200
340#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
341#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
342 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
343#else /*Write Through */
344#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \
345 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
346#endif
347
348
349#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
350#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
351#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
352#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
353
354#define L2_MEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
355
356#define SIZE_1K 0x00000400 /* 1K */
357#define SIZE_4K 0x00001000 /* 4K */
358#define SIZE_1M 0x00100000 /* 1M */
359#define SIZE_4M 0x00400000 /* 4M */
360
361#define MAX_CPLBS (16 * 2)
362
363/*
364* Number of required data CPLB switchtable entries
365* MEMSIZE / 4 (we mostly install 4M page size CPLBs
366* approx 16 for smaller 1MB page size CPLBs for allignment purposes
367* 1 for L1 Data Memory
368* 1 for L2 Data Memory
369* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
370* 64 for ASYNC Memory
371*/
372
373
374#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 + 64) * 2)
375
376/*
377* Number of required instruction CPLB switchtable entries
378* MEMSIZE / 4 (we mostly install 4M page size CPLBs
379* approx 12 for smaller 1MB page size CPLBs for allignment purposes
380* 1 for L1 Instruction Memory
381* 1 for L2 Instruction Memory
382* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
383*/
384
385#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
386
387#if 0 /* comment by mhfan */
388/* Event Vector Table Address */
389#define EVT_EMULATION_ADDR 0xffe02000
390#define EVT_RESET_ADDR 0xffe02004
391#define EVT_NMI_ADDR 0xffe02008
392#define EVT_EXCEPTION_ADDR 0xffe0200c
393#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
394#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
395#define EVT_TIMER_ADDR 0xffe02018
396#define EVT_IVG7_ADDR 0xffe0201c
397#define EVT_IVG8_ADDR 0xffe02020
398#define EVT_IVG9_ADDR 0xffe02024
399#define EVT_IVG10_ADDR 0xffe02028
400#define EVT_IVG11_ADDR 0xffe0202c
401#define EVT_IVG12_ADDR 0xffe02030
402#define EVT_IVG13_ADDR 0xffe02034
403#define EVT_IVG14_ADDR 0xffe02038
404#define EVT_IVG15_ADDR 0xffe0203c
405#define EVT_OVERRIDE_ADDR 0xffe02100
406#endif /* comment by mhfan */
407
408#endif /* __MACH_BF561_H__ */
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
new file mode 100644
index 000000000000..23bf76aa3451
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -0,0 +1,108 @@
1#include <linux/serial.h>
2#include <asm/dma.h>
3
4#define NR_PORTS 1
5
6#define OFFSET_THR 0x00 /* Transmit Holding register */
7#define OFFSET_RBR 0x00 /* Receive Buffer register */
8#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
9#define OFFSET_IER 0x04 /* Interrupt Enable Register */
10#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
11#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
12#define OFFSET_LCR 0x0C /* Line Control Register */
13#define OFFSET_MCR 0x10 /* Modem Control Register */
14#define OFFSET_LSR 0x14 /* Line Status Register */
15#define OFFSET_MSR 0x18 /* Modem Status Register */
16#define OFFSET_SCR 0x1C /* SCR Scratch Register */
17#define OFFSET_GCTL 0x24 /* Global Control Register */
18
19#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
20#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
21#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
22#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
23#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
24#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
25#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
26#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
27
28#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
29#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
30#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
31#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
32#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
33#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
34
35#ifdef CONFIG_BFIN_UART0_CTSRTS
36# define CONFIG_SERIAL_BFIN_CTSRTS
37# ifndef CONFIG_UART0_CTS_PIN
38# define CONFIG_UART0_CTS_PIN -1
39# endif
40# ifndef CONFIG_UART0_RTS_PIN
41# define CONFIG_UART0_RTS_PIN -1
42# endif
43#endif
44
45struct bfin_serial_port {
46 struct uart_port port;
47 unsigned int old_status;
48#ifdef CONFIG_SERIAL_BFIN_DMA
49 int tx_done;
50 int tx_count;
51 struct circ_buf rx_dma_buf;
52 struct timer_list rx_dma_timer;
53 int rx_dma_nrows;
54 unsigned int tx_dma_channel;
55 unsigned int rx_dma_channel;
56 struct work_struct tx_dma_workqueue;
57#else
58 struct work_struct cts_workqueue;
59#endif
60#ifdef CONFIG_SERIAL_BFIN_CTSRTS
61 int cts_pin;
62 int rts_pin;
63#endif
64};
65
66struct bfin_serial_port bfin_serial_ports[NR_PORTS];
67struct bfin_serial_res {
68 unsigned long uart_base_addr;
69 int uart_irq;
70#ifdef CONFIG_SERIAL_BFIN_DMA
71 unsigned int uart_tx_dma_channel;
72 unsigned int uart_rx_dma_channel;
73#endif
74#ifdef CONFIG_SERIAL_BFIN_CTSRTS
75 int uart_cts_pin;
76 int uart_rts_pin;
77#endif
78};
79
80struct bfin_serial_res bfin_serial_resource[] = {
81 0xFFC00400,
82 IRQ_UART_RX,
83#ifdef CONFIG_SERIAL_BFIN_DMA
84 CH_UART_TX,
85 CH_UART_RX,
86#endif
87#ifdef CONFIG_BFIN_UART0_CTSRTS
88 CONFIG_UART0_CTS_PIN,
89 CONFIG_UART0_RTS_PIN,
90#endif
91};
92
93
94int nr_ports = NR_PORTS;
95static void bfin_serial_hw_init(struct bfin_serial_port *uart)
96{
97
98#ifdef CONFIG_SERIAL_BFIN_CTSRTS
99 if (uart->cts_pin >= 0) {
100 gpio_request(uart->cts_pin, NULL);
101 gpio_direction_input(uart->cts_pin);
102 }
103 if (uart->rts_pin >= 0) {
104 gpio_request(uart->rts_pin, NULL);
105 gpio_direction_input(uart->rts_pin);
106 }
107#endif
108}
diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h
new file mode 100644
index 000000000000..2537c845e8b0
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/blackfin.h
@@ -0,0 +1,52 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _MACH_BLACKFIN_H_
32#define _MACH_BLACKFIN_H_
33
34#define BF561_FAMILY
35
36#include "bf561.h"
37#include "mem_map.h"
38#include "defBF561.h"
39#include "anomaly.h"
40
41#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
42#include "cdefBF561.h"
43#endif
44
45#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
46#define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
47#define bfin_read_FIO_DIR() bfin_read_FIO0_DIR()
48#define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
49#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
50#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
51
52#endif /* _MACH_BLACKFIN_H_ */
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
new file mode 100644
index 000000000000..5dc0ed835447
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -0,0 +1,1543 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/cdefBF561.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF561_H
32#define _CDEF_BF561_H
33
34/*
35#if !defined(__ADSPBF561__)
36#warning cdefBF561.h should only be included for BF561 chip.
37#endif
38*/
39/* include all Core registers and bit definitions */
40#include "defBF561.h"
41
42/*include core specific register pointer definitions*/
43#include <asm/mach-common/cdef_LPBlackfin.h>
44
45#include <asm/system.h>
46
47/*********************************************************************************** */
48/* System MMR Register Map */
49/*********************************************************************************** */
50
51/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
52#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
53#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val)
54#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
55#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
56#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
57/* Writing to VR_CTL initiates a PLL relock sequence. */
58static __inline__ void bfin_write_VR_CTL(unsigned int val)
59{
60 unsigned long flags, iwr;
61
62 bfin_write16(VR_CTL, val);
63 __builtin_bfin_ssync();
64 /* Enable the PLL Wakeup bit in SIC IWR */
65 iwr = bfin_read32(SICA_IWR0);
66 /* Only allow PPL Wakeup) */
67 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
68 local_irq_save(flags);
69 asm("IDLE;");
70 local_irq_restore(flags);
71 bfin_write32(SICA_IWR0, iwr);
72}
73#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
74#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
75#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
76#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
77#define bfin_read_CHIPID() bfin_read32(CHIPID)
78
79/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
80#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
81#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val)
82#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR)
83#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val)
84#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT)
85#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val)
86#define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK)
87#define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val)
88#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0)
89#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val)
90#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1)
91#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val)
92#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0)
93#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val)
94#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1)
95#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val)
96#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2)
97#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val)
98#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3)
99#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val)
100#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4)
101#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val)
102#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5)
103#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val)
104#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6)
105#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val)
106#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7)
107#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val)
108#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0)
109#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val)
110#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1)
111#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val)
112#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0)
113#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val)
114#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1)
115#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val)
116
117/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
118#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
119#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST,val)
120#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR)
121#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR,val)
122#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT)
123#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT,val)
124#define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0)
125#define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val)
126#define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1)
127#define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1,val)
128#define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0)
129#define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0,val)
130#define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1)
131#define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1,val)
132#define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2)
133#define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2,val)
134#define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3)
135#define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3,val)
136#define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4)
137#define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4,val)
138#define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5)
139#define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5,val)
140#define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6)
141#define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6,val)
142#define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7)
143#define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7,val)
144#define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0)
145#define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0,val)
146#define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1)
147#define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1,val)
148#define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0)
149#define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0,val)
150#define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1)
151#define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1,val)
152/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
153#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL)
154#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL,val)
155#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT)
156#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT,val)
157#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT)
158#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT,val)
159
160/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
161#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL)
162#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL,val)
163#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT)
164#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT,val)
165#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT)
166#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT,val)
167
168/* UART Controller (0xFFC00400 - 0xFFC004FF) */
169#define bfin_read_UART_THR() bfin_read16(UART_THR)
170#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
171#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
172#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
173#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
174#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
175#define bfin_read_UART_IER() bfin_read16(UART_IER)
176#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
177#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
178#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
179#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
180#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
181#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
182#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
183#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
184#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
185#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
186#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
187#define bfin_read_UART_MSR() bfin_read16(UART_MSR)
188#define bfin_write_UART_MSR(val) bfin_write16(UART_MSR,val)
189#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
190#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
191#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
192#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
193
194/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
195#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
196#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
197#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
198#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
199#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
200#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
201#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
202#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
203#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
204#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
205#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
206#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
207#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
208#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
209
210/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
211#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
212#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
213#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
214#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
215#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
216#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
217#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
218#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
219#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
220#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
221#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
222#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
223#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
224#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
225#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
226#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
227#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
228#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
229#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
230#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
231#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
232#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
233#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
234#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
235#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
236#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
237#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
238#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
239#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
240#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
241#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
242#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
243#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
244#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
245#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
246#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
247#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
248#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
249#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
250#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
251#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
252#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
253#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
254#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
255#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
256#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
257#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
258#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
259#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
260#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
261#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
262#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
263#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
264#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
265#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
266#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
267#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
268#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
269#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
270#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
271#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
272#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
273#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
274#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
275
276/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
277#define bfin_read_TMRS8_ENABLE() bfin_read16(TMRS8_ENABLE)
278#define bfin_write_TMRS8_ENABLE(val) bfin_write16(TMRS8_ENABLE,val)
279#define bfin_read_TMRS8_DISABLE() bfin_read16(TMRS8_DISABLE)
280#define bfin_write_TMRS8_DISABLE(val) bfin_write16(TMRS8_DISABLE,val)
281#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS)
282#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS,val)
283#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
284#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG,val)
285#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
286#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER,val)
287#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
288#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD,val)
289#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
290#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH,val)
291#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
292#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG,val)
293#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
294#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER,val)
295#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
296#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD,val)
297#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
298#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH,val)
299#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
300#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG,val)
301#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
302#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER,val)
303#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
304#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD,val)
305#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
306#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH,val)
307#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG)
308#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG,val)
309#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER)
310#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER,val)
311#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD)
312#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD,val)
313#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH)
314#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH,val)
315#define bfin_read_TMRS4_ENABLE() bfin_read16(TMRS4_ENABLE)
316#define bfin_write_TMRS4_ENABLE(val) bfin_write16(TMRS4_ENABLE,val)
317#define bfin_read_TMRS4_DISABLE() bfin_read16(TMRS4_DISABLE)
318#define bfin_write_TMRS4_DISABLE(val) bfin_write16(TMRS4_DISABLE,val)
319#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS)
320#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS,val)
321
322/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
323#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D)
324#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D,val)
325#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C)
326#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C,val)
327#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S)
328#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S,val)
329#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T)
330#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T,val)
331#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D)
332#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D,val)
333#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C)
334#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C,val)
335#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S)
336#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S,val)
337#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T)
338#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T,val)
339#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D)
340#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D,val)
341#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C)
342#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C,val)
343#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S)
344#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S,val)
345#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T)
346#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T,val)
347#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR)
348#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR,val)
349#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR)
350#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR,val)
351#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE)
352#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE,val)
353#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH)
354#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH,val)
355#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN)
356#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN,val)
357/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
358#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D)
359#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D,val)
360#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C)
361#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C,val)
362#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S)
363#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S,val)
364#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T)
365#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T,val)
366#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D)
367#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D,val)
368#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C)
369#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C,val)
370#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S)
371#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S,val)
372#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T)
373#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T,val)
374#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D)
375#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D,val)
376#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C)
377#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C,val)
378#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S)
379#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S,val)
380#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T)
381#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T,val)
382#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR)
383#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR,val)
384#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR)
385#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR,val)
386#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE)
387#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE,val)
388#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH)
389#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH,val)
390#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN)
391#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN,val)
392/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
393#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D)
394#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D,val)
395#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C)
396#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C,val)
397#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S)
398#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S,val)
399#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T)
400#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T,val)
401#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D)
402#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D,val)
403#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C)
404#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C,val)
405#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S)
406#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S,val)
407#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T)
408#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T,val)
409#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D)
410#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D,val)
411#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C)
412#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C,val)
413#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S)
414#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S,val)
415#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T)
416#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T,val)
417#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR)
418#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR,val)
419#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR)
420#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR,val)
421#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE)
422#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE,val)
423#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH)
424#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH,val)
425#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN)
426#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN,val)
427/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
428#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
429#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
430#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
431#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
432#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
433#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
434#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
435#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
436#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
437#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
438#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
439#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
440#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
441#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
442#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
443#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
444#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
445#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
446#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
447#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
448#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
449#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
450#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
451#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
452#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
453#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
454#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
455#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
456#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
457#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
458#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
459#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
460#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
461#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
462#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
463#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
464#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
465#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
466#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
467#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
468#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
469#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
470#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
471#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
472#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
473#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
474#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
475#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
476#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
477#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
478#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
479#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
480/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
481#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
482#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
483#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
484#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
485#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
486#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
487#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
488#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
489#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
490#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
491#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
492#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
493#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
494#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
495#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
496#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
497#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
498#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
499#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
500#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
501#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
502#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
503#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
504#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
505#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
506#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
507#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
508#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
509#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
510#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
511#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
512#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
513#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
514#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
515#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
516#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
517#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
518#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
519#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
520#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
521#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
522#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
523#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
524#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
525#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
526#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
527#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
528#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
529#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
530#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
531#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
532#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
533/* Asynchronous Memory Controller - External Bus Interface Unit */
534#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
535#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
536#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
537#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
538#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
539#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
540/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
541#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
542#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
543#define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL)
544#define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val)
545#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
546#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
547#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
548#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
549/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
550#define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL)
551#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val)
552#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS)
553#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val)
554#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT)
555#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val)
556#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY)
557#define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY,val)
558#define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME)
559#define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME,val)
560/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
561#define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL)
562#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val)
563#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS)
564#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val)
565#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT)
566#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val)
567#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY)
568#define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY,val)
569#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME)
570#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val)
571/*DMA traffic control registers */
572#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER)
573#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER,val)
574#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT)
575#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT,val)
576#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER)
577#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER,val)
578#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT)
579#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT,val)
580/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
581#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG)
582#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val)
583#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_read32(DMA1_0_NEXT_DESC_PTR)
584#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_write32(DMA1_0_NEXT_DESC_PTR,val)
585#define bfin_read_DMA1_0_START_ADDR() bfin_read32(DMA1_0_START_ADDR)
586#define bfin_write_DMA1_0_START_ADDR(val) bfin_write32(DMA1_0_START_ADDR,val)
587#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT)
588#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT,val)
589#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT)
590#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT,val)
591#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY)
592#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY,val)
593#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY)
594#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY,val)
595#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_read32(DMA1_0_CURR_DESC_PTR)
596#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_write32(DMA1_0_CURR_DESC_PTR,val)
597#define bfin_read_DMA1_0_CURR_ADDR() bfin_read32(DMA1_0_CURR_ADDR)
598#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_write32(DMA1_0_CURR_ADDR,val)
599#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)
600#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT,val)
601#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)
602#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT,val)
603#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS)
604#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS,val)
605#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)
606#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP,val)
607#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG)
608#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG,val)
609#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_read32(DMA1_1_NEXT_DESC_PTR)
610#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_write32(DMA1_1_NEXT_DESC_PTR,val)
611#define bfin_read_DMA1_1_START_ADDR() bfin_read32(DMA1_1_START_ADDR)
612#define bfin_write_DMA1_1_START_ADDR(val) bfin_write32(DMA1_1_START_ADDR,val)
613#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT)
614#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT,val)
615#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT)
616#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT,val)
617#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY)
618#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY,val)
619#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY)
620#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY,val)
621#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_read32(DMA1_1_CURR_DESC_PTR)
622#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_write32(DMA1_1_CURR_DESC_PTR,val)
623#define bfin_read_DMA1_1_CURR_ADDR() bfin_read32(DMA1_1_CURR_ADDR)
624#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_write32(DMA1_1_CURR_ADDR,val)
625#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)
626#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT,val)
627#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)
628#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT,val)
629#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS)
630#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS,val)
631#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)
632#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP,val)
633#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG)
634#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG,val)
635#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_read32(DMA1_2_NEXT_DESC_PTR)
636#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_write32(DMA1_2_NEXT_DESC_PTR,val)
637#define bfin_read_DMA1_2_START_ADDR() bfin_read32(DMA1_2_START_ADDR)
638#define bfin_write_DMA1_2_START_ADDR(val) bfin_write32(DMA1_2_START_ADDR,val)
639#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT)
640#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT,val)
641#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT)
642#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT,val)
643#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY)
644#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY,val)
645#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY)
646#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY,val)
647#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_read32(DMA1_2_CURR_DESC_PTR)
648#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_write32(DMA1_2_CURR_DESC_PTR,val)
649#define bfin_read_DMA1_2_CURR_ADDR() bfin_read32(DMA1_2_CURR_ADDR)
650#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_write32(DMA1_2_CURR_ADDR,val)
651#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)
652#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT,val)
653#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)
654#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT,val)
655#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS)
656#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS,val)
657#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)
658#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP,val)
659#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG)
660#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG,val)
661#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_read32(DMA1_3_NEXT_DESC_PTR)
662#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_write32(DMA1_3_NEXT_DESC_PTR,val)
663#define bfin_read_DMA1_3_START_ADDR() bfin_read32(DMA1_3_START_ADDR)
664#define bfin_write_DMA1_3_START_ADDR(val) bfin_write32(DMA1_3_START_ADDR,val)
665#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT)
666#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT,val)
667#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT)
668#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT,val)
669#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY)
670#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY,val)
671#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY)
672#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY,val)
673#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_read32(DMA1_3_CURR_DESC_PTR)
674#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_write32(DMA1_3_CURR_DESC_PTR,val)
675#define bfin_read_DMA1_3_CURR_ADDR() bfin_read32(DMA1_3_CURR_ADDR)
676#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_write32(DMA1_3_CURR_ADDR,val)
677#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)
678#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT,val)
679#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)
680#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT,val)
681#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS)
682#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS,val)
683#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)
684#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP,val)
685#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG)
686#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG,val)
687#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_read32(DMA1_4_NEXT_DESC_PTR)
688#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_write32(DMA1_4_NEXT_DESC_PTR,val)
689#define bfin_read_DMA1_4_START_ADDR() bfin_read32(DMA1_4_START_ADDR)
690#define bfin_write_DMA1_4_START_ADDR(val) bfin_write32(DMA1_4_START_ADDR,val)
691#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT)
692#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT,val)
693#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT)
694#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT,val)
695#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY)
696#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY,val)
697#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY)
698#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY,val)
699#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_read32(DMA1_4_CURR_DESC_PTR)
700#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_write32(DMA1_4_CURR_DESC_PTR,val)
701#define bfin_read_DMA1_4_CURR_ADDR() bfin_read32(DMA1_4_CURR_ADDR)
702#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_write32(DMA1_4_CURR_ADDR,val)
703#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)
704#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT,val)
705#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)
706#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT,val)
707#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS)
708#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS,val)
709#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)
710#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP,val)
711#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG)
712#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG,val)
713#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_read32(DMA1_5_NEXT_DESC_PTR)
714#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_write32(DMA1_5_NEXT_DESC_PTR,val)
715#define bfin_read_DMA1_5_START_ADDR() bfin_read32(DMA1_5_START_ADDR)
716#define bfin_write_DMA1_5_START_ADDR(val) bfin_write32(DMA1_5_START_ADDR,val)
717#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT)
718#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT,val)
719#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT)
720#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT,val)
721#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY)
722#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY,val)
723#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY)
724#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY,val)
725#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_read32(DMA1_5_CURR_DESC_PTR)
726#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_write32(DMA1_5_CURR_DESC_PTR,val)
727#define bfin_read_DMA1_5_CURR_ADDR() bfin_read32(DMA1_5_CURR_ADDR)
728#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_write32(DMA1_5_CURR_ADDR,val)
729#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)
730#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT,val)
731#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)
732#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT,val)
733#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS)
734#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS,val)
735#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)
736#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP,val)
737#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG)
738#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG,val)
739#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_read32(DMA1_6_NEXT_DESC_PTR)
740#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_write32(DMA1_6_NEXT_DESC_PTR,val)
741#define bfin_read_DMA1_6_START_ADDR() bfin_read32(DMA1_6_START_ADDR)
742#define bfin_write_DMA1_6_START_ADDR(val) bfin_write32(DMA1_6_START_ADDR,val)
743#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT)
744#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT,val)
745#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT)
746#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT,val)
747#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY)
748#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY,val)
749#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY)
750#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY,val)
751#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_read32(DMA1_6_CURR_DESC_PTR)
752#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_write32(DMA1_6_CURR_DESC_PTR,val)
753#define bfin_read_DMA1_6_CURR_ADDR() bfin_read32(DMA1_6_CURR_ADDR)
754#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_write32(DMA1_6_CURR_ADDR,val)
755#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)
756#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT,val)
757#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)
758#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT,val)
759#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS)
760#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS,val)
761#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)
762#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP,val)
763#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG)
764#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG,val)
765#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_read32(DMA1_7_NEXT_DESC_PTR)
766#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_write32(DMA1_7_NEXT_DESC_PTR,val)
767#define bfin_read_DMA1_7_START_ADDR() bfin_read32(DMA1_7_START_ADDR)
768#define bfin_write_DMA1_7_START_ADDR(val) bfin_write32(DMA1_7_START_ADDR,val)
769#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT)
770#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT,val)
771#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT)
772#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT,val)
773#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY)
774#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY,val)
775#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY)
776#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY,val)
777#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_read32(DMA1_7_CURR_DESC_PTR)
778#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_write32(DMA1_7_CURR_DESC_PTR,val)
779#define bfin_read_DMA1_7_CURR_ADDR() bfin_read32(DMA1_7_CURR_ADDR)
780#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_write32(DMA1_7_CURR_ADDR,val)
781#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT)
782#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT,val)
783#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT)
784#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT,val)
785#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS)
786#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS,val)
787#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP)
788#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP,val)
789#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG)
790#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG,val)
791#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_read32(DMA1_8_NEXT_DESC_PTR)
792#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_write32(DMA1_8_NEXT_DESC_PTR,val)
793#define bfin_read_DMA1_8_START_ADDR() bfin_read32(DMA1_8_START_ADDR)
794#define bfin_write_DMA1_8_START_ADDR(val) bfin_write32(DMA1_8_START_ADDR,val)
795#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT)
796#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT,val)
797#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT)
798#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT,val)
799#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY)
800#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY,val)
801#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY)
802#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY,val)
803#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_read32(DMA1_8_CURR_DESC_PTR)
804#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_write32(DMA1_8_CURR_DESC_PTR,val)
805#define bfin_read_DMA1_8_CURR_ADDR() bfin_read32(DMA1_8_CURR_ADDR)
806#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_write32(DMA1_8_CURR_ADDR,val)
807#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT)
808#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT,val)
809#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT)
810#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT,val)
811#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS)
812#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS,val)
813#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP)
814#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP,val)
815#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG)
816#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG,val)
817#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_read32(DMA1_9_NEXT_DESC_PTR)
818#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_write32(DMA1_9_NEXT_DESC_PTR,val)
819#define bfin_read_DMA1_9_START_ADDR() bfin_read32(DMA1_9_START_ADDR)
820#define bfin_write_DMA1_9_START_ADDR(val) bfin_write32(DMA1_9_START_ADDR,val)
821#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT)
822#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT,val)
823#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT)
824#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT,val)
825#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY)
826#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY,val)
827#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY)
828#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY,val)
829#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_read32(DMA1_9_CURR_DESC_PTR)
830#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_write32(DMA1_9_CURR_DESC_PTR,val)
831#define bfin_read_DMA1_9_CURR_ADDR() bfin_read32(DMA1_9_CURR_ADDR)
832#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_write32(DMA1_9_CURR_ADDR,val)
833#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT)
834#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT,val)
835#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT)
836#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT,val)
837#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS)
838#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS,val)
839#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP)
840#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP,val)
841#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG)
842#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG,val)
843#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_read32(DMA1_10_NEXT_DESC_PTR)
844#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_write32(DMA1_10_NEXT_DESC_PTR,val)
845#define bfin_read_DMA1_10_START_ADDR() bfin_read32(DMA1_10_START_ADDR)
846#define bfin_write_DMA1_10_START_ADDR(val) bfin_write32(DMA1_10_START_ADDR,val)
847#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT)
848#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT,val)
849#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT)
850#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT,val)
851#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY)
852#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY,val)
853#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY)
854#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY,val)
855#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_read32(DMA1_10_CURR_DESC_PTR)
856#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_write32(DMA1_10_CURR_DESC_PTR,val)
857#define bfin_read_DMA1_10_CURR_ADDR() bfin_read32(DMA1_10_CURR_ADDR)
858#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_write32(DMA1_10_CURR_ADDR,val)
859#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT)
860#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT,val)
861#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT)
862#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT,val)
863#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS)
864#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS,val)
865#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP)
866#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP,val)
867#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG)
868#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG,val)
869#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_read32(DMA1_11_NEXT_DESC_PTR)
870#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_write32(DMA1_11_NEXT_DESC_PTR,val)
871#define bfin_read_DMA1_11_START_ADDR() bfin_read32(DMA1_11_START_ADDR)
872#define bfin_write_DMA1_11_START_ADDR(val) bfin_write32(DMA1_11_START_ADDR,val)
873#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT)
874#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT,val)
875#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT)
876#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT,val)
877#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY)
878#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY,val)
879#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY)
880#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY,val)
881#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_read32(DMA1_11_CURR_DESC_PTR)
882#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_write32(DMA1_11_CURR_DESC_PTR,val)
883#define bfin_read_DMA1_11_CURR_ADDR() bfin_read32(DMA1_11_CURR_ADDR)
884#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_write32(DMA1_11_CURR_ADDR,val)
885#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT)
886#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT,val)
887#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT)
888#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT,val)
889#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS)
890#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS,val)
891#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
892#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
893/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
894#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG)
895#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG,val)
896#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_read32(MDMA1_D0_NEXT_DESC_PTR)
897#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D0_NEXT_DESC_PTR,val)
898#define bfin_read_MDMA1_D0_START_ADDR() bfin_read32(MDMA1_D0_START_ADDR)
899#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_write32(MDMA1_D0_START_ADDR,val)
900#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT)
901#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT,val)
902#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT)
903#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT,val)
904#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY)
905#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY,val)
906#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY)
907#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY,val)
908#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_read32(MDMA1_D0_CURR_DESC_PTR)
909#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_write32(MDMA1_D0_CURR_DESC_PTR,val)
910#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_read32(MDMA1_D0_CURR_ADDR)
911#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_write32(MDMA1_D0_CURR_ADDR,val)
912#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
913#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT,val)
914#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
915#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT,val)
916#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
917#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS,val)
918#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
919#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP,val)
920#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG)
921#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG,val)
922#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_read32(MDMA1_S0_NEXT_DESC_PTR)
923#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S0_NEXT_DESC_PTR,val)
924#define bfin_read_MDMA1_S0_START_ADDR() bfin_read32(MDMA1_S0_START_ADDR)
925#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_write32(MDMA1_S0_START_ADDR,val)
926#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT)
927#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT,val)
928#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT)
929#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT,val)
930#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY)
931#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY,val)
932#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY)
933#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY,val)
934#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_read32(MDMA1_S0_CURR_DESC_PTR)
935#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_write32(MDMA1_S0_CURR_DESC_PTR,val)
936#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_read32(MDMA1_S0_CURR_ADDR)
937#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_write32(MDMA1_S0_CURR_ADDR,val)
938#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
939#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT,val)
940#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
941#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT,val)
942#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
943#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS,val)
944#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
945#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP,val)
946#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG)
947#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG,val)
948#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_read32(MDMA1_D1_NEXT_DESC_PTR)
949#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D1_NEXT_DESC_PTR,val)
950#define bfin_read_MDMA1_D1_START_ADDR() bfin_read32(MDMA1_D1_START_ADDR)
951#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_write32(MDMA1_D1_START_ADDR,val)
952#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT)
953#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT,val)
954#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT)
955#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT,val)
956#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY)
957#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY,val)
958#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY)
959#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY,val)
960#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_read32(MDMA1_D1_CURR_DESC_PTR)
961#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_write32(MDMA1_D1_CURR_DESC_PTR,val)
962#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_read32(MDMA1_D1_CURR_ADDR)
963#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_write32(MDMA1_D1_CURR_ADDR,val)
964#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
965#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT,val)
966#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
967#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT,val)
968#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
969#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS,val)
970#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
971#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP,val)
972#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG)
973#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG,val)
974#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_read32(MDMA1_S1_NEXT_DESC_PTR)
975#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S1_NEXT_DESC_PTR,val)
976#define bfin_read_MDMA1_S1_START_ADDR() bfin_read32(MDMA1_S1_START_ADDR)
977#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_write32(MDMA1_S1_START_ADDR,val)
978#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT)
979#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT,val)
980#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT)
981#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT,val)
982#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY)
983#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY,val)
984#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY)
985#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY,val)
986#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_read32(MDMA1_S1_CURR_DESC_PTR)
987#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_write32(MDMA1_S1_CURR_DESC_PTR,val)
988#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_read32(MDMA1_S1_CURR_ADDR)
989#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_write32(MDMA1_S1_CURR_ADDR,val)
990#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
991#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT,val)
992#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
993#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT,val)
994#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
995#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS,val)
996#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
997#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP,val)
998/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
999#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG)
1000#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val)
1001#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_read32(DMA2_0_NEXT_DESC_PTR)
1002#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_write32(DMA2_0_NEXT_DESC_PTR,val)
1003#define bfin_read_DMA2_0_START_ADDR() bfin_read32(DMA2_0_START_ADDR)
1004#define bfin_write_DMA2_0_START_ADDR(val) bfin_write32(DMA2_0_START_ADDR,val)
1005#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT)
1006#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT,val)
1007#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT)
1008#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT,val)
1009#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY)
1010#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY,val)
1011#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY)
1012#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY,val)
1013#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_read32(DMA2_0_CURR_DESC_PTR)
1014#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_write32(DMA2_0_CURR_DESC_PTR,val)
1015#define bfin_read_DMA2_0_CURR_ADDR() bfin_read32(DMA2_0_CURR_ADDR)
1016#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_write32(DMA2_0_CURR_ADDR,val)
1017#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT)
1018#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT,val)
1019#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT)
1020#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT,val)
1021#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS)
1022#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS,val)
1023#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP)
1024#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP,val)
1025#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG)
1026#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG,val)
1027#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_read32(DMA2_1_NEXT_DESC_PTR)
1028#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_write32(DMA2_1_NEXT_DESC_PTR,val)
1029#define bfin_read_DMA2_1_START_ADDR() bfin_read32(DMA2_1_START_ADDR)
1030#define bfin_write_DMA2_1_START_ADDR(val) bfin_write32(DMA2_1_START_ADDR,val)
1031#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT)
1032#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT,val)
1033#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT)
1034#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT,val)
1035#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY)
1036#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY,val)
1037#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY)
1038#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY,val)
1039#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_read32(DMA2_1_CURR_DESC_PTR)
1040#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_write32(DMA2_1_CURR_DESC_PTR,val)
1041#define bfin_read_DMA2_1_CURR_ADDR() bfin_read32(DMA2_1_CURR_ADDR)
1042#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_write32(DMA2_1_CURR_ADDR,val)
1043#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT)
1044#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT,val)
1045#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT)
1046#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT,val)
1047#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS)
1048#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS,val)
1049#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP)
1050#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP,val)
1051#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG)
1052#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG,val)
1053#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_read32(DMA2_2_NEXT_DESC_PTR)
1054#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_write32(DMA2_2_NEXT_DESC_PTR,val)
1055#define bfin_read_DMA2_2_START_ADDR() bfin_read32(DMA2_2_START_ADDR)
1056#define bfin_write_DMA2_2_START_ADDR(val) bfin_write32(DMA2_2_START_ADDR,val)
1057#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT)
1058#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT,val)
1059#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT)
1060#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT,val)
1061#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY)
1062#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY,val)
1063#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY)
1064#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY,val)
1065#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_read32(DMA2_2_CURR_DESC_PTR)
1066#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_write32(DMA2_2_CURR_DESC_PTR,val)
1067#define bfin_read_DMA2_2_CURR_ADDR() bfin_read32(DMA2_2_CURR_ADDR)
1068#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_write32(DMA2_2_CURR_ADDR,val)
1069#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT)
1070#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT,val)
1071#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT)
1072#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT,val)
1073#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS)
1074#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS,val)
1075#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP)
1076#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP,val)
1077#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG)
1078#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG,val)
1079#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_read32(DMA2_3_NEXT_DESC_PTR)
1080#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_write32(DMA2_3_NEXT_DESC_PTR,val)
1081#define bfin_read_DMA2_3_START_ADDR() bfin_read32(DMA2_3_START_ADDR)
1082#define bfin_write_DMA2_3_START_ADDR(val) bfin_write32(DMA2_3_START_ADDR,val)
1083#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT)
1084#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT,val)
1085#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT)
1086#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT,val)
1087#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY)
1088#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY,val)
1089#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY)
1090#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY,val)
1091#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_read32(DMA2_3_CURR_DESC_PTR)
1092#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_write32(DMA2_3_CURR_DESC_PTR,val)
1093#define bfin_read_DMA2_3_CURR_ADDR() bfin_read32(DMA2_3_CURR_ADDR)
1094#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_write32(DMA2_3_CURR_ADDR,val)
1095#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT)
1096#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT,val)
1097#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT)
1098#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT,val)
1099#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS)
1100#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS,val)
1101#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP)
1102#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP,val)
1103#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG)
1104#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG,val)
1105#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_read32(DMA2_4_NEXT_DESC_PTR)
1106#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_write32(DMA2_4_NEXT_DESC_PTR,val)
1107#define bfin_read_DMA2_4_START_ADDR() bfin_read32(DMA2_4_START_ADDR)
1108#define bfin_write_DMA2_4_START_ADDR(val) bfin_write32(DMA2_4_START_ADDR,val)
1109#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT)
1110#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT,val)
1111#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT)
1112#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT,val)
1113#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY)
1114#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY,val)
1115#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY)
1116#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY,val)
1117#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_read32(DMA2_4_CURR_DESC_PTR)
1118#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_write32(DMA2_4_CURR_DESC_PTR,val)
1119#define bfin_read_DMA2_4_CURR_ADDR() bfin_read32(DMA2_4_CURR_ADDR)
1120#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_write32(DMA2_4_CURR_ADDR,val)
1121#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT)
1122#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT,val)
1123#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT)
1124#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT,val)
1125#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS)
1126#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS,val)
1127#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP)
1128#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP,val)
1129#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG)
1130#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG,val)
1131#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_read32(DMA2_5_NEXT_DESC_PTR)
1132#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_write32(DMA2_5_NEXT_DESC_PTR,val)
1133#define bfin_read_DMA2_5_START_ADDR() bfin_read32(DMA2_5_START_ADDR)
1134#define bfin_write_DMA2_5_START_ADDR(val) bfin_write32(DMA2_5_START_ADDR,val)
1135#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT)
1136#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT,val)
1137#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT)
1138#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT,val)
1139#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY)
1140#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY,val)
1141#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY)
1142#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY,val)
1143#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_read32(DMA2_5_CURR_DESC_PTR)
1144#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_write32(DMA2_5_CURR_DESC_PTR,val)
1145#define bfin_read_DMA2_5_CURR_ADDR() bfin_read32(DMA2_5_CURR_ADDR)
1146#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_write32(DMA2_5_CURR_ADDR,val)
1147#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT)
1148#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT,val)
1149#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT)
1150#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT,val)
1151#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS)
1152#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS,val)
1153#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP)
1154#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP,val)
1155#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG)
1156#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG,val)
1157#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_read32(DMA2_6_NEXT_DESC_PTR)
1158#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_write32(DMA2_6_NEXT_DESC_PTR,val)
1159#define bfin_read_DMA2_6_START_ADDR() bfin_read32(DMA2_6_START_ADDR)
1160#define bfin_write_DMA2_6_START_ADDR(val) bfin_write32(DMA2_6_START_ADDR,val)
1161#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT)
1162#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT,val)
1163#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT)
1164#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT,val)
1165#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY)
1166#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY,val)
1167#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY)
1168#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY,val)
1169#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_read32(DMA2_6_CURR_DESC_PTR)
1170#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_write32(DMA2_6_CURR_DESC_PTR,val)
1171#define bfin_read_DMA2_6_CURR_ADDR() bfin_read32(DMA2_6_CURR_ADDR)
1172#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_write32(DMA2_6_CURR_ADDR,val)
1173#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT)
1174#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT,val)
1175#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT)
1176#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT,val)
1177#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS)
1178#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS,val)
1179#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP)
1180#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP,val)
1181#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG)
1182#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG,val)
1183#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_read32(DMA2_7_NEXT_DESC_PTR)
1184#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_write32(DMA2_7_NEXT_DESC_PTR,val)
1185#define bfin_read_DMA2_7_START_ADDR() bfin_read32(DMA2_7_START_ADDR)
1186#define bfin_write_DMA2_7_START_ADDR(val) bfin_write32(DMA2_7_START_ADDR,val)
1187#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT)
1188#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT,val)
1189#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT)
1190#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT,val)
1191#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY)
1192#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY,val)
1193#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY)
1194#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY,val)
1195#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_read32(DMA2_7_CURR_DESC_PTR)
1196#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_write32(DMA2_7_CURR_DESC_PTR,val)
1197#define bfin_read_DMA2_7_CURR_ADDR() bfin_read32(DMA2_7_CURR_ADDR)
1198#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_write32(DMA2_7_CURR_ADDR,val)
1199#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT)
1200#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT,val)
1201#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT)
1202#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT,val)
1203#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS)
1204#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS,val)
1205#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP)
1206#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP,val)
1207#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG)
1208#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG,val)
1209#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_read32(DMA2_8_NEXT_DESC_PTR)
1210#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_write32(DMA2_8_NEXT_DESC_PTR,val)
1211#define bfin_read_DMA2_8_START_ADDR() bfin_read32(DMA2_8_START_ADDR)
1212#define bfin_write_DMA2_8_START_ADDR(val) bfin_write32(DMA2_8_START_ADDR,val)
1213#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT)
1214#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT,val)
1215#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT)
1216#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT,val)
1217#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY)
1218#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY,val)
1219#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY)
1220#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY,val)
1221#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_read32(DMA2_8_CURR_DESC_PTR)
1222#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_write32(DMA2_8_CURR_DESC_PTR,val)
1223#define bfin_read_DMA2_8_CURR_ADDR() bfin_read32(DMA2_8_CURR_ADDR)
1224#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_write32(DMA2_8_CURR_ADDR,val)
1225#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT)
1226#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT,val)
1227#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT)
1228#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT,val)
1229#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS)
1230#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS,val)
1231#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP)
1232#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP,val)
1233#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG)
1234#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG,val)
1235#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_read32(DMA2_9_NEXT_DESC_PTR)
1236#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_write32(DMA2_9_NEXT_DESC_PTR,val)
1237#define bfin_read_DMA2_9_START_ADDR() bfin_read32(DMA2_9_START_ADDR)
1238#define bfin_write_DMA2_9_START_ADDR(val) bfin_write32(DMA2_9_START_ADDR,val)
1239#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT)
1240#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT,val)
1241#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT)
1242#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT,val)
1243#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY)
1244#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY,val)
1245#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY)
1246#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY,val)
1247#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_read32(DMA2_9_CURR_DESC_PTR)
1248#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_write32(DMA2_9_CURR_DESC_PTR,val)
1249#define bfin_read_DMA2_9_CURR_ADDR() bfin_read32(DMA2_9_CURR_ADDR)
1250#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_write32(DMA2_9_CURR_ADDR,val)
1251#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT)
1252#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT,val)
1253#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT)
1254#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT,val)
1255#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS)
1256#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS,val)
1257#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP)
1258#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP,val)
1259#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG)
1260#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG,val)
1261#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_read32(DMA2_10_NEXT_DESC_PTR)
1262#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_write32(DMA2_10_NEXT_DESC_PTR,val)
1263#define bfin_read_DMA2_10_START_ADDR() bfin_read32(DMA2_10_START_ADDR)
1264#define bfin_write_DMA2_10_START_ADDR(val) bfin_write32(DMA2_10_START_ADDR,val)
1265#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT)
1266#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT,val)
1267#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT)
1268#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT,val)
1269#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY)
1270#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY,val)
1271#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY)
1272#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY,val)
1273#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_read32(DMA2_10_CURR_DESC_PTR)
1274#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_write32(DMA2_10_CURR_DESC_PTR,val)
1275#define bfin_read_DMA2_10_CURR_ADDR() bfin_read32(DMA2_10_CURR_ADDR)
1276#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_write32(DMA2_10_CURR_ADDR,val)
1277#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT)
1278#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT,val)
1279#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT)
1280#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT,val)
1281#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS)
1282#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS,val)
1283#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP)
1284#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP,val)
1285#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG)
1286#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG,val)
1287#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_read32(DMA2_11_NEXT_DESC_PTR)
1288#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_write32(DMA2_11_NEXT_DESC_PTR,val)
1289#define bfin_read_DMA2_11_START_ADDR() bfin_read32(DMA2_11_START_ADDR)
1290#define bfin_write_DMA2_11_START_ADDR(val) bfin_write32(DMA2_11_START_ADDR,val)
1291#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT)
1292#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT,val)
1293#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT)
1294#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT,val)
1295#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY)
1296#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY,val)
1297#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY)
1298#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY,val)
1299#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_read32(DMA2_11_CURR_DESC_PTR)
1300#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_write32(DMA2_11_CURR_DESC_PTR,val)
1301#define bfin_read_DMA2_11_CURR_ADDR() bfin_read32(DMA2_11_CURR_ADDR)
1302#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_write32(DMA2_11_CURR_ADDR,val)
1303#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT)
1304#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT,val)
1305#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT)
1306#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT,val)
1307#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS)
1308#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS,val)
1309#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
1310#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
1311/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
1312#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG)
1313#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG,val)
1314#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_read32(MDMA2_D0_NEXT_DESC_PTR)
1315#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D0_NEXT_DESC_PTR,val)
1316#define bfin_read_MDMA2_D0_START_ADDR() bfin_read32(MDMA2_D0_START_ADDR)
1317#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_write32(MDMA2_D0_START_ADDR,val)
1318#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT)
1319#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT,val)
1320#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT)
1321#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT,val)
1322#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY)
1323#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY,val)
1324#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY)
1325#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY,val)
1326#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_read32(MDMA2_D0_CURR_DESC_PTR)
1327#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_write32(MDMA2_D0_CURR_DESC_PTR,val)
1328#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_read32(MDMA2_D0_CURR_ADDR)
1329#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_write32(MDMA2_D0_CURR_ADDR,val)
1330#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT)
1331#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT,val)
1332#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT)
1333#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT,val)
1334#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS)
1335#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS,val)
1336#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
1337#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP,val)
1338#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG)
1339#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG,val)
1340#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_read32(MDMA2_S0_NEXT_DESC_PTR)
1341#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S0_NEXT_DESC_PTR,val)
1342#define bfin_read_MDMA2_S0_START_ADDR() bfin_read32(MDMA2_S0_START_ADDR)
1343#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_write32(MDMA2_S0_START_ADDR,val)
1344#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT)
1345#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT,val)
1346#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT)
1347#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT,val)
1348#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY)
1349#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY,val)
1350#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY)
1351#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY,val)
1352#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_read32(MDMA2_S0_CURR_DESC_PTR)
1353#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_write32(MDMA2_S0_CURR_DESC_PTR,val)
1354#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_read32(MDMA2_S0_CURR_ADDR)
1355#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_write32(MDMA2_S0_CURR_ADDR,val)
1356#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT)
1357#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT,val)
1358#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT)
1359#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT,val)
1360#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS)
1361#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS,val)
1362#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
1363#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP,val)
1364#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG)
1365#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG,val)
1366#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_read32(MDMA2_D1_NEXT_DESC_PTR)
1367#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D1_NEXT_DESC_PTR,val)
1368#define bfin_read_MDMA2_D1_START_ADDR() bfin_read32(MDMA2_D1_START_ADDR)
1369#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_write32(MDMA2_D1_START_ADDR,val)
1370#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT)
1371#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT,val)
1372#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT)
1373#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT,val)
1374#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY)
1375#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY,val)
1376#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY)
1377#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY,val)
1378#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_read32(MDMA2_D1_CURR_DESC_PTR)
1379#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_write32(MDMA2_D1_CURR_DESC_PTR,val)
1380#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_read32(MDMA2_D1_CURR_ADDR)
1381#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_write32(MDMA2_D1_CURR_ADDR,val)
1382#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT)
1383#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT,val)
1384#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT)
1385#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT,val)
1386#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS)
1387#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS,val)
1388#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
1389#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP,val)
1390#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG)
1391#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG,val)
1392#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_read32(MDMA2_S1_NEXT_DESC_PTR)
1393#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S1_NEXT_DESC_PTR,val)
1394#define bfin_read_MDMA2_S1_START_ADDR() bfin_read32(MDMA2_S1_START_ADDR)
1395#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_write32(MDMA2_S1_START_ADDR,val)
1396#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT)
1397#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT,val)
1398#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT)
1399#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT,val)
1400#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY)
1401#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY,val)
1402#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY)
1403#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY,val)
1404#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_read32(MDMA2_S1_CURR_DESC_PTR)
1405#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_write32(MDMA2_S1_CURR_DESC_PTR,val)
1406#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_read32(MDMA2_S1_CURR_ADDR)
1407#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_write32(MDMA2_S1_CURR_ADDR,val)
1408#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT)
1409#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT,val)
1410#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT)
1411#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT,val)
1412#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS)
1413#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS,val)
1414#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
1415#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP,val)
1416/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
1417#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG)
1418#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val)
1419#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_read32(IMDMA_D0_NEXT_DESC_PTR)
1420#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D0_NEXT_DESC_PTR,val)
1421#define bfin_read_IMDMA_D0_START_ADDR() bfin_read32(IMDMA_D0_START_ADDR)
1422#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_write32(IMDMA_D0_START_ADDR,val)
1423#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT)
1424#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT,val)
1425#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT)
1426#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT,val)
1427#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY)
1428#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY,val)
1429#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY)
1430#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY,val)
1431#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_read32(IMDMA_D0_CURR_DESC_PTR)
1432#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_write32(IMDMA_D0_CURR_DESC_PTR,val)
1433#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_read32(IMDMA_D0_CURR_ADDR)
1434#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_write32(IMDMA_D0_CURR_ADDR,val)
1435#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT)
1436#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT,val)
1437#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT)
1438#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT,val)
1439#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS)
1440#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS,val)
1441#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG)
1442#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG,val)
1443#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_read32(IMDMA_S0_NEXT_DESC_PTR)
1444#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S0_NEXT_DESC_PTR,val)
1445#define bfin_read_IMDMA_S0_START_ADDR() bfin_read32(IMDMA_S0_START_ADDR)
1446#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_write32(IMDMA_S0_START_ADDR,val)
1447#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT)
1448#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT,val)
1449#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT)
1450#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT,val)
1451#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY)
1452#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY,val)
1453#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY)
1454#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY,val)
1455#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_read32(IMDMA_S0_CURR_DESC_PTR)
1456#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_write32(IMDMA_S0_CURR_DESC_PTR,val)
1457#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_read32(IMDMA_S0_CURR_ADDR)
1458#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_write32(IMDMA_S0_CURR_ADDR,val)
1459#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT)
1460#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT,val)
1461#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT)
1462#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT,val)
1463#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS)
1464#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS,val)
1465#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG)
1466#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG,val)
1467#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_read32(IMDMA_D1_NEXT_DESC_PTR)
1468#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D1_NEXT_DESC_PTR,val)
1469#define bfin_read_IMDMA_D1_START_ADDR() bfin_read32(IMDMA_D1_START_ADDR)
1470#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_write32(IMDMA_D1_START_ADDR,val)
1471#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT)
1472#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT,val)
1473#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT)
1474#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT,val)
1475#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY)
1476#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY,val)
1477#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY)
1478#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY,val)
1479#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_read32(IMDMA_D1_CURR_DESC_PTR)
1480#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_write32(IMDMA_D1_CURR_DESC_PTR,val)
1481#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_read32(IMDMA_D1_CURR_ADDR)
1482#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_write32(IMDMA_D1_CURR_ADDR,val)
1483#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT)
1484#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT,val)
1485#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT)
1486#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT,val)
1487#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS)
1488#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS,val)
1489#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG)
1490#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG,val)
1491#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_read32(IMDMA_S1_NEXT_DESC_PTR)
1492#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S1_NEXT_DESC_PTR,val)
1493#define bfin_read_IMDMA_S1_START_ADDR() bfin_read32(IMDMA_S1_START_ADDR)
1494#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_write32(IMDMA_S1_START_ADDR,val)
1495#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT)
1496#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT,val)
1497#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT)
1498#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT,val)
1499#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY)
1500#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY,val)
1501#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY)
1502#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY,val)
1503#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_read32(IMDMA_S1_CURR_DESC_PTR)
1504#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_write32(IMDMA_S1_CURR_DESC_PTR,val)
1505#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_read32(IMDMA_S1_CURR_ADDR)
1506#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_write32(IMDMA_S1_CURR_ADDR,val)
1507#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT)
1508#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT,val)
1509#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT)
1510#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT,val)
1511#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
1512#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val)
1513
1514#define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA1_S0_CONFIG()
1515#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA1_S0_CONFIG(val)
1516#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA1_S0_IRQ_STATUS()
1517#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA1_S0_IRQ_STATUS(val)
1518#define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA1_S0_X_MODIFY()
1519#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA1_S0_X_MODIFY(val)
1520#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA1_S0_Y_MODIFY()
1521#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA1_S0_Y_MODIFY(val)
1522#define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA1_S0_X_COUNT()
1523#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA1_S0_X_COUNT(val)
1524#define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA1_S0_Y_COUNT()
1525#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA1_S0_Y_COUNT(val)
1526#define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA1_S0_START_ADDR()
1527#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA1_S0_START_ADDR(val)
1528#define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA1_D0_CONFIG()
1529#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA1_D0_CONFIG(val)
1530#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA1_D0_IRQ_STATUS()
1531#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA1_D0_IRQ_STATUS(val)
1532#define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA1_D0_X_MODIFY()
1533#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA1_D0_X_MODIFY(val)
1534#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA1_D0_Y_MODIFY()
1535#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA1_D0_Y_MODIFY(val)
1536#define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA1_D0_X_COUNT()
1537#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA1_D0_X_COUNT(val)
1538#define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA1_D0_Y_COUNT()
1539#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA1_D0_Y_COUNT(val)
1540#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR()
1541#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
1542
1543#endif /* _CDEF_BF561_H */
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
new file mode 100644
index 000000000000..a6de4c69ba55
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -0,0 +1,1717 @@
1
2/*
3 * File: include/asm-blackfin/mach-bf561/defBF561.h
4 * Based on:
5 * Author:
6 *
7 * Created:
8 * Description:
9 * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
10 * Rev:
11 *
12 * Modified:
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _DEF_BF561_H
33#define _DEF_BF561_H
34/*
35#if !defined(__ADSPBF561__)
36#warning defBF561.h should only be included for BF561 chip.
37#endif
38*/
39/* include all Core registers and bit definitions */
40#include <asm/mach-common/def_LPBlackfin.h>
41
42/*********************************************************************************** */
43/* System MMR Register Map */
44/*********************************************************************************** */
45
46/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
47
48#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
49#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
50#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
51#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
52#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
53#define CHIPID 0xFFC00014 /* Chip ID Register */
54
55/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
56#define SICA_SWRST 0xFFC00100 /* Software Reset register */
57#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */
58#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
59#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */
60#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
61#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
62#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
63#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
64#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
65#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
66#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
67#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
68#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
69#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
70#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
71#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
72#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
73#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
74
75/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
76#define SICB_SWRST 0xFFC01100 /* reserved */
77#define SICB_SYSCR 0xFFC01104 /* reserved */
78#define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */
79#define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */
80#define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */
81#define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */
82#define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */
83#define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */
84#define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */
85#define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */
86#define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */
87#define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */
88#define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */
89#define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */
90#define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */
91#define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */
92#define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */
93
94/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
95#define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */
96#define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */
97#define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */
98
99/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
100#define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */
101#define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */
102#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
103
104/* UART Controller (0xFFC00400 - 0xFFC004FF) */
105#define UART_THR 0xFFC00400 /* Transmit Holding register */
106#define UART_RBR 0xFFC00400 /* Receive Buffer register */
107#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
108#define UART_IER 0xFFC00404 /* Interrupt Enable Register */
109#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
110#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */
111#define UART_LCR 0xFFC0040C /* Line Control Register */
112#define UART_MCR 0xFFC00410 /* Modem Control Register */
113#define UART_LSR 0xFFC00414 /* Line Status Register */
114#define UART_MSR 0xFFC00418 /* Modem Status Register */
115#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
116#define UART_GCTL 0xFFC00424 /* Global Control Register */
117
118/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
119#define SPI_CTL 0xFFC00500 /* SPI Control Register */
120#define SPI_FLG 0xFFC00504 /* SPI Flag register */
121#define SPI_STAT 0xFFC00508 /* SPI Status register */
122#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
123#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
124#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
125#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
126
127/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
128#define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */
129#define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */
130#define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */
131#define TIMER0_WIDTH 0xFFC0060C /* Timer0 Width register */
132
133#define TIMER1_CONFIG 0xFFC00610 /* Timer1 Configuration register */
134#define TIMER1_COUNTER 0xFFC00614 /* Timer1 Counter register */
135#define TIMER1_PERIOD 0xFFC00618 /* Timer1 Period register */
136#define TIMER1_WIDTH 0xFFC0061C /* Timer1 Width register */
137
138#define TIMER2_CONFIG 0xFFC00620 /* Timer2 Configuration register */
139#define TIMER2_COUNTER 0xFFC00624 /* Timer2 Counter register */
140#define TIMER2_PERIOD 0xFFC00628 /* Timer2 Period register */
141#define TIMER2_WIDTH 0xFFC0062C /* Timer2 Width register */
142
143#define TIMER3_CONFIG 0xFFC00630 /* Timer3 Configuration register */
144#define TIMER3_COUNTER 0xFFC00634 /* Timer3 Counter register */
145#define TIMER3_PERIOD 0xFFC00638 /* Timer3 Period register */
146#define TIMER3_WIDTH 0xFFC0063C /* Timer3 Width register */
147
148#define TIMER4_CONFIG 0xFFC00640 /* Timer4 Configuration register */
149#define TIMER4_COUNTER 0xFFC00644 /* Timer4 Counter register */
150#define TIMER4_PERIOD 0xFFC00648 /* Timer4 Period register */
151#define TIMER4_WIDTH 0xFFC0064C /* Timer4 Width register */
152
153#define TIMER5_CONFIG 0xFFC00650 /* Timer5 Configuration register */
154#define TIMER5_COUNTER 0xFFC00654 /* Timer5 Counter register */
155#define TIMER5_PERIOD 0xFFC00658 /* Timer5 Period register */
156#define TIMER5_WIDTH 0xFFC0065C /* Timer5 Width register */
157
158#define TIMER6_CONFIG 0xFFC00660 /* Timer6 Configuration register */
159#define TIMER6_COUNTER 0xFFC00664 /* Timer6 Counter register */
160#define TIMER6_PERIOD 0xFFC00668 /* Timer6 Period register */
161#define TIMER6_WIDTH 0xFFC0066C /* Timer6 Width register */
162
163#define TIMER7_CONFIG 0xFFC00670 /* Timer7 Configuration register */
164#define TIMER7_COUNTER 0xFFC00674 /* Timer7 Counter register */
165#define TIMER7_PERIOD 0xFFC00678 /* Timer7 Period register */
166#define TIMER7_WIDTH 0xFFC0067C /* Timer7 Width register */
167
168#define TMRS8_ENABLE 0xFFC00680 /* Timer Enable Register */
169#define TMRS8_DISABLE 0xFFC00684 /* Timer Disable register */
170#define TMRS8_STATUS 0xFFC00688 /* Timer Status register */
171
172/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
173#define TIMER8_CONFIG 0xFFC01600 /* Timer8 Configuration register */
174#define TIMER8_COUNTER 0xFFC01604 /* Timer8 Counter register */
175#define TIMER8_PERIOD 0xFFC01608 /* Timer8 Period register */
176#define TIMER8_WIDTH 0xFFC0160C /* Timer8 Width register */
177
178#define TIMER9_CONFIG 0xFFC01610 /* Timer9 Configuration register */
179#define TIMER9_COUNTER 0xFFC01614 /* Timer9 Counter register */
180#define TIMER9_PERIOD 0xFFC01618 /* Timer9 Period register */
181#define TIMER9_WIDTH 0xFFC0161C /* Timer9 Width register */
182
183#define TIMER10_CONFIG 0xFFC01620 /* Timer10 Configuration register */
184#define TIMER10_COUNTER 0xFFC01624 /* Timer10 Counter register */
185#define TIMER10_PERIOD 0xFFC01628 /* Timer10 Period register */
186#define TIMER10_WIDTH 0xFFC0162C /* Timer10 Width register */
187
188#define TIMER11_CONFIG 0xFFC01630 /* Timer11 Configuration register */
189#define TIMER11_COUNTER 0xFFC01634 /* Timer11 Counter register */
190#define TIMER11_PERIOD 0xFFC01638 /* Timer11 Period register */
191#define TIMER11_WIDTH 0xFFC0163C /* Timer11 Width register */
192
193#define TMRS4_ENABLE 0xFFC01640 /* Timer Enable Register */
194#define TMRS4_DISABLE 0xFFC01644 /* Timer Disable register */
195#define TMRS4_STATUS 0xFFC01648 /* Timer Status register */
196
197/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
198#define FIO0_FLAG_D 0xFFC00700 /* Flag Data register */
199#define FIO0_FLAG_C 0xFFC00704 /* Flag Clear register */
200#define FIO0_FLAG_S 0xFFC00708 /* Flag Set register */
201#define FIO0_FLAG_T 0xFFC0070C /* Flag Toggle register */
202#define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */
203#define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */
204#define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */
205#define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */
206#define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */
207#define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */
208#define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */
209#define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */
210#define FIO0_DIR 0xFFC00730 /* Flag Direction register */
211#define FIO0_POLAR 0xFFC00734 /* Flag Polarity register */
212#define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */
213#define FIO0_BOTH 0xFFC0073C /* Flag Set on Both Edges register */
214#define FIO0_INEN 0xFFC00740 /* Flag Input Enable register */
215
216/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
217#define FIO1_FLAG_D 0xFFC01500 /* Flag Data register (mask used to directly */
218#define FIO1_FLAG_C 0xFFC01504 /* Flag Clear register */
219#define FIO1_FLAG_S 0xFFC01508 /* Flag Set register */
220#define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register (mask used to */
221#define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */
222#define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */
223#define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */
224#define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */
225#define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */
226#define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */
227#define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */
228#define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */
229#define FIO1_DIR 0xFFC01530 /* Flag Direction register */
230#define FIO1_POLAR 0xFFC01534 /* Flag Polarity register */
231#define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */
232#define FIO1_BOTH 0xFFC0153C /* Flag Set on Both Edges register */
233#define FIO1_INEN 0xFFC01540 /* Flag Input Enable register */
234
235/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
236#define FIO2_FLAG_D 0xFFC01700 /* Flag Data register (mask used to directly */
237#define FIO2_FLAG_C 0xFFC01704 /* Flag Clear register */
238#define FIO2_FLAG_S 0xFFC01708 /* Flag Set register */
239#define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register (mask used to */
240#define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */
241#define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */
242#define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */
243#define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */
244#define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */
245#define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */
246#define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */
247#define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */
248#define FIO2_DIR 0xFFC01730 /* Flag Direction register */
249#define FIO2_POLAR 0xFFC01734 /* Flag Polarity register */
250#define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */
251#define FIO2_BOTH 0xFFC0173C /* Flag Set on Both Edges register */
252#define FIO2_INEN 0xFFC01740 /* Flag Input Enable register */
253
254/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
255#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
256#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
257#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
258#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
259#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
260#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
261#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
262#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
263#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
264#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
265#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
266#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
267#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
268#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
269#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
270#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
271#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
272#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
273#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
274#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
275#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
276#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
277
278/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
279#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
280#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
281#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
282#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
283#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
284#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
285#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
286#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
287#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
288#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
289#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
290#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
291#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
292#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
293#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
294#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
295#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
296#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
297#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
298#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
299#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
300#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
301
302/* Asynchronous Memory Controller - External Bus Interface Unit */
303#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
304#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
305#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
306
307/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
308#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
309#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
310#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
311#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
312
313/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
314#define PPI0_CONTROL 0xFFC01000 /* PPI0 Control register */
315#define PPI0_STATUS 0xFFC01004 /* PPI0 Status register */
316#define PPI0_COUNT 0xFFC01008 /* PPI0 Transfer Count register */
317#define PPI0_DELAY 0xFFC0100C /* PPI0 Delay Count register */
318#define PPI0_FRAME 0xFFC01010 /* PPI0 Frame Length register */
319
320/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
321#define PPI1_CONTROL 0xFFC01300 /* PPI1 Control register */
322#define PPI1_STATUS 0xFFC01304 /* PPI1 Status register */
323#define PPI1_COUNT 0xFFC01308 /* PPI1 Transfer Count register */
324#define PPI1_DELAY 0xFFC0130C /* PPI1 Delay Count register */
325#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */
326
327/*DMA traffic control registers */
328#define DMA1_TC_PER 0xFFC01B0C /* Traffic control periods */
329#define DMA1_TC_CNT 0xFFC01B10 /* Traffic control current counts */
330#define DMA2_TC_PER 0xFFC00B0C /* Traffic control periods */
331#define DMA2_TC_CNT 0xFFC00B10 /* Traffic control current counts */
332
333/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
334#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */
335#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */
336#define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */
337#define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */
338#define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */
339#define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */
340#define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */
341#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */
342#define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */
343#define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */
344#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */
345#define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */
346#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */
347
348#define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */
349#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */
350#define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */
351#define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */
352#define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */
353#define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */
354#define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */
355#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */
356#define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */
357#define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */
358#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */
359#define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt/Status Register */
360#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */
361
362#define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */
363#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */
364#define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */
365#define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */
366#define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */
367#define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */
368#define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */
369#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */
370#define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */
371#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */
372#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */
373#define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */
374#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */
375
376#define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */
377#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */
378#define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */
379#define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */
380#define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */
381#define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */
382#define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */
383#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */
384#define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */
385#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */
386#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */
387#define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt/Status Register */
388#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */
389
390#define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */
391#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */
392#define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */
393#define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */
394#define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */
395#define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */
396#define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */
397#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */
398#define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */
399#define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */
400#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */
401#define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt/Status Register */
402#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */
403
404#define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */
405#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */
406#define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */
407#define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */
408#define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */
409#define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */
410#define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */
411#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */
412#define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */
413#define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */
414#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */
415#define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt/Status Register */
416#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */
417
418#define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */
419#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */
420#define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */
421#define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */
422#define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */
423#define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */
424#define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */
425#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */
426#define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */
427#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */
428#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */
429#define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt/Status Register */
430#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */
431
432#define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */
433#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */
434#define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */
435#define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */
436#define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */
437#define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */
438#define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */
439#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */
440#define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */
441#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */
442#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */
443#define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt/Status Register */
444#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */
445
446#define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */
447#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */
448#define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */
449#define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */
450#define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */
451#define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */
452#define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */
453#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */
454#define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */
455#define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */
456#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */
457#define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt/Status Register */
458#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */
459
460#define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */
461#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */
462#define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */
463#define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */
464#define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */
465#define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */
466#define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */
467#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */
468#define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */
469#define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */
470#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */
471#define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt/Status Register */
472#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */
473
474#define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */
475#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */
476#define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */
477#define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */
478#define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */
479#define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */
480#define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */
481#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */
482#define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */
483#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */
484#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */
485#define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt/Status Register */
486#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */
487
488#define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */
489#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */
490#define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */
491#define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */
492#define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */
493#define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */
494#define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */
495#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */
496#define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */
497#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */
498#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */
499#define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt/Status Register */
500#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */
501
502/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
503#define MDMA1_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */
504#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
505#define MDMA1_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */
506#define MDMA1_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */
507#define MDMA1_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */
508#define MDMA1_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
509#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
510#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
511#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */
512#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
513#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
514#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */
515#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */
516
517#define MDMA1_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */
518#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
519#define MDMA1_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */
520#define MDMA1_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */
521#define MDMA1_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */
522#define MDMA1_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
523#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
524#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
525#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */
526#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
527#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
528#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */
529#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */
530
531#define MDMA1_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */
532#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
533#define MDMA1_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */
534#define MDMA1_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */
535#define MDMA1_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */
536#define MDMA1_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
537#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
538#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
539#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */
540#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
541#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
542#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */
543#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */
544
545#define MDMA1_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */
546#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
547#define MDMA1_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */
548#define MDMA1_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */
549#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */
550#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
551#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
552#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
553#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */
554#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
555#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
556#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */
557#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */
558
559/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
560#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */
561#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */
562#define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */
563#define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */
564#define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */
565#define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */
566#define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */
567#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */
568#define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */
569#define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */
570#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */
571#define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */
572#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */
573
574#define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */
575#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */
576#define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */
577#define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */
578#define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */
579#define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */
580#define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */
581#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */
582#define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */
583#define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */
584#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */
585#define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */
586#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */
587
588#define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */
589#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */
590#define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */
591#define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */
592#define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */
593#define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */
594#define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */
595#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */
596#define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */
597#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */
598#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */
599#define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */
600#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */
601
602#define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */
603#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */
604#define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */
605#define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */
606#define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */
607#define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */
608#define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */
609#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */
610#define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */
611#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */
612#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */
613#define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */
614#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */
615
616#define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */
617#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */
618#define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */
619#define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */
620#define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */
621#define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */
622#define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */
623#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */
624#define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */
625#define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */
626#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */
627#define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */
628#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */
629
630#define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */
631#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */
632#define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */
633#define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */
634#define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */
635#define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */
636#define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */
637#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */
638#define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */
639#define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */
640#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */
641#define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */
642#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */
643
644#define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */
645#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */
646#define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */
647#define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */
648#define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */
649#define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */
650#define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */
651#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */
652#define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */
653#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */
654#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */
655#define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */
656#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */
657
658#define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */
659#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */
660#define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */
661#define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */
662#define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */
663#define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */
664#define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */
665#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */
666#define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */
667#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */
668#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */
669#define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */
670#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */
671
672#define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */
673#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */
674#define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */
675#define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */
676#define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */
677#define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */
678#define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */
679#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */
680#define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */
681#define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */
682#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */
683#define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */
684#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */
685
686#define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */
687#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */
688#define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */
689#define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */
690#define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */
691#define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */
692#define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */
693#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */
694#define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */
695#define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */
696#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */
697#define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */
698#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */
699
700#define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */
701#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */
702#define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */
703#define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */
704#define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */
705#define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */
706#define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */
707#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */
708#define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */
709#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */
710#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */
711#define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */
712#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */
713
714#define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */
715#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */
716#define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */
717#define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */
718#define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */
719#define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */
720#define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */
721#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */
722#define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */
723#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */
724#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */
725#define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */
726#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */
727
728/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
729#define MDMA2_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */
730#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
731#define MDMA2_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */
732#define MDMA2_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
733#define MDMA2_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
734#define MDMA2_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
735#define MDMA2_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
736#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
737#define MDMA2_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */
738#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
739#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
740#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
741#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */
742
743#define MDMA2_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */
744#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
745#define MDMA2_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */
746#define MDMA2_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */
747#define MDMA2_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */
748#define MDMA2_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
749#define MDMA2_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
750#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
751#define MDMA2_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */
752#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
753#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
754#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */
755#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */
756
757#define MDMA2_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */
758#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
759#define MDMA2_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */
760#define MDMA2_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
761#define MDMA2_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
762#define MDMA2_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
763#define MDMA2_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
764#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
765#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */
766#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
767#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
768#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
769#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */
770
771#define MDMA2_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */
772#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
773#define MDMA2_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */
774#define MDMA2_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */
775#define MDMA2_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */
776#define MDMA2_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
777#define MDMA2_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
778#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
779#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */
780#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
781#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
782#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
783#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
784
785/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
786#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
787#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
788#define IMDMA_D0_START_ADDR 0xFFC01804 /*IMDMA Stream 0 Destination Start Address */
789#define IMDMA_D0_X_COUNT 0xFFC01810 /*IMDMA Stream 0 Destination Inner-Loop Count */
790#define IMDMA_D0_Y_COUNT 0xFFC01818 /*IMDMA Stream 0 Destination Outer-Loop Count */
791#define IMDMA_D0_X_MODIFY 0xFFC01814 /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
792#define IMDMA_D0_Y_MODIFY 0xFFC0181C /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
793#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /*IMDMA Stream 0 Destination Current Descriptor Ptr */
794#define IMDMA_D0_CURR_ADDR 0xFFC01824 /*IMDMA Stream 0 Destination Current Address */
795#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */
796#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */
797#define IMDMA_D0_IRQ_STATUS 0xFFC01828 /*IMDMA Stream 0 Destination Interrupt/Status */
798
799#define IMDMA_S0_CONFIG 0xFFC01848 /*IMDMA Stream 0 Source Configuration */
800#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */
801#define IMDMA_S0_START_ADDR 0xFFC01844 /*IMDMA Stream 0 Source Start Address */
802#define IMDMA_S0_X_COUNT 0xFFC01850 /*IMDMA Stream 0 Source Inner-Loop Count */
803#define IMDMA_S0_Y_COUNT 0xFFC01858 /*IMDMA Stream 0 Source Outer-Loop Count */
804#define IMDMA_S0_X_MODIFY 0xFFC01854 /*IMDMA Stream 0 Source Inner-Loop Address-Increment */
805#define IMDMA_S0_Y_MODIFY 0xFFC0185C /*IMDMA Stream 0 Source Outer-Loop Address-Increment */
806#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /*IMDMA Stream 0 Source Current Descriptor Ptr reg */
807#define IMDMA_S0_CURR_ADDR 0xFFC01864 /*IMDMA Stream 0 Source Current Address */
808#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */
809#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */
810#define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */
811
812#define IMDMA_D1_CONFIG 0xFFC01888 /*IMDMA Stream 1 Destination Configuration */
813#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
814#define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */
815#define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */
816#define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */
817#define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
818#define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
819#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */
820#define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */
821#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */
822#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */
823#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */
824
825#define IMDMA_S1_CONFIG 0xFFC018C8 /*IMDMA Stream 1 Source Configuration */
826#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
827#define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */
828#define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */
829#define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */
830#define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
831#define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
832#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */
833#define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */
834#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */
835#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */
836#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */
837
838/*********************************************************************************** */
839/* System MMR Register Bits */
840/******************************************************************************* */
841
842/* ********************* PLL AND RESET MASKS ************************ */
843
844/* PLL_CTL Masks */
845#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */
846#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */
847#define PLL_OFF 0x00000002 /* Shut off PLL clocks */
848#define STOPCK_OFF 0x00000008 /* Core clock off */
849#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */
850#define BYPASS 0x00000100 /* Bypass the PLL */
851
852/* CHIPID Masks */
853#define CHIPID_VERSION 0xF0000000
854#define CHIPID_FAMILY 0x0FFFF000
855#define CHIPID_MANUFACTURE 0x00000FFE
856
857/* PLL_DIV Masks */
858#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
859
860#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
861#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
862#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
863#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
864
865/* PLL_STAT Masks */
866#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
867#define FULL_ON 0x0002 /* Processor In Full On Mode */
868#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
869#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
870
871/* SWRST Mask */
872#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */
873#define SWRST_DBL_FAULT_B 0x00000800 /* SWRST Core B Double Fault */
874#define SWRST_DBL_FAULT_A 0x00001000 /* SWRST Core A Double Fault */
875#define SWRST_WDT_B 0x00002000 /* SWRST Watchdog B */
876#define SWRST_WDT_A 0x00004000 /* SWRST Watchdog A */
877#define SWRST_OCCURRED 0x00008000 /* SWRST Status */
878
879/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
880
881/* SICu_IARv Masks */
882/* u = A or B */
883/* v = 0 to 7 */
884/* w = 0 or 1 */
885
886/* Per_number = 0 to 63 */
887/* IVG_number = 7 to 15 */
888#define Peripheral_IVG(Per_number, IVG_number) \
889 ((IVG_number) - 7) << (((Per_number) % 8) * 4) /* Peripheral #Per_number assigned IVG #IVG_number */
890 /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
891 /* r0.h = hi(Peripheral_IVG(62, 10)); */
892
893/* SICx_IMASKw Masks */
894/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */
895#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
896#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
897#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
898#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
899
900/* SIC_IWR Masks */
901#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
902#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
903/* x = pos 0 to 31, for 32-63 use value-32 */
904#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
905#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
906
907/* ********* WATCHDOG TIMER MASKS ********************8 */
908
909/* Watchdog Timer WDOG_CTL Register */
910#define ICTL(x) ((x<<1) & 0x0006)
911#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */
912#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */
913#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */
914#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */
915
916#define TMR_EN 0x0000
917#define TMR_DIS 0x0AD0
918#define TRO 0x8000
919
920#define ICTL_P0 0x01
921#define ICTL_P1 0x02
922#define TRO_P 0x0F
923
924/* ***************************** UART CONTROLLER MASKS ********************** */
925
926/* UART_LCR Register */
927
928#define DLAB 0x80
929#define SB 0x40
930#define STP 0x20
931#define EPS 0x10
932#define PEN 0x08
933#define STB 0x04
934#define WLS(x) ((x-5) & 0x03)
935
936#define DLAB_P 0x07
937#define SB_P 0x06
938#define STP_P 0x05
939#define EPS_P 0x04
940#define PEN_P 0x03
941#define STB_P 0x02
942#define WLS_P1 0x01
943#define WLS_P0 0x00
944
945/* UART_MCR Register */
946#define LOOP_ENA 0x10
947#define LOOP_ENA_P 0x04
948
949/* UART_LSR Register */
950#define TEMT 0x40
951#define THRE 0x20
952#define BI 0x10
953#define FE 0x08
954#define PE 0x04
955#define OE 0x02
956#define DR 0x01
957
958#define TEMP_P 0x06
959#define THRE_P 0x05
960#define BI_P 0x04
961#define FE_P 0x03
962#define PE_P 0x02
963#define OE_P 0x01
964#define DR_P 0x00
965
966/* UART_IER Register */
967#define ELSI 0x04
968#define ETBEI 0x02
969#define ERBFI 0x01
970
971#define ELSI_P 0x02
972#define ETBEI_P 0x01
973#define ERBFI_P 0x00
974
975/* UART_IIR Register */
976#define STATUS(x) ((x << 1) & 0x06)
977#define NINT 0x01
978#define STATUS_P1 0x02
979#define STATUS_P0 0x01
980#define NINT_P 0x00
981#define IIR_TX_READY 0x02 /* UART_THR empty */
982#define IIR_RX_READY 0x04 /* Receive data ready */
983#define IIR_LINE_CHANGE 0x06 /* Receive line status */
984#define IIR_STATUS 0x06
985
986/* UART_GCTL Register */
987#define FFE 0x20
988#define FPE 0x10
989#define RPOLC 0x08
990#define TPOLC 0x04
991#define IREN 0x02
992#define UCEN 0x01
993
994#define FFE_P 0x05
995#define FPE_P 0x04
996#define RPOLC_P 0x03
997#define TPOLC_P 0x02
998#define IREN_P 0x01
999#define UCEN_P 0x00
1000
1001/* ********** SERIAL PORT MASKS ********************** */
1002
1003/* SPORTx_TCR1 Masks */
1004#define TSPEN 0x0001 /* TX enable */
1005#define ITCLK 0x0002 /* Internal TX Clock Select */
1006#define TDTYPE 0x000C /* TX Data Formatting Select */
1007#define TLSBIT 0x0010 /* TX Bit Order */
1008#define ITFS 0x0200 /* Internal TX Frame Sync Select */
1009#define TFSR 0x0400 /* TX Frame Sync Required Select */
1010#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
1011#define LTFS 0x1000 /* Low TX Frame Sync Select */
1012#define LATFS 0x2000 /* Late TX Frame Sync Select */
1013#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
1014
1015/* SPORTx_TCR2 Masks */
1016#define SLEN 0x001F /*TX Word Length */
1017#define TXSE 0x0100 /*TX Secondary Enable */
1018#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
1019#define TRFST 0x0400 /*TX Right-First Data Order */
1020
1021/* SPORTx_RCR1 Masks */
1022#define RSPEN 0x0001 /* RX enable */
1023#define IRCLK 0x0002 /* Internal RX Clock Select */
1024#define RDTYPE 0x000C /* RX Data Formatting Select */
1025#define RULAW 0x0008 /* u-Law enable */
1026#define RALAW 0x000C /* A-Law enable */
1027#define RLSBIT 0x0010 /* RX Bit Order */
1028#define IRFS 0x0200 /* Internal RX Frame Sync Select */
1029#define RFSR 0x0400 /* RX Frame Sync Required Select */
1030#define LRFS 0x1000 /* Low RX Frame Sync Select */
1031#define LARFS 0x2000 /* Late RX Frame Sync Select */
1032#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
1033
1034/* SPORTx_RCR2 Masks */
1035#define SLEN 0x001F /*RX Word Length */
1036#define RXSE 0x0100 /*RX Secondary Enable */
1037#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
1038#define RRFST 0x0400 /*Right-First Data Order */
1039
1040/*SPORTx_STAT Masks */
1041#define RXNE 0x0001 /*RX FIFO Not Empty Status */
1042#define RUVF 0x0002 /*RX Underflow Status */
1043#define ROVF 0x0004 /*RX Overflow Status */
1044#define TXF 0x0008 /*TX FIFO Full Status */
1045#define TUVF 0x0010 /*TX Underflow Status */
1046#define TOVF 0x0020 /*TX Overflow Status */
1047#define TXHRE 0x0040 /*TX Hold Register Empty */
1048
1049/*SPORTx_MCMC1 Masks */
1050#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
1051#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
1052
1053/*SPORTx_MCMC2 Masks */
1054#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
1055#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
1056#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
1057#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
1058#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
1059#define MFD 0x0000F000 /*Multichannel Frame Delay */
1060
1061/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
1062
1063/* PPI_CONTROL Masks */
1064#define PORT_EN 0x00000001 /* PPI Port Enable */
1065#define PORT_DIR 0x00000002 /* PPI Port Direction */
1066#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
1067#define PORT_CFG 0x00000030 /* PPI Port Configuration */
1068#define FLD_SEL 0x00000040 /* PPI Active Field Select */
1069#define PACK_EN 0x00000080 /* PPI Packing Mode */
1070#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
1071#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
1072#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
1073#define DLENGTH 0x00003800 /* PPI Data Length */
1074#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
1075#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
1076#define POL 0x0000C000 /* PPI Signal Polarities */
1077
1078/* PPI_STATUS Masks */
1079#define FLD 0x00000400 /* Field Indicator */
1080#define FT_ERR 0x00000800 /* Frame Track Error */
1081#define OVR 0x00001000 /* FIFO Overflow Error */
1082#define UNDR 0x00002000 /* FIFO Underrun Error */
1083#define ERR_DET 0x00004000 /* Error Detected Indicator */
1084#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
1085
1086/* ********** DMA CONTROLLER MASKS *********************8 */
1087
1088/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
1089#define DMAEN 0x00000001 /* Channel Enable */
1090#define WNR 0x00000002 /* Channel Direction (W/R*) */
1091#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
1092#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
1093#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
1094#define DMA2D 0x00000010 /* 2D/1D* Mode */
1095#define RESTART 0x00000020 /* Restart */
1096#define DI_SEL 0x00000040 /* Data Interrupt Select */
1097#define DI_EN 0x00000080 /* Data Interrupt Enable */
1098#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1099#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1100#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1101#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1102#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1103#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1104#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1105#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1106#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1107#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1108#define NDSIZE 0x00000900 /* Next Descriptor Size */
1109#define DMAFLOW 0x00007000 /* Flow Control */
1110#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1111#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1112#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1113#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1114#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1115
1116#define DMAEN_P 0 /* Channel Enable */
1117#define WNR_P 1 /* Channel Direction (W/R*) */
1118#define DMA2D_P 4 /* 2D/1D* Mode */
1119#define RESTART_P 5 /* Restart */
1120#define DI_SEL_P 6 /* Data Interrupt Select */
1121#define DI_EN_P 7 /* Data Interrupt Enable */
1122
1123/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */
1124
1125#define DMA_DONE 0x00000001 /* DMA Done Indicator */
1126#define DMA_ERR 0x00000002 /* DMA Error Indicator */
1127#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
1128#define DMA_RUN 0x00000008 /* DMA Running Indicator */
1129
1130#define DMA_DONE_P 0 /* DMA Done Indicator */
1131#define DMA_ERR_P 1 /* DMA Error Indicator */
1132#define DFETCH_P 2 /* Descriptor Fetch Indicator */
1133#define DMA_RUN_P 3 /* DMA Running Indicator */
1134
1135/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
1136
1137#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
1138#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
1139#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
1140#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
1141#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
1142#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
1143#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
1144#define PMAP 0x00007000 /* DMA Peripheral Map Field */
1145
1146/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
1147
1148/* PWM Timer bit definitions */
1149
1150/* TIMER_ENABLE Register */
1151#define TIMEN0 0x0001
1152#define TIMEN1 0x0002
1153#define TIMEN2 0x0004
1154#define TIMEN3 0x0008
1155#define TIMEN4 0x0010
1156#define TIMEN5 0x0020
1157#define TIMEN6 0x0040
1158#define TIMEN7 0x0080
1159#define TIMEN8 0x0001
1160#define TIMEN9 0x0002
1161#define TIMEN10 0x0004
1162#define TIMEN11 0x0008
1163
1164#define TIMEN0_P 0x00
1165#define TIMEN1_P 0x01
1166#define TIMEN2_P 0x02
1167#define TIMEN3_P 0x03
1168#define TIMEN4_P 0x04
1169#define TIMEN5_P 0x05
1170#define TIMEN6_P 0x06
1171#define TIMEN7_P 0x07
1172#define TIMEN8_P 0x00
1173#define TIMEN9_P 0x01
1174#define TIMEN10_P 0x02
1175#define TIMEN11_P 0x03
1176
1177/* TIMER_DISABLE Register */
1178#define TIMDIS0 0x0001
1179#define TIMDIS1 0x0002
1180#define TIMDIS2 0x0004
1181#define TIMDIS3 0x0008
1182#define TIMDIS4 0x0010
1183#define TIMDIS5 0x0020
1184#define TIMDIS6 0x0040
1185#define TIMDIS7 0x0080
1186#define TIMDIS8 0x0001
1187#define TIMDIS9 0x0002
1188#define TIMDIS10 0x0004
1189#define TIMDIS11 0x0008
1190
1191#define TIMDIS0_P 0x00
1192#define TIMDIS1_P 0x01
1193#define TIMDIS2_P 0x02
1194#define TIMDIS3_P 0x03
1195#define TIMDIS4_P 0x04
1196#define TIMDIS5_P 0x05
1197#define TIMDIS6_P 0x06
1198#define TIMDIS7_P 0x07
1199#define TIMDIS8_P 0x00
1200#define TIMDIS9_P 0x01
1201#define TIMDIS10_P 0x02
1202#define TIMDIS11_P 0x03
1203
1204/* TIMER_STATUS Register */
1205#define TIMIL0 0x00000001
1206#define TIMIL1 0x00000002
1207#define TIMIL2 0x00000004
1208#define TIMIL3 0x00000008
1209#define TIMIL4 0x00010000
1210#define TIMIL5 0x00020000
1211#define TIMIL6 0x00040000
1212#define TIMIL7 0x00080000
1213#define TIMIL8 0x0001
1214#define TIMIL9 0x0002
1215#define TIMIL10 0x0004
1216#define TIMIL11 0x0008
1217#define TOVL_ERR0 0x00000010
1218#define TOVL_ERR1 0x00000020
1219#define TOVL_ERR2 0x00000040
1220#define TOVL_ERR3 0x00000080
1221#define TOVL_ERR4 0x00100000
1222#define TOVL_ERR5 0x00200000
1223#define TOVL_ERR6 0x00400000
1224#define TOVL_ERR7 0x00800000
1225#define TOVL_ERR8 0x0010
1226#define TOVL_ERR9 0x0020
1227#define TOVL_ERR10 0x0040
1228#define TOVL_ERR11 0x0080
1229#define TRUN0 0x00001000
1230#define TRUN1 0x00002000
1231#define TRUN2 0x00004000
1232#define TRUN3 0x00008000
1233#define TRUN4 0x10000000
1234#define TRUN5 0x20000000
1235#define TRUN6 0x40000000
1236#define TRUN7 0x80000000
1237#define TRUN8 0x1000
1238#define TRUN9 0x2000
1239#define TRUN10 0x4000
1240#define TRUN11 0x8000
1241
1242#define TIMIL0_P 0x00
1243#define TIMIL1_P 0x01
1244#define TIMIL2_P 0x02
1245#define TIMIL3_P 0x03
1246#define TIMIL4_P 0x10
1247#define TIMIL5_P 0x11
1248#define TIMIL6_P 0x12
1249#define TIMIL7_P 0x13
1250#define TIMIL8_P 0x00
1251#define TIMIL9_P 0x01
1252#define TIMIL10_P 0x02
1253#define TIMIL11_P 0x03
1254#define TOVL_ERR0_P 0x04
1255#define TOVL_ERR1_P 0x05
1256#define TOVL_ERR2_P 0x06
1257#define TOVL_ERR3_P 0x07
1258#define TOVL_ERR4_P 0x14
1259#define TOVL_ERR5_P 0x15
1260#define TOVL_ERR6_P 0x16
1261#define TOVL_ERR7_P 0x17
1262#define TOVL_ERR8_P 0x04
1263#define TOVL_ERR9_P 0x05
1264#define TOVL_ERR10_P 0x06
1265#define TOVL_ERR11_P 0x07
1266#define TRUN0_P 0x0C
1267#define TRUN1_P 0x0D
1268#define TRUN2_P 0x0E
1269#define TRUN3_P 0x0F
1270#define TRUN4_P 0x1C
1271#define TRUN5_P 0x1D
1272#define TRUN6_P 0x1E
1273#define TRUN7_P 0x1F
1274#define TRUN8_P 0x0C
1275#define TRUN9_P 0x0D
1276#define TRUN10_P 0x0E
1277#define TRUN11_P 0x0F
1278
1279/* TIMERx_CONFIG Registers */
1280#define PWM_OUT 0x0001
1281#define WDTH_CAP 0x0002
1282#define EXT_CLK 0x0003
1283#define PULSE_HI 0x0004
1284#define PERIOD_CNT 0x0008
1285#define IRQ_ENA 0x0010
1286#define TIN_SEL 0x0020
1287#define OUT_DIS 0x0040
1288#define CLK_SEL 0x0080
1289#define TOGGLE_HI 0x0100
1290#define EMU_RUN 0x0200
1291#define ERR_TYP(x) ((x & 0x03) << 14)
1292
1293#define TMODE_P0 0x00
1294#define TMODE_P1 0x01
1295#define PULSE_HI_P 0x02
1296#define PERIOD_CNT_P 0x03
1297#define IRQ_ENA_P 0x04
1298#define TIN_SEL_P 0x05
1299#define OUT_DIS_P 0x06
1300#define CLK_SEL_P 0x07
1301#define TOGGLE_HI_P 0x08
1302#define EMU_RUN_P 0x09
1303#define ERR_TYP_P0 0x0E
1304#define ERR_TYP_P1 0x0F
1305
1306/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
1307
1308/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1309#define PF0 0x0001
1310#define PF1 0x0002
1311#define PF2 0x0004
1312#define PF3 0x0008
1313#define PF4 0x0010
1314#define PF5 0x0020
1315#define PF6 0x0040
1316#define PF7 0x0080
1317#define PF8 0x0100
1318#define PF9 0x0200
1319#define PF10 0x0400
1320#define PF11 0x0800
1321#define PF12 0x1000
1322#define PF13 0x2000
1323#define PF14 0x4000
1324#define PF15 0x8000
1325
1326/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
1327#define PF0_P 0
1328#define PF1_P 1
1329#define PF2_P 2
1330#define PF3_P 3
1331#define PF4_P 4
1332#define PF5_P 5
1333#define PF6_P 6
1334#define PF7_P 7
1335#define PF8_P 8
1336#define PF9_P 9
1337#define PF10_P 10
1338#define PF11_P 11
1339#define PF12_P 12
1340#define PF13_P 13
1341#define PF14_P 14
1342#define PF15_P 15
1343
1344/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
1345
1346/* SPI_CTL Masks */
1347#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
1348#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
1349#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
1350#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
1351#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
1352#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
1353#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
1354#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
1355#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
1356#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
1357#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
1358#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
1359
1360/* SPI_FLG Masks */
1361#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1362#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1363#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1364#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1365#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1366#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1367#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1368#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1369#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1370#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1371#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1372#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1373#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1374#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1375
1376/* SPI_FLG Bit Positions */
1377#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1378#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1379#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1380#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1381#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1382#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1383#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1384#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1385#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1386#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1387#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1388#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1389#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1390#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1391
1392/* SPI_STAT Masks */
1393#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
1394#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
1395#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
1396#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
1397#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
1398#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
1399#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
1400
1401/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
1402
1403/* AMGCTL Masks */
1404#define AMCKEN 0x0001 /* Enable CLKOUT */
1405#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
1406#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
1407#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
1408#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
1409#define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */
1410#define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */
1411#define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */
1412#define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */
1413
1414/* AMGCTL Bit Positions */
1415#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
1416#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
1417#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
1418#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
1419#define B0_PEN_P 0x004 /* Enable 16-bit packing Bank 0 */
1420#define B1_PEN_P 0x005 /* Enable 16-bit packing Bank 1 */
1421#define B2_PEN_P 0x006 /* Enable 16-bit packing Bank 2 */
1422#define B3_PEN_P 0x007 /* Enable 16-bit packing Bank 3 */
1423
1424/* AMBCTL0 Masks */
1425#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
1426#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
1427#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
1428#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
1429#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
1430#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
1431#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
1432#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
1433#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
1434#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
1435#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
1436#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
1437#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
1438#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
1439#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
1440#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
1441#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
1442#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
1443#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
1444#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
1445#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
1446#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
1447#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
1448#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
1449#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
1450#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
1451#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
1452#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
1453#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
1454#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
1455#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
1456#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
1457#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
1458#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
1459#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
1460#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
1461#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
1462#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
1463#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
1464#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
1465#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
1466#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
1467#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
1468#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
1469#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
1470#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
1471#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
1472#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
1473#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
1474#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
1475#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1476#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1477#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1478#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1479#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1480#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1481#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1482#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1483#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
1484#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
1485#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
1486#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
1487#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
1488#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
1489#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
1490#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
1491#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
1492#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
1493#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
1494#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
1495#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
1496#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
1497#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
1498#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
1499#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
1500#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
1501#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
1502#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
1503#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
1504#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
1505#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
1506#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
1507#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
1508#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
1509#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
1510#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
1511#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
1512#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
1513
1514/* AMBCTL1 Masks */
1515#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
1516#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
1517#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
1518#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
1519#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
1520#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
1521#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1522#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1523#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1524#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1525#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1526#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1527#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1528#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1529#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
1530#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
1531#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
1532#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
1533#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
1534#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
1535#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
1536#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
1537#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
1538#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
1539#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
1540#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
1541#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
1542#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
1543#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
1544#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
1545#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
1546#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
1547#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
1548#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
1549#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
1550#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
1551#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
1552#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
1553#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
1554#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
1555#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
1556#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
1557#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
1558#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
1559#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
1560#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
1561#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
1562#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
1563#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
1564#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
1565#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1566#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1567#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1568#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1569#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1570#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1571#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1572#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1573#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
1574#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
1575#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
1576#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
1577#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
1578#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
1579#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
1580#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
1581#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
1582#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
1583#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
1584#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
1585#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
1586#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
1587#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
1588#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
1589#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
1590#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
1591#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
1592#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
1593#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
1594#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
1595#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
1596#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
1597#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
1598#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
1599#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
1600#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
1601#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
1602#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
1603
1604/* ********************** SDRAM CONTROLLER MASKS *************************** */
1605
1606/* EBIU_SDGCTL Masks */
1607#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
1608#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
1609#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
1610#define PFE 0x00000010 /* Enable SDRAM prefetch */
1611#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
1612#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1613#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1614#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1615#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1616#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1617#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1618#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1619#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1620#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1621#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1622#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1623#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1624#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1625#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1626#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1627#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1628#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1629#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1630#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1631#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1632#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1633#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1634#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1635#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1636#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1637#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1638#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1639#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1640#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1641#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1642#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1643#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1644#define PUPSD 0x00200000 /*Power-up start delay */
1645#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
1646#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
1647#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
1648#define EBUFE 0x02000000 /* Enable external buffering timing */
1649#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
1650#define EMREN 0x10000000 /* Extended mode register enable */
1651#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
1652#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
1653
1654/* EBIU_SDBCTL Masks */
1655#define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */
1656#define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1657#define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */
1658#define EB0_SZ_64 0x00000004 /* SDRAM external bank size = 64MB */
1659#define EB0_SZ_128 0x00000006 /* SDRAM external bank size = 128MB */
1660#define EB0_CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1661#define EB0_CAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
1662#define EB0_CAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
1663#define EB0_CAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
1664
1665#define EB1_E 0x00000100 /* Enable SDRAM external bank 1 */
1666#define EB1__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1667#define EB1__SZ_32 0x00000200 /* SDRAM external bank size = 32MB */
1668#define EB1__SZ_64 0x00000400 /* SDRAM external bank size = 64MB */
1669#define EB1__SZ_128 0x00000600 /* SDRAM external bank size = 128MB */
1670#define EB1__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1671#define EB1__CAW_9 0x00001000 /* SDRAM external bank column address width = 9 bits */
1672#define EB1__CAW_10 0x00002000 /* SDRAM external bank column address width = 9 bits */
1673#define EB1__CAW_11 0x00003000 /* SDRAM external bank column address width = 9 bits */
1674
1675#define EB2__E 0x00010000 /* Enable SDRAM external bank 2 */
1676#define EB2__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1677#define EB2__SZ_32 0x00020000 /* SDRAM external bank size = 32MB */
1678#define EB2__SZ_64 0x00040000 /* SDRAM external bank size = 64MB */
1679#define EB2__SZ_128 0x00060000 /* SDRAM external bank size = 128MB */
1680#define EB2__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1681#define EB2__CAW_9 0x00100000 /* SDRAM external bank column address width = 9 bits */
1682#define EB2__CAW_10 0x00200000 /* SDRAM external bank column address width = 9 bits */
1683#define EB2__CAW_11 0x00300000 /* SDRAM external bank column address width = 9 bits */
1684
1685#define EB3__E 0x01000000 /* Enable SDRAM external bank 3 */
1686#define EB3__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1687#define EB3__SZ_32 0x02000000 /* SDRAM external bank size = 32MB */
1688#define EB3__SZ_64 0x04000000 /* SDRAM external bank size = 64MB */
1689#define EB3__SZ_128 0x06000000 /* SDRAM external bank size = 128MB */
1690#define EB3__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1691#define EB3__CAW_9 0x10000000 /* SDRAM external bank column address width = 9 bits */
1692#define EB3__CAW_10 0x20000000 /* SDRAM external bank column address width = 9 bits */
1693#define EB3__CAW_11 0x30000000 /* SDRAM external bank column address width = 9 bits */
1694
1695/* EBIU_SDSTAT Masks */
1696#define SDCI 0x00000001 /* SDRAM controller is idle */
1697#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
1698#define SDPUA 0x00000004 /* SDRAM power up active */
1699#define SDRS 0x00000008 /* SDRAM is in reset state */
1700#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1701#define BGSTAT 0x00000020 /* Bus granted */
1702
1703/*VR_CTL Masks*/
1704#define WAKE 0x100
1705#define VLEV_6 0x60
1706#define VLEV_7 0x70
1707#define VLEV_8 0x80
1708#define VLEV_9 0x90
1709#define VLEV_10 0xA0
1710#define VLEV_11 0xB0
1711#define VLEV_12 0xC0
1712#define VLEV_13 0xD0
1713#define VLEV_14 0xE0
1714#define VLEV_15 0xF0
1715#define FREQ_3 0x03
1716
1717#endif /* _DEF_BF561_H */
diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h
new file mode 100644
index 000000000000..21d982003e75
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/dma.h
@@ -0,0 +1,35 @@
1/*****************************************************************************
2*
3* BF-533/2/1 Specific Declarations
4*
5****************************************************************************/
6
7#ifndef _MACH_DMA_H_
8#define _MACH_DMA_H_
9
10#define MAX_BLACKFIN_DMA_CHANNEL 36
11
12#define CH_PPI0 0
13#define CH_PPI (CH_PPI0)
14#define CH_PPI1 1
15#define CH_SPORT0_RX 12
16#define CH_SPORT0_TX 13
17#define CH_SPORT1_RX 14
18#define CH_SPORT1_TX 15
19#define CH_SPI 16
20#define CH_UART_RX 17
21#define CH_UART_TX 18
22#define CH_MEM_STREAM0_DEST 24 /* TX */
23#define CH_MEM_STREAM0_SRC 25 /* RX */
24#define CH_MEM_STREAM1_DEST 26 /* TX */
25#define CH_MEM_STREAM1_SRC 27 /* RX */
26#define CH_MEM_STREAM2_DEST 28
27#define CH_MEM_STREAM2_SRC 29
28#define CH_MEM_STREAM3_SRC 30
29#define CH_MEM_STREAM3_DEST 31
30#define CH_IMEM_STREAM0_DEST 32
31#define CH_IMEM_STREAM0_SRC 33
32#define CH_IMEM_STREAM1_SRC 34
33#define CH_IMEM_STREAM1_DEST 35
34
35#endif
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h
new file mode 100644
index 000000000000..a753ce720d74
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/irq.h
@@ -0,0 +1,450 @@
1
2/*
3 * File: include/asm-blackfin/mach-bf561/irq.h
4 * Based on:
5 * Author:
6 *
7 * Created:
8 * Description:
9 *
10 * Rev:
11 *
12 * Modified:
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _BF561_IRQ_H_
33#define _BF561_IRQ_H_
34
35/***********************************************************************
36 * Interrupt source definitions:
37 Event Source Core Event Name IRQ No
38 (highest priority)
39 Emulation Events EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47 PLL Wakeup Interrupt IVG7 7
48 DMA1 Error (generic) IVG7 8
49 DMA2 Error (generic) IVG7 9
50 IMDMA Error (generic) IVG7 10
51 PPI1 Error Interrupt IVG7 11
52 PPI2 Error Interrupt IVG7 12
53 SPORT0 Error Interrupt IVG7 13
54 SPORT1 Error Interrupt IVG7 14
55 SPI Error Interrupt IVG7 15
56 UART Error Interrupt IVG7 16
57 Reserved Interrupt IVG7 17
58
59 DMA1 0 Interrupt(PPI1) IVG8 18
60 DMA1 1 Interrupt(PPI2) IVG8 19
61 DMA1 2 Interrupt IVG8 20
62 DMA1 3 Interrupt IVG8 21
63 DMA1 4 Interrupt IVG8 22
64 DMA1 5 Interrupt IVG8 23
65 DMA1 6 Interrupt IVG8 24
66 DMA1 7 Interrupt IVG8 25
67 DMA1 8 Interrupt IVG8 26
68 DMA1 9 Interrupt IVG8 27
69 DMA1 10 Interrupt IVG8 28
70 DMA1 11 Interrupt IVG8 29
71
72 DMA2 0 (SPORT0 RX) IVG9 30
73 DMA2 1 (SPORT0 TX) IVG9 31
74 DMA2 2 (SPORT1 RX) IVG9 32
75 DMA2 3 (SPORT2 TX) IVG9 33
76 DMA2 4 (SPI) IVG9 34
77 DMA2 5 (UART RX) IVG9 35
78 DMA2 6 (UART TX) IVG9 36
79 DMA2 7 Interrupt IVG9 37
80 DMA2 8 Interrupt IVG9 38
81 DMA2 9 Interrupt IVG9 39
82 DMA2 10 Interrupt IVG9 40
83 DMA2 11 Interrupt IVG9 41
84
85 TIMER 0 Interrupt IVG10 42
86 TIMER 1 Interrupt IVG10 43
87 TIMER 2 Interrupt IVG10 44
88 TIMER 3 Interrupt IVG10 45
89 TIMER 4 Interrupt IVG10 46
90 TIMER 5 Interrupt IVG10 47
91 TIMER 6 Interrupt IVG10 48
92 TIMER 7 Interrupt IVG10 49
93 TIMER 8 Interrupt IVG10 50
94 TIMER 9 Interrupt IVG10 51
95 TIMER 10 Interrupt IVG10 52
96 TIMER 11 Interrupt IVG10 53
97
98 Programmable Flags0 A (8) IVG11 54
99 Programmable Flags0 B (8) IVG11 55
100 Programmable Flags1 A (8) IVG11 56
101 Programmable Flags1 B (8) IVG11 57
102 Programmable Flags2 A (8) IVG11 58
103 Programmable Flags2 B (8) IVG11 59
104
105 MDMA1 0 write/read INT IVG8 60
106 MDMA1 1 write/read INT IVG8 61
107
108 MDMA2 0 write/read INT IVG9 62
109 MDMA2 1 write/read INT IVG9 63
110
111 IMDMA 0 write/read INT IVG12 64
112 IMDMA 1 write/read INT IVG12 65
113
114 Watch Dog Timer IVG13 66
115
116 Reserved interrupt IVG7 67
117 Reserved interrupt IVG7 68
118 Supplemental interrupt 0 IVG7 69
119 supplemental interrupt 1 IVG7 70
120
121 Software Interrupt 1 IVG14 71
122 Software Interrupt 2 IVG15 72 *
123 (lowest priority)
124 **********************************************************************/
125
126#define SYS_IRQS 72
127#define NR_PERI_INTS 64
128
129/*
130 * The ABSTRACT IRQ definitions
131 * the first seven of the following are fixed,
132 * the rest you change if you need to.
133 */
134/* IVG 0-6*/
135#define IRQ_EMU 0 /* Emulation */
136#define IRQ_RST 1 /* Reset */
137#define IRQ_NMI 2 /* Non Maskable Interrupt */
138#define IRQ_EVX 3 /* Exception */
139#define IRQ_UNUSED 4 /* Reserved interrupt */
140#define IRQ_HWERR 5 /* Hardware Error */
141#define IRQ_CORETMR 6 /* Core timer */
142
143#define IVG_BASE 7
144/* IVG 7 */
145#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */
146#define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */
147#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
148#define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */
149#define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */
150#define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */
151#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
152#define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */
153#define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */
154#define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */
155#define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */
156#define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */
157#define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */
158/* IVG 8 */
159#define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */
160#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
161#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
162#define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */
163#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
164#define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */
165#define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */
166#define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */
167#define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */
168#define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */
169#define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */
170#define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */
171#define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */
172#define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */
173#define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */
174/* IVG 9 */
175#define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */
176#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
177#define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */
178#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
179#define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */
180#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
181#define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */
182#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
183#define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */
184#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
185#define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */
186#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
187#define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */
188#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
189#define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */
190#define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */
191#define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */
192#define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */
193#define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */
194/* IVG 10 */
195#define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */
196#define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */
197#define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */
198#define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */
199#define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */
200#define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */
201#define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */
202#define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */
203#define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */
204#define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */
205#define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */
206#define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */
207/* IVG 11 */
208#define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */
209#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
210#define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */
211#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
212#define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */
213#define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */
214#define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */
215#define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */
216/* IVG 8 */
217#define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */
218#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
219#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
220#define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */
221#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
222#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
223/* IVG 9 */
224#define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */
225#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
226#define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */
227#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
228/* IVG 12 */
229#define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */
230#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
231#define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */
232#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
233/* IVG 13 */
234#define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */
235/* IVG 7 */
236#define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */
237#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
238#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */
239#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */
240#define IRQ_SW_INT1 71 /* Software Interrupt 1 */
241#define IRQ_SW_INT2 72 /* Software Interrupt 2 */
242 /* reserved for SYSCALL */
243#define IRQ_PF0 73
244#define IRQ_PF1 74
245#define IRQ_PF2 75
246#define IRQ_PF3 76
247#define IRQ_PF4 77
248#define IRQ_PF5 78
249#define IRQ_PF6 79
250#define IRQ_PF7 80
251#define IRQ_PF8 81
252#define IRQ_PF9 82
253#define IRQ_PF10 83
254#define IRQ_PF11 84
255#define IRQ_PF12 85
256#define IRQ_PF13 86
257#define IRQ_PF14 87
258#define IRQ_PF15 88
259#define IRQ_PF16 89
260#define IRQ_PF17 90
261#define IRQ_PF18 91
262#define IRQ_PF19 92
263#define IRQ_PF20 93
264#define IRQ_PF21 94
265#define IRQ_PF22 95
266#define IRQ_PF23 96
267#define IRQ_PF24 97
268#define IRQ_PF25 98
269#define IRQ_PF26 99
270#define IRQ_PF27 100
271#define IRQ_PF28 101
272#define IRQ_PF29 102
273#define IRQ_PF30 103
274#define IRQ_PF31 104
275#define IRQ_PF32 105
276#define IRQ_PF33 106
277#define IRQ_PF34 107
278#define IRQ_PF35 108
279#define IRQ_PF36 109
280#define IRQ_PF37 110
281#define IRQ_PF38 111
282#define IRQ_PF39 112
283#define IRQ_PF40 113
284#define IRQ_PF41 114
285#define IRQ_PF42 115
286#define IRQ_PF43 116
287#define IRQ_PF44 117
288#define IRQ_PF45 118
289#define IRQ_PF46 119
290#define IRQ_PF47 120
291
292#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
293#define NR_IRQS (IRQ_PF47 + 1)
294#else
295#define NR_IRQS SYS_IRQS
296#endif
297
298#define IVG7 7
299#define IVG8 8
300#define IVG9 9
301#define IVG10 10
302#define IVG11 11
303#define IVG12 12
304#define IVG13 13
305#define IVG14 14
306#define IVG15 15
307
308/*
309 * DEFAULT PRIORITIES:
310 */
311
312#define CONFIG_DEF_PLL_WAKEUP 7
313#define CONFIG_DEF_DMA1_ERROR 7
314#define CONFIG_DEF_DMA2_ERROR 7
315#define CONFIG_DEF_IMDMA_ERROR 7
316#define CONFIG_DEF_PPI1_ERROR 7
317#define CONFIG_DEF_PPI2_ERROR 7
318#define CONFIG_DEF_SPORT0_ERROR 7
319#define CONFIG_DEF_SPORT1_ERROR 7
320#define CONFIG_DEF_SPI_ERROR 7
321#define CONFIG_DEF_UART_ERROR 7
322#define CONFIG_DEF_RESERVED_ERROR 7
323#define CONFIG_DEF_DMA1_0 8
324#define CONFIG_DEF_DMA1_1 8
325#define CONFIG_DEF_DMA1_2 8
326#define CONFIG_DEF_DMA1_3 8
327#define CONFIG_DEF_DMA1_4 8
328#define CONFIG_DEF_DMA1_5 8
329#define CONFIG_DEF_DMA1_6 8
330#define CONFIG_DEF_DMA1_7 8
331#define CONFIG_DEF_DMA1_8 8
332#define CONFIG_DEF_DMA1_9 8
333#define CONFIG_DEF_DMA1_10 8
334#define CONFIG_DEF_DMA1_11 8
335#define CONFIG_DEF_DMA2_0 9
336#define CONFIG_DEF_DMA2_1 9
337#define CONFIG_DEF_DMA2_2 9
338#define CONFIG_DEF_DMA2_3 9
339#define CONFIG_DEF_DMA2_4 9
340#define CONFIG_DEF_DMA2_5 9
341#define CONFIG_DEF_DMA2_6 9
342#define CONFIG_DEF_DMA2_7 9
343#define CONFIG_DEF_DMA2_8 9
344#define CONFIG_DEF_DMA2_9 9
345#define CONFIG_DEF_DMA2_10 9
346#define CONFIG_DEF_DMA2_11 9
347#define CONFIG_DEF_TIMER0 10
348#define CONFIG_DEF_TIMER1 10
349#define CONFIG_DEF_TIMER2 10
350#define CONFIG_DEF_TIMER3 10
351#define CONFIG_DEF_TIMER4 10
352#define CONFIG_DEF_TIMER5 10
353#define CONFIG_DEF_TIMER6 10
354#define CONFIG_DEF_TIMER7 10
355#define CONFIG_DEF_TIMER8 10
356#define CONFIG_DEF_TIMER9 10
357#define CONFIG_DEF_TIMER10 10
358#define CONFIG_DEF_TIMER11 10
359#define CONFIG_DEF_PROG0_INTA 11
360#define CONFIG_DEF_PROG0_INTB 11
361#define CONFIG_DEF_PROG1_INTA 11
362#define CONFIG_DEF_PROG1_INTB 11
363#define CONFIG_DEF_PROG2_INTA 11
364#define CONFIG_DEF_PROG2_INTB 11
365#define CONFIG_DEF_DMA1_WRRD0 8
366#define CONFIG_DEF_DMA1_WRRD1 8
367#define CONFIG_DEF_DMA2_WRRD0 9
368#define CONFIG_DEF_DMA2_WRRD1 9
369#define CONFIG_DEF_IMDMA_WRRD0 12
370#define CONFIG_DEF_IMDMA_WRRD1 12
371#define CONFIG_DEF_WATCH 13
372#define CONFIG_DEF_RESERVED_1 7
373#define CONFIG_DEF_RESERVED_2 7
374#define CONFIG_DEF_SUPPLE_0 7
375#define CONFIG_DEF_SUPPLE_1 7
376
377/* IAR0 BIT FIELDS */
378#define IRQ_PLL_WAKEUP_POS 0
379#define IRQ_DMA1_ERROR_POS 4
380#define IRQ_DMA2_ERROR_POS 8
381#define IRQ_IMDMA_ERROR_POS 12
382#define IRQ_PPI0_ERROR_POS 16
383#define IRQ_PPI1_ERROR_POS 20
384#define IRQ_SPORT0_ERROR_POS 24
385#define IRQ_SPORT1_ERROR_POS 28
386/* IAR1 BIT FIELDS */
387#define IRQ_SPI_ERROR_POS 0
388#define IRQ_UART_ERROR_POS 4
389#define IRQ_RESERVED_ERROR_POS 8
390#define IRQ_DMA1_0_POS 12
391#define IRQ_DMA1_1_POS 16
392#define IRQ_DMA1_2_POS 20
393#define IRQ_DMA1_3_POS 24
394#define IRQ_DMA1_4_POS 28
395/* IAR2 BIT FIELDS */
396#define IRQ_DMA1_5_POS 0
397#define IRQ_DMA1_6_POS 4
398#define IRQ_DMA1_7_POS 8
399#define IRQ_DMA1_8_POS 12
400#define IRQ_DMA1_9_POS 16
401#define IRQ_DMA1_10_POS 20
402#define IRQ_DMA1_11_POS 24
403#define IRQ_DMA2_0_POS 28
404/* IAR3 BIT FIELDS */
405#define IRQ_DMA2_1_POS 0
406#define IRQ_DMA2_2_POS 4
407#define IRQ_DMA2_3_POS 8
408#define IRQ_DMA2_4_POS 12
409#define IRQ_DMA2_5_POS 16
410#define IRQ_DMA2_6_POS 20
411#define IRQ_DMA2_7_POS 24
412#define IRQ_DMA2_8_POS 28
413/* IAR4 BIT FIELDS */
414#define IRQ_DMA2_9_POS 0
415#define IRQ_DMA2_10_POS 4
416#define IRQ_DMA2_11_POS 8
417#define IRQ_TIMER0_POS 12
418#define IRQ_TIMER1_POS 16
419#define IRQ_TIMER2_POS 20
420#define IRQ_TIMER3_POS 24
421#define IRQ_TIMER4_POS 28
422/* IAR5 BIT FIELDS */
423#define IRQ_TIMER5_POS 0
424#define IRQ_TIMER6_POS 4
425#define IRQ_TIMER7_POS 8
426#define IRQ_TIMER8_POS 12
427#define IRQ_TIMER9_POS 16
428#define IRQ_TIMER10_POS 20
429#define IRQ_TIMER11_POS 24
430#define IRQ_PROG0_INTA_POS 28
431/* IAR6 BIT FIELDS */
432#define IRQ_PROG0_INTB_POS 0
433#define IRQ_PROG1_INTA_POS 4
434#define IRQ_PROG1_INTB_POS 8
435#define IRQ_PROG2_INTA_POS 12
436#define IRQ_PROG2_INTB_POS 16
437#define IRQ_DMA1_WRRD0_POS 20
438#define IRQ_DMA1_WRRD1_POS 24
439#define IRQ_DMA2_WRRD0_POS 28
440/* IAR7 BIT FIELDS */
441#define IRQ_DMA2_WRRD1_POS 0
442#define IRQ_IMDMA_WRRD0_POS 4
443#define IRQ_IMDMA_WRRD1_POS 8
444#define IRQ_WDTIMER_POS 12
445#define IRQ_RESERVED_1_POS 16
446#define IRQ_RESERVED_2_POS 20
447#define IRQ_SUPPLE_0_POS 24
448#define IRQ_SUPPLE_1_POS 28
449
450#endif /* _BF561_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf561/mem_init.h b/include/asm-blackfin/mach-bf561/mem_init.h
new file mode 100644
index 000000000000..439a5895b346
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/mem_init.h
@@ -0,0 +1,322 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC8M32B2B5_7)
32#if (CONFIG_SCLK_HZ > 119402985)
33#define SDRAM_tRP TRP_2
34#define SDRAM_tRP_num 2
35#define SDRAM_tRAS TRAS_7
36#define SDRAM_tRAS_num 7
37#define SDRAM_tRCD TRCD_2
38#define SDRAM_tWR TWR_2
39#endif
40#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
41#define SDRAM_tRP TRP_2
42#define SDRAM_tRP_num 2
43#define SDRAM_tRAS TRAS_6
44#define SDRAM_tRAS_num 6
45#define SDRAM_tRCD TRCD_2
46#define SDRAM_tWR TWR_2
47#endif
48#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
49#define SDRAM_tRP TRP_2
50#define SDRAM_tRP_num 2
51#define SDRAM_tRAS TRAS_5
52#define SDRAM_tRAS_num 5
53#define SDRAM_tRCD TRCD_2
54#define SDRAM_tWR TWR_2
55#endif
56#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
57#define SDRAM_tRP TRP_2
58#define SDRAM_tRP_num 2
59#define SDRAM_tRAS TRAS_4
60#define SDRAM_tRAS_num 4
61#define SDRAM_tRCD TRCD_2
62#define SDRAM_tWR TWR_2
63#endif
64#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
65#define SDRAM_tRP TRP_2
66#define SDRAM_tRP_num 2
67#define SDRAM_tRAS TRAS_3
68#define SDRAM_tRAS_num 3
69#define SDRAM_tRCD TRCD_2
70#define SDRAM_tWR TWR_2
71#endif
72#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
73#define SDRAM_tRP TRP_1
74#define SDRAM_tRP_num 1
75#define SDRAM_tRAS TRAS_4
76#define SDRAM_tRAS_num 3
77#define SDRAM_tRCD TRCD_1
78#define SDRAM_tWR TWR_2
79#endif
80#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
81#define SDRAM_tRP TRP_1
82#define SDRAM_tRP_num 1
83#define SDRAM_tRAS TRAS_3
84#define SDRAM_tRAS_num 3
85#define SDRAM_tRCD TRCD_1
86#define SDRAM_tWR TWR_2
87#endif
88#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
89#define SDRAM_tRP TRP_1
90#define SDRAM_tRP_num 1
91#define SDRAM_tRAS TRAS_2
92#define SDRAM_tRAS_num 2
93#define SDRAM_tRCD TRCD_1
94#define SDRAM_tWR TWR_2
95#endif
96#if (CONFIG_SCLK_HZ <= 29850746)
97#define SDRAM_tRP TRP_1
98#define SDRAM_tRP_num 1
99#define SDRAM_tRAS TRAS_1
100#define SDRAM_tRAS_num 1
101#define SDRAM_tRCD TRCD_1
102#define SDRAM_tWR TWR_2
103#endif
104#endif
105
106#if (CONFIG_MEM_MT48LC16M16A2TG_75)
107 /*SDRAM INFORMATION: */
108#define SDRAM_Tref 64 /* Refresh period in milliseconds */
109#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
110#define SDRAM_CL CL_3
111#endif
112
113#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
114 /*SDRAM INFORMATION: */
115#define SDRAM_Tref 64 /* Refresh period in milliseconds */
116#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
117#define SDRAM_CL CL_3
118#endif
119
120#if (CONFIG_MEM_MT48LC8M32B2B5_7)
121 /*SDRAM INFORMATION: */
122#define SDRAM_Tref 64 /* Refresh period in milliseconds */
123#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
124#define SDRAM_CL CL_3
125#endif
126
127#if (CONFIG_MEM_GENERIC_BOARD)
128 /*SDRAM INFORMATION: Modify this for your board */
129#define SDRAM_Tref 64 /* Refresh period in milliseconds */
130#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
131#define SDRAM_CL CL_3
132#endif
133
134#if (CONFIG_MEM_SIZE == 128)
135#define SDRAM_SIZE EB0_SZ_128
136#endif
137#if (CONFIG_MEM_SIZE == 64)
138#define SDRAM_SIZE EB0_SZ_64
139#endif
140#if ( CONFIG_MEM_SIZE == 32)
141#define SDRAM_SIZE EB0_SZ_32
142#endif
143#if (CONFIG_MEM_SIZE == 16)
144#define SDRAM_SIZE EB0_SZ_16
145#endif
146#if (CONFIG_MEM_ADD_WIDTH == 11)
147#define SDRAM_WIDTH EB0_CAW_11
148#endif
149#if (CONFIG_MEM_ADD_WIDTH == 10)
150#define SDRAM_WIDTH EB0_CAW_10
151#endif
152#if (CONFIG_MEM_ADD_WIDTH == 9)
153#define SDRAM_WIDTH EB0_CAW_9
154#endif
155#if (CONFIG_MEM_ADD_WIDTH == 8)
156#define SDRAM_WIDTH EB0_CAW_8
157#endif
158
159#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EB0_E)
160
161/* Equation from section 17 (p17-46) of BF533 HRM */
162#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
163
164/* Enable SCLK Out */
165#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
166
167#if defined CONFIG_CLKIN_HALF
168#define CLKIN_HALF 1
169#else
170#define CLKIN_HALF 0
171#endif
172
173#if defined CONFIG_PLL_BYPASS
174#define PLL_BYPASS 1
175#else
176#define PLL_BYPASS 0
177#endif
178
179/***************************************Currently Not Being Used *********************************/
180#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
181#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
182#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
183#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
184#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
185
186#if (flash_EBIU_AMBCTL_TT > 3)
187#define flash_EBIU_AMBCTL0_TT B0TT_4
188#endif
189#if (flash_EBIU_AMBCTL_TT == 3)
190#define flash_EBIU_AMBCTL0_TT B0TT_3
191#endif
192#if (flash_EBIU_AMBCTL_TT == 2)
193#define flash_EBIU_AMBCTL0_TT B0TT_2
194#endif
195#if (flash_EBIU_AMBCTL_TT < 2)
196#define flash_EBIU_AMBCTL0_TT B0TT_1
197#endif
198
199#if (flash_EBIU_AMBCTL_ST > 3)
200#define flash_EBIU_AMBCTL0_ST B0ST_4
201#endif
202#if (flash_EBIU_AMBCTL_ST == 3)
203#define flash_EBIU_AMBCTL0_ST B0ST_3
204#endif
205#if (flash_EBIU_AMBCTL_ST == 2)
206#define flash_EBIU_AMBCTL0_ST B0ST_2
207#endif
208#if (flash_EBIU_AMBCTL_ST < 2)
209#define flash_EBIU_AMBCTL0_ST B0ST_1
210#endif
211
212#if (flash_EBIU_AMBCTL_HT > 2)
213#define flash_EBIU_AMBCTL0_HT B0HT_3
214#endif
215#if (flash_EBIU_AMBCTL_HT == 2)
216#define flash_EBIU_AMBCTL0_HT B0HT_2
217#endif
218#if (flash_EBIU_AMBCTL_HT == 1)
219#define flash_EBIU_AMBCTL0_HT B0HT_1
220#endif
221#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
222#define flash_EBIU_AMBCTL0_HT B0HT_0
223#endif
224#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
225#define flash_EBIU_AMBCTL0_HT B0HT_1
226#endif
227
228#if (flash_EBIU_AMBCTL_WAT > 14)
229#define flash_EBIU_AMBCTL0_WAT B0WAT_15
230#endif
231#if (flash_EBIU_AMBCTL_WAT == 14)
232#define flash_EBIU_AMBCTL0_WAT B0WAT_14
233#endif
234#if (flash_EBIU_AMBCTL_WAT == 13)
235#define flash_EBIU_AMBCTL0_WAT B0WAT_13
236#endif
237#if (flash_EBIU_AMBCTL_WAT == 12)
238#define flash_EBIU_AMBCTL0_WAT B0WAT_12
239#endif
240#if (flash_EBIU_AMBCTL_WAT == 11)
241#define flash_EBIU_AMBCTL0_WAT B0WAT_11
242#endif
243#if (flash_EBIU_AMBCTL_WAT == 10)
244#define flash_EBIU_AMBCTL0_WAT B0WAT_10
245#endif
246#if (flash_EBIU_AMBCTL_WAT == 9)
247#define flash_EBIU_AMBCTL0_WAT B0WAT_9
248#endif
249#if (flash_EBIU_AMBCTL_WAT == 8)
250#define flash_EBIU_AMBCTL0_WAT B0WAT_8
251#endif
252#if (flash_EBIU_AMBCTL_WAT == 7)
253#define flash_EBIU_AMBCTL0_WAT B0WAT_7
254#endif
255#if (flash_EBIU_AMBCTL_WAT == 6)
256#define flash_EBIU_AMBCTL0_WAT B0WAT_6
257#endif
258#if (flash_EBIU_AMBCTL_WAT == 5)
259#define flash_EBIU_AMBCTL0_WAT B0WAT_5
260#endif
261#if (flash_EBIU_AMBCTL_WAT == 4)
262#define flash_EBIU_AMBCTL0_WAT B0WAT_4
263#endif
264#if (flash_EBIU_AMBCTL_WAT == 3)
265#define flash_EBIU_AMBCTL0_WAT B0WAT_3
266#endif
267#if (flash_EBIU_AMBCTL_WAT == 2)
268#define flash_EBIU_AMBCTL0_WAT B0WAT_2
269#endif
270#if (flash_EBIU_AMBCTL_WAT == 1)
271#define flash_EBIU_AMBCTL0_WAT B0WAT_1
272#endif
273
274#if (flash_EBIU_AMBCTL_RAT > 14)
275#define flash_EBIU_AMBCTL0_RAT B0RAT_15
276#endif
277#if (flash_EBIU_AMBCTL_RAT == 14)
278#define flash_EBIU_AMBCTL0_RAT B0RAT_14
279#endif
280#if (flash_EBIU_AMBCTL_RAT == 13)
281#define flash_EBIU_AMBCTL0_RAT B0RAT_13
282#endif
283#if (flash_EBIU_AMBCTL_RAT == 12)
284#define flash_EBIU_AMBCTL0_RAT B0RAT_12
285#endif
286#if (flash_EBIU_AMBCTL_RAT == 11)
287#define flash_EBIU_AMBCTL0_RAT B0RAT_11
288#endif
289#if (flash_EBIU_AMBCTL_RAT == 10)
290#define flash_EBIU_AMBCTL0_RAT B0RAT_10
291#endif
292#if (flash_EBIU_AMBCTL_RAT == 9)
293#define flash_EBIU_AMBCTL0_RAT B0RAT_9
294#endif
295#if (flash_EBIU_AMBCTL_RAT == 8)
296#define flash_EBIU_AMBCTL0_RAT B0RAT_8
297#endif
298#if (flash_EBIU_AMBCTL_RAT == 7)
299#define flash_EBIU_AMBCTL0_RAT B0RAT_7
300#endif
301#if (flash_EBIU_AMBCTL_RAT == 6)
302#define flash_EBIU_AMBCTL0_RAT B0RAT_6
303#endif
304#if (flash_EBIU_AMBCTL_RAT == 5)
305#define flash_EBIU_AMBCTL0_RAT B0RAT_5
306#endif
307#if (flash_EBIU_AMBCTL_RAT == 4)
308#define flash_EBIU_AMBCTL0_RAT B0RAT_4
309#endif
310#if (flash_EBIU_AMBCTL_RAT == 3)
311#define flash_EBIU_AMBCTL0_RAT B0RAT_3
312#endif
313#if (flash_EBIU_AMBCTL_RAT == 2)
314#define flash_EBIU_AMBCTL0_RAT B0RAT_2
315#endif
316#if (flash_EBIU_AMBCTL_RAT == 1)
317#define flash_EBIU_AMBCTL0_RAT B0RAT_1
318#endif
319
320#define flash_EBIU_AMBCTL0 \
321 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
322 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h
new file mode 100644
index 000000000000..ebac9a8d838d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/mem_map.h
@@ -0,0 +1,75 @@
1/*
2 * Memory MAP
3 * Common header file for blackfin BF561 of processors.
4 */
5
6#ifndef _MEM_MAP_561_H_
7#define _MEM_MAP_561_H_
8
9#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
10#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
11
12/* Async Memory Banks */
13#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
14#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
15#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
16#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
17#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
18#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
19#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
20#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
21
22/* Level 1 Memory */
23
24#ifdef CONFIG_BLKFIN_CACHE
25#define BLKFIN_ICACHESIZE (16*1024)
26#else
27#define BLKFIN_ICACHESIZE (0*1024)
28#endif
29
30/* Memory Map for ADSP-BF561 processors */
31
32#ifdef CONFIG_BF561
33#define L1_CODE_START 0xFFA00000
34#define L1_DATA_A_START 0xFF800000
35#define L1_DATA_B_START 0xFF900000
36
37#define L1_CODE_LENGTH 0x4000
38
39#ifdef CONFIG_BLKFIN_DCACHE
40
41#ifdef CONFIG_BLKFIN_DCACHE_BANKA
42#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
43#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
44#define L1_DATA_B_LENGTH 0x8000
45#define BLKFIN_DCACHESIZE (16*1024)
46#define BLKFIN_DSUPBANKS 1
47#else
48#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
49#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
50#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
51#define BLKFIN_DCACHESIZE (32*1024)
52#define BLKFIN_DSUPBANKS 2
53#endif
54
55#else
56#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
57#define L1_DATA_A_LENGTH 0x8000
58#define L1_DATA_B_LENGTH 0x8000
59#define BLKFIN_DCACHESIZE (0*1024)
60#define BLKFIN_DSUPBANKS 0
61#endif /*CONFIG_BLKFIN_DCACHE*/
62#endif
63
64/* Level 2 Memory */
65#define L2_START 0xFEB00000
66#define L2_LENGTH 0x20000
67
68/* Scratch Pad Memory */
69
70#if defined(CONFIG_BF561)
71#define L1_SCRATCH_START 0xFFB00000
72#define L1_SCRATCH_LENGTH 0x1000
73#endif
74
75#endif /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
new file mode 100644
index 000000000000..22aa5e637993
--- /dev/null
+++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
@@ -0,0 +1,471 @@
1 /*
2 * File: include/asm-blackfin/mach-common/cdef_LPBlackfin.h
3 * Based on:
4 * Author: unknown
5 * COPYRIGHT 2005 Analog Devices
6 * Created: ?
7 * Description:
8 *
9 * Modified:
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING.
25 * If not, write to the Free Software Foundation,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29#ifndef _CDEF_LPBLACKFIN_H
30#define _CDEF_LPBLACKFIN_H
31
32/*#if !defined(__ADSPLPBLACKFIN__)
33#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
34#endif
35*/
36#include <asm/mach-common/def_LPBlackfin.h>
37
38/*Cache & SRAM Memory*/
39#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
40#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
41#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
42#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
43#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
44#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
45#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
46#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
47#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
48#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
49#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
50#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val)
51/*
52#define MMR_TIMEOUT 0xFFE00010
53*/
54#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
55#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0)
56#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val)
57#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
58#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1)
59#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val)
60#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
61#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2)
62#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val)
63#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3)
64#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3)
65#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val)
66#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4)
67#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4)
68#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val)
69#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5)
70#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5)
71#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val)
72#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6)
73#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6)
74#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6,val)
75#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7)
76#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7)
77#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7,val)
78#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8)
79#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8)
80#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8,val)
81#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9)
82#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9)
83#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9,val)
84#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10)
85#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10)
86#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10,val)
87#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11)
88#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11)
89#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11,val)
90#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12)
91#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12)
92#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12,val)
93#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13)
94#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13)
95#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13,val)
96#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14)
97#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14)
98#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14,val)
99#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15)
100#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15)
101#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15,val)
102#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
103#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
104#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0,val)
105#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
106#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
107#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1,val)
108#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
109#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
110#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2,val)
111#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
112#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
113#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3,val)
114#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
115#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
116#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4,val)
117#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
118#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
119#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5,val)
120#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
121#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
122#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6,val)
123#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
124#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
125#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7,val)
126#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
127#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
128#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8,val)
129#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
130#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
131#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9,val)
132#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
133#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
134#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10,val)
135#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
136#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
137#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11,val)
138#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
139#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
140#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12,val)
141#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
142#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
143#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13,val)
144#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
145#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
146#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14,val)
147#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
148#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
149#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15,val)
150#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
151#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
152#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND,val)
153/*
154#define DTEST_INDEX 0xFFE00304
155*/
156#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
157#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
158#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0,val)
159#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
160#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
161#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1,val)
162/*
163#define DTEST_DATA2 0xFFE00408
164#define DTEST_DATA3 0xFFE0040C
165*/
166#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
167#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
168#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
169#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
170#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
171#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val)
172#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
173#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
174#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR,val)
175#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0)
176#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0)
177#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0,val)
178#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1)
179#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1)
180#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1,val)
181#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2)
182#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2)
183#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2,val)
184#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3)
185#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3)
186#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3,val)
187#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4)
188#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4)
189#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4,val)
190#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5)
191#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5)
192#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5,val)
193#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6)
194#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6)
195#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6,val)
196#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7)
197#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7)
198#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7,val)
199#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8)
200#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8)
201#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8,val)
202#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9)
203#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9)
204#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9,val)
205#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10)
206#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10)
207#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10,val)
208#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11)
209#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11)
210#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11,val)
211#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12)
212#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12)
213#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12,val)
214#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13)
215#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13)
216#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13,val)
217#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14)
218#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14)
219#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14,val)
220#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15)
221#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15)
222#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15,val)
223#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
224#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
225#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0,val)
226#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
227#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
228#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1,val)
229#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
230#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
231#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2,val)
232#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
233#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
234#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3,val)
235#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
236#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
237#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4,val)
238#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
239#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
240#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5,val)
241#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
242#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
243#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6,val)
244#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
245#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
246#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7,val)
247#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
248#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
249#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8,val)
250#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
251#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
252#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9,val)
253#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
254#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
255#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10,val)
256#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
257#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
258#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11,val)
259#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
260#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
261#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12,val)
262#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
263#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
264#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13,val)
265#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
266#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
267#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val)
268#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
269#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
270#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val)
271#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
272#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
273#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val)
274#if 0
275#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
276#endif
277#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
278#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
279#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val)
280#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
281#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
282#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val)
283
284/* Event/Interrupt Registers*/
285
286#define pEVT0 ((volatile void **)EVT0)
287#define bfin_read_EVT0() bfin_read32(EVT0)
288#define bfin_write_EVT0(val) bfin_write32(EVT0,val)
289#define pEVT1 ((volatile void **)EVT1)
290#define bfin_read_EVT1() bfin_read32(EVT1)
291#define bfin_write_EVT1(val) bfin_write32(EVT1,val)
292#define pEVT2 ((volatile void **)EVT2)
293#define bfin_read_EVT2() bfin_read32(EVT2)
294#define bfin_write_EVT2(val) bfin_write32(EVT2,val)
295#define pEVT3 ((volatile void **)EVT3)
296#define bfin_read_EVT3() bfin_read32(EVT3)
297#define bfin_write_EVT3(val) bfin_write32(EVT3,val)
298#define pEVT4 ((volatile void **)EVT4)
299#define bfin_read_EVT4() bfin_read32(EVT4)
300#define bfin_write_EVT4(val) bfin_write32(EVT4,val)
301#define pEVT5 ((volatile void **)EVT5)
302#define bfin_read_EVT5() bfin_read32(EVT5)
303#define bfin_write_EVT5(val) bfin_write32(EVT5,val)
304#define pEVT6 ((volatile void **)EVT6)
305#define bfin_read_EVT6() bfin_read32(EVT6)
306#define bfin_write_EVT6(val) bfin_write32(EVT6,val)
307#define pEVT7 ((volatile void **)EVT7)
308#define bfin_read_EVT7() bfin_read32(EVT7)
309#define bfin_write_EVT7(val) bfin_write32(EVT7,val)
310#define pEVT8 ((volatile void **)EVT8)
311#define bfin_read_EVT8() bfin_read32(EVT8)
312#define bfin_write_EVT8(val) bfin_write32(EVT8,val)
313#define pEVT9 ((volatile void **)EVT9)
314#define bfin_read_EVT9() bfin_read32(EVT9)
315#define bfin_write_EVT9(val) bfin_write32(EVT9,val)
316#define pEVT10 ((volatile void **)EVT10)
317#define bfin_read_EVT10() bfin_read32(EVT10)
318#define bfin_write_EVT10(val) bfin_write32(EVT10,val)
319#define pEVT11 ((volatile void **)EVT11)
320#define bfin_read_EVT11() bfin_read32(EVT11)
321#define bfin_write_EVT11(val) bfin_write32(EVT11,val)
322#define pEVT12 ((volatile void **)EVT12)
323#define bfin_read_EVT12() bfin_read32(EVT12)
324#define bfin_write_EVT12(val) bfin_write32(EVT12,val)
325#define pEVT13 ((volatile void **)EVT13)
326#define bfin_read_EVT13() bfin_read32(EVT13)
327#define bfin_write_EVT13(val) bfin_write32(EVT13,val)
328#define pEVT14 ((volatile void **)EVT14)
329#define bfin_read_EVT14() bfin_read32(EVT14)
330#define bfin_write_EVT14(val) bfin_write32(EVT14,val)
331#define pEVT15 ((volatile void **)EVT15)
332#define bfin_read_EVT15() bfin_read32(EVT15)
333#define bfin_write_EVT15(val) bfin_write32(EVT15,val)
334#define pIMASK ((volatile unsigned long *)IMASK)
335#define bfin_read_IMASK() bfin_read32(IMASK)
336#define bfin_write_IMASK(val) bfin_write32(IMASK,val)
337#define pIPEND ((volatile unsigned long *)IPEND)
338#define bfin_read_IPEND() bfin_read32(IPEND)
339#define bfin_write_IPEND(val) bfin_write32(IPEND,val)
340#define pILAT ((volatile unsigned long *)ILAT)
341#define bfin_read_ILAT() bfin_read32(ILAT)
342#define bfin_write_ILAT(val) bfin_write32(ILAT,val)
343
344/*Core Timer Registers*/
345#define pTCNTL ((volatile unsigned long *)TCNTL)
346#define bfin_read_TCNTL() bfin_read32(TCNTL)
347#define bfin_write_TCNTL(val) bfin_write32(TCNTL,val)
348#define pTPERIOD ((volatile unsigned long *)TPERIOD)
349#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
350#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD,val)
351#define pTSCALE ((volatile unsigned long *)TSCALE)
352#define bfin_read_TSCALE() bfin_read32(TSCALE)
353#define bfin_write_TSCALE(val) bfin_write32(TSCALE,val)
354#define pTCOUNT ((volatile unsigned long *)TCOUNT)
355#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
356#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT,val)
357
358/*Debug/MP/Emulation Registers*/
359#define pDSPID ((volatile unsigned long *)DSPID)
360#define bfin_read_DSPID() bfin_read32(DSPID)
361#define bfin_write_DSPID(val) bfin_write32(DSPID,val)
362#define pDBGCTL ((volatile unsigned long *)DBGCTL)
363#define bfin_read_DBGCTL() bfin_read32(DBGCTL)
364#define bfin_write_DBGCTL(val) bfin_write32(DBGCTL,val)
365#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
366#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
367#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT,val)
368#define pEMUDAT ((volatile unsigned long *)EMUDAT)
369#define bfin_read_EMUDAT() bfin_read32(EMUDAT)
370#define bfin_write_EMUDAT(val) bfin_write32(EMUDAT,val)
371
372/*Trace Buffer Registers*/
373#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
374#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
375#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL,val)
376#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
377#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
378#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT,val)
379#define pTBUF ((volatile void **)TBUF)
380#define bfin_read_TBUF() bfin_read32(TBUF)
381#define bfin_write_TBUF(val) bfin_write32(TBUF,val)
382
383/*Watch Point Control Registers*/
384#define pWPIACTL ((volatile unsigned long *)WPIACTL)
385#define bfin_read_WPIACTL() bfin_read32(WPIACTL)
386#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL,val)
387#define pWPIA0 ((volatile void **)WPIA0)
388#define bfin_read_WPIA0() bfin_read32(WPIA0)
389#define bfin_write_WPIA0(val) bfin_write32(WPIA0,val)
390#define pWPIA1 ((volatile void **)WPIA1)
391#define bfin_read_WPIA1() bfin_read32(WPIA1)
392#define bfin_write_WPIA1(val) bfin_write32(WPIA1,val)
393#define pWPIA2 ((volatile void **)WPIA2)
394#define bfin_read_WPIA2() bfin_read32(WPIA2)
395#define bfin_write_WPIA2(val) bfin_write32(WPIA2,val)
396#define pWPIA3 ((volatile void **)WPIA3)
397#define bfin_read_WPIA3() bfin_read32(WPIA3)
398#define bfin_write_WPIA3(val) bfin_write32(WPIA3,val)
399#define pWPIA4 ((volatile void **)WPIA4)
400#define bfin_read_WPIA4() bfin_read32(WPIA4)
401#define bfin_write_WPIA4(val) bfin_write32(WPIA4,val)
402#define pWPIA5 ((volatile void **)WPIA5)
403#define bfin_read_WPIA5() bfin_read32(WPIA5)
404#define bfin_write_WPIA5(val) bfin_write32(WPIA5,val)
405#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
406#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0)
407#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0,val)
408#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
409#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1)
410#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1,val)
411#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
412#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2)
413#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2,val)
414#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
415#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3)
416#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3,val)
417#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
418#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4)
419#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4,val)
420#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
421#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5)
422#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5,val)
423#define pWPDACTL ((volatile unsigned long *)WPDACTL)
424#define bfin_read_WPDACTL() bfin_read32(WPDACTL)
425#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL,val)
426#define pWPDA0 ((volatile void **)WPDA0)
427#define bfin_read_WPDA0() bfin_read32(WPDA0)
428#define bfin_write_WPDA0(val) bfin_write32(WPDA0,val)
429#define pWPDA1 ((volatile void **)WPDA1)
430#define bfin_read_WPDA1() bfin_read32(WPDA1)
431#define bfin_write_WPDA1(val) bfin_write32(WPDA1,val)
432#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
433#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0)
434#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0,val)
435#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
436#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1)
437#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1,val)
438#define pWPSTAT ((volatile unsigned long *)WPSTAT)
439#define bfin_read_WPSTAT() bfin_read32(WPSTAT)
440#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT,val)
441
442/*Performance Monitor Registers*/
443#define pPFCTL ((volatile unsigned long *)PFCTL)
444#define bfin_read_PFCTL() bfin_read32(PFCTL)
445#define bfin_write_PFCTL(val) bfin_write32(PFCTL,val)
446#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
447#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
448#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0,val)
449#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
450#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
451#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val)
452
453/*
454#define IPRIO 0xFFE02110
455*/
456
457#if defined(CONFIG_BFIN_ALIVE_LED)
458#define pCONFIG_BFIN_ALIVE_LED_DPORT \
459 (volatile unsigned short *)CONFIG_BFIN_ALIVE_LED_DPORT
460#define pCONFIG_BFIN_ALIVE_LED_PORT \
461 (volatile unsigned short *)CONFIG_BFIN_ALIVE_LED_PORT
462#endif
463
464#if defined(CONFIG_BFIN_IDLE_LED)
465#define pCONFIG_BFIN_IDLE_LED_DPORT \
466 (volatile unsigned short *)CONFIG_BFIN_IDLE_LED_DPORT
467#define pCONFIG_BFIN_IDLE_LED_PORT \
468 (volatile unsigned short *)CONFIG_BFIN_IDLE_LED_PORT
469#endif
470
471#endif /* _CDEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/mach-common/context.S b/include/asm-blackfin/mach-common/context.S
new file mode 100644
index 000000000000..fd0ebe1862b8
--- /dev/null
+++ b/include/asm-blackfin/mach-common/context.S
@@ -0,0 +1,350 @@
1/*
2 * File: arch/blackfin/kernel/context.S
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30/*
31 * Code to save processor context.
32 * We even save the register which are preserved by a function call
33 * - r4, r5, r6, r7, p3, p4, p5
34 */
35.macro save_context_with_interrupts
36 [--sp] = SYSCFG;
37
38 [--sp] = P0; /*orig_p0*/
39 [--sp] = R0; /*orig_r0*/
40
41 [--sp] = ( R7:0, P5:0 );
42 [--sp] = fp;
43 [--sp] = usp;
44
45 [--sp] = i0;
46 [--sp] = i1;
47 [--sp] = i2;
48 [--sp] = i3;
49
50 [--sp] = m0;
51 [--sp] = m1;
52 [--sp] = m2;
53 [--sp] = m3;
54
55 [--sp] = l0;
56 [--sp] = l1;
57 [--sp] = l2;
58 [--sp] = l3;
59
60 [--sp] = b0;
61 [--sp] = b1;
62 [--sp] = b2;
63 [--sp] = b3;
64 [--sp] = a0.x;
65 [--sp] = a0.w;
66 [--sp] = a1.x;
67 [--sp] = a1.w;
68
69 [--sp] = LC0;
70 [--sp] = LC1;
71 [--sp] = LT0;
72 [--sp] = LT1;
73 [--sp] = LB0;
74 [--sp] = LB1;
75
76 [--sp] = ASTAT;
77
78 [--sp] = r0; /* Skip reserved */
79 [--sp] = RETS;
80 r0 = RETI;
81 [--sp] = r0;
82 [--sp] = RETX;
83 [--sp] = RETN;
84 [--sp] = RETE;
85 [--sp] = SEQSTAT;
86 [--sp] = r0; /* Skip IPEND as well. */
87 /* Switch to other method of keeping interrupts disabled. */
88#ifdef CONFIG_DEBUG_HWERR
89 r0 = 0x3f;
90 sti r0;
91#else
92 cli r0;
93#endif
94 [--sp] = RETI; /*orig_pc*/
95 /* Clear all L registers. */
96 r0 = 0 (x);
97 l0 = r0;
98 l1 = r0;
99 l2 = r0;
100 l3 = r0;
101.endm
102
103.macro save_context_syscall
104 [--sp] = SYSCFG;
105
106 [--sp] = P0; /*orig_p0*/
107 [--sp] = R0; /*orig_r0*/
108 [--sp] = ( R7:0, P5:0 );
109 [--sp] = fp;
110 [--sp] = usp;
111
112 [--sp] = i0;
113 [--sp] = i1;
114 [--sp] = i2;
115 [--sp] = i3;
116
117 [--sp] = m0;
118 [--sp] = m1;
119 [--sp] = m2;
120 [--sp] = m3;
121
122 [--sp] = l0;
123 [--sp] = l1;
124 [--sp] = l2;
125 [--sp] = l3;
126
127 [--sp] = b0;
128 [--sp] = b1;
129 [--sp] = b2;
130 [--sp] = b3;
131 [--sp] = a0.x;
132 [--sp] = a0.w;
133 [--sp] = a1.x;
134 [--sp] = a1.w;
135
136 [--sp] = LC0;
137 [--sp] = LC1;
138 [--sp] = LT0;
139 [--sp] = LT1;
140 [--sp] = LB0;
141 [--sp] = LB1;
142
143 [--sp] = ASTAT;
144
145 [--sp] = r0; /* Skip reserved */
146 [--sp] = RETS;
147 r0 = RETI;
148 [--sp] = r0;
149 [--sp] = RETX;
150 [--sp] = RETN;
151 [--sp] = RETE;
152 [--sp] = SEQSTAT;
153 [--sp] = r0; /* Skip IPEND as well. */
154 [--sp] = RETI; /*orig_pc*/
155 /* Clear all L registers. */
156 r0 = 0 (x);
157 l0 = r0;
158 l1 = r0;
159 l2 = r0;
160 l3 = r0;
161.endm
162
163.macro save_context_no_interrupts
164 [--sp] = SYSCFG;
165 [--sp] = P0; /* orig_p0 */
166 [--sp] = R0; /* orig_r0 */
167 [--sp] = ( R7:0, P5:0 );
168 [--sp] = fp;
169 [--sp] = usp;
170
171 [--sp] = i0;
172 [--sp] = i1;
173 [--sp] = i2;
174 [--sp] = i3;
175
176 [--sp] = m0;
177 [--sp] = m1;
178 [--sp] = m2;
179 [--sp] = m3;
180
181 [--sp] = l0;
182 [--sp] = l1;
183 [--sp] = l2;
184 [--sp] = l3;
185
186 [--sp] = b0;
187 [--sp] = b1;
188 [--sp] = b2;
189 [--sp] = b3;
190 [--sp] = a0.x;
191 [--sp] = a0.w;
192 [--sp] = a1.x;
193 [--sp] = a1.w;
194
195 [--sp] = LC0;
196 [--sp] = LC1;
197 [--sp] = LT0;
198 [--sp] = LT1;
199 [--sp] = LB0;
200 [--sp] = LB1;
201
202 [--sp] = ASTAT;
203
204#ifdef CONFIG_KGDB
205 fp = 0(Z);
206 r1 = sp;
207 r1 += 60;
208 r1 += 60;
209 r1 += 60;
210 [--sp] = r1;
211#else
212 [--sp] = r0; /* Skip reserved */
213#endif
214 [--sp] = RETS;
215 r0 = RETI;
216 [--sp] = r0;
217 [--sp] = RETX;
218 [--sp] = RETN;
219 [--sp] = RETE;
220 [--sp] = SEQSTAT;
221#ifdef CONFIG_KGDB
222 r1.l = lo(IPEND);
223 r1.h = hi(IPEND);
224 [--sp] = r1;
225#else
226 [--sp] = r0; /* Skip IPEND as well. */
227#endif
228 [--sp] = r0; /*orig_pc*/
229 /* Clear all L registers. */
230 r0 = 0 (x);
231 l0 = r0;
232 l1 = r0;
233 l2 = r0;
234 l3 = r0;
235.endm
236
237.macro restore_context_no_interrupts
238 sp += 4; /* Skip orig_pc */
239 sp += 4; /* Skip IPEND */
240 SEQSTAT = [sp++];
241 RETE = [sp++];
242 RETN = [sp++];
243 RETX = [sp++];
244 r0 = [sp++];
245 RETI = r0; /* Restore RETI indirectly when in exception */
246 RETS = [sp++];
247
248 sp += 4; /* Skip Reserved */
249
250 ASTAT = [sp++];
251
252 LB1 = [sp++];
253 LB0 = [sp++];
254 LT1 = [sp++];
255 LT0 = [sp++];
256 LC1 = [sp++];
257 LC0 = [sp++];
258
259 a1.w = [sp++];
260 a1.x = [sp++];
261 a0.w = [sp++];
262 a0.x = [sp++];
263 b3 = [sp++];
264 b2 = [sp++];
265 b1 = [sp++];
266 b0 = [sp++];
267
268 l3 = [sp++];
269 l2 = [sp++];
270 l1 = [sp++];
271 l0 = [sp++];
272
273 m3 = [sp++];
274 m2 = [sp++];
275 m1 = [sp++];
276 m0 = [sp++];
277
278 i3 = [sp++];
279 i2 = [sp++];
280 i1 = [sp++];
281 i0 = [sp++];
282
283 sp += 4;
284 fp = [sp++];
285
286 ( R7 : 0, P5 : 0) = [ SP ++ ];
287 sp += 8; /* Skip orig_r0/orig_p0 */
288 SYSCFG = [sp++];
289.endm
290
291.macro restore_context_with_interrupts
292 sp += 4; /* Skip orig_pc */
293 sp += 4; /* Skip IPEND */
294 SEQSTAT = [sp++];
295 RETE = [sp++];
296 RETN = [sp++];
297 RETX = [sp++];
298 RETI = [sp++];
299 RETS = [sp++];
300
301 p0.h = _irq_flags;
302 p0.l = _irq_flags;
303 r0 = [p0];
304 sti r0;
305
306 sp += 4; /* Skip Reserved */
307
308 ASTAT = [sp++];
309
310 LB1 = [sp++];
311 LB0 = [sp++];
312 LT1 = [sp++];
313 LT0 = [sp++];
314 LC1 = [sp++];
315 LC0 = [sp++];
316
317 a1.w = [sp++];
318 a1.x = [sp++];
319 a0.w = [sp++];
320 a0.x = [sp++];
321 b3 = [sp++];
322 b2 = [sp++];
323 b1 = [sp++];
324 b0 = [sp++];
325
326 l3 = [sp++];
327 l2 = [sp++];
328 l1 = [sp++];
329 l0 = [sp++];
330
331 m3 = [sp++];
332 m2 = [sp++];
333 m1 = [sp++];
334 m0 = [sp++];
335
336 i3 = [sp++];
337 i2 = [sp++];
338 i1 = [sp++];
339 i0 = [sp++];
340
341 sp += 4;
342 fp = [sp++];
343
344 ( R7 : 0, P5 : 0) = [ SP ++ ];
345 sp += 8; /* Skip orig_r0/orig_p0 */
346 csync;
347 SYSCFG = [sp++];
348 csync;
349.endm
350
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
new file mode 100644
index 000000000000..76103526aec1
--- /dev/null
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -0,0 +1,691 @@
1 /*
2 * File: include/asm-blackfin/mach-common/def_LPBlackfin.h
3 * Based on:
4 * Author: unknown
5 * COPYRIGHT 2005 Analog Devices
6 * Created: ?
7 * Description:
8 *
9 * Modified:
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING.
25 * If not, write to the Free Software Foundation,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532/33 */
30
31#ifndef _DEF_LPBLACKFIN_H
32#define _DEF_LPBLACKFIN_H
33
34#include <asm/mach/anomaly.h>
35
36/*#if !defined(__ADSPLPBLACKFIN__)
37#warning def_LPBlackfin.h should only be included for 532 compatible chips.
38#endif
39*/
40
41#define MK_BMSK_(x) (1<<x)
42
43#if defined(ANOMALY_05000198)
44
45#define bfin_read16(addr) ({ unsigned __v; \
46 __asm__ __volatile__ ("NOP;\n\t"\
47 "%0 = w[%1] (z);\n\t"\
48 : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
49
50#define bfin_read32(addr) ({ unsigned __v; \
51 __asm__ __volatile__ ("NOP;\n\t"\
52 "%0 = [%1];\n\t"\
53 : "=d"(__v) : "a"(addr)); __v; })
54
55#define bfin_write16(addr,val) ({\
56 __asm__ __volatile__ ("NOP;\n\t"\
57 "w[%0] = %1;\n\t"\
58 : : "a"(addr) , "d"(val) : "memory");})
59
60#define bfin_write32(addr,val) ({\
61 __asm__ __volatile__ ("NOP;\n\t"\
62 "[%0] = %1;\n\t"\
63 : : "a"(addr) , "d"(val) : "memory");})
64
65#else
66
67#define bfin_read16(addr) ({ unsigned __v; \
68 __asm__ __volatile__ (\
69 "%0 = w[%1] (z);\n\t"\
70 : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
71
72#define bfin_read32(addr) ({ unsigned __v; \
73 __asm__ __volatile__ (\
74 "%0 = [%1];\n\t"\
75 : "=d"(__v) : "a"(addr)); __v; })
76
77#define bfin_write16(addr,val) ({\
78 __asm__ __volatile__ (\
79 "w[%0] = %1;\n\t"\
80 : : "a"(addr) , "d"(val) : "memory");})
81
82#define bfin_write32(addr,val) ({\
83 __asm__ __volatile__ (\
84 "[%0] = %1;\n\t"\
85 : : "a"(addr) , "d"(val) : "memory");})
86
87#endif
88
89/**************************************************
90 * System Register Bits
91 **************************************************/
92
93/**************************************************
94 * ASTAT register
95 **************************************************/
96
97/* definitions of ASTAT bit positions*/
98
99/*Result of last ALU0 or shifter operation is zero*/
100#define ASTAT_AZ_P 0x00000000
101/*Result of last ALU0 or shifter operation is negative*/
102#define ASTAT_AN_P 0x00000001
103/*Condition Code, used for holding comparison results*/
104#define ASTAT_CC_P 0x00000005
105/*Quotient Bit*/
106#define ASTAT_AQ_P 0x00000006
107/*Rounding mode, set for biased, clear for unbiased*/
108#define ASTAT_RND_MOD_P 0x00000008
109/*Result of last ALU0 operation generated a carry*/
110#define ASTAT_AC0_P 0x0000000C
111/*Result of last ALU0 operation generated a carry*/
112#define ASTAT_AC0_COPY_P 0x00000002
113/*Result of last ALU1 operation generated a carry*/
114#define ASTAT_AC1_P 0x0000000D
115/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
116#define ASTAT_AV0_P 0x00000010
117/*Sticky version of ASTAT_AV0 */
118#define ASTAT_AV0S_P 0x00000011
119/*Result of last MAC1 operation overflowed, sticky for MAC*/
120#define ASTAT_AV1_P 0x00000012
121/*Sticky version of ASTAT_AV1 */
122#define ASTAT_AV1S_P 0x00000013
123/*Result of last ALU0 or MAC0 operation overflowed*/
124#define ASTAT_V_P 0x00000018
125/*Result of last ALU0 or MAC0 operation overflowed*/
126#define ASTAT_V_COPY_P 0x00000003
127/*Sticky version of ASTAT_V*/
128#define ASTAT_VS_P 0x00000019
129
130/* Masks */
131
132/*Result of last ALU0 or shifter operation is zero*/
133#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
134/*Result of last ALU0 or shifter operation is negative*/
135#define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
136/*Result of last ALU0 operation generated a carry*/
137#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
138/*Result of last ALU0 operation generated a carry*/
139#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
140/*Result of last ALU0 operation generated a carry*/
141#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
142/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
143#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
144/*Result of last MAC1 operation overflowed, sticky for MAC*/
145#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
146/*Condition Code, used for holding comparison results*/
147#define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
148/*Quotient Bit*/
149#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
150/*Rounding mode, set for biased, clear for unbiased*/
151#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
152/*Overflow Bit*/
153#define ASTAT_V MK_BMSK_(ASTAT_V_P)
154/*Overflow Bit*/
155#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
156
157/**************************************************
158 * SEQSTAT register
159 **************************************************/
160
161/* Bit Positions */
162#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
163#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
164#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
165#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
166#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
167#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
168#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request,
169 * set by IDLE instruction.
170 */
171#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last
172 * reset was a software reset
173 * (=1)
174 */
175#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
176#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
177#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
178#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
179#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
180/* Masks */
181/* Exception cause */
182#define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
183 MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
184 MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
185 MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
186 MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
187 MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
188 0)
189
190/* Indicates whether the last reset was a software reset (=1) */
191#define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
192
193/* Last hw error cause */
194#define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
195 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
196 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
197 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
198 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
199 0)
200
201/* Translate bits to something useful */
202
203/* Last hw error cause */
204#define SEQSTAT_HWERRCAUSE_SHIFT (14)
205#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
206#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
207#define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
208#define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
209
210/**************************************************
211 * SYSCFG register
212 **************************************************/
213
214/* Bit Positions */
215#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when
216 * set it forces an exception
217 * for each instruction executed
218 */
219#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
220#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
221
222/* Masks */
223
224/* Supervisor single step, when set it forces an exception for each
225 *instruction executed
226 */
227#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
228/* Enable cycle counter (=1) */
229#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
230/* Self Nesting Interrupt Enable */
231#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
232/* Backward-compatibility for typos in prior releases */
233#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
234#define SYSCFG_CCCEN SYSCFG_CCEN
235
236/****************************************************
237 * Core MMR Register Map
238 ****************************************************/
239
240/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
241
242#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
243#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
244#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside
245 * Buffer Status
246 */
247#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
248#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside
249 * Buffer Fault Address
250 */
251#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside
252 * Buffer 0
253 */
254#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside
255 * Buffer 1
256 */
257#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside
258 * Buffer 2
259 */
260#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection
261 * Lookaside Buffer 3
262 */
263#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection
264 * Lookaside Buffer 4
265 */
266#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection
267 * Lookaside Buffer 5
268 */
269#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection
270 * Lookaside Buffer 6
271 */
272#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection
273 * Lookaside Buffer 7
274 */
275#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection
276 * Lookaside Buffer 8
277 */
278#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection
279 * Lookaside Buffer 9
280 */
281#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection
282 * Lookaside Buffer 10
283 */
284#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection
285 * Lookaside Buffer 11
286 */
287#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection
288 * Lookaside Buffer 12
289 */
290#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection
291 * Lookaside Buffer 13
292 */
293#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection
294 * Lookaside Buffer 14
295 */
296#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection
297 * Lookaside Buffer 15
298 */
299#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
300#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
301#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
302#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
303#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
304#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
305#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
306#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
307#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
308#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
309#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
310#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
311#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
312#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
313#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
314#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
315#define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */
316
317#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
318#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
319#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
320
321/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
322
323#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
324#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
325#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
326#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
327#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
328#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability
329 * Protection Lookaside Buffer 0
330 */
331#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability
332 * Protection Lookaside Buffer 1
333 */
334#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability
335 * Protection Lookaside Buffer 2
336 */
337#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability
338 * Protection Lookaside Buffer 3
339 */
340#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability
341 * Protection Lookaside Buffer 4
342 */
343#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability
344 * Protection Lookaside Buffer 5
345 */
346#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability
347 * Protection Lookaside Buffer 6
348 */
349#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability
350 * Protection Lookaside Buffer 7
351 */
352#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability
353 * Protection Lookaside Buffer 8
354 */
355#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability
356 * Protection Lookaside Buffer 9
357 */
358#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability
359 * Protection Lookaside Buffer 10
360 */
361#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability
362 * Protection Lookaside Buffer 11
363 */
364#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability
365 * Protection Lookaside Buffer 12
366 */
367#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability
368 * Protection Lookaside Buffer 13
369 */
370#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability
371 * Protection Lookaside Buffer 14
372 */
373#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability
374 * Protection Lookaside Buffer 15
375 */
376#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
377#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
378#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
379#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
380#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
381#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
382#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
383#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
384#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
385#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
386#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
387#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
388#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
389#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
390#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
391#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
392#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
393#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
394#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
395
396/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
397
398#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
399#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
400#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
401#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
402#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
403#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
404#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
405#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
406#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
407#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
408#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
409#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
410#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
411#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
412#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
413#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
414#define IMASK 0xFFE02104 /* Interrupt Mask Register */
415#define IPEND 0xFFE02108 /* Interrupt Pending Register */
416#define ILAT 0xFFE0210C /* Interrupt Latch Register */
417#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
418
419/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
420
421#define TCNTL 0xFFE03000 /* Core Timer Control Register */
422#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
423#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
424#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
425
426/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
427#define DSPID 0xFFE05000 /* DSP Processor ID Register for
428 * MP implementations
429 */
430
431#define DBGSTAT 0xFFE05008 /* Debug Status Register */
432
433/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
434
435#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
436#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
437#define TBUF 0xFFE06100 /* Trace Buffer */
438
439/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
440
441/* Watchpoint Instruction Address Control Register */
442#define WPIACTL 0xFFE07000
443/* Watchpoint Instruction Address Register 0 */
444#define WPIA0 0xFFE07040
445/* Watchpoint Instruction Address Register 1 */
446#define WPIA1 0xFFE07044
447/* Watchpoint Instruction Address Register 2 */
448#define WPIA2 0xFFE07048
449/* Watchpoint Instruction Address Register 3 */
450#define WPIA3 0xFFE0704C
451/* Watchpoint Instruction Address Register 4 */
452#define WPIA4 0xFFE07050
453/* Watchpoint Instruction Address Register 5 */
454#define WPIA5 0xFFE07054
455/* Watchpoint Instruction Address Count Register 0 */
456#define WPIACNT0 0xFFE07080
457/* Watchpoint Instruction Address Count Register 1 */
458#define WPIACNT1 0xFFE07084
459/* Watchpoint Instruction Address Count Register 2 */
460#define WPIACNT2 0xFFE07088
461/* Watchpoint Instruction Address Count Register 3 */
462#define WPIACNT3 0xFFE0708C
463/* Watchpoint Instruction Address Count Register 4 */
464#define WPIACNT4 0xFFE07090
465/* Watchpoint Instruction Address Count Register 5 */
466#define WPIACNT5 0xFFE07094
467/* Watchpoint Data Address Control Register */
468#define WPDACTL 0xFFE07100
469/* Watchpoint Data Address Register 0 */
470#define WPDA0 0xFFE07140
471/* Watchpoint Data Address Register 1 */
472#define WPDA1 0xFFE07144
473/* Watchpoint Data Address Count Value Register 0 */
474#define WPDACNT0 0xFFE07180
475/* Watchpoint Data Address Count Value Register 1 */
476#define WPDACNT1 0xFFE07184
477/* Watchpoint Status Register */
478#define WPSTAT 0xFFE07200
479
480/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
481
482/* Performance Monitor Control Register */
483#define PFCTL 0xFFE08000
484/* Performance Monitor Counter Register 0 */
485#define PFCNTR0 0xFFE08100
486/* Performance Monitor Counter Register 1 */
487#define PFCNTR1 0xFFE08104
488
489/****************************************************
490 * Core MMR Register Bits
491 ****************************************************/
492
493/**************************************************
494 * EVT registers (ILAT, IMASK, and IPEND).
495 **************************************************/
496
497/* Bit Positions */
498#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
499#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
500#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
501#define EVT_EVX_P 0x00000003 /* Exception bit position */
502#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
503#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
504#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
505#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
506#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
507#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
508#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
509#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
510#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
511#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
512#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
513#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
514
515/* Masks */
516#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
517#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
518#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
519#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
520#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
521#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
522#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
523#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
524#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
525#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
526#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
527#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
528#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
529#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
530#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
531#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
532
533/**************************************************
534 * DMEM_CONTROL Register
535 **************************************************/
536/* Bit Positions */
537#define ENDM_P 0x00 /* (doesn't really exist) Enable
538 *Data Memory L1
539 */
540#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
541
542#define ENDCPLB_P 0x01 /* Enable DCPLBS */
543#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
544#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
545#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
546#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
547#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
548#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
549#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
550#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
551
552/* Masks */
553#define ENDM 0x00000001 /* (doesn't really exist) Enable
554 * Data Memory L1
555 */
556#define ENDCPLB 0x00000002 /* Enable DCPLB */
557#define ASRAM_BSRAM 0x00000000
558#define ACACHE_BSRAM 0x00000008
559#define ACACHE_BCACHE 0x0000000C
560#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
561#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
562#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
563
564/* IMEM_CONTROL Register */
565/* Bit Positions */
566#define ENIM_P 0x00 /* Enable L1 Code Memory */
567#define IMCTL_ENIM_P 0x00 /* "" (older define) */
568#define ENICPLB_P 0x01 /* Enable ICPLB */
569#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
570#define IMC_P 0x02 /* Enable */
571#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as
572 * cache (0=SRAM)
573 */
574#define ILOC0_P 0x03 /* Lock Way 0 */
575#define ILOC1_P 0x04 /* Lock Way 1 */
576#define ILOC2_P 0x05 /* Lock Way 2 */
577#define ILOC3_P 0x06 /* Lock Way 3 */
578#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement
579 * Priority
580 */
581/* Masks */
582#define ENIM 0x00000001 /* Enable L1 Code Memory */
583#define ENICPLB 0x00000002 /* Enable ICPLB */
584#define IMC 0x00000004 /* Configure L1 code memory as
585 * cache (0=SRAM)
586 */
587#define ILOC0 0x00000008 /* Lock Way 0 */
588#define ILOC1 0x00000010 /* Lock Way 1 */
589#define ILOC2 0x00000020 /* Lock Way 2 */
590#define ILOC3 0x00000040 /* Lock Way 3 */
591#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement
592 * Priority
593 */
594
595/* TCNTL Masks */
596#define TMPWR 0x00000001 /* Timer Low Power Control,
597 * 0=low power mode, 1=active state
598 */
599#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
600#define TAUTORLD 0x00000004 /* Timer auto reload */
601#define TINT 0x00000008 /* Timer generated interrupt 0=no
602 * interrupt has been generated,
603 * 1=interrupt has been generated
604 * (sticky)
605 */
606
607/* DCPLB_DATA and ICPLB_DATA Registers */
608/* Bit Positions */
609#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
610#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry
611 * locked
612 */
613#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access
614 * allowed (user mode)
615 */
616/* Masks */
617#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
618#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry
619 * locked
620 */
621#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
622 * allowed (user mode)
623 */
624#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
625#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
626#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
627#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
628#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
629 * mapped to L1
630 */
631#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high
632 * priority port
633 */
634#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable
635 * in L1
636 */
637/* ICPLB_DATA only */
638#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line,
639 * 1=priority for non-replacement
640 */
641/* DCPLB_DATA only */
642#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write
643 * access allowed (user mode)
644 */
645#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write
646 * access allowed (supervisor mode)
647 */
648#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
649#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on
650 * write-through writes,
651 * 1= allocate cache lines on
652 * write-through writes.
653 */
654#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
655
656/* TBUFCTL Masks */
657#define TBUFPWR 0x0001
658#define TBUFEN 0x0002
659#define TBUFOVF 0x0004
660#define TBUFCMPLP_SINGLE 0x0008
661#define TBUFCMPLP_DOUBLE 0x0010
662#define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
663
664/* TBUFSTAT Masks */
665#define TBUFCNT 0x001F
666
667/* ITEST_COMMAND and DTEST_COMMAND Registers */
668/* Masks */
669#define TEST_READ 0x00000000 /* Read Access */
670#define TEST_WRITE 0x00000002 /* Write Access */
671#define TEST_TAG 0x00000000 /* Access TAG */
672#define TEST_DATA 0x00000004 /* Access DATA */
673#define TEST_DW0 0x00000000 /* Select Double Word 0 */
674#define TEST_DW1 0x00000008 /* Select Double Word 1 */
675#define TEST_DW2 0x00000010 /* Select Double Word 2 */
676#define TEST_DW3 0x00000018 /* Select Double Word 3 */
677#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
678#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
679#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
680#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
681#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
682#define TEST_WAY0 0x00000000 /* Access Way0 */
683#define TEST_WAY1 0x04000000 /* Access Way1 */
684/* ITEST_COMMAND only */
685#define TEST_WAY2 0x08000000 /* Access Way2 */
686#define TEST_WAY3 0x0C000000 /* Access Way3 */
687/* DTEST_COMMAND only */
688#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
689#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
690
691#endif /* _DEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/macros.h b/include/asm-blackfin/macros.h
new file mode 100644
index 000000000000..c0c04a2f2dd5
--- /dev/null
+++ b/include/asm-blackfin/macros.h
@@ -0,0 +1,95 @@
1/************************************************************************
2 *
3 * macros.h
4 *
5 * (c) Copyright 2001-2003 Analog Devices, Inc. All rights reserved.
6 *
7 ************************************************************************/
8
9/* Defines various assembly macros. */
10
11#ifndef _MACROS_H
12#define _MACROS_H
13
14#define LO(con32) ((con32) & 0xFFFF)
15#define lo(con32) ((con32) & 0xFFFF)
16#define HI(con32) (((con32) >> 16) & 0xFFFF)
17#define hi(con32) (((con32) >> 16) & 0xFFFF)
18
19/*
20 * Set the corresponding bits in a System Register (SR);
21 * All bits set in "mask" will be set in the system register
22 * specified by "sys_reg" bitset_SR(sys_reg, mask), where
23 * sys_reg is the system register and mask are the bits to be set.
24 */
25#define bitset_SR(sys_reg, mask)\
26 [--SP] = (R7:6);\
27 r7 = sys_reg;\
28 r6.l = (mask) & 0xffff;\
29 r6.h = (mask) >> 16;\
30 r7 = r7 | r6;\
31 sys_reg = r7;\
32 csync;\
33 (R7:6) = [SP++]
34
35/*
36 * Clear the corresponding bits in a System Register (SR);
37 * All bits set in "mask" will be cleared in the SR
38 * specified by "sys_reg" bitclr_SR(sys_reg, mask), where
39 * sys_reg is the SR and mask are the bits to be cleared.
40 */
41#define bitclr_SR(sys_reg, mask)\
42 [--SP] = (R7:6);\
43 r7 = sys_reg;\
44 r7 =~ r7;\
45 r6.l = (mask) & 0xffff;\
46 r6.h = (mask) >> 16;\
47 r7 = r7 | r6;\
48 r7 =~ r7;\
49 sys_reg = r7;\
50 csync;\
51 (R7:6) = [SP++]
52
53/*
54 * Set the corresponding bits in a Memory Mapped Register (MMR);
55 * All bits set in "mask" will be set in the MMR specified by "mmr_reg"
56 * bitset_MMR(mmr_reg, mask), where mmr_reg is the MMR and mask are
57 * the bits to be set.
58 */
59#define bitset_MMR(mmr_reg, mask)\
60 [--SP] = (R7:6);\
61 [--SP] = P5;\
62 p5.l = mmr_reg & 0xffff;\
63 p5.h = mmr_reg >> 16;\
64 r7 = [p5];\
65 r6.l = (mask) & 0xffff;\
66 r6.h = (mask) >> 16;\
67 r7 = r7 | r6;\
68 [p5] = r7;\
69 csync;\
70 p5 = [SP++];\
71 (R7:6) = [SP++]
72
73/*
74 * Clear the corresponding bits in a Memory Mapped Register (MMR);
75 * All bits set in "mask" will be cleared in the MMR specified by "mmr_reg"
76 * bitclr_MMRreg(mmr_reg, mask), where sys_reg is the MMR and mask are
77 * the bits to be cleared.
78 */
79#define bitclr_MMR(mmr_reg, mask)\
80 [--SP] = (R7:6);\
81 [--SP] = P5;\
82 p5.l = mmr_reg & 0xffff;\
83 p5.h = mmr_reg >> 16;\
84 r7 = [p5];\
85 r7 =~ r7;\
86 r6.l = (mask) & 0xffff;\
87 r6.h = (mask) >> 16;\
88 r7 = r7 | r6;\
89 r7 =~ r7;\
90 [p5] = r7;\
91 csync;\
92 p5 = [SP++];\
93 (R7:6) = [SP++]
94
95#endif /* _MACROS_H */
diff --git a/include/asm-blackfin/mem_map.h b/include/asm-blackfin/mem_map.h
new file mode 100644
index 000000000000..42d1f37f6d9c
--- /dev/null
+++ b/include/asm-blackfin/mem_map.h
@@ -0,0 +1,12 @@
1/*
2 * mem_map.h
3 * Common header file for blackfin family of processors.
4 *
5 */
6
7#ifndef _MEM_MAP_H_
8#define _MEM_MAP_H_
9
10#include <asm/mach/mem_map.h>
11
12#endif /* _MEM_MAP_H_ */
diff --git a/include/asm-blackfin/mman.h b/include/asm-blackfin/mman.h
new file mode 100644
index 000000000000..4d504f908c0c
--- /dev/null
+++ b/include/asm-blackfin/mman.h
@@ -0,0 +1,45 @@
1#ifndef __BFIN_MMAN_H__
2#define __BFIN_MMAN_H__
3
4#define PROT_READ 0x1 /* page can be read */
5#define PROT_WRITE 0x2 /* page can be written */
6#define PROT_EXEC 0x4 /* page can be executed */
7#define PROT_SEM 0x8 /* page may be used for atomic ops */
8#define PROT_NONE 0x0 /* page can not be accessed */
9#define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
10#define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
11
12#define MAP_SHARED 0x01 /* Share changes */
13#define MAP_PRIVATE 0x02 /* Changes are private */
14#define MAP_TYPE 0x0f /* Mask for type of mapping */
15#define MAP_FIXED 0x10 /* Interpret addr exactly */
16#define MAP_ANONYMOUS 0x20 /* don't use a file */
17
18#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
19#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
20#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
21#define MAP_LOCKED 0x2000 /* pages are locked */
22#define MAP_NORESERVE 0x4000 /* don't check for reservations */
23#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
24#define MAP_NONBLOCK 0x10000 /* do not block on IO */
25#define MAP_UNINITIALIZE 0x4000000 /* For anonymous mmap, memory could
26 be uninitialized. */
27
28#define MS_ASYNC 1 /* sync memory asynchronously */
29#define MS_INVALIDATE 2 /* invalidate the caches */
30#define MS_SYNC 4 /* synchronous memory sync */
31
32#define MCL_CURRENT 1 /* lock all current mappings */
33#define MCL_FUTURE 2 /* lock all future mappings */
34
35#define MADV_NORMAL 0x0 /* default page-in behavior */
36#define MADV_RANDOM 0x1 /* page-in minimum required */
37#define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */
38#define MADV_WILLNEED 0x3 /* pre-fault pages */
39#define MADV_DONTNEED 0x4 /* discard these pages */
40
41/* compatibility flags */
42#define MAP_ANON MAP_ANONYMOUS
43#define MAP_FILE 0
44
45#endif /* __BFIN_MMAN_H__ */
diff --git a/include/asm-blackfin/mmu.h b/include/asm-blackfin/mmu.h
new file mode 100644
index 000000000000..11d52f1167d0
--- /dev/null
+++ b/include/asm-blackfin/mmu.h
@@ -0,0 +1,30 @@
1#ifndef __MMU_H
2#define __MMU_H
3
4/* Copyright (C) 2002, David McCullough <davidm@snapgear.com> */
5
6struct sram_list_struct {
7 struct sram_list_struct *next;
8 void *addr;
9 size_t length;
10};
11
12typedef struct {
13 struct vm_list_struct *vmlist;
14 unsigned long end_brk;
15 unsigned long stack_start;
16
17 /* Points to the location in SDRAM where the L1 stack is normally
18 saved, or NULL if the stack is always in SDRAM. */
19 void *l1_stack_save;
20
21 struct sram_list_struct *sram_list;
22
23#ifdef CONFIG_BINFMT_ELF_FDPIC
24 unsigned long exec_fdpic_loadmap;
25 unsigned long interp_fdpic_loadmap;
26#endif
27
28} mm_context_t;
29
30#endif
diff --git a/include/asm-blackfin/mmu_context.h b/include/asm-blackfin/mmu_context.h
new file mode 100644
index 000000000000..c5c71a6aaf19
--- /dev/null
+++ b/include/asm-blackfin/mmu_context.h
@@ -0,0 +1,129 @@
1/*
2 * File: include/asm-blackfin/mmu_context.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __BLACKFIN_MMU_CONTEXT_H__
31#define __BLACKFIN_MMU_CONTEXT_H__
32
33#include <asm/setup.h>
34#include <asm/page.h>
35#include <asm/pgalloc.h>
36
37extern void *current_l1_stack_save;
38extern int nr_l1stack_tasks;
39extern void *l1_stack_base;
40extern unsigned long l1_stack_len;
41
42extern int l1sram_free(const void*);
43extern void *l1sram_alloc_max(void*);
44
45static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
46{
47}
48
49/* Called when creating a new context during fork() or execve(). */
50static inline int
51init_new_context(struct task_struct *tsk, struct mm_struct *mm)
52{
53 return 0;
54}
55
56static inline void free_l1stack(void)
57{
58 nr_l1stack_tasks--;
59 if (nr_l1stack_tasks == 0)
60 l1sram_free(l1_stack_base);
61}
62static inline void destroy_context(struct mm_struct *mm)
63{
64 struct sram_list_struct *tmp;
65
66 if (current_l1_stack_save == mm->context.l1_stack_save)
67 current_l1_stack_save = 0;
68 if (mm->context.l1_stack_save)
69 free_l1stack();
70
71 while ((tmp = mm->context.sram_list)) {
72 mm->context.sram_list = tmp->next;
73 sram_free(tmp->addr);
74 kfree(tmp);
75 }
76}
77
78static inline unsigned long
79alloc_l1stack(unsigned long length, unsigned long *stack_base)
80{
81 if (nr_l1stack_tasks == 0) {
82 l1_stack_base = l1sram_alloc_max(&l1_stack_len);
83 if (!l1_stack_base)
84 return 0;
85 }
86
87 if (l1_stack_len < length) {
88 if (nr_l1stack_tasks == 0)
89 l1sram_free(l1_stack_base);
90 return 0;
91 }
92 *stack_base = (unsigned long)l1_stack_base;
93 nr_l1stack_tasks++;
94 return l1_stack_len;
95}
96
97static inline int
98activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
99{
100 if (current_l1_stack_save)
101 memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
102 mm->context.l1_stack_save = current_l1_stack_save = (void*)sp_base;
103 memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
104 return 1;
105}
106
107#define deactivate_mm(tsk,mm) do { } while (0)
108
109static inline void activate_mm(struct mm_struct *prev_mm,
110 struct mm_struct *next_mm)
111{
112 if (!next_mm->context.l1_stack_save)
113 return;
114 if (next_mm->context.l1_stack_save == current_l1_stack_save)
115 return;
116 if (current_l1_stack_save) {
117 memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
118 }
119 current_l1_stack_save = next_mm->context.l1_stack_save;
120 memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
121}
122
123static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
124 struct task_struct *tsk)
125{
126 activate_mm(prev, next);
127}
128
129#endif
diff --git a/include/asm-blackfin/module.h b/include/asm-blackfin/module.h
new file mode 100644
index 000000000000..3c7ce1644280
--- /dev/null
+++ b/include/asm-blackfin/module.h
@@ -0,0 +1,19 @@
1#ifndef _ASM_BFIN_MODULE_H
2#define _ASM_BFIN_MODULE_H
3
4#define MODULE_SYMBOL_PREFIX "_"
5
6#define Elf_Shdr Elf32_Shdr
7#define Elf_Sym Elf32_Sym
8#define Elf_Ehdr Elf32_Ehdr
9#define FLG_CODE_IN_L1 0x10
10#define FLG_DATA_IN_L1 0x20
11
12struct mod_arch_specific {
13 Elf_Shdr *text_l1;
14 Elf_Shdr *data_a_l1;
15 Elf_Shdr *bss_a_l1;
16 Elf_Shdr *data_b_l1;
17 Elf_Shdr *bss_b_l1;
18};
19#endif /* _ASM_BFIN_MODULE_H */
diff --git a/include/asm-blackfin/msgbuf.h b/include/asm-blackfin/msgbuf.h
new file mode 100644
index 000000000000..6fcbe8cd801d
--- /dev/null
+++ b/include/asm-blackfin/msgbuf.h
@@ -0,0 +1,31 @@
1#ifndef _BFIN_MSGBUF_H
2#define _BFIN_MSGBUF_H
3
4/*
5 * The msqid64_ds structure for bfin architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct msqid64_ds {
15 struct ipc64_perm msg_perm;
16 __kernel_time_t msg_stime; /* last msgsnd time */
17 unsigned long __unused1;
18 __kernel_time_t msg_rtime; /* last msgrcv time */
19 unsigned long __unused2;
20 __kernel_time_t msg_ctime; /* last change time */
21 unsigned long __unused3;
22 unsigned long msg_cbytes; /* current number of bytes on queue */
23 unsigned long msg_qnum; /* number of messages in queue */
24 unsigned long msg_qbytes; /* max number of bytes on queue */
25 __kernel_pid_t msg_lspid; /* pid of last msgsnd */
26 __kernel_pid_t msg_lrpid; /* last receive pid */
27 unsigned long __unused4;
28 unsigned long __unused5;
29};
30
31#endif /* _BFIN_MSGBUF_H */
diff --git a/include/asm-blackfin/mutex.h b/include/asm-blackfin/mutex.h
new file mode 100644
index 000000000000..458c1f7fbc18
--- /dev/null
+++ b/include/asm-blackfin/mutex.h
@@ -0,0 +1,9 @@
1/*
2 * Pull in the generic implementation for the mutex fastpath.
3 *
4 * TODO: implement optimized primitives instead, or leave the generic
5 * implementation in place, or pick the atomic_xchg() based generic
6 * implementation. (see asm-generic/mutex-xchg.h for details)
7 */
8
9#include <asm-generic/mutex-dec.h>
diff --git a/include/asm-blackfin/namei.h b/include/asm-blackfin/namei.h
new file mode 100644
index 000000000000..8b89a2d65cb4
--- /dev/null
+++ b/include/asm-blackfin/namei.h
@@ -0,0 +1,19 @@
1/*
2 * linux/include/asm/namei.h
3 *
4 * Included from linux/fs/namei.c
5 *
6 * Changes made by Lineo Inc. May 2001
7 */
8
9#ifndef __BFIN_NAMEI_H
10#define __BFIN_NAMEI_H
11
12/* This dummy routine maybe changed to something useful
13 * for /usr/gnemul/ emulation stuff.
14 * Look at asm-sparc/namei.h for details.
15 */
16
17#define __emul_prefix() NULL
18
19#endif
diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h
new file mode 100644
index 000000000000..ffad947f1b2a
--- /dev/null
+++ b/include/asm-blackfin/page.h
@@ -0,0 +1,89 @@
1#ifndef _BLACKFIN_PAGE_H
2#define _BLACKFIN_PAGE_H
3
4/* PAGE_SHIFT determines the page size */
5
6#define PAGE_SHIFT 12
7#define PAGE_SIZE (1UL << PAGE_SHIFT)
8#define PAGE_MASK (~(PAGE_SIZE-1))
9
10#ifdef __KERNEL__
11
12#include <asm/setup.h>
13
14#ifndef __ASSEMBLY__
15
16#define get_user_page(vaddr) __get_free_page(GFP_KERNEL)
17#define free_user_page(page, addr) free_page(addr)
18
19#define clear_page(page) memset((page), 0, PAGE_SIZE)
20#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE)
21
22#define clear_user_page(page, vaddr,pg) clear_page(page)
23#define copy_user_page(to, from, vaddr,pg) copy_page(to, from)
24
25/*
26 * These are used to make use of C type-checking..
27 */
28typedef struct {
29 unsigned long pte;
30} pte_t;
31typedef struct {
32 unsigned long pmd[16];
33} pmd_t;
34typedef struct {
35 unsigned long pgd;
36} pgd_t;
37typedef struct {
38 unsigned long pgprot;
39} pgprot_t;
40
41#define pte_val(x) ((x).pte)
42#define pmd_val(x) ((&x)->pmd[0])
43#define pgd_val(x) ((x).pgd)
44#define pgprot_val(x) ((x).pgprot)
45
46#define __pte(x) ((pte_t) { (x) } )
47#define __pmd(x) ((pmd_t) { (x) } )
48#define __pgd(x) ((pgd_t) { (x) } )
49#define __pgprot(x) ((pgprot_t) { (x) } )
50
51/* to align the pointer to the (next) page boundary */
52#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
53
54extern unsigned long memory_start;
55extern unsigned long memory_end;
56
57#endif /* !__ASSEMBLY__ */
58
59#include <asm/page_offset.h>
60#include <asm/io.h>
61
62#define PAGE_OFFSET (PAGE_OFFSET_RAW)
63
64#ifndef __ASSEMBLY__
65
66#define __pa(vaddr) virt_to_phys((void *)(vaddr))
67#define __va(paddr) phys_to_virt((unsigned long)(paddr))
68
69#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
70
71#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
72#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT)
73#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
74#define page_to_virt(page) ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
75#define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
76
77#define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn))
78#define page_to_pfn(page) virt_to_pfn(page_to_virt(page))
79#define pfn_valid(pfn) ((pfn) < max_mapnr)
80
81#define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
82 ((void *)(kaddr) < (void *)memory_end))
83
84#include <asm-generic/page.h>
85
86#endif /* __ASSEMBLY__ */
87#endif /* __KERNEL__ */
88
89#endif /* _BLACKFIN_PAGE_H */
diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h
new file mode 100644
index 000000000000..3b671d5fd70d
--- /dev/null
+++ b/include/asm-blackfin/page_offset.h
@@ -0,0 +1,6 @@
1
2/* This handles the memory map.. */
3
4#ifdef CONFIG_BFIN
5#define PAGE_OFFSET_RAW 0x00000000
6#endif
diff --git a/include/asm-blackfin/param.h b/include/asm-blackfin/param.h
new file mode 100644
index 000000000000..41564a6347f8
--- /dev/null
+++ b/include/asm-blackfin/param.h
@@ -0,0 +1,22 @@
1#ifndef _BLACKFIN_PARAM_H
2#define _BLACKFIN_PARAM_H
3
4#ifdef __KERNEL__
5#define HZ CONFIG_HZ
6#define USER_HZ 100
7#define CLOCKS_PER_SEC (USER_HZ)
8#endif
9
10#ifndef HZ
11#define HZ 100
12#endif
13
14#define EXEC_PAGESIZE 4096
15
16#ifndef NOGROUP
17#define NOGROUP (-1)
18#endif
19
20#define MAXHOSTNAMELEN 64 /* max length of hostname */
21
22#endif /* _BLACKFIN_PARAM_H */
diff --git a/include/asm-blackfin/pci.h b/include/asm-blackfin/pci.h
new file mode 100644
index 000000000000..61277358c865
--- /dev/null
+++ b/include/asm-blackfin/pci.h
@@ -0,0 +1,148 @@
1/* Changed from asm-m68k version, Lineo Inc. May 2001 */
2
3#ifndef _ASM_BFIN_PCI_H
4#define _ASM_BFIN_PCI_H
5
6#include <asm/scatterlist.h>
7
8/*
9 *
10 * Written by Wout Klaren.
11 */
12
13/* Added by Chang Junxiao */
14#define PCIBIOS_MIN_IO 0x00001000
15#define PCIBIOS_MIN_MEM 0x10000000
16
17#define PCI_DMA_BUS_IS_PHYS (1)
18struct pci_ops;
19
20/*
21 * Structure with hardware dependent information and functions of the
22 * PCI bus.
23 */
24struct pci_bus_info {
25
26 /*
27 * Resources of the PCI bus.
28 */
29 struct resource mem_space;
30 struct resource io_space;
31
32 /*
33 * System dependent functions.
34 */
35 struct pci_ops *bfin_pci_ops;
36 void (*fixup) (int pci_modify);
37 void (*conf_device) (unsigned char bus, unsigned char device_fn);
38};
39
40#define pcibios_assign_all_busses() 0
41static inline void pcibios_set_master(struct pci_dev *dev)
42{
43
44 /* No special bus mastering setup handling */
45}
46static inline void pcibios_penalize_isa_irq(int irq)
47{
48
49 /* We don't do dynamic PCI IRQ allocation */
50}
51static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
52 size_t size, int direction)
53{
54 if (direction == PCI_DMA_NONE)
55 BUG();
56
57 /* return virt_to_bus(ptr); */
58 return (dma_addr_t) ptr;
59}
60
61/* Unmap a single streaming mode DMA translation. The dma_addr and size
62 * must match what was provided for in a previous pci_map_single call. All
63 * other usages are undefined.
64 *
65 * After this call, reads by the cpu to the buffer are guarenteed to see
66 * whatever the device wrote there.
67 */
68static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
69 size_t size, int direction)
70{
71 if (direction == PCI_DMA_NONE)
72 BUG();
73
74 /* Nothing to do */
75}
76
77/* Map a set of buffers described by scatterlist in streaming
78 * mode for DMA. This is the scather-gather version of the
79 * above pci_map_single interface. Here the scatter gather list
80 * elements are each tagged with the appropriate dma address
81 * and length. They are obtained via sg_dma_{address,length}(SG).
82 *
83 * NOTE: An implementation may be able to use a smaller number of
84 * DMA address/length pairs than there are SG table elements.
85 * (for example via virtual mapping capabilities)
86 * The routine returns the number of addr/length pairs actually
87 * used, at most nents.
88 *
89 * Device ownership issues as mentioned above for pci_map_single are
90 * the same here.
91 */
92static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
93 int nents, int direction)
94{
95 if (direction == PCI_DMA_NONE)
96 BUG();
97 return nents;
98}
99
100/* Unmap a set of streaming mode DMA translations.
101 * Again, cpu read rules concerning calls here are the same as for
102 * pci_unmap_single() above.
103 */
104static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
105 int nents, int direction)
106{
107 if (direction == PCI_DMA_NONE)
108 BUG();
109
110 /* Nothing to do */
111}
112
113/* Make physical memory consistent for a single
114 * streaming mode DMA translation after a transfer.
115 *
116 * If you perform a pci_map_single() but wish to interrogate the
117 * buffer using the cpu, yet do not wish to teardown the PCI dma
118 * mapping, you must call this function before doing so. At the
119 * next point you give the PCI dma address back to the card, the
120 * device again owns the buffer.
121 */
122static inline void pci_dma_sync_single(struct pci_dev *hwdev,
123 dma_addr_t dma_handle, size_t size,
124 int direction)
125{
126 if (direction == PCI_DMA_NONE)
127 BUG();
128
129 /* Nothing to do */
130}
131
132/* Make physical memory consistent for a set of streaming
133 * mode DMA translations after a transfer.
134 *
135 * The same as pci_dma_sync_single but for a scatter-gather list,
136 * same rules and usage.
137 */
138static inline void pci_dma_sync_sg(struct pci_dev *hwdev,
139 struct scatterlist *sg, int nelems,
140 int direction)
141{
142 if (direction == PCI_DMA_NONE)
143 BUG();
144
145 /* Nothing to do */
146}
147
148#endif /* _ASM_BFIN_PCI_H */
diff --git a/include/asm-blackfin/percpu.h b/include/asm-blackfin/percpu.h
new file mode 100644
index 000000000000..78dd61f6b39f
--- /dev/null
+++ b/include/asm-blackfin/percpu.h
@@ -0,0 +1,6 @@
1#ifndef __ARCH_BLACKFIN_PERCPU__
2#define __ARCH_BLACKFIN_PERCPU__
3
4#include <asm-generic/percpu.h>
5
6#endif /* __ARCH_BLACKFIN_PERCPU__ */
diff --git a/include/asm-blackfin/pgalloc.h b/include/asm-blackfin/pgalloc.h
new file mode 100644
index 000000000000..c686e0542fd0
--- /dev/null
+++ b/include/asm-blackfin/pgalloc.h
@@ -0,0 +1,8 @@
1#ifndef _BLACKFIN_PGALLOC_H
2#define _BLACKFIN_PGALLOC_H
3
4#include <asm/setup.h>
5
6#define check_pgt_cache() do { } while (0)
7
8#endif /* _BLACKFIN_PGALLOC_H */
diff --git a/include/asm-blackfin/pgtable.h b/include/asm-blackfin/pgtable.h
new file mode 100644
index 000000000000..5a8f9e431c40
--- /dev/null
+++ b/include/asm-blackfin/pgtable.h
@@ -0,0 +1,96 @@
1#ifndef _BLACKFIN_PGTABLE_H
2#define _BLACKFIN_PGTABLE_H
3
4#include <asm-generic/4level-fixup.h>
5
6#include <asm/page.h>
7#include <asm/cplb.h>
8
9typedef pte_t *pte_addr_t;
10/*
11* Trivial page table functions.
12*/
13#define pgd_present(pgd) (1)
14#define pgd_none(pgd) (0)
15#define pgd_bad(pgd) (0)
16#define pgd_clear(pgdp)
17#define kern_addr_valid(addr) (1)
18
19#define pmd_offset(a, b) ((void *)0)
20#define pmd_none(x) (!pmd_val(x))
21#define pmd_present(x) (pmd_val(x))
22#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
23#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
24
25#define kern_addr_valid(addr) (1)
26
27#define PAGE_NONE __pgprot(0) /* these mean nothing to NO_MM */
28#define PAGE_SHARED __pgprot(0) /* these mean nothing to NO_MM */
29#define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */
30#define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */
31#define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */
32
33extern void paging_init(void);
34
35#define __swp_type(x) (0)
36#define __swp_offset(x) (0)
37#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
38#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
39#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
40
41static inline int pte_file(pte_t pte)
42{
43 return 0;
44}
45
46#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
47#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
48
49/*
50 * Page assess control based on Blackfin CPLB management
51 */
52#define _PAGE_RD (CPLB_USER_RD)
53#define _PAGE_WR (CPLB_USER_WR)
54#define _PAGE_USER (CPLB_USER_RD | CPLB_USER_WR)
55#define _PAGE_ACCESSED CPLB_ALL_ACCESS
56#define _PAGE_DIRTY (CPLB_DIRTY)
57
58#define PTE_BIT_FUNC(fn, op) \
59 static inline pte_t pte_##fn(pte_t _pte) { _pte.pte op; return _pte; }
60
61PTE_BIT_FUNC(rdprotect, &= ~_PAGE_RD);
62PTE_BIT_FUNC(mkread, |= _PAGE_RD);
63PTE_BIT_FUNC(wrprotect, &= ~_PAGE_WR);
64PTE_BIT_FUNC(mkwrite, |= _PAGE_WR);
65PTE_BIT_FUNC(exprotect, &= ~_PAGE_USER);
66PTE_BIT_FUNC(mkexec, |= _PAGE_USER);
67PTE_BIT_FUNC(mkclean, &= ~_PAGE_DIRTY);
68PTE_BIT_FUNC(mkdirty, |= _PAGE_DIRTY);
69PTE_BIT_FUNC(mkold, &= ~_PAGE_ACCESSED);
70PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED);
71
72/*
73 * ZERO_PAGE is a global shared page that is always zero: used
74 * for zero-mapped memory areas etc..
75 */
76#define ZERO_PAGE(vaddr) (virt_to_page(0))
77
78extern unsigned int kobjsize(const void *objp);
79
80#define swapper_pg_dir ((pgd_t *) 0)
81/*
82 * No page table caches to initialise.
83 */
84#define pgtable_cache_init() do { } while (0)
85#define io_remap_pfn_range remap_pfn_range
86
87/*
88 * All 32bit addresses are effectively valid for vmalloc...
89 * Sort of meaningless for non-VM targets.
90 */
91#define VMALLOC_START 0
92#define VMALLOC_END 0xffffffff
93
94#include <asm-generic/pgtable.h>
95
96#endif /* _BLACKFIN_PGTABLE_H */
diff --git a/include/asm-blackfin/poll.h b/include/asm-blackfin/poll.h
new file mode 100644
index 000000000000..94cc2636e0e2
--- /dev/null
+++ b/include/asm-blackfin/poll.h
@@ -0,0 +1,24 @@
1#ifndef __BFIN_POLL_H
2#define __BFIN_POLL_H
3
4#define POLLIN 1
5#define POLLPRI 2
6#define POLLOUT 4
7#define POLLERR 8
8#define POLLHUP 16
9#define POLLNVAL 32
10#define POLLRDNORM 64
11#define POLLWRNORM POLLOUT
12#define POLLRDBAND 128
13#define POLLWRBAND 256
14#define POLLMSG 0x0400
15#define POLLREMOVE 0x1000
16#define POLLRDHUP 0x2000
17
18struct pollfd {
19 int fd;
20 short events;
21 short revents;
22};
23
24#endif /* __BFIN_POLL_H */
diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h
new file mode 100644
index 000000000000..c3fa50fa50b8
--- /dev/null
+++ b/include/asm-blackfin/posix_types.h
@@ -0,0 +1,65 @@
1#ifndef __ARCH_BFIN_POSIX_TYPES_H
2#define __ARCH_BFIN_POSIX_TYPES_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 */
9
10typedef unsigned long __kernel_ino_t;
11typedef unsigned short __kernel_mode_t;
12typedef unsigned short __kernel_nlink_t;
13typedef long __kernel_off_t;
14typedef int __kernel_pid_t;
15typedef unsigned int __kernel_ipc_pid_t;
16typedef unsigned int __kernel_uid_t;
17typedef unsigned int __kernel_gid_t;
18typedef unsigned long __kernel_size_t;
19typedef long __kernel_ssize_t;
20typedef int __kernel_ptrdiff_t;
21typedef long __kernel_time_t;
22typedef long __kernel_suseconds_t;
23typedef long __kernel_clock_t;
24typedef int __kernel_timer_t;
25typedef int __kernel_clockid_t;
26typedef int __kernel_daddr_t;
27typedef char *__kernel_caddr_t;
28typedef unsigned short __kernel_uid16_t;
29typedef unsigned short __kernel_gid16_t;
30typedef unsigned int __kernel_uid32_t;
31typedef unsigned int __kernel_gid32_t;
32
33typedef unsigned short __kernel_old_uid_t;
34typedef unsigned short __kernel_old_gid_t;
35typedef unsigned short __kernel_old_dev_t;
36
37#ifdef __GNUC__
38typedef long long __kernel_loff_t;
39#endif
40
41typedef struct {
42#if defined(__KERNEL__) || defined(__USE_ALL)
43 int val[2];
44#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
45 int __val[2];
46#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
47} __kernel_fsid_t;
48
49#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
50
51#undef __FD_SET
52#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
53
54#undef __FD_CLR
55#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
56
57#undef __FD_ISSET
58#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
59
60#undef __FD_ZERO
61#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
62
63#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
64
65#endif
diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h
new file mode 100644
index 000000000000..997465c93e82
--- /dev/null
+++ b/include/asm-blackfin/processor.h
@@ -0,0 +1,130 @@
1#ifndef __ASM_BFIN_PROCESSOR_H
2#define __ASM_BFIN_PROCESSOR_H
3
4/*
5 * Default implementation of macro that returns current
6 * instruction pointer ("program counter").
7 */
8#define current_text_addr() ({ __label__ _l; _l: &&_l;})
9
10#include <asm/blackfin.h>
11#include <asm/segment.h>
12#include <linux/compiler.h>
13
14static inline unsigned long rdusp(void)
15{
16 unsigned long usp;
17
18 __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp));
19 return usp;
20}
21
22static inline void wrusp(unsigned long usp)
23{
24 __asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
25}
26
27/*
28 * User space process size: 1st byte beyond user address space.
29 */
30extern unsigned long memory_end;
31#define TASK_SIZE (memory_end)
32
33#define TASK_UNMAPPED_BASE 0
34
35struct thread_struct {
36 unsigned long ksp; /* kernel stack pointer */
37 unsigned long usp; /* user stack pointer */
38 unsigned short seqstat; /* saved status register */
39 unsigned long esp0; /* points to SR of stack frame pt_regs */
40 unsigned long pc; /* instruction pointer */
41 void * debuggerinfo;
42};
43
44#define INIT_THREAD { \
45 sizeof(init_stack) + (unsigned long) init_stack, 0, \
46 PS_S, 0, 0 \
47}
48
49/*
50 * Do necessary setup to start up a newly executed thread.
51 *
52 * pass the data segment into user programs if it exists,
53 * it can't hurt anything as far as I can tell
54 */
55#define start_thread(_regs, _pc, _usp) \
56do { \
57 set_fs(USER_DS); \
58 (_regs)->pc = (_pc); \
59 if (current->mm) \
60 (_regs)->p5 = current->mm->start_data; \
61 current->thread_info->l1_task_info.stack_start \
62 = (void *)current->mm->context.stack_start; \
63 current->thread_info->l1_task_info.lowest_sp = (void *)(_usp); \
64 memcpy(L1_SCRATCH_TASK_INFO, &current->thread_info->l1_task_info, \
65 sizeof(*L1_SCRATCH_TASK_INFO)); \
66 wrusp(_usp); \
67} while(0)
68
69/* Forward declaration, a strange C thing */
70struct task_struct;
71
72/* Free all resources held by a thread. */
73static inline void release_thread(struct task_struct *dead_task)
74{
75}
76
77#define prepare_to_copy(tsk) do { } while (0)
78
79extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags);
80
81/*
82 * Free current thread data structures etc..
83 */
84static inline void exit_thread(void)
85{
86}
87
88/*
89 * Return saved PC of a blocked thread.
90 */
91#define thread_saved_pc(tsk) (tsk->thread.pc)
92
93unsigned long get_wchan(struct task_struct *p);
94
95#define KSTK_EIP(tsk) \
96 ({ \
97 unsigned long eip = 0; \
98 if ((tsk)->thread.esp0 > PAGE_SIZE && \
99 MAP_NR((tsk)->thread.esp0) < max_mapnr) \
100 eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
101 eip; })
102#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
103
104#define cpu_relax() barrier()
105
106/* Get the Silicon Revision of the chip */
107static inline uint32_t bfin_revid(void)
108{
109 /* stored in the upper 4 bits */
110 return bfin_read_CHIPID() >> 28;
111}
112
113static inline uint32_t bfin_compiled_revid(void)
114{
115#if defined(CONFIG_BF_REV_0_0)
116 return 0;
117#elif defined(CONFIG_BF_REV_0_1)
118 return 1;
119#elif defined(CONFIG_BF_REV_0_2)
120 return 2;
121#elif defined(CONFIG_BF_REV_0_3)
122 return 3;
123#elif defined(CONFIG_BF_REV_0_4)
124 return 4;
125#elif defined(CONFIG_BF_REV_0_5)
126 return 5;
127#endif
128}
129
130#endif
diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h
new file mode 100644
index 000000000000..b8346cd3a6f6
--- /dev/null
+++ b/include/asm-blackfin/ptrace.h
@@ -0,0 +1,166 @@
1#ifndef _BFIN_PTRACE_H
2#define _BFIN_PTRACE_H
3
4/*
5 * GCC defines register number like this:
6 * -----------------------------
7 * 0 - 7 are data registers R0-R7
8 * 8 - 15 are address registers P0-P7
9 * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
10 * 32 - 33 A registers A0 & A1
11 * 34 - status register
12 * -----------------------------
13 *
14 * We follows above, except:
15 * 32-33 --- Low 32-bit of A0&1
16 * 34-35 --- High 8-bit of A0&1
17 */
18
19#ifndef __ASSEMBLY__
20
21/* this struct defines the way the registers are stored on the
22 stack during a system call. */
23
24struct pt_regs {
25 long orig_pc;
26 long ipend;
27 long seqstat;
28 long rete;
29 long retn;
30 long retx;
31 long pc; /* PC == RETI */
32 long rets;
33 long reserved; /* Used as scratch during system calls */
34 long astat;
35 long lb1;
36 long lb0;
37 long lt1;
38 long lt0;
39 long lc1;
40 long lc0;
41 long a1w;
42 long a1x;
43 long a0w;
44 long a0x;
45 long b3;
46 long b2;
47 long b1;
48 long b0;
49 long l3;
50 long l2;
51 long l1;
52 long l0;
53 long m3;
54 long m2;
55 long m1;
56 long m0;
57 long i3;
58 long i2;
59 long i1;
60 long i0;
61 long usp;
62 long fp;
63 long p5;
64 long p4;
65 long p3;
66 long p2;
67 long p1;
68 long p0;
69 long r7;
70 long r6;
71 long r5;
72 long r4;
73 long r3;
74 long r2;
75 long r1;
76 long r0;
77 long orig_r0;
78 long orig_p0;
79 long syscfg;
80};
81
82/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
83#define PTRACE_GETREGS 12
84#define PTRACE_SETREGS 13 /* ptrace signal */
85
86#ifdef CONFIG_BINFMT_ELF_FDPIC
87#define PTRACE_GETFDPIC 31
88#define PTRACE_GETFDPIC_EXEC 0
89#define PTRACE_GETFDPIC_INTERP 1
90#endif
91
92#define PS_S (0x0002)
93
94/* user_mode returns true if only one bit is set in IPEND, other than the
95 master interrupt enable. */
96#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
97#define instruction_pointer(regs) ((regs)->pc)
98#define profile_pc(regs) instruction_pointer(regs)
99extern void show_regs(struct pt_regs *);
100
101#endif /* __ASSEMBLY__ */
102
103/*
104 * Offsets used by 'ptrace' system call interface.
105 */
106
107#define PT_R0 204
108#define PT_R1 200
109#define PT_R2 196
110#define PT_R3 192
111#define PT_R4 188
112#define PT_R5 184
113#define PT_R6 180
114#define PT_R7 176
115#define PT_P0 172
116#define PT_P1 168
117#define PT_P2 164
118#define PT_P3 160
119#define PT_P4 156
120#define PT_P5 152
121#define PT_FP 148
122#define PT_USP 144
123#define PT_I0 140
124#define PT_I1 136
125#define PT_I2 132
126#define PT_I3 128
127#define PT_M0 124
128#define PT_M1 120
129#define PT_M2 116
130#define PT_M3 112
131#define PT_L0 108
132#define PT_L1 104
133#define PT_L2 100
134#define PT_L3 96
135#define PT_B0 92
136#define PT_B1 88
137#define PT_B2 84
138#define PT_B3 80
139#define PT_A0X 76
140#define PT_A0W 72
141#define PT_A1X 68
142#define PT_A1W 64
143#define PT_LC0 60
144#define PT_LC1 56
145#define PT_LT0 52
146#define PT_LT1 48
147#define PT_LB0 44
148#define PT_LB1 40
149#define PT_ASTAT 36
150#define PT_RESERVED 32
151#define PT_RETS 28
152#define PT_PC 24
153#define PT_RETX 20
154#define PT_RETN 16
155#define PT_RETE 12
156#define PT_SEQSTAT 8
157#define PT_IPEND 4
158
159#define PT_SYSCFG 216
160#define PT_TEXT_ADDR 220
161#define PT_TEXT_END_ADDR 224
162#define PT_DATA_ADDR 228
163#define PT_FDPIC_EXEC 232
164#define PT_FDPIC_INTERP 236
165
166#endif /* _BFIN_PTRACE_H */
diff --git a/include/asm-blackfin/resource.h b/include/asm-blackfin/resource.h
new file mode 100644
index 000000000000..091355ab3495
--- /dev/null
+++ b/include/asm-blackfin/resource.h
@@ -0,0 +1,6 @@
1#ifndef _BFIN_RESOURCE_H
2#define _BFIN_RESOURCE_H
3
4#include <asm-generic/resource.h>
5
6#endif /* _BFIN_RESOURCE_H */
diff --git a/include/asm-blackfin/scatterlist.h b/include/asm-blackfin/scatterlist.h
new file mode 100644
index 000000000000..60e07b92044c
--- /dev/null
+++ b/include/asm-blackfin/scatterlist.h
@@ -0,0 +1,26 @@
1#ifndef _BLACKFIN_SCATTERLIST_H
2#define _BLACKFIN_SCATTERLIST_H
3
4#include <linux/mm.h>
5
6struct scatterlist {
7 struct page *page;
8 unsigned int offset;
9 dma_addr_t dma_address;
10 unsigned int length;
11};
12
13/*
14 * These macros should be used after a pci_map_sg call has been done
15 * to get bus addresses of each of the SG entries and their lengths.
16 * You should only work with the number of sg entries pci_map_sg
17 * returns, or alternatively stop on the first sg_dma_len(sg) which
18 * is 0.
19 */
20#define sg_address(sg) (page_address((sg)->page) + (sg)->offset)
21#define sg_dma_address(sg) ((sg)->dma_address)
22#define sg_dma_len(sg) ((sg)->length)
23
24#define ISA_DMA_THRESHOLD (0xffffffff)
25
26#endif /* !(_BLACKFIN_SCATTERLIST_H) */
diff --git a/include/asm-blackfin/sections.h b/include/asm-blackfin/sections.h
new file mode 100644
index 000000000000..1443c3353a8c
--- /dev/null
+++ b/include/asm-blackfin/sections.h
@@ -0,0 +1,7 @@
1#ifndef _BLACKFIN_SECTIONS_H
2#define _BLACKFIN_SECTIONS_H
3
4/* nothing to see, move along */
5#include <asm-generic/sections.h>
6
7#endif
diff --git a/include/asm-blackfin/segment.h b/include/asm-blackfin/segment.h
new file mode 100644
index 000000000000..02cfd09b5a99
--- /dev/null
+++ b/include/asm-blackfin/segment.h
@@ -0,0 +1,7 @@
1#ifndef _BFIN_SEGMENT_H
2#define _BFIN_SEGMENT_H
3
4#define KERNEL_DS (0x5)
5#define USER_DS (0x1)
6
7#endif /* _BFIN_SEGMENT_H */
diff --git a/include/asm-blackfin/semaphore-helper.h b/include/asm-blackfin/semaphore-helper.h
new file mode 100644
index 000000000000..9082b0dc3eb5
--- /dev/null
+++ b/include/asm-blackfin/semaphore-helper.h
@@ -0,0 +1,82 @@
1/* Based on M68K version, Lineo Inc. May 2001 */
2
3#ifndef _BFIN_SEMAPHORE_HELPER_H
4#define _BFIN_SEMAPHORE_HELPER_H
5
6/*
7 * SMP- and interrupt-safe semaphores helper functions.
8 *
9 * (C) Copyright 1996 Linus Torvalds
10 *
11 */
12
13#include <asm/errno.h>
14
15/*
16 * These two _must_ execute atomically wrt each other.
17 */
18static inline void wake_one_more(struct semaphore *sem)
19{
20 atomic_inc(&sem->waking);
21}
22
23static inline int waking_non_zero(struct semaphore *sem)
24{
25 int ret;
26 unsigned long flags = 0;
27
28 spin_lock_irqsave(&semaphore_wake_lock, flags);
29 ret = 0;
30 if (atomic_read(&sem->waking) > 0) {
31 atomic_dec(&sem->waking);
32 ret = 1;
33 }
34 spin_unlock_irqrestore(&semaphore_wake_lock, flags);
35 return ret;
36}
37
38/*
39 * waking_non_zero_interruptible:
40 * 1 got the lock
41 * 0 go to sleep
42 * -EINTR interrupted
43 */
44static inline int waking_non_zero_interruptible(struct semaphore *sem,
45 struct task_struct *tsk)
46{
47 int ret = 0;
48 unsigned long flags = 0;
49
50 spin_lock_irqsave(&semaphore_wake_lock, flags);
51 if (atomic_read(&sem->waking) > 0) {
52 atomic_dec(&sem->waking);
53 ret = 1;
54 } else if (signal_pending(tsk)) {
55 atomic_inc(&sem->count);
56 ret = -EINTR;
57 }
58 spin_unlock_irqrestore(&semaphore_wake_lock, flags);
59 return ret;
60}
61
62/*
63 * waking_non_zero_trylock:
64 * 1 failed to lock
65 * 0 got the lock
66 */
67static inline int waking_non_zero_trylock(struct semaphore *sem)
68{
69 int ret = 1;
70 unsigned long flags = 0;
71
72 spin_lock_irqsave(&semaphore_wake_lock, flags);
73 if (atomic_read(&sem->waking) > 0) {
74 atomic_dec(&sem->waking);
75 ret = 0;
76 } else
77 atomic_inc(&sem->count);
78 spin_unlock_irqrestore(&semaphore_wake_lock, flags);
79 return ret;
80}
81
82#endif /* _BFIN_SEMAPHORE_HELPER_H */
diff --git a/include/asm-blackfin/semaphore.h b/include/asm-blackfin/semaphore.h
new file mode 100644
index 000000000000..94c04d7ab23e
--- /dev/null
+++ b/include/asm-blackfin/semaphore.h
@@ -0,0 +1,106 @@
1#ifndef _BFIN_SEMAPHORE_H
2#define _BFIN_SEMAPHORE_H
3
4#ifndef __ASSEMBLY__
5
6#include <linux/linkage.h>
7#include <linux/wait.h>
8#include <linux/spinlock.h>
9#include <linux/rwsem.h>
10#include <asm/atomic.h>
11
12/*
13 * Interrupt-safe semaphores..
14 *
15 * (C) Copyright 1996 Linus Torvalds
16 *
17 * BFIN version by akbar hussain Lineo Inc April 2001
18 *
19 */
20
21struct semaphore {
22 atomic_t count;
23 int sleepers;
24 wait_queue_head_t wait;
25};
26
27#define __SEMAPHORE_INITIALIZER(name, n) \
28{ \
29 .count = ATOMIC_INIT(n), \
30 .sleepers = 0, \
31 .wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
32}
33
34#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
35 struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
36
37#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1)
38#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0)
39
40static inline void sema_init(struct semaphore *sem, int val)
41{
42 *sem = (struct semaphore)__SEMAPHORE_INITIALIZER(*sem, val);
43}
44
45static inline void init_MUTEX(struct semaphore *sem)
46{
47 sema_init(sem, 1);
48}
49
50static inline void init_MUTEX_LOCKED(struct semaphore *sem)
51{
52 sema_init(sem, 0);
53}
54
55asmlinkage void __down(struct semaphore *sem);
56asmlinkage int __down_interruptible(struct semaphore *sem);
57asmlinkage int __down_trylock(struct semaphore *sem);
58asmlinkage void __up(struct semaphore *sem);
59
60extern spinlock_t semaphore_wake_lock;
61
62/*
63 * This is ugly, but we want the default case to fall through.
64 * "down_failed" is a special asm handler that calls the C
65 * routine that actually waits.
66 */
67static inline void down(struct semaphore *sem)
68{
69 might_sleep();
70 if (atomic_dec_return(&sem->count) < 0)
71 __down(sem);
72}
73
74static inline int down_interruptible(struct semaphore *sem)
75{
76 int ret = 0;
77
78 might_sleep();
79 if (atomic_dec_return(&sem->count) < 0)
80 ret = __down_interruptible(sem);
81 return (ret);
82}
83
84static inline int down_trylock(struct semaphore *sem)
85{
86 int ret = 0;
87
88 if (atomic_dec_return(&sem->count) < 0)
89 ret = __down_trylock(sem);
90 return ret;
91}
92
93/*
94 * Note! This is subtle. We jump to wake people up only if
95 * the semaphore was negative (== somebody was waiting on it).
96 * The default case (no contention) will result in NO
97 * jumps for both down() and up().
98 */
99static inline void up(struct semaphore *sem)
100{
101 if (atomic_inc_return(&sem->count) <= 0)
102 __up(sem);
103}
104
105#endif /* __ASSEMBLY__ */
106#endif /* _BFIN_SEMAPHORE_H */
diff --git a/include/asm-blackfin/sembuf.h b/include/asm-blackfin/sembuf.h
new file mode 100644
index 000000000000..18deb5c7fa5d
--- /dev/null
+++ b/include/asm-blackfin/sembuf.h
@@ -0,0 +1,25 @@
1#ifndef _BFIN_SEMBUF_H
2#define _BFIN_SEMBUF_H
3
4/*
5 * The semid64_ds structure for bfin architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct semid64_ds {
15 struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
16 __kernel_time_t sem_otime; /* last semop time */
17 unsigned long __unused1;
18 __kernel_time_t sem_ctime; /* last change time */
19 unsigned long __unused2;
20 unsigned long sem_nsems; /* no. of semaphores in array */
21 unsigned long __unused3;
22 unsigned long __unused4;
23};
24
25#endif /* _BFIN_SEMBUF_H */
diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h
new file mode 100644
index 000000000000..01c8c6cbe6fc
--- /dev/null
+++ b/include/asm-blackfin/setup.h
@@ -0,0 +1,17 @@
1/*
2** asm/setup.h -- Definition of the Linux/bfin setup information
3**
4** This file is subject to the terms and conditions of the GNU General Public
5** License. See the file COPYING in the main directory of this archive
6** for more details.
7**
8** Copyright Lineo, Inc 2001 Tony Kou
9**
10*/
11
12#ifndef _BFIN_SETUP_H
13#define _BFIN_SETUP_H
14
15#define COMMAND_LINE_SIZE 512
16
17#endif /* _BFIN_SETUP_H */
diff --git a/include/asm-blackfin/shmbuf.h b/include/asm-blackfin/shmbuf.h
new file mode 100644
index 000000000000..612436303e89
--- /dev/null
+++ b/include/asm-blackfin/shmbuf.h
@@ -0,0 +1,42 @@
1#ifndef _BFIN_SHMBUF_H
2#define _BFIN_SHMBUF_H
3
4/*
5 * The shmid64_ds structure for bfin architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13
14struct shmid64_ds {
15 struct ipc64_perm shm_perm; /* operation perms */
16 size_t shm_segsz; /* size of segment (bytes) */
17 __kernel_time_t shm_atime; /* last attach time */
18 unsigned long __unused1;
19 __kernel_time_t shm_dtime; /* last detach time */
20 unsigned long __unused2;
21 __kernel_time_t shm_ctime; /* last change time */
22 unsigned long __unused3;
23 __kernel_pid_t shm_cpid; /* pid of creator */
24 __kernel_pid_t shm_lpid; /* pid of last operator */
25 unsigned long shm_nattch; /* no. of current attaches */
26 unsigned long __unused4;
27 unsigned long __unused5;
28};
29
30struct shminfo64 {
31 unsigned long shmmax;
32 unsigned long shmmin;
33 unsigned long shmmni;
34 unsigned long shmseg;
35 unsigned long shmall;
36 unsigned long __unused1;
37 unsigned long __unused2;
38 unsigned long __unused3;
39 unsigned long __unused4;
40};
41
42#endif /* _BFIN_SHMBUF_H */
diff --git a/include/asm-blackfin/shmparam.h b/include/asm-blackfin/shmparam.h
new file mode 100644
index 000000000000..3c03906b7664
--- /dev/null
+++ b/include/asm-blackfin/shmparam.h
@@ -0,0 +1,6 @@
1#ifndef _BFIN_SHMPARAM_H
2#define _BFIN_SHMPARAM_H
3
4#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
5
6#endif /* _BFIN_SHMPARAM_H */
diff --git a/include/asm-blackfin/sigcontext.h b/include/asm-blackfin/sigcontext.h
new file mode 100644
index 000000000000..ce00b03c2775
--- /dev/null
+++ b/include/asm-blackfin/sigcontext.h
@@ -0,0 +1,55 @@
1#ifndef _ASM_BLACKFIN_SIGCONTEXT_H
2#define _ASM_BLACKFIN_SIGCONTEXT_H
3
4/* Add new entries at the end of the structure only. */
5struct sigcontext {
6 unsigned long sc_r0;
7 unsigned long sc_r1;
8 unsigned long sc_r2;
9 unsigned long sc_r3;
10 unsigned long sc_r4;
11 unsigned long sc_r5;
12 unsigned long sc_r6;
13 unsigned long sc_r7;
14 unsigned long sc_p0;
15 unsigned long sc_p1;
16 unsigned long sc_p2;
17 unsigned long sc_p3;
18 unsigned long sc_p4;
19 unsigned long sc_p5;
20 unsigned long sc_usp;
21 unsigned long sc_a0w;
22 unsigned long sc_a1w;
23 unsigned long sc_a0x;
24 unsigned long sc_a1x;
25 unsigned long sc_astat;
26 unsigned long sc_rets;
27 unsigned long sc_pc;
28 unsigned long sc_retx;
29 unsigned long sc_fp;
30 unsigned long sc_i0;
31 unsigned long sc_i1;
32 unsigned long sc_i2;
33 unsigned long sc_i3;
34 unsigned long sc_m0;
35 unsigned long sc_m1;
36 unsigned long sc_m2;
37 unsigned long sc_m3;
38 unsigned long sc_l0;
39 unsigned long sc_l1;
40 unsigned long sc_l2;
41 unsigned long sc_l3;
42 unsigned long sc_b0;
43 unsigned long sc_b1;
44 unsigned long sc_b2;
45 unsigned long sc_b3;
46 unsigned long sc_lc0;
47 unsigned long sc_lc1;
48 unsigned long sc_lt0;
49 unsigned long sc_lt1;
50 unsigned long sc_lb0;
51 unsigned long sc_lb1;
52 unsigned long sc_seqstat;
53};
54
55#endif
diff --git a/include/asm-blackfin/siginfo.h b/include/asm-blackfin/siginfo.h
new file mode 100644
index 000000000000..eca4565cea37
--- /dev/null
+++ b/include/asm-blackfin/siginfo.h
@@ -0,0 +1,35 @@
1#ifndef _BFIN_SIGINFO_H
2#define _BFIN_SIGINFO_H
3
4#include <linux/types.h>
5#include <asm-generic/siginfo.h>
6
7#define UID16_SIGINFO_COMPAT_NEEDED
8
9#define si_uid16 _sifields._kill._uid
10
11#define ILL_ILLPARAOP (__SI_FAULT|2) /* illegal opcode combine ********** */
12#define ILL_ILLEXCPT (__SI_FAULT|4) /* unrecoverable exception ********** */
13#define ILL_CPLB_VI (__SI_FAULT|9) /* D/I CPLB protect violation ******** */
14#define ILL_CPLB_MISS (__SI_FAULT|10) /* D/I CPLB miss ******** */
15#define ILL_CPLB_MULHIT (__SI_FAULT|11) /* D/I CPLB multiple hit ******** */
16
17/*
18 * SIGBUS si_codes
19 */
20#define BUS_OPFETCH (__SI_FAULT|4) /* error from instruction fetch ******** */
21
22/*
23 * SIGTRAP si_codes
24 */
25#define TRAP_STEP (__SI_FAULT|1) /* single-step breakpoint************* */
26#define TRAP_TRACEFLOW (__SI_FAULT|2) /* trace buffer overflow ************* */
27#define TRAP_WATCHPT (__SI_FAULT|3) /* watchpoint match ************* */
28#define TRAP_ILLTRAP (__SI_FAULT|4) /* illegal trap ************* */
29
30/*
31 * SIGSEGV si_codes
32 */
33#define SEGV_STACKFLOW (__SI_FAULT|3) /* stack overflow */
34
35#endif
diff --git a/include/asm-blackfin/signal.h b/include/asm-blackfin/signal.h
new file mode 100644
index 000000000000..0250429b736a
--- /dev/null
+++ b/include/asm-blackfin/signal.h
@@ -0,0 +1,160 @@
1#ifndef _BLACKFIN_SIGNAL_H
2#define _BLACKFIN_SIGNAL_H
3
4#include <linux/types.h>
5
6/* Avoid too many header ordering problems. */
7struct siginfo;
8
9#ifdef __KERNEL__
10/* Most things should be clean enough to redefine this at will, if care
11 is taken to make libc match. */
12
13#define _NSIG 64
14#define _NSIG_BPW 32
15#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
16
17typedef unsigned long old_sigset_t; /* at least 32 bits */
18
19typedef struct {
20 unsigned long sig[_NSIG_WORDS];
21} sigset_t;
22
23#else
24/* Here we must cater to libcs that poke about in kernel headers. */
25
26#define NSIG 32
27typedef unsigned long sigset_t;
28
29#endif /* __KERNEL__ */
30
31#define SIGHUP 1
32#define SIGINT 2
33#define SIGQUIT 3
34#define SIGILL 4
35#define SIGTRAP 5
36#define SIGABRT 6
37#define SIGIOT 6
38#define SIGBUS 7
39#define SIGFPE 8
40#define SIGKILL 9
41#define SIGUSR1 10
42#define SIGSEGV 11
43#define SIGUSR2 12
44#define SIGPIPE 13
45#define SIGALRM 14
46#define SIGTERM 15
47#define SIGSTKFLT 16
48#define SIGCHLD 17
49#define SIGCONT 18
50#define SIGSTOP 19
51#define SIGTSTP 20
52#define SIGTTIN 21
53#define SIGTTOU 22
54#define SIGURG 23
55#define SIGXCPU 24
56#define SIGXFSZ 25
57#define SIGVTALRM 26
58#define SIGPROF 27
59#define SIGWINCH 28
60#define SIGIO 29
61#define SIGPOLL SIGIO
62/*
63#define SIGLOST 29
64*/
65#define SIGPWR 30
66#define SIGSYS 31
67#define SIGUNUSED 31
68
69/* These should not be considered constants from userland. */
70#define SIGRTMIN 32
71#define SIGRTMAX _NSIG
72
73/*
74 * SA_FLAGS values:
75 *
76 * SA_ONSTACK indicates that a registered stack_t will be used.
77 * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
78 * SA_RESTART flag to get restarting signals (which were the default long ago)
79 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
80 * SA_RESETHAND clears the handler when the signal is delivered.
81 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
82 * SA_NODEFER prevents the current signal from being masked in the handler.
83 *
84 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
85 * Unix names RESETHAND and NODEFER respectively.
86 */
87#define SA_NOCLDSTOP 0x00000001
88#define SA_NOCLDWAIT 0x00000002 /* not supported yet */
89#define SA_SIGINFO 0x00000004
90#define SA_ONSTACK 0x08000000
91#define SA_RESTART 0x10000000
92#define SA_NODEFER 0x40000000
93#define SA_RESETHAND 0x80000000
94
95#define SA_NOMASK SA_NODEFER
96#define SA_ONESHOT SA_RESETHAND
97
98/*
99 * sigaltstack controls
100 */
101#define SS_ONSTACK 1
102#define SS_DISABLE 2
103
104#define MINSIGSTKSZ 2048
105#define SIGSTKSZ 8192
106
107#include <asm-generic/signal.h>
108
109#ifdef __KERNEL__
110struct old_sigaction {
111 __sighandler_t sa_handler;
112 old_sigset_t sa_mask;
113 unsigned long sa_flags;
114 void (*sa_restorer) (void);
115};
116
117struct sigaction {
118 __sighandler_t sa_handler;
119 unsigned long sa_flags;
120 void (*sa_restorer) (void);
121 sigset_t sa_mask; /* mask last for extensibility */
122};
123
124struct k_sigaction {
125 struct sigaction sa;
126};
127#else
128/* Here we must cater to libcs that poke about in kernel headers. */
129
130struct sigaction {
131 union {
132 __sighandler_t _sa_handler;
133 void (*_sa_sigaction) (int, struct siginfo *, void *);
134 } _u;
135 sigset_t sa_mask;
136 unsigned long sa_flags;
137 void (*sa_restorer) (void);
138};
139
140#define sa_handler _u._sa_handler
141#define sa_sigaction _u._sa_sigaction
142
143#endif /* __KERNEL__ */
144
145typedef struct sigaltstack {
146 void *ss_sp;
147 int ss_flags;
148 size_t ss_size;
149} stack_t;
150
151#ifdef __KERNEL__
152
153#include <asm/sigcontext.h>
154#undef __HAVE_ARCH_SIG_BITOPS
155
156#define ptrace_signal_deliver(regs, cookie) do { } while (0)
157
158#endif /* __KERNEL__ */
159
160#endif /* _BLACKFIN_SIGNAL_H */
diff --git a/include/asm-blackfin/socket.h b/include/asm-blackfin/socket.h
new file mode 100644
index 000000000000..5213c9652186
--- /dev/null
+++ b/include/asm-blackfin/socket.h
@@ -0,0 +1,53 @@
1#ifndef _ASM_SOCKET_H
2#define _ASM_SOCKET_H
3
4#include <asm/sockios.h>
5
6/* For setsockoptions(2) */
7#define SOL_SOCKET 1
8
9#define SO_DEBUG 1
10#define SO_REUSEADDR 2
11#define SO_TYPE 3
12#define SO_ERROR 4
13#define SO_DONTROUTE 5
14#define SO_BROADCAST 6
15#define SO_SNDBUF 7
16#define SO_RCVBUF 8
17#define SO_SNDBUFFORCE 32
18#define SO_RCVBUFFORCE 33
19#define SO_KEEPALIVE 9
20#define SO_OOBINLINE 10
21#define SO_NO_CHECK 11
22#define SO_PRIORITY 12
23#define SO_LINGER 13
24#define SO_BSDCOMPAT 14
25/* To add :#define SO_REUSEPORT 15 */
26#define SO_PASSCRED 16
27#define SO_PEERCRED 17
28#define SO_RCVLOWAT 18
29#define SO_SNDLOWAT 19
30#define SO_RCVTIMEO 20
31#define SO_SNDTIMEO 21
32
33/* Security levels - as per NRL IPv6 - don't actually do anything */
34#define SO_SECURITY_AUTHENTICATION 22
35#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
36#define SO_SECURITY_ENCRYPTION_NETWORK 24
37
38#define SO_BINDTODEVICE 25
39
40/* Socket filtering */
41#define SO_ATTACH_FILTER 26
42#define SO_DETACH_FILTER 27
43
44#define SO_PEERNAME 28
45#define SO_TIMESTAMP 29
46#define SCM_TIMESTAMP SO_TIMESTAMP
47
48#define SO_ACCEPTCONN 30
49#define SO_PEERSEC 31
50#define SO_PASSSEC 34
51#define SO_TIMESTAMPNS 35
52#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
53#endif /* _ASM_SOCKET_H */
diff --git a/include/asm-blackfin/sockios.h b/include/asm-blackfin/sockios.h
new file mode 100644
index 000000000000..426b89bfaa8b
--- /dev/null
+++ b/include/asm-blackfin/sockios.h
@@ -0,0 +1,13 @@
1#ifndef __ARCH_BFIN_SOCKIOS__
2#define __ARCH_BFIN_SOCKIOS__
3
4/* Socket-level I/O control calls. */
5#define FIOSETOWN 0x8901
6#define SIOCSPGRP 0x8902
7#define FIOGETOWN 0x8903
8#define SIOCGPGRP 0x8904
9#define SIOCATMARK 0x8905
10#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
11#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
12
13#endif /* __ARCH_BFIN_SOCKIOS__ */
diff --git a/include/asm-blackfin/spinlock.h b/include/asm-blackfin/spinlock.h
new file mode 100644
index 000000000000..64e908a50646
--- /dev/null
+++ b/include/asm-blackfin/spinlock.h
@@ -0,0 +1,6 @@
1#ifndef __BFIN_SPINLOCK_H
2#define __BFIN_SPINLOCK_H
3
4#error blackfin architecture does not support SMP spin lock yet
5
6#endif
diff --git a/include/asm-blackfin/stat.h b/include/asm-blackfin/stat.h
new file mode 100644
index 000000000000..d2b6f11ec231
--- /dev/null
+++ b/include/asm-blackfin/stat.h
@@ -0,0 +1,63 @@
1#ifndef _BFIN_STAT_H
2#define _BFIN_STAT_H
3
4struct stat {
5 unsigned short st_dev;
6 unsigned short __pad1;
7 unsigned long st_ino;
8 unsigned short st_mode;
9 unsigned short st_nlink;
10 unsigned short st_uid;
11 unsigned short st_gid;
12 unsigned short st_rdev;
13 unsigned short __pad2;
14 unsigned long st_size;
15 unsigned long st_blksize;
16 unsigned long st_blocks;
17 unsigned long st_atime;
18 unsigned long __unused1;
19 unsigned long st_mtime;
20 unsigned long __unused2;
21 unsigned long st_ctime;
22 unsigned long __unused3;
23 unsigned long __unused4;
24 unsigned long __unused5;
25};
26
27/* This matches struct stat64 in glibc2.1, hence the absolutely
28 * insane amounts of padding around dev_t's.
29 */
30struct stat64 {
31 unsigned long long st_dev;
32 unsigned char __pad1[4];
33
34#define STAT64_HAS_BROKEN_ST_INO 1
35 unsigned long __st_ino;
36
37 unsigned int st_mode;
38 unsigned int st_nlink;
39
40 unsigned long st_uid;
41 unsigned long st_gid;
42
43 unsigned long long st_rdev;
44 unsigned char __pad2[4];
45
46 long long st_size;
47 unsigned long st_blksize;
48
49 long long st_blocks; /* Number 512-byte blocks allocated. */
50
51 unsigned long st_atime;
52 unsigned long st_atime_nsec;
53
54 unsigned long st_mtime;
55 unsigned long st_mtime_nsec;
56
57 unsigned long st_ctime;
58 unsigned long st_ctime_nsec;
59
60 unsigned long long st_ino;
61};
62
63#endif /* _BFIN_STAT_H */
diff --git a/include/asm-blackfin/statfs.h b/include/asm-blackfin/statfs.h
new file mode 100644
index 000000000000..350672091ba3
--- /dev/null
+++ b/include/asm-blackfin/statfs.h
@@ -0,0 +1,6 @@
1#ifndef _BFIN_STATFS_H
2#define _BFIN_STATFS_H
3
4#include <asm-generic/statfs.h>
5
6#endif /* _BFIN_STATFS_H */
diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
new file mode 100644
index 000000000000..6f1eb7d6d3cb
--- /dev/null
+++ b/include/asm-blackfin/string.h
@@ -0,0 +1,104 @@
1#ifndef _BLACKFIN_STRING_H_
2#define _BLACKFIN_STRING_H_
3
4#ifdef __KERNEL__ /* only set these up for kernel code */
5
6#define __HAVE_ARCH_STRCPY
7extern inline char *strcpy(char *dest, const char *src)
8{
9 char *xdest = dest;
10 char temp = 0;
11
12 __asm__ __volatile__
13 ("1:\t%2 = B [%1++] (Z);\n\t"
14 "B [%0++] = %2;\n\t"
15 "CC = %2;\n\t"
16 "if cc jump 1b (bp);\n"
17 : "+&a" (dest), "+&a" (src), "=&d" (temp)
18 ::"memory", "CC");
19 return xdest;
20}
21
22#define __HAVE_ARCH_STRNCPY
23extern inline char *strncpy(char *dest, const char *src, size_t n)
24{
25 char *xdest = dest;
26 char temp = 0;
27
28 if (n == 0)
29 return xdest;
30
31 __asm__ __volatile__
32 ("1:\t%3 = B [%1++] (Z);\n\t"
33 "B [%0++] = %3;\n\t"
34 "CC = %3;\n\t"
35 "if ! cc jump 2f;\n\t"
36 "%2 += -1;\n\t"
37 "CC = %2 == 0;\n\t"
38 "if ! cc jump 1b (bp);\n"
39 "2:\n"
40 : "+&a" (dest), "+&a" (src), "+&da" (n), "=&d" (temp)
41 ::"memory", "CC");
42 return xdest;
43}
44
45#define __HAVE_ARCH_STRCMP
46extern inline int strcmp(const char *cs, const char *ct)
47{
48 char __res1, __res2;
49
50 __asm__
51 ("1:\t%2 = B[%0++] (Z);\n\t" /* get *cs */
52 "%3 = B[%1++] (Z);\n\t" /* get *ct */
53 "CC = %2 == %3;\n\t" /* compare a byte */
54 "if ! cc jump 2f;\n\t" /* not equal, break out */
55 "CC = %2;\n\t" /* at end of cs? */
56 "if cc jump 1b (bp);\n\t" /* no, keep going */
57 "jump.s 3f;\n" /* strings are equal */
58 "2:\t%2 = %2 - %3;\n" /* *cs - *ct */
59 "3:\n"
60 : "+&a" (cs), "+&a" (ct), "=&d" (__res1), "=&d" (__res2)
61 : : "CC");
62
63 return __res1;
64}
65
66#define __HAVE_ARCH_STRNCMP
67extern inline int strncmp(const char *cs, const char *ct, size_t count)
68{
69 char __res1, __res2;
70
71 if (!count)
72 return 0;
73 __asm__
74 ("1:\t%3 = B[%0++] (Z);\n\t" /* get *cs */
75 "%4 = B[%1++] (Z);\n\t" /* get *ct */
76 "CC = %3 == %4;\n\t" /* compare a byte */
77 "if ! cc jump 3f;\n\t" /* not equal, break out */
78 "CC = %3;\n\t" /* at end of cs? */
79 "if ! cc jump 4f;\n\t" /* yes, all done */
80 "%2 += -1;\n\t" /* no, adjust count */
81 "CC = %2 == 0;\n\t"
82 "if ! cc jump 1b;\n" /* more to do, keep going */
83 "2:\t%3 = 0;\n\t" /* strings are equal */
84 "jump.s 4f;\n"
85 "3:\t%3 = %3 - %4;\n" /* *cs - *ct */
86 "4:"
87 : "+&a" (cs), "+&a" (ct), "+&da" (count), "=&d" (__res1), "=&d" (__res2)
88 : : "CC");
89 return __res1;
90}
91
92#define __HAVE_ARCH_MEMSET
93extern void *memset(void *s, int c, size_t count);
94#define __HAVE_ARCH_MEMCPY
95extern void *memcpy(void *d, const void *s, size_t count);
96#define __HAVE_ARCH_MEMCMP
97extern int memcmp(const void *, const void *, __kernel_size_t);
98#define __HAVE_ARCH_MEMCHR
99extern void *memchr(const void *s, int c, size_t n);
100#define __HAVE_ARCH_MEMMOVE
101extern void *memmove(void *dest, const void *src, size_t count);
102
103#endif /*__KERNEL__*/
104#endif /* _BLACKFIN_STRING_H_ */
diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h
new file mode 100644
index 000000000000..758bac7c1e74
--- /dev/null
+++ b/include/asm-blackfin/system.h
@@ -0,0 +1,250 @@
1/*
2 * File: include/asm/system.h
3 * Based on:
4 * Author: Tony Kou (tonyko@lineo.ca)
5 * Copyright (c) 2002 Arcturus Networks Inc.
6 * (www.arcturusnetworks.com)
7 * Copyright (c) 2003 Metrowerks (www.metrowerks.com)
8 * Copyright (c) 2004 Analog Device Inc.
9 * Created: 25Jan2001 - Tony Kou
10 * Description: system.h include file
11 *
12 * Modified: 22Sep2006 - Robin Getz
13 * - move include blackfin.h down, so I can get access to
14 * irq functions in other include files.
15 *
16 * Bugs: Enter bugs at http://blackfin.uclinux.org/
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2, or (at your option)
21 * any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; see the file COPYING.
30 * If not, write to the Free Software Foundation,
31 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33
34#ifndef _BLACKFIN_SYSTEM_H
35#define _BLACKFIN_SYSTEM_H
36
37#include <linux/linkage.h>
38#include <linux/compiler.h>
39
40/*
41 * Interrupt configuring macros.
42 */
43
44extern unsigned long irq_flags;
45
46#define local_irq_enable() do { \
47 __asm__ __volatile__ ( \
48 "sti %0;" \
49 ::"d"(irq_flags)); \
50} while (0)
51
52#define local_irq_disable() do { \
53 int _tmp_dummy; \
54 __asm__ __volatile__ ( \
55 "cli %0;" \
56 :"=d" (_tmp_dummy):); \
57} while (0)
58
59#if defined(ANOMALY_05000244) && defined (CONFIG_BLKFIN_CACHE)
60#define idle_with_irq_disabled() do { \
61 __asm__ __volatile__ ( \
62 "nop; nop;\n" \
63 ".align 8;\n" \
64 "sti %0; idle;\n" \
65 ::"d" (irq_flags)); \
66} while (0)
67#else
68#define idle_with_irq_disabled() do { \
69 __asm__ __volatile__ ( \
70 ".align 8;\n" \
71 "sti %0; idle;\n" \
72 ::"d" (irq_flags)); \
73} while (0)
74#endif
75
76#ifdef CONFIG_DEBUG_HWERR
77#define __save_and_cli(x) do { \
78 __asm__ __volatile__ ( \
79 "cli %0;\n\tsti %1;" \
80 :"=&d"(x): "d" (0x3F)); \
81} while (0)
82#else
83#define __save_and_cli(x) do { \
84 __asm__ __volatile__ ( \
85 "cli %0;" \
86 :"=&d"(x):); \
87} while (0)
88#endif
89
90#define local_save_flags(x) asm volatile ("cli %0;" \
91 "sti %0;" \
92 :"=d"(x):);
93
94#ifdef CONFIG_DEBUG_HWERR
95#define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0)
96#else
97#define irqs_enabled_from_flags(x) ((x) != 0x1f)
98#endif
99
100#define local_irq_restore(x) do { \
101 if (irqs_enabled_from_flags(x)) \
102 local_irq_enable (); \
103} while (0)
104
105/* For spinlocks etc */
106#define local_irq_save(x) __save_and_cli(x)
107
108#define irqs_disabled() \
109({ \
110 unsigned long flags; \
111 local_save_flags(flags); \
112 !irqs_enabled_from_flags(flags); \
113})
114
115/*
116 * Force strict CPU ordering.
117 */
118#define nop() asm volatile ("nop;\n\t"::)
119#define mb() asm volatile ("" : : :"memory")
120#define rmb() asm volatile ("" : : :"memory")
121#define wmb() asm volatile ("" : : :"memory")
122#define set_rmb(var, value) do { (void) xchg(&var, value); } while (0)
123#define set_mb(var, value) set_rmb(var, value)
124#define set_wmb(var, value) do { var = value; wmb(); } while (0)
125
126#define read_barrier_depends() do { } while(0)
127
128#ifdef CONFIG_SMP
129#define smp_mb() mb()
130#define smp_rmb() rmb()
131#define smp_wmb() wmb()
132#define smp_read_barrier_depends() read_barrier_depends()
133#else
134#define smp_mb() barrier()
135#define smp_rmb() barrier()
136#define smp_wmb() barrier()
137#define smp_read_barrier_depends() do { } while(0)
138#endif
139
140#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
141#define tas(ptr) ((void)xchg((ptr),1))
142
143struct __xchg_dummy {
144 unsigned long a[100];
145};
146#define __xg(x) ((volatile struct __xchg_dummy *)(x))
147
148static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
149 int size)
150{
151 unsigned long tmp = 0;
152 unsigned long flags = 0;
153
154 local_irq_save(flags);
155
156 switch (size) {
157 case 1:
158 __asm__ __volatile__
159 ("%0 = b%2 (z);\n\t"
160 "b%2 = %1;\n\t"
161 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
162 break;
163 case 2:
164 __asm__ __volatile__
165 ("%0 = w%2 (z);\n\t"
166 "w%2 = %1;\n\t"
167 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
168 break;
169 case 4:
170 __asm__ __volatile__
171 ("%0 = %2;\n\t"
172 "%2 = %1;\n\t"
173 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
174 break;
175 }
176 local_irq_restore(flags);
177 return tmp;
178}
179
180/*
181 * Atomic compare and exchange. Compare OLD with MEM, if identical,
182 * store NEW in MEM. Return the initial value in MEM. Success is
183 * indicated by comparing RETURN with OLD.
184 */
185static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
186 unsigned long new, int size)
187{
188 unsigned long tmp = 0;
189 unsigned long flags = 0;
190
191 local_irq_save(flags);
192
193 switch (size) {
194 case 1:
195 __asm__ __volatile__
196 ("%0 = b%3 (z);\n\t"
197 "CC = %1 == %0;\n\t"
198 "IF !CC JUMP 1f;\n\t"
199 "b%3 = %2;\n\t"
200 "1:\n\t"
201 : "=&d" (tmp) : "d" (old), "d" (new), "m" (*__xg(ptr)) : "memory");
202 break;
203 case 2:
204 __asm__ __volatile__
205 ("%0 = w%3 (z);\n\t"
206 "CC = %1 == %0;\n\t"
207 "IF !CC JUMP 1f;\n\t"
208 "w%3 = %2;\n\t"
209 "1:\n\t"
210 : "=&d" (tmp) : "d" (old), "d" (new), "m" (*__xg(ptr)) : "memory");
211 break;
212 case 4:
213 __asm__ __volatile__
214 ("%0 = %3;\n\t"
215 "CC = %1 == %0;\n\t"
216 "IF !CC JUMP 1f;\n\t"
217 "%3 = %2;\n\t"
218 "1:\n\t"
219 : "=&d" (tmp) : "d" (old), "d" (new), "m" (*__xg(ptr)) : "memory");
220 break;
221 }
222 local_irq_restore(flags);
223 return tmp;
224}
225
226#define cmpxchg(ptr,o,n)\
227 ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
228 (unsigned long)(n),sizeof(*(ptr))))
229
230#define prepare_to_switch() do { } while(0)
231
232/*
233 * switch_to(n) should switch tasks to task ptr, first checking that
234 * ptr isn't the current task, in which case it does nothing.
235 */
236
237#include <asm/blackfin.h>
238
239asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next);
240
241#define switch_to(prev,next,last) \
242do { \
243 memcpy (&prev->thread_info->l1_task_info, L1_SCRATCH_TASK_INFO, \
244 sizeof *L1_SCRATCH_TASK_INFO); \
245 memcpy (L1_SCRATCH_TASK_INFO, &next->thread_info->l1_task_info, \
246 sizeof *L1_SCRATCH_TASK_INFO); \
247 (last) = resume (prev, next); \
248} while (0)
249
250#endif /* _BLACKFIN_SYSTEM_H */
diff --git a/include/asm-blackfin/termbits.h b/include/asm-blackfin/termbits.h
new file mode 100644
index 000000000000..2fd9dabdba77
--- /dev/null
+++ b/include/asm-blackfin/termbits.h
@@ -0,0 +1,184 @@
1#ifndef __ARCH_BFIN_TERMBITS_H__
2#define __ARCH_BFIN_TERMBITS_H__
3
4#include <linux/posix_types.h>
5
6typedef unsigned char cc_t;
7typedef unsigned int speed_t;
8typedef unsigned int tcflag_t;
9
10#define NCCS 19
11struct termios {
12 tcflag_t c_iflag; /* input mode flags */
13 tcflag_t c_oflag; /* output mode flags */
14 tcflag_t c_cflag; /* control mode flags */
15 tcflag_t c_lflag; /* local mode flags */
16 cc_t c_line; /* line discipline */
17 cc_t c_cc[NCCS]; /* control characters */
18};
19
20struct ktermios {
21 tcflag_t c_iflag; /* input mode flags */
22 tcflag_t c_oflag; /* output mode flags */
23 tcflag_t c_cflag; /* control mode flags */
24 tcflag_t c_lflag; /* local mode flags */
25 cc_t c_line; /* line discipline */
26 cc_t c_cc[NCCS]; /* control characters */
27 speed_t c_ispeed; /* input speed */
28 speed_t c_ospeed; /* output speed */
29};
30
31/* c_cc characters */
32#define VINTR 0
33#define VQUIT 1
34#define VERASE 2
35#define VKILL 3
36#define VEOF 4
37#define VTIME 5
38#define VMIN 6
39#define VSWTC 7
40#define VSTART 8
41#define VSTOP 9
42#define VSUSP 10
43#define VEOL 11
44#define VREPRINT 12
45#define VDISCARD 13
46#define VWERASE 14
47#define VLNEXT 15
48#define VEOL2 16
49
50/* c_iflag bits */
51#define IGNBRK 0000001
52#define BRKINT 0000002
53#define IGNPAR 0000004
54#define PARMRK 0000010
55#define INPCK 0000020
56#define ISTRIP 0000040
57#define INLCR 0000100
58#define IGNCR 0000200
59#define ICRNL 0000400
60#define IUCLC 0001000
61#define IXON 0002000
62#define IXANY 0004000
63#define IXOFF 0010000
64#define IMAXBEL 0020000
65#define IUTF8 0040000
66
67/* c_oflag bits */
68#define OPOST 0000001
69#define OLCUC 0000002
70#define ONLCR 0000004
71#define OCRNL 0000010
72#define ONOCR 0000020
73#define ONLRET 0000040
74#define OFILL 0000100
75#define OFDEL 0000200
76#define NLDLY 0000400
77#define NL0 0000000
78#define NL1 0000400
79#define CRDLY 0003000
80#define CR0 0000000
81#define CR1 0001000
82#define CR2 0002000
83#define CR3 0003000
84#define TABDLY 0014000
85#define TAB0 0000000
86#define TAB1 0004000
87#define TAB2 0010000
88#define TAB3 0014000
89#define XTABS 0014000
90#define BSDLY 0020000
91#define BS0 0000000
92#define BS1 0020000
93#define VTDLY 0040000
94#define VT0 0000000
95#define VT1 0040000
96#define FFDLY 0100000
97#define FF0 0000000
98#define FF1 0100000
99
100/* c_cflag bit meaning */
101#define CBAUD 0010017
102#define B0 0000000 /* hang up */
103#define B50 0000001
104#define B75 0000002
105#define B110 0000003
106#define B134 0000004
107#define B150 0000005
108#define B200 0000006
109#define B300 0000007
110#define B600 0000010
111#define B1200 0000011
112#define B1800 0000012
113#define B2400 0000013
114#define B4800 0000014
115#define B9600 0000015
116#define B19200 0000016
117#define B38400 0000017
118#define EXTA B19200
119#define EXTB B38400
120#define CSIZE 0000060
121#define CS5 0000000
122#define CS6 0000020
123#define CS7 0000040
124#define CS8 0000060
125#define CSTOPB 0000100
126#define CREAD 0000200
127#define PARENB 0000400
128#define PARODD 0001000
129#define HUPCL 0002000
130#define CLOCAL 0004000
131#define CBAUDEX 0010000
132#define B57600 0010001
133#define B115200 0010002
134#define B230400 0010003
135#define B460800 0010004
136#define B500000 0010005
137#define B576000 0010006
138#define B921600 0010007
139#define B1000000 0010010
140#define B1152000 0010011
141#define B1500000 0010012
142#define B2000000 0010013
143#define B2500000 0010014
144#define B3000000 0010015
145#define B3500000 0010016
146#define B4000000 0010017
147#define CIBAUD 002003600000 /* input baud rate (not used) */
148#define CMSPAR 010000000000 /* mark or space (stick) parity */
149#define CRTSCTS 020000000000 /* flow control */
150
151/* c_lflag bits */
152#define ISIG 0000001
153#define ICANON 0000002
154#define XCASE 0000004
155#define ECHO 0000010
156#define ECHOE 0000020
157#define ECHOK 0000040
158#define ECHONL 0000100
159#define NOFLSH 0000200
160#define TOSTOP 0000400
161#define ECHOCTL 0001000
162#define ECHOPRT 0002000
163#define ECHOKE 0004000
164#define FLUSHO 0010000
165#define PENDIN 0040000
166#define IEXTEN 0100000
167
168/* tcflow() and TCXONC use these */
169#define TCOOFF 0
170#define TCOON 1
171#define TCIOFF 2
172#define TCION 3
173
174/* tcflush() and TCFLSH use these */
175#define TCIFLUSH 0
176#define TCOFLUSH 1
177#define TCIOFLUSH 2
178
179/* tcsetattr uses these */
180#define TCSANOW 0
181#define TCSADRAIN 1
182#define TCSAFLUSH 2
183
184#endif /* __ARCH_BFIN_TERMBITS_H__ */
diff --git a/include/asm-blackfin/termios.h b/include/asm-blackfin/termios.h
new file mode 100644
index 000000000000..5c41478a51c6
--- /dev/null
+++ b/include/asm-blackfin/termios.h
@@ -0,0 +1,106 @@
1#ifndef __BFIN_TERMIOS_H__
2#define __BFIN_TERMIOS_H__
3
4#include <asm/termbits.h>
5#include <asm/ioctls.h>
6
7struct winsize {
8 unsigned short ws_row;
9 unsigned short ws_col;
10 unsigned short ws_xpixel;
11 unsigned short ws_ypixel;
12};
13
14#define NCC 8
15struct termio {
16 unsigned short c_iflag; /* input mode flags */
17 unsigned short c_oflag; /* output mode flags */
18 unsigned short c_cflag; /* control mode flags */
19 unsigned short c_lflag; /* local mode flags */
20 unsigned char c_line; /* line discipline */
21 unsigned char c_cc[NCC]; /* control characters */
22};
23
24/* modem lines */
25#define TIOCM_LE 0x001
26#define TIOCM_DTR 0x002
27#define TIOCM_RTS 0x004
28#define TIOCM_ST 0x008
29#define TIOCM_SR 0x010
30#define TIOCM_CTS 0x020
31#define TIOCM_CAR 0x040
32#define TIOCM_RNG 0x080
33#define TIOCM_DSR 0x100
34#define TIOCM_CD TIOCM_CAR
35#define TIOCM_RI TIOCM_RNG
36#define TIOCM_OUT1 0x2000
37#define TIOCM_OUT2 0x4000
38#define TIOCM_LOOP 0x8000
39
40/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
41
42/* line disciplines */
43#define N_TTY 0
44#define N_SLIP 1
45#define N_MOUSE 2
46#define N_PPP 3
47#define N_STRIP 4
48#define N_AX25 5
49#define N_X25 6 /* X.25 async */
50#define N_6PACK 7
51#define N_MASC 8 /* Reserved for Mobitex module <kaz@cafe.net> */
52#define N_R3964 9 /* Reserved for Simatic R3964 module */
53#define N_PROFIBUS_FDL 10 /* Reserved for Profibus <Dave@mvhi.com> */
54#define N_IRDA 11 /* Linux IR - http://irda.sourceforge.net/ */
55#define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data cards about SMS messages */
56#define N_HDLC 13 /* synchronous HDLC */
57#define N_SYNC_PPP 14 /* synchronous PPP */
58#define N_HCI 15 /* Bluetooth HCI UART */
59
60#ifdef __KERNEL__
61
62/* intr=^C quit=^\ erase=del kill=^U
63 eof=^D vtime=\0 vmin=\1 sxtc=\0
64 start=^Q stop=^S susp=^Z eol=\0
65 reprint=^R discard=^U werase=^W lnext=^V
66 eol2=\0
67*/
68#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
69
70/*
71 * Translate a "termio" structure into a "termios". Ugh.
72 */
73#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
74 unsigned short __tmp; \
75 get_user(__tmp,&(termio)->x); \
76 *(unsigned short *) &(termios)->x = __tmp; \
77}
78
79#define user_termio_to_kernel_termios(termios, termio) \
80({ \
81 SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
82 SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
83 SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
84 SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
85 copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
86})
87
88/*
89 * Translate a "termios" structure into a "termio". Ugh.
90 */
91#define kernel_termios_to_user_termio(termio, termios) \
92({ \
93 put_user((termios)->c_iflag, &(termio)->c_iflag); \
94 put_user((termios)->c_oflag, &(termio)->c_oflag); \
95 put_user((termios)->c_cflag, &(termio)->c_cflag); \
96 put_user((termios)->c_lflag, &(termio)->c_lflag); \
97 put_user((termios)->c_line, &(termio)->c_line); \
98 copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
99})
100
101#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
102#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
103
104#endif /* __KERNEL__ */
105
106#endif /* __BFIN_TERMIOS_H__ */
diff --git a/include/asm-blackfin/thread_info.h b/include/asm-blackfin/thread_info.h
new file mode 100644
index 000000000000..fa8f08cf283e
--- /dev/null
+++ b/include/asm-blackfin/thread_info.h
@@ -0,0 +1,143 @@
1/*
2 * File: include/asm-blackfin/thread_info.h
3 * Based on: include/asm-m68knommu/thread_info.h
4 * Author: LG Soft India
5 * Copyright (C) 2004-2005 Analog Devices Inc.
6 * Created: Tue Sep 21 2004
7 * Description: Blackfin low-level thread information
8 * Modified:
9 * Bugs: Enter bugs at http://blackfin.uclinux.org/
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING.
23 * If not, write to the Free Software Foundation,
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 */
26
27#ifndef _ASM_THREAD_INFO_H
28#define _ASM_THREAD_INFO_H
29
30#include <asm/page.h>
31#include <asm/entry.h>
32#include <asm/l1layout.h>
33#include <linux/compiler.h>
34
35#ifdef __KERNEL__
36
37/* Thread Align Mask to reach to the top of the stack
38 * for any process
39 */
40#define ALIGN_PAGE_MASK 0xffffe000
41
42#ifndef __ASSEMBLY__
43
44typedef unsigned long mm_segment_t;
45
46/*
47 * low level task data.
48 * If you change this, change the TI_* offsets below to match.
49 */
50
51struct thread_info {
52 struct task_struct *task; /* main task structure */
53 struct exec_domain *exec_domain; /* execution domain */
54 unsigned long flags; /* low level flags */
55 int cpu; /* cpu we're on */
56 int preempt_count; /* 0 => preemptable, <0 => BUG */
57 mm_segment_t addr_limit; /* address limit */
58 struct restart_block restart_block;
59 struct l1_scratch_task_info l1_task_info;
60};
61
62/*
63 * macros/functions for gaining access to the thread information structure
64 */
65#define INIT_THREAD_INFO(tsk) \
66{ \
67 .task = &tsk, \
68 .exec_domain = &default_exec_domain, \
69 .flags = 0, \
70 .cpu = 0, \
71 .preempt_count = 1, \
72 .restart_block = { \
73 .fn = do_no_restart_syscall, \
74 }, \
75}
76#define init_thread_info (init_thread_union.thread_info)
77#define init_stack (init_thread_union.stack)
78
79/*
80 * Size of kernel stack for each process. This must be a power of 2...
81 */
82#define THREAD_SIZE 8192 /* 2 pages */
83
84/* How to get the thread information struct from C */
85
86static inline struct thread_info *current_thread_info(void)
87 __attribute__ ((__const__));
88
89/* Given a task stack pointer, you can find it's task structure
90 * just by masking it to the 8K boundary.
91 */
92static inline struct thread_info *current_thread_info(void)
93{
94 struct thread_info *ti;
95 __asm__("%0 = sp;": "=&d"(ti):
96 );
97 return (struct thread_info *)((long)ti & ~8191UL);
98}
99
100/* thread information allocation */
101#define alloc_thread_info(tsk) ((struct thread_info *) \
102 __get_free_pages(GFP_KERNEL, 1))
103#define free_thread_info(ti) free_pages((unsigned long) (ti), 1)
104#endif /* __ASSEMBLY__ */
105
106/*
107 * Offsets in thread_info structure, used in assembly code
108 */
109#define TI_TASK 0
110#define TI_EXECDOMAIN 4
111#define TI_FLAGS 8
112#define TI_CPU 12
113#define TI_PREEMPT 16
114
115#define PREEMPT_ACTIVE 0x4000000
116
117/*
118 * thread information flag bit numbers
119 */
120#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
121#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */
122#define TIF_SIGPENDING 2 /* signal pending */
123#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
124#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling
125 TIF_NEED_RESCHED */
126#define TIF_MEMDIE 5
127#define TIF_RESTORE_SIGMASK 6 /* restore signal mask in do_signal() */
128#define TIF_FREEZE 7 /* is freezing for suspend */
129
130/* as above, but as bit values */
131#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
132#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
133#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
134#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
135#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
136#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
137#define _TIF_FREEZE (1<<TIF_FREEZE)
138
139#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
140
141#endif /* __KERNEL__ */
142
143#endif /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-blackfin/timex.h b/include/asm-blackfin/timex.h
new file mode 100644
index 000000000000..828590117f51
--- /dev/null
+++ b/include/asm-blackfin/timex.h
@@ -0,0 +1,18 @@
1/* blackfin architecture timex specifications: Lineo Inc. 2001
2 *
3 * Based on: include/asm-m68knommu/timex.h
4 */
5
6#ifndef _ASMBLACKFIN_TIMEX_H
7#define _ASMBLACKFIN_TIMEX_H
8
9#define CLOCK_TICK_RATE 1000000 /* Underlying HZ */
10
11typedef unsigned long cycles_t;
12
13static inline cycles_t get_cycles(void)
14{
15 return 0;
16}
17
18#endif
diff --git a/include/asm-blackfin/tlb.h b/include/asm-blackfin/tlb.h
new file mode 100644
index 000000000000..89a12ee916d8
--- /dev/null
+++ b/include/asm-blackfin/tlb.h
@@ -0,0 +1,16 @@
1#ifndef _BLACKFIN_TLB_H
2#define _BLACKFIN_TLB_H
3
4#define tlb_start_vma(tlb, vma) do { } while (0)
5#define tlb_end_vma(tlb, vma) do { } while (0)
6#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
7
8/*
9 * .. because we flush the whole mm when it
10 * fills up.
11 */
12#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
13
14#include <asm-generic/tlb.h>
15
16#endif /* _BLACKFIN_TLB_H */
diff --git a/include/asm-blackfin/tlbflush.h b/include/asm-blackfin/tlbflush.h
new file mode 100644
index 000000000000..10a07ba1e011
--- /dev/null
+++ b/include/asm-blackfin/tlbflush.h
@@ -0,0 +1,62 @@
1#ifndef _BLACKFIN_TLBFLUSH_H
2#define _BLACKFIN_TLBFLUSH_H
3
4/*
5 * Copyright (C) 2000 Lineo, David McCullough <davidm@uclinux.org>
6 * Copyright (C) 2000-2002, Greg Ungerer <gerg@snapgear.com>
7 */
8
9#include <asm/setup.h>
10
11/*
12 * flush all user-space atc entries.
13 */
14static inline void __flush_tlb(void)
15{
16 BUG();
17}
18
19static inline void __flush_tlb_one(unsigned long addr)
20{
21 BUG();
22}
23
24#define flush_tlb() __flush_tlb()
25
26/*
27 * flush all atc entries (both kernel and user-space entries).
28 */
29static inline void flush_tlb_all(void)
30{
31 BUG();
32}
33
34static inline void flush_tlb_mm(struct mm_struct *mm)
35{
36 BUG();
37}
38
39static inline void flush_tlb_page(struct vm_area_struct *vma,
40 unsigned long addr)
41{
42 BUG();
43}
44
45static inline void flush_tlb_range(struct mm_struct *mm,
46 unsigned long start, unsigned long end)
47{
48 BUG();
49}
50
51static inline void flush_tlb_kernel_page(unsigned long addr)
52{
53 BUG();
54}
55
56static inline void flush_tlb_pgtables(struct mm_struct *mm,
57 unsigned long start, unsigned long end)
58{
59 BUG();
60}
61
62#endif
diff --git a/include/asm-blackfin/topology.h b/include/asm-blackfin/topology.h
new file mode 100644
index 000000000000..acee23987897
--- /dev/null
+++ b/include/asm-blackfin/topology.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_BLACKFIN_TOPOLOGY_H
2#define _ASM_BLACKFIN_TOPOLOGY_H
3
4#include <asm-generic/topology.h>
5
6#endif /* _ASM_BLACKFIN_TOPOLOGY_H */
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
new file mode 100644
index 000000000000..fe365b1b7ca8
--- /dev/null
+++ b/include/asm-blackfin/traps.h
@@ -0,0 +1,75 @@
1/*
2 * linux/include/asm/traps.h
3 *
4 * Copyright (C) 1993 Hamish Macdonald
5 *
6 * Lineo, Inc Jul 2001 Tony Kou
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
10 * for more details.
11 */
12
13#ifndef _BFIN_TRAPS_H
14#define _BFIN_TRAPS_H
15
16#define VEC_SYS (0)
17#define VEC_EXCPT01 (1)
18#define VEC_EXCPT02 (2)
19#define VEC_EXCPT03 (3)
20#define VEC_EXCPT04 (4)
21#define VEC_EXCPT05 (5)
22#define VEC_EXCPT06 (6)
23#define VEC_EXCPT07 (7)
24#define VEC_EXCPT08 (8)
25#define VEC_EXCPT09 (9)
26#define VEC_EXCPT10 (10)
27#define VEC_EXCPT11 (11)
28#define VEC_EXCPT12 (12)
29#define VEC_EXCPT13 (13)
30#define VEC_EXCPT14 (14)
31#define VEC_EXCPT15 (15)
32#define VEC_STEP (16)
33#define VEC_OVFLOW (17)
34#define VEC_UNDEF_I (33)
35#define VEC_ILGAL_I (34)
36#define VEC_CPLB_VL (35)
37#define VEC_MISALI_D (36)
38#define VEC_UNCOV (37)
39#define VEC_CPLB_M (38)
40#define VEC_CPLB_MHIT (39)
41#define VEC_WATCH (40)
42#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */
43#define VEC_MISALI_I (42)
44#define VEC_CPLB_I_VL (43)
45#define VEC_CPLB_I_M (44)
46#define VEC_CPLB_I_MHIT (45)
47#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
48
49#ifndef __ASSEMBLY__
50
51#define HWC_x2 "System MMR Error\nAn error occurred due to an invalid access to an System MMR location\nPossible reason: a 32-bit register is accessed with a 16-bit instruction,\nor a 16-bit register is accessed with a 32-bit instruction.\n"
52#define HWC_x3 "External Memory Addressing Error\n"
53#define HWC_x12 "Performance Monitor Overflow\n"
54#define HWC_x18 "RAISE 5 instruction\n Software issued a RAISE 5 instruction to invoke the Hardware\n"
55#define HWC_default "Reserved\n"
56
57#define EXC_0x03 "Application stack overflow\n - Please increase the stack size of the application using elf2flt -s option,\n and/or reduce the stack use of the application.\n"
58#define EXC_0x10 "Single step\n - When the processor is in single step mode, every instruction\n generates an exception. Primarily used for debugging.\n"
59#define EXC_0x11 "Exception caused by a trace buffer full condition\n - The processor takes this exception when the trace\n buffer overflows (only when enabled by the Trace Unit Control register).\n"
60#define EXC_0x21 "Undefined instruction\n - May be used to emulate instructions that are not defined for\n a particular processor implementation.\n"
61#define EXC_0x22 "Illegal instruction combination\n - See section for multi-issue rules in the ADSP-BF53x Blackfin\n Processor Instruction Set Reference.\n"
62#define EXC_0x23 "Data access CPLB protection violation\n - Attempted read or write to Supervisor resource,\n or illegal data memory access. \n"
63#define EXC_0x24 "Data access misaligned address violation\n - Attempted misaligned data memory or data cache access.\n"
64#define EXC_0x25 "Unrecoverable event\n - For example, an exception generated while processing a previous exception.\n"
65#define EXC_0x26 "Data access CPLB miss\n - Used by the MMU to signal a CPLB miss on a data access.\n"
66#define EXC_0x27 "Data access multiple CPLB hits\n - More than one CPLB entry matches data fetch address.\n"
67#define EXC_0x28 "Program Sequencer Exception caused by an emulation watchpoint match\n - There is a watchpoint match, and one of the EMUSW\n bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
68#define EXC_0x2A "Instruction fetch misaligned address violation\n - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch exception,\n the return address provided in RETX is the destination address which is misaligned, rather than the address of the offending instruction.\n"
69#define EXC_0x2B "CPLB protection violation\n - Illegal instruction fetch access (memory protection violation).\n"
70#define EXC_0x2C "Instruction fetch CPLB miss\n - CPLB miss on an instruction fetch.\n"
71#define EXC_0x2D "Instruction fetch multiple CPLB hits\n - More than one CPLB entry matches instruction fetch address.\n"
72#define EXC_0x2E "Illegal use of supervisor resource\n - Attempted to use a Supervisor register or instruction from User mode.\n Supervisor resources are registers and instructions that are reserved\n for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n only instructions.\n"
73
74#endif /* __ASSEMBLY__ */
75#endif /* _BFIN_TRAPS_H */
diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h
new file mode 100644
index 000000000000..36f8dc8c52ba
--- /dev/null
+++ b/include/asm-blackfin/types.h
@@ -0,0 +1,66 @@
1#ifndef _BFIN_TYPES_H
2#define _BFIN_TYPES_H
3
4/*
5 * This file is never included by application software unless
6 * explicitly requested (e.g., via linux/types.h) in which case the
7 * application is Linux specific so (user-) name space pollution is
8 * not a major issue. However, for interoperability, libraries still
9 * need to be careful to avoid a name clashes.
10 */
11#ifndef __ASSEMBLY__
12
13typedef unsigned short umode_t;
14
15/*
16 * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
17 * header files exported to user space
18 */
19
20typedef __signed__ char __s8;
21typedef unsigned char __u8;
22
23typedef __signed__ short __s16;
24typedef unsigned short __u16;
25
26typedef __signed__ int __s32;
27typedef unsigned int __u32;
28
29/* HK0617 -- Changes to unsigned long temporarily */
30#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
31typedef __signed__ long long __s64;
32typedef unsigned long long __u64;
33#endif
34
35#endif /* __ASSEMBLY__ */
36/*
37 * These aren't exported outside the kernel to avoid name space clashes
38 */
39#ifdef __KERNEL__
40
41#define BITS_PER_LONG 32
42
43#ifndef __ASSEMBLY__
44
45typedef signed char s8;
46typedef unsigned char u8;
47
48typedef signed short s16;
49typedef unsigned short u16;
50
51typedef signed int s32;
52typedef unsigned int u32;
53
54typedef signed long long s64;
55typedef unsigned long long u64;
56
57/* Dma addresses are 32-bits wide. */
58
59typedef u32 dma_addr_t;
60typedef u64 dma64_addr_t;
61
62#endif /* __ASSEMBLY__ */
63
64#endif /* __KERNEL__ */
65
66#endif /* _BFIN_TYPES_H */
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
new file mode 100644
index 000000000000..bfcb6794c672
--- /dev/null
+++ b/include/asm-blackfin/uaccess.h
@@ -0,0 +1,271 @@
1/* Changes made by Lineo Inc. May 2001
2 *
3 * Based on: include/asm-m68knommu/uaccess.h
4 */
5
6#ifndef __BLACKFIN_UACCESS_H
7#define __BLACKFIN_UACCESS_H
8
9/*
10 * User space memory access functions
11 */
12#include <linux/sched.h>
13#include <linux/mm.h>
14#include <linux/string.h>
15
16#include <asm/segment.h>
17#ifndef CONFIG_NO_ACCESS_CHECK
18# include <asm/bfin-global.h>
19#endif
20
21#define get_ds() (KERNEL_DS)
22#define get_fs() (current_thread_info()->addr_limit)
23
24static inline void set_fs(mm_segment_t fs)
25{
26 current_thread_info()->addr_limit = fs;
27}
28
29#define segment_eq(a,b) ((a) == (b))
30
31#define VERIFY_READ 0
32#define VERIFY_WRITE 1
33
34#define access_ok(type,addr,size) _access_ok((unsigned long)(addr),(size))
35
36static inline int is_in_rom(unsigned long addr)
37{
38 /*
39 * What we are really trying to do is determine if addr is
40 * in an allocated kernel memory region. If not then assume
41 * we cannot free it or otherwise de-allocate it. Ideally
42 * we could restrict this to really being in a ROM or flash,
43 * but that would need to be done on a board by board basis,
44 * not globally.
45 */
46 if ((addr < _ramstart) || (addr >= _ramend))
47 return (1);
48
49 /* Default case, not in ROM */
50 return (0);
51}
52
53/*
54 * The fs value determines whether argument validity checking should be
55 * performed or not. If get_fs() == USER_DS, checking is performed, with
56 * get_fs() == KERNEL_DS, checking is bypassed.
57 */
58
59#ifdef CONFIG_NO_ACCESS_CHECK
60static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; }
61#else
62#ifdef CONFIG_ACCESS_OK_L1
63extern int _access_ok(unsigned long addr, unsigned long size)__attribute__((l1_text));
64#else
65extern int _access_ok(unsigned long addr, unsigned long size);
66#endif
67#endif
68
69/*
70 * The exception table consists of pairs of addresses: the first is the
71 * address of an instruction that is allowed to fault, and the second is
72 * the address at which the program should continue. No registers are
73 * modified, so it is entirely up to the continuation code to figure out
74 * what to do.
75 *
76 * All the routines below use bits of fixup code that are out of line
77 * with the main instruction path. This means when everything is well,
78 * we don't even have to jump over them. Further, they do not intrude
79 * on our cache or tlb entries.
80 */
81
82struct exception_table_entry {
83 unsigned long insn, fixup;
84};
85
86/* Returns 0 if exception not found and fixup otherwise. */
87extern unsigned long search_exception_table(unsigned long);
88
89/*
90 * These are the main single-value transfer routines. They automatically
91 * use the right size if we just have the right pointer type.
92 */
93
94#define put_user(x,p) \
95 ({ \
96 int _err = 0; \
97 typeof(*(p)) _x = (x); \
98 typeof(*(p)) *_p = (p); \
99 if (!access_ok(VERIFY_WRITE, _p, sizeof(*(_p)))) {\
100 _err = -EFAULT; \
101 } \
102 else { \
103 switch (sizeof (*(_p))) { \
104 case 1: \
105 __put_user_asm(_x, _p, B); \
106 break; \
107 case 2: \
108 __put_user_asm(_x, _p, W); \
109 break; \
110 case 4: \
111 __put_user_asm(_x, _p, ); \
112 break; \
113 case 8: { \
114 long _xl, _xh; \
115 _xl = ((long *)&_x)[0]; \
116 _xh = ((long *)&_x)[1]; \
117 __put_user_asm(_xl, ((long *)_p)+0, ); \
118 __put_user_asm(_xh, ((long *)_p)+1, ); \
119 } break; \
120 default: \
121 _err = __put_user_bad(); \
122 break; \
123 } \
124 } \
125 _err; \
126 })
127
128#define __put_user(x,p) put_user(x,p)
129static inline int bad_user_access_length(void)
130{
131 panic("bad_user_access_length");
132 return -1;
133}
134
135#define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\
136 __FILE__, __LINE__, __FUNCTION__),\
137 bad_user_access_length(), (-EFAULT))
138
139/*
140 * Tell gcc we read from memory instead of writing: this is because
141 * we do not write to any memory gcc knows about, so there are no
142 * aliasing issues.
143 */
144
145#define __ptr(x) ((unsigned long *)(x))
146
147#define __put_user_asm(x,p,bhw) \
148 __asm__ (#bhw"[%1] = %0;\n\t" \
149 : /* no outputs */ \
150 :"d" (x),"a" (__ptr(p)) : "memory")
151
152#define get_user(x,p) \
153 ({ \
154 int _err = 0; \
155 typeof(*(p)) *_p = (p); \
156 if (!access_ok(VERIFY_READ, _p, sizeof(*(_p)))) { \
157 _err = -EFAULT; \
158 } \
159 else { \
160 switch (sizeof(*(_p))) { \
161 case 1: \
162 __get_user_asm(x, _p, B,(Z)); \
163 break; \
164 case 2: \
165 __get_user_asm(x, _p, W,(Z)); \
166 break; \
167 case 4: \
168 __get_user_asm(x, _p, , ); \
169 break; \
170 case 8: { \
171 unsigned long _xl, _xh; \
172 __get_user_asm(_xl, ((unsigned long *)_p)+0, , ); \
173 __get_user_asm(_xh, ((unsigned long *)_p)+1, , ); \
174 ((unsigned long *)&x)[0] = _xl; \
175 ((unsigned long *)&x)[1] = _xh; \
176 } break; \
177 default: \
178 x = 0; \
179 printk(KERN_INFO "get_user_bad: %s:%d %s\n", \
180 __FILE__, __LINE__, __FUNCTION__); \
181 _err = __get_user_bad(); \
182 break; \
183 } \
184 } \
185 _err; \
186 })
187
188#define __get_user(x,p) get_user(x,p)
189
190#define __get_user_bad() (bad_user_access_length(), (-EFAULT))
191
192#define __get_user_asm(x,p,bhw,option) \
193 { \
194 unsigned long _tmp; \
195 __asm__ ("%0 =" #bhw "[%1]"#option";\n\t" \
196 : "=d" (_tmp) \
197 : "a" (__ptr(p))); \
198 (x) = (__typeof__(*(p))) _tmp; \
199 }
200
201#define __copy_from_user(to, from, n) copy_from_user(to, from, n)
202#define __copy_to_user(to, from, n) copy_to_user(to, from, n)
203#define __copy_to_user_inatomic __copy_to_user
204#define __copy_from_user_inatomic __copy_from_user
205
206#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n))\
207 return retval; })
208
209#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n))\
210 return retval; })
211
212static inline long copy_from_user(void *to,
213 const void __user * from, unsigned long n)
214{
215 if (access_ok(VERIFY_READ, from, n))
216 memcpy(to, from, n);
217 else
218 return n;
219 return 0;
220}
221
222static inline long copy_to_user(void *to,
223 const void __user * from, unsigned long n)
224{
225 if (access_ok(VERIFY_WRITE, to, n))
226 memcpy(to, from, n);
227 else
228 return n;
229 return 0;
230}
231
232/*
233 * Copy a null terminated string from userspace.
234 */
235
236static inline long strncpy_from_user(char *dst,
237 const char *src, long count)
238{
239 char *tmp;
240 if (!access_ok(VERIFY_READ, src, 1))
241 return -EFAULT;
242 strncpy(dst, src, count);
243 for (tmp = dst; *tmp && count > 0; tmp++, count--) ;
244 return (tmp - dst);
245}
246
247/*
248 * Return the size of a string (including the ending 0)
249 *
250 * Return 0 on exception, a value greater than N if too long
251 */
252static inline long strnlen_user(const char *src, long n)
253{
254 return (strlen(src) + 1);
255}
256
257#define strlen_user(str) strnlen_user(str, 32767)
258
259/*
260 * Zero Userspace
261 */
262
263static inline unsigned long __clear_user(void *to, unsigned long n)
264{
265 memset(to, 0, n);
266 return 0;
267}
268
269#define clear_user(to, n) __clear_user(to, n)
270
271#endif /* _BLACKFIN_UACCESS_H */
diff --git a/include/asm-blackfin/ucontext.h b/include/asm-blackfin/ucontext.h
new file mode 100644
index 000000000000..4a4e3856beba
--- /dev/null
+++ b/include/asm-blackfin/ucontext.h
@@ -0,0 +1,17 @@
1/** Changes made by Tony Kou Lineo Inc. May 2001
2 *
3 * Based on: include/m68knommu/ucontext.h
4 */
5
6#ifndef _BLACKFIN_UCONTEXT_H
7#define _BLACKFIN_UCONTEXT_H
8
9struct ucontext {
10 unsigned long uc_flags; /* the others are necessary */
11 struct ucontext *uc_link;
12 stack_t uc_stack;
13 struct sigcontext uc_mcontext;
14 sigset_t uc_sigmask; /* mask last for extensibility */
15};
16
17#endif /* _BLACKFIN_UCONTEXT_H */
diff --git a/include/asm-blackfin/unaligned.h b/include/asm-blackfin/unaligned.h
new file mode 100644
index 000000000000..10081dc241ef
--- /dev/null
+++ b/include/asm-blackfin/unaligned.h
@@ -0,0 +1,6 @@
1#ifndef __BFIN_UNALIGNED_H
2#define __BFIN_UNALIGNED_H
3
4#include <asm-generic/unaligned.h>
5
6#endif /* __BFIN_UNALIGNED_H */
diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h
new file mode 100644
index 000000000000..4df8790a67d5
--- /dev/null
+++ b/include/asm-blackfin/unistd.h
@@ -0,0 +1,382 @@
1#ifndef __ASM_BFIN_UNISTD_H
2#define __ASM_BFIN_UNISTD_H
3/*
4 * This file contains the system call numbers.
5 */
6#define __NR_exit 1
7#define __NR_fork 2
8#define __NR_read 3
9#define __NR_write 4
10#define __NR_open 5
11#define __NR_close 6
12 /* 7 __NR_waitpid obsolete */
13#define __NR_creat 8
14#define __NR_link 9
15#define __NR_unlink 10
16#define __NR_execve 11
17#define __NR_chdir 12
18#define __NR_time 13
19#define __NR_mknod 14
20#define __NR_chmod 15
21#define __NR_chown 16
22 /* 17 __NR_break obsolete */
23 /* 18 __NR_oldstat obsolete */
24#define __NR_lseek 19
25#define __NR_getpid 20
26#define __NR_mount 21
27 /* 22 __NR_umount obsolete */
28#define __NR_setuid 23
29#define __NR_getuid 24
30#define __NR_stime 25
31#define __NR_ptrace 26
32#define __NR_alarm 27
33 /* 28 __NR_oldfstat obsolete */
34#define __NR_pause 29
35 /* 30 __NR_utime obsolete */
36 /* 31 __NR_stty obsolete */
37 /* 32 __NR_gtty obsolete */
38#define __NR_access 33
39#define __NR_nice 34
40 /* 35 __NR_ftime obsolete */
41#define __NR_sync 36
42#define __NR_kill 37
43#define __NR_rename 38
44#define __NR_mkdir 39
45#define __NR_rmdir 40
46#define __NR_dup 41
47#define __NR_pipe 42
48#define __NR_times 43
49 /* 44 __NR_prof obsolete */
50#define __NR_brk 45
51#define __NR_setgid 46
52#define __NR_getgid 47
53 /* 48 __NR_signal obsolete */
54#define __NR_geteuid 49
55#define __NR_getegid 50
56#define __NR_acct 51
57#define __NR_umount2 52
58 /* 53 __NR_lock obsolete */
59#define __NR_ioctl 54
60#define __NR_fcntl 55
61 /* 56 __NR_mpx obsolete */
62#define __NR_setpgid 57
63 /* 58 __NR_ulimit obsolete */
64 /* 59 __NR_oldolduname obsolete */
65#define __NR_umask 60
66#define __NR_chroot 61
67#define __NR_ustat 62
68#define __NR_dup2 63
69#define __NR_getppid 64
70#define __NR_getpgrp 65
71#define __NR_setsid 66
72 /* 67 __NR_sigaction obsolete */
73#define __NR_sgetmask 68
74#define __NR_ssetmask 69
75#define __NR_setreuid 70
76#define __NR_setregid 71
77 /* 72 __NR_sigsuspend obsolete */
78 /* 73 __NR_sigpending obsolete */
79#define __NR_sethostname 74
80#define __NR_setrlimit 75
81 /* 76 __NR_old_getrlimit obsolete */
82#define __NR_getrusage 77
83#define __NR_gettimeofday 78
84#define __NR_settimeofday 79
85#define __NR_getgroups 80
86#define __NR_setgroups 81
87 /* 82 __NR_select obsolete */
88#define __NR_symlink 83
89 /* 84 __NR_oldlstat obsolete */
90#define __NR_readlink 85
91 /* 86 __NR_uselib obsolete */
92 /* 87 __NR_swapon obsolete */
93#define __NR_reboot 88
94 /* 89 __NR_readdir obsolete */
95 /* 90 __NR_mmap obsolete */
96#define __NR_munmap 91
97#define __NR_truncate 92
98#define __NR_ftruncate 93
99#define __NR_fchmod 94
100#define __NR_fchown 95
101#define __NR_getpriority 96
102#define __NR_setpriority 97
103 /* 98 __NR_profil obsolete */
104#define __NR_statfs 99
105#define __NR_fstatfs 100
106 /* 101 __NR_ioperm */
107 /* 102 __NR_socketcall obsolete */
108#define __NR_syslog 103
109#define __NR_setitimer 104
110#define __NR_getitimer 105
111#define __NR_stat 106
112#define __NR_lstat 107
113#define __NR_fstat 108
114 /* 109 __NR_olduname obsolete */
115 /* 110 __NR_iopl obsolete */
116#define __NR_vhangup 111
117 /* 112 __NR_idle obsolete */
118 /* 113 __NR_vm86old */
119#define __NR_wait4 114
120 /* 115 __NR_swapoff obsolete */
121#define __NR_sysinfo 116
122 /* 117 __NR_ipc oboslete */
123#define __NR_fsync 118
124 /* 119 __NR_sigreturn obsolete */
125#define __NR_clone 120
126#define __NR_setdomainname 121
127#define __NR_uname 122
128 /* 123 __NR_modify_ldt obsolete */
129#define __NR_adjtimex 124
130#define __NR_mprotect 125
131 /* 126 __NR_sigprocmask obsolete */
132 /* 127 __NR_create_module obsolete */
133#define __NR_init_module 128
134#define __NR_delete_module 129
135 /* 130 __NR_get_kernel_syms obsolete */
136#define __NR_quotactl 131
137#define __NR_getpgid 132
138#define __NR_fchdir 133
139#define __NR_bdflush 134
140 /* 135 was sysfs */
141#define __NR_personality 136
142 /* 137 __NR_afs_syscall */
143#define __NR_setfsuid 138
144#define __NR_setfsgid 139
145#define __NR__llseek 140
146#define __NR_getdents 141
147 /* 142 __NR__newselect obsolete */
148#define __NR_flock 143
149 /* 144 __NR_msync obsolete */
150#define __NR_readv 145
151#define __NR_writev 146
152#define __NR_getsid 147
153#define __NR_fdatasync 148
154#define __NR__sysctl 149
155 /* 150 __NR_mlock */
156 /* 151 __NR_munlock */
157 /* 152 __NR_mlockall */
158 /* 153 __NR_munlockall */
159#define __NR_sched_setparam 154
160#define __NR_sched_getparam 155
161#define __NR_sched_setscheduler 156
162#define __NR_sched_getscheduler 157
163#define __NR_sched_yield 158
164#define __NR_sched_get_priority_max 159
165#define __NR_sched_get_priority_min 160
166#define __NR_sched_rr_get_interval 161
167#define __NR_nanosleep 162
168 /* 163 __NR_mremap */
169#define __NR_setresuid 164
170#define __NR_getresuid 165
171 /* 166 __NR_vm86 */
172 /* 167 __NR_query_module */
173 /* 168 __NR_poll */
174 /* 169 __NR_nfsservctl */
175#define __NR_setresgid 170
176#define __NR_getresgid 171
177#define __NR_prctl 172
178#define __NR_rt_sigreturn 173
179#define __NR_rt_sigaction 174
180#define __NR_rt_sigprocmask 175
181#define __NR_rt_sigpending 176
182#define __NR_rt_sigtimedwait 177
183#define __NR_rt_sigqueueinfo 178
184#define __NR_rt_sigsuspend 179
185#define __NR_pread 180
186#define __NR_pwrite 181
187#define __NR_lchown 182
188#define __NR_getcwd 183
189#define __NR_capget 184
190#define __NR_capset 185
191#define __NR_sigaltstack 186
192#define __NR_sendfile 187
193 /* 188 __NR_getpmsg */
194 /* 189 __NR_putpmsg */
195#define __NR_vfork 190
196#define __NR_getrlimit 191
197#define __NR_mmap2 192
198#define __NR_truncate64 193
199#define __NR_ftruncate64 194
200#define __NR_stat64 195
201#define __NR_lstat64 196
202#define __NR_fstat64 197
203#define __NR_chown32 198
204#define __NR_getuid32 199
205#define __NR_getgid32 200
206#define __NR_geteuid32 201
207#define __NR_getegid32 202
208#define __NR_setreuid32 203
209#define __NR_setregid32 204
210#define __NR_getgroups32 205
211#define __NR_setgroups32 206
212#define __NR_fchown32 207
213#define __NR_setresuid32 208
214#define __NR_getresuid32 209
215#define __NR_setresgid32 210
216#define __NR_getresgid32 211
217#define __NR_lchown32 212
218#define __NR_setuid32 213
219#define __NR_setgid32 214
220#define __NR_setfsuid32 215
221#define __NR_setfsgid32 216
222#define __NR_pivot_root 217
223 /* 218 __NR_mincore */
224 /* 219 __NR_madvise */
225#define __NR_getdents64 220
226#define __NR_fcntl64 221
227 /* 222 reserved for TUX */
228 /* 223 reserved for TUX */
229#define __NR_gettid 224
230 /* 225 __NR_readahead */
231#define __NR_setxattr 226
232#define __NR_lsetxattr 227
233#define __NR_fsetxattr 228
234#define __NR_getxattr 229
235#define __NR_lgetxattr 230
236#define __NR_fgetxattr 231
237#define __NR_listxattr 232
238#define __NR_llistxattr 233
239#define __NR_flistxattr 234
240#define __NR_removexattr 235
241#define __NR_lremovexattr 236
242#define __NR_fremovexattr 237
243#define __NR_tkill 238
244#define __NR_sendfile64 239
245#define __NR_futex 240
246#define __NR_sched_setaffinity 241
247#define __NR_sched_getaffinity 242
248 /* 243 __NR_set_thread_area */
249 /* 244 __NR_get_thread_area */
250#define __NR_io_setup 245
251#define __NR_io_destroy 246
252#define __NR_io_getevents 247
253#define __NR_io_submit 248
254#define __NR_io_cancel 249
255 /* 250 __NR_alloc_hugepages */
256 /* 251 __NR_free_hugepages */
257#define __NR_exit_group 252
258#define __NR_lookup_dcookie 253
259#define __NR_bfin_spinlock 254
260
261#define __NR_epoll_create 255
262#define __NR_epoll_ctl 256
263#define __NR_epoll_wait 257
264 /* 258 __NR_remap_file_pages */
265#define __NR_set_tid_address 259
266#define __NR_timer_create 260
267#define __NR_timer_settime (__NR_timer_create+1)
268#define __NR_timer_gettime (__NR_timer_create+2)
269#define __NR_timer_getoverrun (__NR_timer_create+3)
270#define __NR_timer_delete (__NR_timer_create+4)
271#define __NR_clock_settime (__NR_timer_create+5)
272#define __NR_clock_gettime (__NR_timer_create+6)
273#define __NR_clock_getres (__NR_timer_create+7)
274#define __NR_clock_nanosleep (__NR_timer_create+8)
275#define __NR_statfs64 269
276#define __NR_fstatfs64 270
277#define __NR_tgkill 271
278#define __NR_utimes 272
279#define __NR_fadvise64_64 273
280 /* 274 __NR_vserver */
281 /* 275 __NR_mbind */
282 /* 276 __NR_get_mempolicy */
283 /* 277 __NR_set_mempolicy */
284#define __NR_mq_open 278
285#define __NR_mq_unlink (__NR_mq_open+1)
286#define __NR_mq_timedsend (__NR_mq_open+2)
287#define __NR_mq_timedreceive (__NR_mq_open+3)
288#define __NR_mq_notify (__NR_mq_open+4)
289#define __NR_mq_getsetattr (__NR_mq_open+5)
290 /* 284 __NR_sys_kexec_load */
291#define __NR_waitid 285
292#define __NR_add_key 286
293#define __NR_request_key 287
294#define __NR_keyctl 288
295#define __NR_ioprio_set 289
296#define __NR_ioprio_get 290
297#define __NR_inotify_init 291
298#define __NR_inotify_add_watch 292
299#define __NR_inotify_rm_watch 293
300 /* 294 __NR_migrate_pages */
301#define __NR_openat 295
302#define __NR_mkdirat 296
303#define __NR_mknodat 297
304#define __NR_fchownat 298
305#define __NR_futimesat 299
306#define __NR_fstatat64 300
307#define __NR_unlinkat 301
308#define __NR_renameat 302
309#define __NR_linkat 303
310#define __NR_symlinkat 304
311#define __NR_readlinkat 305
312#define __NR_fchmodat 306
313#define __NR_faccessat 307
314#define __NR_pselect6 308
315#define __NR_ppoll 309
316#define __NR_unshare 310
317
318/* Blackfin private syscalls */
319#define __NR_sram_alloc 311
320#define __NR_sram_free 312
321#define __NR_dma_memcpy 313
322
323/* socket syscalls */
324#define __NR_accept 314
325#define __NR_bind 315
326#define __NR_connect 316
327#define __NR_getpeername 317
328#define __NR_getsockname 318
329#define __NR_getsockopt 319
330#define __NR_listen 320
331#define __NR_recv 321
332#define __NR_recvfrom 322
333#define __NR_recvmsg 323
334#define __NR_send 324
335#define __NR_sendmsg 325
336#define __NR_sendto 326
337#define __NR_setsockopt 327
338#define __NR_shutdown 328
339#define __NR_socket 329
340#define __NR_socketpair 330
341
342/* sysv ipc syscalls */
343#define __NR_semctl 331
344#define __NR_semget 332
345#define __NR_semop 333
346#define __NR_msgctl 334
347#define __NR_msgget 335
348#define __NR_msgrcv 336
349#define __NR_msgsnd 337
350#define __NR_shmat 338
351#define __NR_shmctl 339
352#define __NR_shmdt 340
353#define __NR_shmget 341
354
355#define __NR_syscall 342
356#define NR_syscalls __NR_syscall
357
358#ifdef __KERNEL__
359#define __ARCH_WANT_IPC_PARSE_VERSION
360#define __ARCH_WANT_STAT64
361#define __ARCH_WANT_SYS_ALARM
362#define __ARCH_WANT_SYS_GETHOSTNAME
363#define __ARCH_WANT_SYS_PAUSE
364#define __ARCH_WANT_SYS_SGETMASK
365#define __ARCH_WANT_SYS_TIME
366#define __ARCH_WANT_SYS_FADVISE64
367#define __ARCH_WANT_SYS_GETPGRP
368#define __ARCH_WANT_SYS_LLSEEK
369#define __ARCH_WANT_SYS_NICE
370#define __ARCH_WANT_SYS_RT_SIGACTION
371#define __ARCH_WANT_SYS_RT_SIGSUSPEND
372#endif
373
374/*
375 * "Conditional" syscalls
376 *
377 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
378 * but it doesn't work on all toolchains, so we just do it by hand
379 */
380#define cond_syscall(x) asm(".weak\t_" #x "\n\t.set\t_" #x ",_sys_ni_syscall");
381
382#endif /* __ASM_BFIN_UNISTD_H */
diff --git a/include/asm-blackfin/user.h b/include/asm-blackfin/user.h
new file mode 100644
index 000000000000..abc34629bd59
--- /dev/null
+++ b/include/asm-blackfin/user.h
@@ -0,0 +1,89 @@
1#ifndef _BFIN_USER_H
2#define _BFIN_USER_H
3
4/* Changes by Tony Kou Lineo, Inc. July, 2001
5 *
6 * Based include/asm-m68knommu/user.h
7 *
8 */
9
10/* Core file format: The core file is written in such a way that gdb
11 can understand it and provide useful information to the user (under
12 linux we use the 'trad-core' bfd). There are quite a number of
13 obstacles to being able to view the contents of the floating point
14 registers, and until these are solved you will not be able to view the
15 contents of them. Actually, you can read in the core file and look at
16 the contents of the user struct to find out what the floating point
17 registers contain.
18 The actual file contents are as follows:
19 UPAGE: 1 page consisting of a user struct that tells gdb what is present
20 in the file. Directly after this is a copy of the task_struct, which
21 is currently not used by gdb, but it may come in useful at some point.
22 All of the registers are stored as part of the upage. The upage should
23 always be only one page.
24 DATA: The data area is stored. We use current->end_text to
25 current->brk to pick up all of the user variables, plus any memory
26 that may have been malloced. No attempt is made to determine if a page
27 is demand-zero or if a page is totally unused, we just cover the entire
28 range. All of the addresses are rounded in such a way that an integral
29 number of pages is written.
30 STACK: We need the stack information in order to get a meaningful
31 backtrace. We need to write the data from (esp) to
32 current->start_stack, so we round each of these off in order to be able
33 to write an integer number of pages.
34 The minimum core file size is 3 pages, or 12288 bytes.
35*/
36struct user_bfinfp_struct {
37};
38
39/* This is the old layout of "struct pt_regs" as of Linux 1.x, and
40 is still the layout used by user (the new pt_regs doesn't have
41 all registers). */
42struct user_regs_struct {
43 long r0, r1, r2, r3, r4, r5, r6, r7;
44 long p0, p1, p2, p3, p4, p5, usp, fp;
45 long i0, i1, i2, i3;
46 long l0, l1, l2, l3;
47 long b0, b1, b2, b3;
48 long m0, m1, m2, m3;
49 long a0w, a1w;
50 long a0x, a1x;
51 unsigned long rets;
52 unsigned long astat;
53 unsigned long pc;
54 unsigned long orig_p0;
55};
56
57/* When the kernel dumps core, it starts by dumping the user struct -
58 this will be used by gdb to figure out where the data and stack segments
59 are within the file, and what virtual addresses to use. */
60
61struct user {
62/* We start with the registers, to mimic the way that "memory" is returned
63 from the ptrace(3,...) function. */
64
65 struct user_regs_struct regs; /* Where the registers are actually stored */
66
67/* The rest of this junk is to help gdb figure out what goes where */
68 unsigned long int u_tsize; /* Text segment size (pages). */
69 unsigned long int u_dsize; /* Data segment size (pages). */
70 unsigned long int u_ssize; /* Stack segment size (pages). */
71 unsigned long start_code; /* Starting virtual address of text. */
72 unsigned long start_stack; /* Starting virtual address of stack area.
73 This is actually the bottom of the stack,
74 the top of the stack is always found in the
75 esp register. */
76 long int signal; /* Signal that caused the core dump. */
77 int reserved; /* No longer used */
78 struct user_regs_struct *u_ar0;
79 /* Used by gdb to help find the values for */
80 /* the registers. */
81 unsigned long magic; /* To uniquely identify a core file */
82 char u_comm[32]; /* User command that was responsible */
83};
84#define NBPG PAGE_SIZE
85#define UPAGES 1
86#define HOST_TEXT_START_ADDR (u.start_code)
87#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
88
89#endif