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-rw-r--r--include/asm-blackfin/mach-bf548/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf548/mem_init.h1
2 files changed, 3 insertions, 2 deletions
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
index 9fb7bc5399a8..c34507a3f1df 100644
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -88,7 +88,7 @@ Events (highest priority) EMU 0
88#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ 88#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
89#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ 89#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
90#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ 90#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
91#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ 91#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
92#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ 92#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
93#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ 93#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
94#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ 94#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
@@ -406,7 +406,7 @@ Events (highest priority) EMU 0
406#define IRQ_PINT1_POS 16 406#define IRQ_PINT1_POS 16
407#define IRQ_MDMAS0_POS 20 407#define IRQ_MDMAS0_POS 20
408#define IRQ_MDMAS1_POS 24 408#define IRQ_MDMAS1_POS 24
409#define IRQ_WATCHDOG_POS 28 409#define IRQ_WATCH_POS 28
410 410
411/* IAR3 BIT FIELDS */ 411/* IAR3 BIT FIELDS */
412#define IRQ_DMAC1_ERR_POS 0 412#define IRQ_DMAC1_ERR_POS 0
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
index 0cb279e973d7..e792eb7ae6a0 100644
--- a/include/asm-blackfin/mach-bf548/mem_init.h
+++ b/include/asm-blackfin/mach-bf548/mem_init.h
@@ -30,6 +30,7 @@
30 */ 30 */
31 31
32#if (CONFIG_MEM_MT46V32M16) 32#if (CONFIG_MEM_MT46V32M16)
33#endif
33 34
34#if defined CONFIG_CLKIN_HALF 35#if defined CONFIG_CLKIN_HALF
35#define CLKIN_HALF 1 36#define CLKIN_HALF 1