20 files changed, 165 insertions, 205 deletions

diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
index 76033831eb35..320aa5e167e9 100644
--- a/include/asm-blackfin/bfin-global.h
+++ b/include/asm-blackfin/bfin-global.h
@@ -92,16 +92,20 @@ extern void *l1_data_B_sram_alloc(size_t);
 extern void *l1_inst_sram_alloc(size_t);
 extern void *l1_data_sram_alloc(size_t);
 extern void *l1_data_sram_zalloc(size_t);
+extern void *l2_sram_alloc(size_t);
+extern void *l2_sram_zalloc(size_t);
 extern int l1_data_A_sram_free(const void*);
 extern int l1_data_B_sram_free(const void*);
 extern int l1_inst_sram_free(const void*);
 extern int l1_data_sram_free(const void*);
+extern int l2_sram_free(const void *);
 extern int sram_free(const void*);
 
 #define L1_INST_SRAM            0x00000001
 #define L1_DATA_A_SRAM          0x00000002
 #define L1_DATA_B_SRAM          0x00000004
 #define L1_DATA_SRAM            0x00000006
+#define L2_SRAM                 0x00000008
 extern void *sram_alloc_with_lsl(size_t, unsigned long);
 extern int sram_free_with_lsl(const void*);
 
@@ -114,7 +118,9 @@ extern struct file_operations dpmc_fops;
 extern unsigned long _ramstart, _ramend, _rambase;
 extern unsigned long memory_start, memory_end, physical_mem_end;
 extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
-    _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _ebss_b_l1[];
+        _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _ebss_b_l1[],
+        _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[],
+        _ebss_l2[], _l2_lma_start[];
 
 #ifdef CONFIG_MTD_UCLINUX
 extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h
index c0d5259e315b..3cd4b522aa3f 100644
--- a/include/asm-blackfin/dma.h
+++ b/include/asm-blackfin/dma.h
@@ -144,8 +144,16 @@ struct dma_channel {
         void *data;
         unsigned int dma_enable_flag;
         unsigned int loopback_flag;
+#ifdef CONFIG_PM
+        unsigned short saved_peripheral_map;
+#endif
 };
 
+#ifdef CONFIG_PM
+int blackfin_dma_suspend(void);
+void blackfin_dma_resume(void);
+#endif
+
 /*******************************************************************************
 *       DMA API's
 *******************************************************************************/
diff --git a/include/asm-blackfin/dpmc.h b/include/asm-blackfin/dpmc.h
index 7f34cd384f12..de28e6e018b3 100644
--- a/include/asm-blackfin/dpmc.h
+++ b/include/asm-blackfin/dpmc.h
@@ -7,63 +7,18 @@
 #ifndef _BLACKFIN_DPMC_H_
 #define _BLACKFIN_DPMC_H_
 
-#define SLEEP_MODE              1
-#define DEEP_SLEEP_MODE         2
-#define ACTIVE_PLL_DISABLED     3
-#define FULLON_MODE             4
-#define ACTIVE_PLL_ENABLED      5
-#define HIBERNATE_MODE          6
-
-#define IOCTL_FULL_ON_MODE      _IO('s', 0xA0)
-#define IOCTL_ACTIVE_MODE       _IO('s', 0xA1)
-#define IOCTL_SLEEP_MODE        _IO('s', 0xA2)
-#define IOCTL_DEEP_SLEEP_MODE   _IO('s', 0xA3)
-#define IOCTL_HIBERNATE_MODE    _IO('s', 0xA4)
-#define IOCTL_CHANGE_FREQUENCY  _IOW('s', 0xA5, unsigned long)
-#define IOCTL_CHANGE_VOLTAGE    _IOW('s', 0xA6, unsigned long)
-#define IOCTL_SET_CCLK          _IOW('s', 0xA7, unsigned long)
-#define IOCTL_SET_SCLK          _IOW('s', 0xA8, unsigned long)
-#define IOCTL_GET_PLLSTATUS     _IOW('s', 0xA9, unsigned long)
-#define IOCTL_GET_CORECLOCK     _IOW('s', 0xAA, unsigned long)
-#define IOCTL_GET_SYSTEMCLOCK   _IOW('s', 0xAB, unsigned long)
-#define IOCTL_GET_VCO           _IOW('s', 0xAC, unsigned long)
-#define IOCTL_DISABLE_WDOG_TIMER _IO('s', 0xAD)
-#define IOCTL_UNMASK_WDOG_WAKEUP_EVENT _IO('s',0xAE)
-#define IOCTL_PROGRAM_WDOG_TIMER _IOW('s',0xAF,unsigned long)
-#define IOCTL_CLEAR_WDOG_WAKEUP_EVENT _IO('s',0xB0)
-#define IOCTL_SLEEP_DEEPER_MODE _IO('s',0xB1)
-
-#define DPMC_MINOR              254
-
-#define ON      0
-#define OFF     1
-
 #ifdef __KERNEL__
+#ifndef __ASSEMBLY__
 
-unsigned long calc_volt(void);
-int calc_vlev(int vlt);
-unsigned long change_voltage(unsigned long volt);
-int calc_msel(int vco_hz);
-unsigned long change_frequency(unsigned long vco_mhz);
-int set_pll_div(unsigned short sel, unsigned char flag);
-int get_vco(void);
-unsigned long change_system_clock(unsigned long clock);
-unsigned long change_core_clock(unsigned long clock);
-unsigned long get_pll_status(void);
-void change_baud(int baud);
-void fullon_mode(void);
-void active_mode(void);
 void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
 void deep_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
 void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
 void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void program_wdog_timer(unsigned long);
-void unmask_wdog_wakeup_evt(void);
-void clear_wdog_wakeup_evt(void);
-void disable_wdog_timer(void);
+void do_hibernate(int wakeup);
+void set_dram_srfs(void);
+void unset_dram_srfs(void);
 
-extern unsigned long get_cclk(void);
-extern unsigned long get_sclk(void);
+#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
 
 struct bfin_dpmc_platform_data {
         const unsigned int *tuple_tab;
@@ -71,8 +26,33 @@ struct bfin_dpmc_platform_data {
         unsigned short vr_settling_time; /* in us */
 };
 
-#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
+#else
+
+#define PM_PUSH(x) \
+        R0 = [P0 + (x - SRAM_BASE_ADDRESS)];\
+        [--SP] =  R0;\
+
+#define PM_POP(x) \
+        R0 = [SP++];\
+        [P0 + (x - SRAM_BASE_ADDRESS)] = R0;\
+
+#define PM_SYS_PUSH(x) \
+        R0 = [P0 + (x - PLL_CTL)];\
+        [--SP] =  R0;\
+
+#define PM_SYS_POP(x) \
+        R0 = [SP++];\
+        [P0 + (x - PLL_CTL)] = R0;\
+
+#define PM_SYS_PUSH16(x) \
+        R0 = w[P0 + (x - PLL_CTL)];\
+        [--SP] =  R0;\
+
+#define PM_SYS_POP16(x) \
+        R0 = [SP++];\
+        w[P0 + (x - PLL_CTL)] = R0;\
 
+#endif
 #endif  /* __KERNEL__ */
 
 #endif  /*_BLACKFIN_DPMC_H_*/
diff --git a/include/asm-blackfin/elf.h b/include/asm-blackfin/elf.h
index 30303fc8292c..67a03a8a353e 100644
--- a/include/asm-blackfin/elf.h
+++ b/include/asm-blackfin/elf.h
@@ -15,6 +15,8 @@
 #define EF_BFIN_FDPIC           0x00000002      /* -mfdpic */
 #define EF_BFIN_CODE_IN_L1      0x00000010      /* --code-in-l1 */
 #define EF_BFIN_DATA_IN_L1      0x00000020      /* --data-in-l1 */
+#define EF_BFIN_CODE_IN_L2      0x00000040      /* --code-in-l2 */
+#define EF_BFIN_DATA_IN_L2      0x00000080      /* --data-in-l2 */
 
 typedef unsigned long elf_greg_t;
 
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
index ff95e9d88342..168f1251eb4d 100644
--- a/include/asm-blackfin/gpio.h
+++ b/include/asm-blackfin/gpio.h
@@ -376,8 +376,12 @@ struct gpio_port_t {
 #endif
 
 #ifdef CONFIG_PM
-unsigned int bfin_pm_setup(void);
-void bfin_pm_restore(void);
+
+unsigned int bfin_pm_standby_setup(void);
+void bfin_pm_standby_restore(void);
+
+void bfin_gpio_pm_hibernate_restore(void);
+void bfin_gpio_pm_hibernate_suspend(void);
 
 #ifndef CONFIG_BF54x
 #define PM_WAKE_RISING  0x1
@@ -392,17 +396,8 @@ void gpio_pm_wakeup_free(unsigned gpio);
 
 struct gpio_port_s {
         unsigned short data;
-        unsigned short data_clear;
-        unsigned short data_set;
-        unsigned short toggle;
         unsigned short maska;
-        unsigned short maska_clear;
-        unsigned short maska_set;
-        unsigned short maska_toggle;
         unsigned short maskb;
-        unsigned short maskb_clear;
-        unsigned short maskb_set;
-        unsigned short maskb_toggle;
         unsigned short dir;
         unsigned short polar;
         unsigned short edge;
@@ -411,10 +406,10 @@ struct gpio_port_s {
 
         unsigned short fer;
         unsigned short reserved;
+        unsigned short mux;
 };
 #endif /*CONFIG_BF54x*/
 #endif /*CONFIG_PM*/
-
 /***********************************************************
 *
 * FUNCTIONS: Blackfin GPIO Driver
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h
index 4725268a5ada..b7b166f4f064 100644
--- a/include/asm-blackfin/mach-bf527/anomaly.h
+++ b/include/asm-blackfin/mach-bf527/anomaly.h
@@ -23,6 +23,8 @@
 #define ANOMALY_05000245 (1)
 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
 #define ANOMALY_05000265 (1)
+/* New Feature: EMAC TX DMA Word Alignment */
+#define ANOMALY_05000285 (1)
 /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
 #define ANOMALY_05000312 (1)
 /* Incorrect Access of OTP_STATUS During otp_write() Function */
diff --git a/include/asm-blackfin/mach-bf527/bfin_sir.h b/include/asm-blackfin/mach-bf527/bfin_sir.h
index 0612d0c9501c..cfd8ad4f1f2c 100644
--- a/include/asm-blackfin/mach-bf527/bfin_sir.h
+++ b/include/asm-blackfin/mach-bf527/bfin_sir.h
@@ -118,16 +118,25 @@ static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
 
 #define DRIVER_NAME "bfin_sir"
 
-static void bfin_sir_hw_init(void)
+static int bfin_sir_hw_init(void)
 {
+        int ret = -ENODEV;
 #ifdef CONFIG_BFIN_SIR0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
+        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
+        if (ret)
+                return ret;
+        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
+        if (ret)
+                return ret;
 #endif
 
 #ifdef CONFIG_BFIN_SIR1
-        peripheral_request(P_UART1_TX, DRIVER_NAME);
-        peripheral_request(P_UART1_RX, DRIVER_NAME);
+        ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
+        if (ret)
+                return ret;
+        ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
+        if (ret)
+                return ret;
 #endif
-        SSYNC();
+        return ret;
 }
diff --git a/include/asm-blackfin/mach-bf527/defBF527.h b/include/asm-blackfin/mach-bf527/defBF527.h
index 82134f578f32..f1a70db70cb8 100644
--- a/include/asm-blackfin/mach-bf527/defBF527.h
+++ b/include/asm-blackfin/mach-bf527/defBF527.h
@@ -302,6 +302,7 @@
 #define PHYIE             0x00000001    /* PHY_INT Interrupt Enable                               */
 #define RXDWA             0x00000002    /* Receive Frame DMA Word Alignment (Odd/Even*)           */
 #define RXCKS             0x00000004    /* Enable RX Frame TCP/UDP Checksum Computation           */
+#define TXDWA             0x00000010    /* Transmit Frame DMA Word Alignment (Odd/Even*)          */
 #define MDCDIV            0x00003F00    /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]            */
 
 #define SET_MDCDIV(x) (((x)&0x3F)<< 8)   /* Set MDC Clock Divisor                                 */
diff --git a/include/asm-blackfin/mach-bf527/mem_init.h b/include/asm-blackfin/mach-bf527/mem_init.h
index 008ca66719e2..cbe03f4a5698 100644
--- a/include/asm-blackfin/mach-bf527/mem_init.h
+++ b/include/asm-blackfin/mach-bf527/mem_init.h
@@ -146,33 +146,6 @@
 #define SDRAM_CL    CL_3
 #endif
 
-#if (CONFIG_MEM_SIZE == 128)
-#define SDRAM_SIZE      EBSZ_128
-#endif
-#if (CONFIG_MEM_SIZE == 64)
-#define SDRAM_SIZE      EBSZ_64
-#endif
-#if (CONFIG_MEM_SIZE == 32)
-#define SDRAM_SIZE      EBSZ_32
-#endif
-#if (CONFIG_MEM_SIZE == 16)
-#define SDRAM_SIZE      EBSZ_16
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 11)
-#define SDRAM_WIDTH     EBCAW_11
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 10)
-#define SDRAM_WIDTH     EBCAW_10
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 9)
-#define SDRAM_WIDTH     EBCAW_9
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 8)
-#define SDRAM_WIDTH     EBCAW_8
-#endif
-
-#define mem_SDBCTL      (SDRAM_WIDTH | SDRAM_SIZE | EBE)
-
 /* Equation from section 17 (p17-46) of BF533 HRM */
 #define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
 
diff --git a/include/asm-blackfin/mach-bf533/bfin_sir.h b/include/asm-blackfin/mach-bf533/bfin_sir.h
index cefcf8bb505b..9bb87e9e2e9b 100644
--- a/include/asm-blackfin/mach-bf533/bfin_sir.h
+++ b/include/asm-blackfin/mach-bf533/bfin_sir.h
@@ -110,11 +110,16 @@ static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
 
 #define DRIVER_NAME "bfin_sir"
 
-static void bfin_sir_hw_init(void)
+static int bfin_sir_hw_init(void)
 {
+        int ret = -ENODEV;
 #ifdef CONFIG_BFIN_SIR0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
+        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
+        if (ret)
+                return ret;
+        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
+        if (ret)
+                return ret;
 #endif
-        SSYNC();
+        return ret;
 }
diff --git a/include/asm-blackfin/mach-bf533/mem_init.h b/include/asm-blackfin/mach-bf533/mem_init.h
index f8f31901fca9..995c06b2b1ef 100644
--- a/include/asm-blackfin/mach-bf533/mem_init.h
+++ b/include/asm-blackfin/mach-bf533/mem_init.h
@@ -133,33 +133,6 @@
 #define SDRAM_CL    CL_3
 #endif
 
-#if (CONFIG_MEM_SIZE == 128)
-#define SDRAM_SIZE      EBSZ_128
-#endif
-#if (CONFIG_MEM_SIZE == 64)
-#define SDRAM_SIZE      EBSZ_64
-#endif
-#if (CONFIG_MEM_SIZE == 32)
-#define SDRAM_SIZE      EBSZ_32
-#endif
-#if (CONFIG_MEM_SIZE == 16)
-#define SDRAM_SIZE      EBSZ_16
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 11)
-#define SDRAM_WIDTH     EBCAW_11
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 10)
-#define SDRAM_WIDTH     EBCAW_10
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 9)
-#define SDRAM_WIDTH     EBCAW_9
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 8)
-#define SDRAM_WIDTH     EBCAW_8
-#endif
-
-#define mem_SDBCTL      (SDRAM_WIDTH | SDRAM_SIZE | EBE)
-
 /* Equation from section 17 (p17-46) of BF533 HRM */
 #define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref)  / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
 
diff --git a/include/asm-blackfin/mach-bf537/bfin_sir.h b/include/asm-blackfin/mach-bf537/bfin_sir.h
index 0612d0c9501c..cfd8ad4f1f2c 100644
--- a/include/asm-blackfin/mach-bf537/bfin_sir.h
+++ b/include/asm-blackfin/mach-bf537/bfin_sir.h
@@ -118,16 +118,25 @@ static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
 
 #define DRIVER_NAME "bfin_sir"
 
-static void bfin_sir_hw_init(void)
+static int bfin_sir_hw_init(void)
 {
+        int ret = -ENODEV;
 #ifdef CONFIG_BFIN_SIR0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
+        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
+        if (ret)
+                return ret;
+        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
+        if (ret)
+                return ret;
 #endif
 
 #ifdef CONFIG_BFIN_SIR1
-        peripheral_request(P_UART1_TX, DRIVER_NAME);
-        peripheral_request(P_UART1_RX, DRIVER_NAME);
+        ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
+        if (ret)
+                return ret;
+        ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
+        if (ret)
+                return ret;
 #endif
-        SSYNC();
+        return ret;
 }
diff --git a/include/asm-blackfin/mach-bf537/defBF537.h b/include/asm-blackfin/mach-bf537/defBF537.h
index 3f455909c418..abde24c6d3b1 100644
--- a/include/asm-blackfin/mach-bf537/defBF537.h
+++ b/include/asm-blackfin/mach-bf537/defBF537.h
@@ -290,6 +290,7 @@
 #define PHYIE           0x00000001      /* PHY_INT Interrupt Enable                                                     */
 #define RXDWA           0x00000002      /* Receive Frame DMA Word Alignment (Odd/Even*)         */
 #define RXCKS           0x00000004      /* Enable RX Frame TCP/UDP Checksum Computation         */
+#define TXDWA           0x00000010      /* Transmit Frame DMA Word Alignment (Odd/Even*)        */
 #define MDCDIV          0x00003F00      /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]          */
 
 #define SET_MDCDIV(x)   (((x)&0x3F)<< 8)        /* Set MDC Clock Divisor                                */
diff --git a/include/asm-blackfin/mach-bf537/mem_init.h b/include/asm-blackfin/mach-bf537/mem_init.h
index 9ad979d416c6..f67698f670ca 100644
--- a/include/asm-blackfin/mach-bf537/mem_init.h
+++ b/include/asm-blackfin/mach-bf537/mem_init.h
@@ -139,33 +139,6 @@
 #define SDRAM_CL    CL_3
 #endif
 
-#if (CONFIG_MEM_SIZE == 128)
-#define SDRAM_SIZE      EBSZ_128
-#endif
-#if (CONFIG_MEM_SIZE == 64)
-#define SDRAM_SIZE      EBSZ_64
-#endif
-#if (CONFIG_MEM_SIZE == 32)
-#define SDRAM_SIZE      EBSZ_32
-#endif
-#if (CONFIG_MEM_SIZE == 16)
-#define SDRAM_SIZE      EBSZ_16
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 11)
-#define SDRAM_WIDTH     EBCAW_11
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 10)
-#define SDRAM_WIDTH     EBCAW_10
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 9)
-#define SDRAM_WIDTH     EBCAW_9
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 8)
-#define SDRAM_WIDTH     EBCAW_8
-#endif
-
-#define mem_SDBCTL      (SDRAM_WIDTH | SDRAM_SIZE | EBE)
-
 /* Equation from section 17 (p17-46) of BF533 HRM */
 #define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
 
diff --git a/include/asm-blackfin/mach-bf548/bfin_sir.h b/include/asm-blackfin/mach-bf548/bfin_sir.h
index 5e94271c7e3b..c41f9cf00268 100644
--- a/include/asm-blackfin/mach-bf548/bfin_sir.h
+++ b/include/asm-blackfin/mach-bf548/bfin_sir.h
@@ -124,26 +124,43 @@ struct bfin_sir_self {
 
 #define DRIVER_NAME "bfin_sir"
 
-static void bfin_sir_hw_init(void)
+static int bfin_sir_hw_init(void)
 {
+        int ret = -ENODEV;
 #ifdef CONFIG_BFIN_SIR0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
+        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
+        if (ret)
+                return ret;
+        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
+        if (ret)
+                return ret;
 #endif
 
 #ifdef CONFIG_BFIN_SIR1
-        peripheral_request(P_UART1_TX, DRIVER_NAME);
-        peripheral_request(P_UART1_RX, DRIVER_NAME);
+        ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
+        if (ret)
+                return ret;
+        ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
+        if (ret)
+                return ret;
 #endif
 
 #ifdef CONFIG_BFIN_SIR2
-        peripheral_request(P_UART2_TX, DRIVER_NAME);
-        peripheral_request(P_UART2_RX, DRIVER_NAME);
+        ret = peripheral_request(P_UART2_TX, DRIVER_NAME);
+        if (ret)
+                return ret;
+        ret = peripheral_request(P_UART2_RX, DRIVER_NAME);
+        if (ret)
+                return ret;
 #endif
 
 #ifdef CONFIG_BFIN_SIR3
-        peripheral_request(P_UART3_TX, DRIVER_NAME);
-        peripheral_request(P_UART3_RX, DRIVER_NAME);
+        ret = peripheral_request(P_UART3_TX, DRIVER_NAME);
+        if (ret)
+                return ret;
+        ret = peripheral_request(P_UART3_RX, DRIVER_NAME);
+        if (ret)
+                return ret;
 #endif
-        SSYNC();
+        return ret;
 }
diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h
index cb8b0f15c9a6..bba82dc75f16 100644
--- a/include/asm-blackfin/mach-bf548/gpio.h
+++ b/include/asm-blackfin/mach-bf548/gpio.h
@@ -209,3 +209,11 @@ struct gpio_port_t {
         unsigned short dummy7;
         unsigned int port_mux;
 };
+
+struct gpio_port_s {
+        unsigned short fer;
+        unsigned short data;
+        unsigned short dir;
+        unsigned short inen;
+        unsigned int mux;
+};
diff --git a/include/asm-blackfin/mach-bf561/bfin_sir.h b/include/asm-blackfin/mach-bf561/bfin_sir.h
index cefcf8bb505b..9bb87e9e2e9b 100644
--- a/include/asm-blackfin/mach-bf561/bfin_sir.h
+++ b/include/asm-blackfin/mach-bf561/bfin_sir.h
@@ -110,11 +110,16 @@ static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
 
 #define DRIVER_NAME "bfin_sir"
 
-static void bfin_sir_hw_init(void)
+static int bfin_sir_hw_init(void)
 {
+        int ret = -ENODEV;
 #ifdef CONFIG_BFIN_SIR0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
+        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
+        if (ret)
+                return ret;
+        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
+        if (ret)
+                return ret;
 #endif
-        SSYNC();
+        return ret;
 }
diff --git a/include/asm-blackfin/mach-bf561/mem_init.h b/include/asm-blackfin/mach-bf561/mem_init.h
index 439a5895b346..e163260bca18 100644
--- a/include/asm-blackfin/mach-bf561/mem_init.h
+++ b/include/asm-blackfin/mach-bf561/mem_init.h
@@ -131,33 +131,6 @@
 #define SDRAM_CL    CL_3
 #endif
 
-#if (CONFIG_MEM_SIZE == 128)
-#define SDRAM_SIZE      EB0_SZ_128
-#endif
-#if (CONFIG_MEM_SIZE == 64)
-#define SDRAM_SIZE      EB0_SZ_64
-#endif
-#if ( CONFIG_MEM_SIZE == 32)
-#define SDRAM_SIZE      EB0_SZ_32
-#endif
-#if (CONFIG_MEM_SIZE == 16)
-#define SDRAM_SIZE      EB0_SZ_16
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 11)
-#define SDRAM_WIDTH     EB0_CAW_11
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 10)
-#define SDRAM_WIDTH     EB0_CAW_10
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 9)
-#define SDRAM_WIDTH     EB0_CAW_9
-#endif
-#if (CONFIG_MEM_ADD_WIDTH == 8)
-#define SDRAM_WIDTH     EB0_CAW_8
-#endif
-
-#define mem_SDBCTL      (SDRAM_WIDTH | SDRAM_SIZE | EB0_E)
-
 /* Equation from section 17 (p17-46) of BF533 HRM */
 #define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
 
diff --git a/include/asm-blackfin/module.h b/include/asm-blackfin/module.h
index 3c7ce1644280..e3128df139d6 100644
--- a/include/asm-blackfin/module.h
+++ b/include/asm-blackfin/module.h
@@ -6,8 +6,6 @@
 #define Elf_Shdr        Elf32_Shdr
 #define Elf_Sym         Elf32_Sym
 #define Elf_Ehdr        Elf32_Ehdr
-#define FLG_CODE_IN_L1  0x10
-#define FLG_DATA_IN_L1  0x20
 
 struct mod_arch_specific {
         Elf_Shdr        *text_l1;
@@ -15,5 +13,8 @@ struct mod_arch_specific {
         Elf_Shdr        *bss_a_l1;
         Elf_Shdr        *data_b_l1;
         Elf_Shdr        *bss_b_l1;
+        Elf_Shdr        *text_l2;
+        Elf_Shdr        *data_l2;
+        Elf_Shdr        *bss_l2;
 };
 #endif                          /* _ASM_BFIN_MODULE_H */
diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h
index 1c0040724612..6f3995b119d8 100644
--- a/include/asm-blackfin/processor.h
+++ b/include/asm-blackfin/processor.h
@@ -112,7 +112,26 @@ unsigned long get_wchan(struct task_struct *p);
 static inline uint32_t __pure bfin_revid(void)
 {
         /* stored in the upper 4 bits */
-        return bfin_read_CHIPID() >> 28;
+        uint32_t revid = bfin_read_CHIPID() >> 28;
+
+#ifdef CONFIG_BF52x
+        /* ANOMALY_05000357
+         * Incorrect Revision Number in DSPID Register
+         */
+        if (revid == 0)
+                switch (bfin_read16(_BOOTROM_GET_DXE_ADDRESS_TWI)) {
+                case 0x0010:
+                        revid = 0;
+                        break;
+                case 0x2796:
+                        revid = 1;
+                        break;
+                default:
+                        revid = 0xFFFF;
+                        break;
+                }
+#endif
+        return revid;
 }
 
 static inline uint32_t __pure bfin_compiled_revid(void)