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-rw-r--r--include/asm-blackfin/bfin-global.h6
-rw-r--r--include/asm-blackfin/bfin5xx_spi.h3
-rw-r--r--include/asm-blackfin/cplb-mpu.h61
-rw-r--r--include/asm-blackfin/cplb.h4
-rw-r--r--include/asm-blackfin/cplbinit.h39
-rw-r--r--include/asm-blackfin/delay.h66
-rw-r--r--include/asm-blackfin/dma.h6
-rw-r--r--include/asm-blackfin/elf.h2
-rw-r--r--include/asm-blackfin/fixed_code.h4
-rw-r--r--include/asm-blackfin/gpio.h84
-rw-r--r--include/asm-blackfin/gptimers.h2
-rw-r--r--include/asm-blackfin/io.h3
-rw-r--r--include/asm-blackfin/mach-bf527/bfin_serial_5xx.h2
-rw-r--r--include/asm-blackfin/mach-bf527/defBF52x_base.h86
-rw-r--r--include/asm-blackfin/mach-bf527/dma.h7
-rw-r--r--include/asm-blackfin/mach-bf527/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf527/mem_map.h3
-rw-r--r--include/asm-blackfin/mach-bf527/portmux.h2
-rw-r--r--include/asm-blackfin/mach-bf533/anomaly.h12
-rw-r--r--include/asm-blackfin/mach-bf533/bfin_serial_5xx.h2
-rw-r--r--include/asm-blackfin/mach-bf533/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf533/mem_map.h4
-rw-r--r--include/asm-blackfin/mach-bf533/portmux.h4
-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h14
-rw-r--r--include/asm-blackfin/mach-bf537/bfin_serial_5xx.h2
-rw-r--r--include/asm-blackfin/mach-bf537/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf537/mem_map.h3
-rw-r--r--include/asm-blackfin/mach-bf537/portmux.h2
-rw-r--r--include/asm-blackfin/mach-bf548/anomaly.h54
-rw-r--r--include/asm-blackfin/mach-bf548/bf548.h34
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_serial_5xx.h2
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF54x_base.h33
-rw-r--r--include/asm-blackfin/mach-bf548/defBF542.h4
-rw-r--r--include/asm-blackfin/mach-bf548/defBF544.h2
-rw-r--r--include/asm-blackfin/mach-bf548/defBF548.h6
-rw-r--r--include/asm-blackfin/mach-bf548/defBF549.h2
-rw-r--r--include/asm-blackfin/mach-bf548/defBF54x_base.h55
-rw-r--r--include/asm-blackfin/mach-bf548/irq.h8
-rw-r--r--include/asm-blackfin/mach-bf548/mem_init.h62
-rw-r--r--include/asm-blackfin/mach-bf548/mem_map.h18
-rw-r--r--include/asm-blackfin/mach-bf548/portmux.h16
-rw-r--r--include/asm-blackfin/mach-bf561/anomaly.h18
-rw-r--r--include/asm-blackfin/mach-bf561/bf561.h19
-rw-r--r--include/asm-blackfin/mach-bf561/bfin_serial_5xx.h2
-rw-r--r--include/asm-blackfin/mach-bf561/defBF561.h18
-rw-r--r--include/asm-blackfin/mach-bf561/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf561/mem_map.h7
-rw-r--r--include/asm-blackfin/mach-bf561/portmux.h2
-rw-r--r--include/asm-blackfin/mach-common/def_LPBlackfin.h8
-rw-r--r--include/asm-blackfin/mmu.h4
-rw-r--r--include/asm-blackfin/mmu_context.h62
-rw-r--r--include/asm-blackfin/page.h3
-rw-r--r--include/asm-blackfin/page_offset.h2
-rw-r--r--include/asm-blackfin/socket.h3
-rw-r--r--include/asm-blackfin/string.h2
-rw-r--r--include/asm-blackfin/system.h57
-rw-r--r--include/asm-blackfin/traps.h100
-rw-r--r--include/asm-blackfin/uaccess.h2
-rw-r--r--include/asm-blackfin/unistd.h3
-rw-r--r--include/asm-blackfin/user.h2
60 files changed, 669 insertions, 380 deletions
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
index 14cb8d35924e..6ae0619d7696 100644
--- a/include/asm-blackfin/bfin-global.h
+++ b/include/asm-blackfin/bfin-global.h
@@ -50,8 +50,8 @@ extern unsigned long get_sclk(void);
50extern unsigned long sclk_to_usecs(unsigned long sclk); 50extern unsigned long sclk_to_usecs(unsigned long sclk);
51extern unsigned long usecs_to_sclk(unsigned long usecs); 51extern unsigned long usecs_to_sclk(unsigned long usecs);
52 52
53extern void dump_thread(struct pt_regs *regs, struct user *dump); 53extern void dump_bfin_process(struct pt_regs *regs);
54extern void dump_bfin_regs(struct pt_regs *fp, void *retaddr); 54extern void dump_bfin_mem(struct pt_regs *regs);
55extern void dump_bfin_trace_buffer(void); 55extern void dump_bfin_trace_buffer(void);
56 56
57extern int init_arch_irq(void); 57extern int init_arch_irq(void);
@@ -63,6 +63,7 @@ extern void bfin_dcache_init(void);
63extern int read_iloc(void); 63extern int read_iloc(void);
64extern int bfin_console_init(void); 64extern int bfin_console_init(void);
65extern asmlinkage void lower_to_irq14(void); 65extern asmlinkage void lower_to_irq14(void);
66extern asmlinkage void bfin_return_from_exception(void);
66extern void init_exception_vectors(void); 67extern void init_exception_vectors(void);
67extern void init_dma(void); 68extern void init_dma(void);
68extern void program_IAR(void); 69extern void program_IAR(void);
@@ -80,6 +81,7 @@ extern int atomic_sub32(void);
80extern int atomic_ior32(void); 81extern int atomic_ior32(void);
81extern int atomic_and32(void); 82extern int atomic_and32(void);
82extern int atomic_xor32(void); 83extern int atomic_xor32(void);
84extern void safe_user_instruction(void);
83extern void sigreturn_stub(void); 85extern void sigreturn_stub(void);
84 86
85extern void *l1_data_A_sram_alloc(size_t); 87extern void *l1_data_A_sram_alloc(size_t);
diff --git a/include/asm-blackfin/bfin5xx_spi.h b/include/asm-blackfin/bfin5xx_spi.h
index f617d8765451..1a0b57f6a3d4 100644
--- a/include/asm-blackfin/bfin5xx_spi.h
+++ b/include/asm-blackfin/bfin5xx_spi.h
@@ -152,6 +152,7 @@
152struct bfin5xx_spi_master { 152struct bfin5xx_spi_master {
153 u16 num_chipselect; 153 u16 num_chipselect;
154 u8 enable_dma; 154 u8 enable_dma;
155 u16 pin_req[4];
155}; 156};
156 157
157/* spi_board_info.controller_data for SPI slave devices, 158/* spi_board_info.controller_data for SPI slave devices,
@@ -162,7 +163,7 @@ struct bfin5xx_spi_chip {
162 u8 enable_dma; 163 u8 enable_dma;
163 u8 bits_per_word; 164 u8 bits_per_word;
164 u8 cs_change_per_word; 165 u8 cs_change_per_word;
165 u8 cs_chg_udelay; 166 u16 cs_chg_udelay; /* Some devices require 16-bit delays */
166}; 167};
167 168
168#endif /* _SPI_CHANNEL_H_ */ 169#endif /* _SPI_CHANNEL_H_ */
diff --git a/include/asm-blackfin/cplb-mpu.h b/include/asm-blackfin/cplb-mpu.h
new file mode 100644
index 000000000000..75c67b99d607
--- /dev/null
+++ b/include/asm-blackfin/cplb-mpu.h
@@ -0,0 +1,61 @@
1/*
2 * File: include/asm-blackfin/cplbinit.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29#ifndef __ASM_BFIN_CPLB_MPU_H
30#define __ASM_BFIN_CPLB_MPU_H
31
32struct cplb_entry {
33 unsigned long data, addr;
34};
35
36struct mem_region {
37 unsigned long start, end;
38 unsigned long dcplb_data;
39 unsigned long icplb_data;
40};
41
42extern struct cplb_entry dcplb_tbl[MAX_CPLBS];
43extern struct cplb_entry icplb_tbl[MAX_CPLBS];
44extern int first_switched_icplb;
45extern int first_mask_dcplb;
46extern int first_switched_dcplb;
47
48extern int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot;
49extern int nr_cplb_flush;
50
51extern int page_mask_order;
52extern int page_mask_nelts;
53
54extern unsigned long *current_rwx_mask;
55
56extern void flush_switched_cplbs(void);
57extern void set_mask_dcplbs(unsigned long *);
58
59extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
60
61#endif /* __ASM_BFIN_CPLB_MPU_H */
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index 06828d77a58f..654375c2b746 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -65,7 +65,11 @@
65#define SIZE_1M 0x00100000 /* 1M */ 65#define SIZE_1M 0x00100000 /* 1M */
66#define SIZE_4M 0x00400000 /* 4M */ 66#define SIZE_4M 0x00400000 /* 4M */
67 67
68#ifdef CONFIG_MPU
69#define MAX_CPLBS 16
70#else
68#define MAX_CPLBS (16 * 2) 71#define MAX_CPLBS (16 * 2)
72#endif
69 73
70#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ 74#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
71 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) 75 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
index bec6ecdf1bdb..0eb1c1b685a7 100644
--- a/include/asm-blackfin/cplbinit.h
+++ b/include/asm-blackfin/cplbinit.h
@@ -27,9 +27,18 @@
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */ 28 */
29 29
30#ifndef __ASM_CPLBINIT_H__
31#define __ASM_CPLBINIT_H__
32
30#include <asm/blackfin.h> 33#include <asm/blackfin.h>
31#include <asm/cplb.h> 34#include <asm/cplb.h>
32 35
36#ifdef CONFIG_MPU
37
38#include <asm/cplb-mpu.h>
39
40#else
41
33#define INITIAL_T 0x1 42#define INITIAL_T 0x1
34#define SWITCH_T 0x2 43#define SWITCH_T 0x2
35#define I_CPLB 0x4 44#define I_CPLB 0x4
@@ -57,8 +66,8 @@ struct cplb_tab {
57 u16 size; 66 u16 size;
58}; 67};
59 68
60extern u_long icplb_table[MAX_CPLBS+1]; 69extern u_long icplb_table[];
61extern u_long dcplb_table[MAX_CPLBS+1]; 70extern u_long dcplb_table[];
62 71
63/* Till here we are discussing about the static memory management model. 72/* Till here we are discussing about the static memory management model.
64 * However, the operating envoronments commonly define more CPLB 73 * However, the operating envoronments commonly define more CPLB
@@ -69,28 +78,18 @@ extern u_long dcplb_table[MAX_CPLBS+1];
69 * This is how Page descriptor Table is implemented in uClinux/Blackfin. 78 * This is how Page descriptor Table is implemented in uClinux/Blackfin.
70 */ 79 */
71 80
72#ifdef CONFIG_CPLB_SWITCH_TAB_L1 81extern u_long ipdt_table[];
73extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data)); 82extern u_long dpdt_table[];
74extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
75
76#ifdef CONFIG_CPLB_INFO 83#ifdef CONFIG_CPLB_INFO
77extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data)); 84extern u_long ipdt_swapcount_table[];
78extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data)); 85extern u_long dpdt_swapcount_table[];
79#endif /* CONFIG_CPLB_INFO */ 86#endif
80 87
81#else 88#endif /* CONFIG_MPU */
82
83extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
84extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
85
86#ifdef CONFIG_CPLB_INFO
87extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
88extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
89#endif /* CONFIG_CPLB_INFO */
90
91#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
92 89
93extern unsigned long reserved_mem_dcache_on; 90extern unsigned long reserved_mem_dcache_on;
94extern unsigned long reserved_mem_icache_on; 91extern unsigned long reserved_mem_icache_on;
95 92
96extern void generate_cpl_tables(void); 93extern void generate_cpl_tables(void);
94
95#endif
diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h
index 52e7a10d7ff8..473a8113277f 100644
--- a/include/asm-blackfin/delay.h
+++ b/include/asm-blackfin/delay.h
@@ -1,29 +1,47 @@
1#ifndef _BLACKFIN_DELAY_H
2#define _BLACKFIN_DELAY_H
3
4static inline void __delay(unsigned long loops)
5{
6
7/* FIXME: Currently the assembler doesn't recognize Loop Register Clobbers,
8 uncomment this as soon those are implemented */
9/* 1/*
10 __asm__ __volatile__ ( "\t LSETUP (1f,1f) LC0= %0\n\t" 2 * delay.h - delay functions
11 "1:\t NOP;\n\t" 3 *
12 : :"a" (loops) 4 * Copyright (c) 2004-2007 Analog Devices Inc.
13 : "LT0","LB0","LC0"); 5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_DELAY_H__
10#define __ASM_DELAY_H__
14 11
15*/ 12#include <asm/mach/anomaly.h>
16 13
17 __asm__ __volatile__("[--SP] = LC0;\n\t" 14static inline void __delay(unsigned long loops)
18 "[--SP] = LT0;\n\t" 15{
19 "[--SP] = LB0;\n\t" 16 if (ANOMALY_05000312) {
20 "LSETUP (1f,1f) LC0 = %0;\n\t" 17 /* Interrupted loads to loop registers -> bad */
21 "1:\t NOP;\n\t" 18 unsigned long tmp;
22 "LB0 = [SP++];\n\t" 19 __asm__ __volatile__(
23 "LT0 = [SP++];\n\t" 20 "[--SP] = LC0;"
24 "LC0 = [SP++];\n" 21 "[--SP] = LT0;"
25 : 22 "[--SP] = LB0;"
26 :"a" (loops)); 23 "LSETUP (1f,1f) LC0 = %1;"
24 "1: NOP;"
25 /* We take advantage of the fact that LC0 is 0 at
26 * the end of the loop. Otherwise we'd need some
27 * NOPs after the CLI here.
28 */
29 "CLI %0;"
30 "LB0 = [SP++];"
31 "LT0 = [SP++];"
32 "LC0 = [SP++];"
33 "STI %0;"
34 : "=d" (tmp)
35 : "a" (loops)
36 );
37 } else
38 __asm__ __volatile__ (
39 "LSETUP(1f, 1f) LC0 = %0;"
40 "1: NOP;"
41 :
42 : "a" (loops)
43 : "LT0", "LB0", "LC0"
44 );
27} 45}
28 46
29#include <linux/param.h> /* needed for HZ */ 47#include <linux/param.h> /* needed for HZ */
@@ -41,4 +59,4 @@ static inline void udelay(unsigned long usecs)
41 __delay(usecs * loops_per_jiffy / (1000000 / HZ)); 59 __delay(usecs * loops_per_jiffy / (1000000 / HZ));
42} 60}
43 61
44#endif /* defined(_BLACKFIN_DELAY_H) */ 62#endif
diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h
index b469505af364..5abaa2cee8db 100644
--- a/include/asm-blackfin/dma.h
+++ b/include/asm-blackfin/dma.h
@@ -76,6 +76,9 @@ enum dma_chan_status {
76#define INTR_ON_BUF 2 76#define INTR_ON_BUF 2
77#define INTR_ON_ROW 3 77#define INTR_ON_ROW 3
78 78
79#define DMA_NOSYNC_KEEP_DMA_BUF 0
80#define DMA_SYNC_RESTART 1
81
79struct dmasg { 82struct dmasg {
80 unsigned long next_desc_addr; 83 unsigned long next_desc_addr;
81 unsigned long start_addr; 84 unsigned long start_addr;
@@ -157,7 +160,8 @@ void set_dma_y_count(unsigned int channel, unsigned short y_count);
157void set_dma_y_modify(unsigned int channel, short y_modify); 160void set_dma_y_modify(unsigned int channel, short y_modify);
158void set_dma_config(unsigned int channel, unsigned short config); 161void set_dma_config(unsigned int channel, unsigned short config);
159unsigned short set_bfin_dma_config(char direction, char flow_mode, 162unsigned short set_bfin_dma_config(char direction, char flow_mode,
160 char intr_mode, char dma_mode, char width); 163 char intr_mode, char dma_mode, char width,
164 char syncmode);
161void set_dma_curr_addr(unsigned int channel, unsigned long addr); 165void set_dma_curr_addr(unsigned int channel, unsigned long addr);
162 166
163/* get curr status for polling */ 167/* get curr status for polling */
diff --git a/include/asm-blackfin/elf.h b/include/asm-blackfin/elf.h
index 5264b5536a70..30303fc8292c 100644
--- a/include/asm-blackfin/elf.h
+++ b/include/asm-blackfin/elf.h
@@ -120,8 +120,6 @@ do { \
120 120
121#define ELF_PLATFORM (NULL) 121#define ELF_PLATFORM (NULL)
122 122
123#ifdef __KERNEL__
124#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX) 123#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
125#endif
126 124
127#endif 125#endif
diff --git a/include/asm-blackfin/fixed_code.h b/include/asm-blackfin/fixed_code.h
index e6df84ee1557..37db66c7030d 100644
--- a/include/asm-blackfin/fixed_code.h
+++ b/include/asm-blackfin/fixed_code.h
@@ -17,4 +17,6 @@
17 17
18#define ATOMIC_SEQS_END 0x480 18#define ATOMIC_SEQS_END 0x480
19 19
20#define FIXED_CODE_END 0x480 20#define SAFE_USER_INSTRUCTION 0x480
21
22#define FIXED_CODE_END 0x490
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
index 33ce98ef7e0f..d0426c108262 100644
--- a/include/asm-blackfin/gpio.h
+++ b/include/asm-blackfin/gpio.h
@@ -7,7 +7,7 @@
7 * Description: 7 * Description:
8 * 8 *
9 * Modified: 9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc. 10 * Copyright 2004-2008 Analog Devices Inc.
11 * 11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 * 13 *
@@ -304,39 +304,39 @@
304**************************************************************/ 304**************************************************************/
305 305
306#ifndef BF548_FAMILY 306#ifndef BF548_FAMILY
307void set_gpio_dir(unsigned short, unsigned short); 307void set_gpio_dir(unsigned, unsigned short);
308void set_gpio_inen(unsigned short, unsigned short); 308void set_gpio_inen(unsigned, unsigned short);
309void set_gpio_polar(unsigned short, unsigned short); 309void set_gpio_polar(unsigned, unsigned short);
310void set_gpio_edge(unsigned short, unsigned short); 310void set_gpio_edge(unsigned, unsigned short);
311void set_gpio_both(unsigned short, unsigned short); 311void set_gpio_both(unsigned, unsigned short);
312void set_gpio_data(unsigned short, unsigned short); 312void set_gpio_data(unsigned, unsigned short);
313void set_gpio_maska(unsigned short, unsigned short); 313void set_gpio_maska(unsigned, unsigned short);
314void set_gpio_maskb(unsigned short, unsigned short); 314void set_gpio_maskb(unsigned, unsigned short);
315void set_gpio_toggle(unsigned short); 315void set_gpio_toggle(unsigned);
316void set_gpiop_dir(unsigned short, unsigned short); 316void set_gpiop_dir(unsigned, unsigned short);
317void set_gpiop_inen(unsigned short, unsigned short); 317void set_gpiop_inen(unsigned, unsigned short);
318void set_gpiop_polar(unsigned short, unsigned short); 318void set_gpiop_polar(unsigned, unsigned short);
319void set_gpiop_edge(unsigned short, unsigned short); 319void set_gpiop_edge(unsigned, unsigned short);
320void set_gpiop_both(unsigned short, unsigned short); 320void set_gpiop_both(unsigned, unsigned short);
321void set_gpiop_data(unsigned short, unsigned short); 321void set_gpiop_data(unsigned, unsigned short);
322void set_gpiop_maska(unsigned short, unsigned short); 322void set_gpiop_maska(unsigned, unsigned short);
323void set_gpiop_maskb(unsigned short, unsigned short); 323void set_gpiop_maskb(unsigned, unsigned short);
324unsigned short get_gpio_dir(unsigned short); 324unsigned short get_gpio_dir(unsigned);
325unsigned short get_gpio_inen(unsigned short); 325unsigned short get_gpio_inen(unsigned);
326unsigned short get_gpio_polar(unsigned short); 326unsigned short get_gpio_polar(unsigned);
327unsigned short get_gpio_edge(unsigned short); 327unsigned short get_gpio_edge(unsigned);
328unsigned short get_gpio_both(unsigned short); 328unsigned short get_gpio_both(unsigned);
329unsigned short get_gpio_maska(unsigned short); 329unsigned short get_gpio_maska(unsigned);
330unsigned short get_gpio_maskb(unsigned short); 330unsigned short get_gpio_maskb(unsigned);
331unsigned short get_gpio_data(unsigned short); 331unsigned short get_gpio_data(unsigned);
332unsigned short get_gpiop_dir(unsigned short); 332unsigned short get_gpiop_dir(unsigned);
333unsigned short get_gpiop_inen(unsigned short); 333unsigned short get_gpiop_inen(unsigned);
334unsigned short get_gpiop_polar(unsigned short); 334unsigned short get_gpiop_polar(unsigned);
335unsigned short get_gpiop_edge(unsigned short); 335unsigned short get_gpiop_edge(unsigned);
336unsigned short get_gpiop_both(unsigned short); 336unsigned short get_gpiop_both(unsigned);
337unsigned short get_gpiop_maska(unsigned short); 337unsigned short get_gpiop_maska(unsigned);
338unsigned short get_gpiop_maskb(unsigned short); 338unsigned short get_gpiop_maskb(unsigned);
339unsigned short get_gpiop_data(unsigned short); 339unsigned short get_gpiop_data(unsigned);
340 340
341struct gpio_port_t { 341struct gpio_port_t {
342 unsigned short data; 342 unsigned short data;
@@ -382,8 +382,8 @@ struct gpio_port_t {
382#define PM_WAKE_LOW 0x8 382#define PM_WAKE_LOW 0x8
383#define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING) 383#define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING)
384 384
385int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type); 385int gpio_pm_wakeup_request(unsigned gpio, unsigned char type);
386void gpio_pm_wakeup_free(unsigned short gpio); 386void gpio_pm_wakeup_free(unsigned gpio);
387unsigned int gpio_pm_setup(void); 387unsigned int gpio_pm_setup(void);
388void gpio_pm_restore(void); 388void gpio_pm_restore(void);
389 389
@@ -426,19 +426,19 @@ struct gpio_port_s {
426* MODIFICATION HISTORY : 426* MODIFICATION HISTORY :
427**************************************************************/ 427**************************************************************/
428 428
429int gpio_request(unsigned short, const char *); 429int gpio_request(unsigned, const char *);
430void gpio_free(unsigned short); 430void gpio_free(unsigned);
431 431
432void gpio_set_value(unsigned short gpio, unsigned short arg); 432void gpio_set_value(unsigned gpio, int arg);
433unsigned short gpio_get_value(unsigned short gpio); 433int gpio_get_value(unsigned gpio);
434 434
435#ifndef BF548_FAMILY 435#ifndef BF548_FAMILY
436#define gpio_get_value(gpio) get_gpio_data(gpio) 436#define gpio_get_value(gpio) get_gpio_data(gpio)
437#define gpio_set_value(gpio, value) set_gpio_data(gpio, value) 437#define gpio_set_value(gpio, value) set_gpio_data(gpio, value)
438#endif 438#endif
439 439
440void gpio_direction_input(unsigned short gpio); 440int gpio_direction_input(unsigned gpio);
441void gpio_direction_output(unsigned short gpio); 441int gpio_direction_output(unsigned gpio, int value);
442 442
443#include <asm-generic/gpio.h> /* cansleep wrappers */ 443#include <asm-generic/gpio.h> /* cansleep wrappers */
444#include <asm/irq.h> 444#include <asm/irq.h>
diff --git a/include/asm-blackfin/gptimers.h b/include/asm-blackfin/gptimers.h
index c97ab03e43a6..8265ea473d5b 100644
--- a/include/asm-blackfin/gptimers.h
+++ b/include/asm-blackfin/gptimers.h
@@ -197,6 +197,8 @@ uint32_t get_gptimer_period (int timer_id);
197uint32_t get_gptimer_count (int timer_id); 197uint32_t get_gptimer_count (int timer_id);
198uint16_t get_gptimer_intr (int timer_id); 198uint16_t get_gptimer_intr (int timer_id);
199void clear_gptimer_intr (int timer_id); 199void clear_gptimer_intr (int timer_id);
200uint16_t get_gptimer_over (int timer_id);
201void clear_gptimer_over (int timer_id);
200void set_gptimer_config (int timer_id, uint16_t config); 202void set_gptimer_config (int timer_id, uint16_t config);
201uint16_t get_gptimer_config (int timer_id); 203uint16_t get_gptimer_config (int timer_id);
202void set_gptimer_pulse_hi (int timer_id); 204void set_gptimer_pulse_hi (int timer_id);
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
index d1d2e6be3b59..574fe56989d1 100644
--- a/include/asm-blackfin/io.h
+++ b/include/asm-blackfin/io.h
@@ -122,6 +122,7 @@ extern void outsl(unsigned long port, const void *addr, unsigned long count);
122extern void insb(unsigned long port, void *addr, unsigned long count); 122extern void insb(unsigned long port, void *addr, unsigned long count);
123extern void insw(unsigned long port, void *addr, unsigned long count); 123extern void insw(unsigned long port, void *addr, unsigned long count);
124extern void insl(unsigned long port, void *addr, unsigned long count); 124extern void insl(unsigned long port, void *addr, unsigned long count);
125extern void insl_16(unsigned long port, void *addr, unsigned long count);
125 126
126extern void dma_outsb(unsigned long port, const void *addr, unsigned short count); 127extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
127extern void dma_outsw(unsigned long port, const void *addr, unsigned short count); 128extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
@@ -187,8 +188,6 @@ extern void blkfin_inv_cache_all(void);
187#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT) 188#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
188#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT) 189#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT)
189 190
190#define mm_ptov(vaddr) ((void *) (vaddr))
191#define mm_vtop(vaddr) ((unsigned long) (vaddr))
192#define phys_to_virt(vaddr) ((void *) (vaddr)) 191#define phys_to_virt(vaddr) ((void *) (vaddr))
193#define virt_to_phys(vaddr) ((unsigned long) (vaddr)) 192#define virt_to_phys(vaddr) ((unsigned long) (vaddr))
194 193
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
index 0b867e6a76c4..15dbc21eed8b 100644
--- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
@@ -146,7 +146,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
146 146
147 if (uart->rts_pin >= 0) { 147 if (uart->rts_pin >= 0) {
148 gpio_request(uart->rts_pin, DRIVER_NAME); 148 gpio_request(uart->rts_pin, DRIVER_NAME);
149 gpio_direction_output(uart->rts_pin); 149 gpio_direction_output(uart->rts_pin, 0);
150 } 150 }
151#endif 151#endif
152} 152}
diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h
index d6c24c54699d..fc69cf93f149 100644
--- a/include/asm-blackfin/mach-bf527/defBF52x_base.h
+++ b/include/asm-blackfin/mach-bf527/defBF52x_base.h
@@ -1718,55 +1718,55 @@
1718 1718
1719/* Bit masks for HOST_CONTROL */ 1719/* Bit masks for HOST_CONTROL */
1720 1720
1721#define HOST_EN 0x1 /* Host Enable */ 1721#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
1722#define nHOST_EN 0x0 1722#define HOST_CNTR_nHOST_EN 0x0
1723#define HOST_END 0x2 /* Host Endianess */ 1723#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
1724#define nHOST_END 0x0 1724#define HOST_CNTR_nHOST_END 0x0
1725#define DATA_SIZE 0x4 /* Data Size */ 1725#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
1726#define nDATA_SIZE 0x0 1726#define HOST_CNTR_nDATA_SIZE 0x0
1727#define HOST_RST 0x8 /* Host Reset */ 1727#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
1728#define nHOST_RST 0x0 1728#define HOST_CNTR_nHOST_RST 0x0
1729#define HRDY_OVR 0x20 /* Host Ready Override */ 1729#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
1730#define nHRDY_OVR 0x0 1730#define HOST_CNTR_nHRDY_OVR 0x0
1731#define INT_MODE 0x40 /* Interrupt Mode */ 1731#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
1732#define nINT_MODE 0x0 1732#define HOST_CNTR_nINT_MODE 0x0
1733#define BT_EN 0x80 /* Bus Timeout Enable */ 1733#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
1734#define nBT_EN 0x0 1734#define HOST_CNTR_ nBT_EN 0x0
1735#define EHW 0x100 /* Enable Host Write */ 1735#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
1736#define nEHW 0x0 1736#define HOST_CNTR_nEHW 0x0
1737#define EHR 0x200 /* Enable Host Read */ 1737#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
1738#define nEHR 0x0 1738#define HOST_CNTR_nEHR 0x0
1739#define BDR 0x400 /* Burst DMA Requests */ 1739#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
1740#define nBDR 0x0 1740#define HOST_CNTR_nBDR 0x0
1741 1741
1742/* Bit masks for HOST_STATUS */ 1742/* Bit masks for HOST_STATUS */
1743 1743
1744#define READY 0x1 /* DMA Ready */ 1744#define HOST_STAT_READY 0x1 /* DMA Ready */
1745#define nREADY 0x0 1745#define HOST_STAT_nREADY 0x0
1746#define FIFOFULL 0x2 /* FIFO Full */ 1746#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
1747#define nFIFOFULL 0x0 1747#define HOST_STAT_nFIFOFULL 0x0
1748#define FIFOEMPTY 0x4 /* FIFO Empty */ 1748#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
1749#define nFIFOEMPTY 0x0 1749#define HOST_STAT_nFIFOEMPTY 0x0
1750#define COMPLETE 0x8 /* DMA Complete */ 1750#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
1751#define nCOMPLETE 0x0 1751#define HOST_STAT_nCOMPLETE 0x0
1752#define HSHK 0x10 /* Host Handshake */ 1752#define HOST_STAT_HSHK 0x10 /* Host Handshake */
1753#define nHSHK 0x0 1753#define HOST_STAT_nHSHK 0x0
1754#define TIMEOUT 0x20 /* Host Timeout */ 1754#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
1755#define nTIMEOUT 0x0 1755#define HOST_STAT_nTIMEOUT 0x0
1756#define HIRQ 0x40 /* Host Interrupt Request */ 1756#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
1757#define nHIRQ 0x0 1757#define HOST_STAT_nHIRQ 0x0
1758#define ALLOW_CNFG 0x80 /* Allow New Configuration */ 1758#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
1759#define nALLOW_CNFG 0x0 1759#define HOST_STAT_nALLOW_CNFG 0x0
1760#define DMA_DIR 0x100 /* DMA Direction */ 1760#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
1761#define nDMA_DIR 0x0 1761#define HOST_STAT_nDMA_DIR 0x0
1762#define BTE 0x200 /* Bus Timeout Enabled */ 1762#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
1763#define nBTE 0x0 1763#define HOST_STAT_nBTE 0x0
1764#define HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ 1764#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
1765#define nHOSTRD_DONE 0x0 1765#define HOST_STAT_nHOSTRD_DONE 0x0
1766 1766
1767/* Bit masks for HOST_TIMEOUT */ 1767/* Bit masks for HOST_TIMEOUT */
1768 1768
1769#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ 1769#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1770 1770
1771/* Bit masks for CNT_CONFIG */ 1771/* Bit masks for CNT_CONFIG */
1772 1772
diff --git a/include/asm-blackfin/mach-bf527/dma.h b/include/asm-blackfin/mach-bf527/dma.h
index a41627ae9134..2dfee12864f6 100644
--- a/include/asm-blackfin/mach-bf527/dma.h
+++ b/include/asm-blackfin/mach-bf527/dma.h
@@ -35,7 +35,6 @@
35#define MAX_BLACKFIN_DMA_CHANNEL 16 35#define MAX_BLACKFIN_DMA_CHANNEL 16
36 36
37#define CH_PPI 0 /* PPI receive/transmit or NFC */ 37#define CH_PPI 0 /* PPI receive/transmit or NFC */
38#define CH_NFC 0 /* PPI receive/transmit or NFC */
39#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */ 38#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
40#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */ 39#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */
41#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */ 40#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */
@@ -54,6 +53,12 @@
54#define CH_MEM_STREAM1_DEST 14 /* TX */ 53#define CH_MEM_STREAM1_DEST 14 /* TX */
55#define CH_MEM_STREAM1_SRC 15 /* RX */ 54#define CH_MEM_STREAM1_SRC 15 /* RX */
56 55
56#if defined(CONFIG_BF527_NAND_D_PORTF)
57#define CH_NFC CH_PPI /* PPI receive/transmit or NFC */
58#elif defined(CONFIG_BF527_NAND_D_PORTH)
59#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */
60#endif
61
57extern int channel2irq(unsigned int channel); 62extern int channel2irq(unsigned int channel);
58extern struct dma_register *base_addr[]; 63extern struct dma_register *base_addr[];
59 64
diff --git a/include/asm-blackfin/mach-bf527/irq.h b/include/asm-blackfin/mach-bf527/irq.h
index 304f5bcfebe4..4e2b3f2020e5 100644
--- a/include/asm-blackfin/mach-bf527/irq.h
+++ b/include/asm-blackfin/mach-bf527/irq.h
@@ -176,11 +176,7 @@
176 176
177#define GPIO_IRQ_BASE IRQ_PF0 177#define GPIO_IRQ_BASE IRQ_PF0
178 178
179#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
180#define NR_IRQS (IRQ_PH15+1) 179#define NR_IRQS (IRQ_PH15+1)
181#else
182#define NR_IRQS (SYS_IRQS+1)
183#endif
184 180
185#define IVG7 7 181#define IVG7 7
186#define IVG8 8 182#define IVG8 8
diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h
index c5aa20102b24..193082deaa4e 100644
--- a/include/asm-blackfin/mach-bf527/mem_map.h
+++ b/include/asm-blackfin/mach-bf527/mem_map.h
@@ -47,6 +47,7 @@
47/* Boot ROM Memory */ 47/* Boot ROM Memory */
48 48
49#define BOOT_ROM_START 0xEF000000 49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x8000
50 51
51/* Level 1 Memory */ 52/* Level 1 Memory */
52 53
@@ -90,9 +91,7 @@
90 91
91/* Scratch Pad Memory */ 92/* Scratch Pad Memory */
92 93
93#if defined(CONFIG_BF527) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
94#define L1_SCRATCH_START 0xFFB00000 94#define L1_SCRATCH_START 0xFFB00000
95#define L1_SCRATCH_LENGTH 0x1000 95#define L1_SCRATCH_LENGTH 0x1000
96#endif
97 96
98#endif /* _MEM_MAP_527_H_ */ 97#endif /* _MEM_MAP_527_H_ */
diff --git a/include/asm-blackfin/mach-bf527/portmux.h b/include/asm-blackfin/mach-bf527/portmux.h
index dcf001adc63c..ae4d205bfcf5 100644
--- a/include/asm-blackfin/mach-bf527/portmux.h
+++ b/include/asm-blackfin/mach-bf527/portmux.h
@@ -1,6 +1,8 @@
1#ifndef _MACH_PORTMUX_H_ 1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_ 2#define _MACH_PORTMUX_H_
3 3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
4#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) 6#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
5#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) 7#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
6#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) 8#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
index f36ff5af1b91..98209d40abba 100644
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -7,9 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision X, March 23, 2007; ADSP-BF533 Blackfin Processor Anomaly List 10 * - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
11 * - Revision AB, March 23, 2007; ADSP-BF532 Blackfin Processor Anomaly List
12 * - Revision W, March 23, 2007; ADSP-BF531 Blackfin Processor Anomaly List
13 */ 11 */
14 12
15#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -17,7 +15,7 @@
17 15
18/* We do not support 0.1 or 0.2 silicon - sorry */ 16/* We do not support 0.1 or 0.2 silicon - sorry */
19#if __SILICON_REVISION__ < 3 17#if __SILICON_REVISION__ < 3
20# error Kernel will not work on BF533 silicon version 0.0, 0.1, or 0.2 18# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
21#endif 19#endif
22 20
23#if defined(__ADSPBF531__) 21#if defined(__ADSPBF531__)
@@ -251,6 +249,12 @@
251#define ANOMALY_05000192 (__SILICON_REVISION__ < 3) 249#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
252/* Internal Voltage Regulator may not start up */ 250/* Internal Voltage Regulator may not start up */
253#define ANOMALY_05000206 (__SILICON_REVISION__ < 3) 251#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
252/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
253#define ANOMALY_05000357 (1)
254/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
255#define ANOMALY_05000366 (1)
256/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
257#define ANOMALY_05000371 (1)
254 258
255/* Anomalies that don't exist on this proc */ 259/* Anomalies that don't exist on this proc */
256#define ANOMALY_05000266 (0) 260#define ANOMALY_05000266 (0)
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index 69b9f8e120e9..7871d4313f49 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -111,7 +111,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
111 } 111 }
112 if (uart->rts_pin >= 0) { 112 if (uart->rts_pin >= 0) {
113 gpio_request(uart->rts_pin, DRIVER_NAME); 113 gpio_request(uart->rts_pin, DRIVER_NAME);
114 gpio_direction_input(uart->rts_pin); 114 gpio_direction_input(uart->rts_pin, 0);
115 } 115 }
116#endif 116#endif
117} 117}
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
index 452fb825d891..832e6f6122da 100644
--- a/include/asm-blackfin/mach-bf533/irq.h
+++ b/include/asm-blackfin/mach-bf533/irq.h
@@ -130,11 +130,7 @@ Core Emulation **
130 130
131#define GPIO_IRQ_BASE IRQ_PF0 131#define GPIO_IRQ_BASE IRQ_PF0
132 132
133#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
134#define NR_IRQS (IRQ_PF15+1) 133#define NR_IRQS (IRQ_PF15+1)
135#else
136#define NR_IRQS SYS_IRQS
137#endif
138 134
139#define IVG7 7 135#define IVG7 7
140#define IVG8 8 136#define IVG8 8
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h
index 94d8c4062eb7..bd30b6f3be00 100644
--- a/include/asm-blackfin/mach-bf533/mem_map.h
+++ b/include/asm-blackfin/mach-bf533/mem_map.h
@@ -1,4 +1,3 @@
1
2/* 1/*
3 * File: include/asm-blackfin/mach-bf533/mem_map.h 2 * File: include/asm-blackfin/mach-bf533/mem_map.h
4 * Based on: 3 * Based on:
@@ -48,6 +47,7 @@
48/* Boot ROM Memory */ 47/* Boot ROM Memory */
49 48
50#define BOOT_ROM_START 0xEF000000 49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x400
51 51
52/* Level 1 Memory */ 52/* Level 1 Memory */
53 53
@@ -160,9 +160,7 @@
160 160
161/* Scratch Pad Memory */ 161/* Scratch Pad Memory */
162 162
163#if defined(CONFIG_BF533) || defined(CONFIG_BF532) || defined(CONFIG_BF531)
164#define L1_SCRATCH_START 0xFFB00000 163#define L1_SCRATCH_START 0xFFB00000
165#define L1_SCRATCH_LENGTH 0x1000 164#define L1_SCRATCH_LENGTH 0x1000
166#endif
167 165
168#endif /* _MEM_MAP_533_H_ */ 166#endif /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h
index b88d7a03ee3e..685a2651dcda 100644
--- a/include/asm-blackfin/mach-bf533/portmux.h
+++ b/include/asm-blackfin/mach-bf533/portmux.h
@@ -1,6 +1,8 @@
1#ifndef _MACH_PORTMUX_H_ 1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_ 2#define _MACH_PORTMUX_H_
3 3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
4#define P_PPI0_CLK (P_DONTCARE) 6#define P_PPI0_CLK (P_DONTCARE)
5#define P_PPI0_FS1 (P_DONTCARE) 7#define P_PPI0_FS1 (P_DONTCARE)
6#define P_PPI0_FS2 (P_DONTCARE) 8#define P_PPI0_FS2 (P_DONTCARE)
@@ -42,7 +44,7 @@
42#define P_SPORT0_DRPRI (P_DONTCARE) 44#define P_SPORT0_DRPRI (P_DONTCARE)
43 45
44#define P_SPI0_MOSI (P_DONTCARE) 46#define P_SPI0_MOSI (P_DONTCARE)
45#define P_SPI0_MIS0 (P_DONTCARE) 47#define P_SPI0_MISO (P_DONTCARE)
46#define P_SPI0_SCK (P_DONTCARE) 48#define P_SPI0_SCK (P_DONTCARE)
47#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) 49#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
48#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) 50#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 2b66ecf489f7..746a794b3119 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -7,9 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List 10 * - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
11 * - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List
12 * - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List
13 */ 11 */
14 12
15#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -17,7 +15,7 @@
17 15
18/* We do not support 0.1 silicon - sorry */ 16/* We do not support 0.1 silicon - sorry */
19#if __SILICON_REVISION__ < 2 17#if __SILICON_REVISION__ < 2
20# error Kernel will not work on BF537 silicon version 0.0 or 0.1 18# error will not work on BF537 silicon version 0.0 or 0.1
21#endif 19#endif
22 20
23#if defined(__ADSPBF534__) 21#if defined(__ADSPBF534__)
@@ -44,6 +42,8 @@
44#define ANOMALY_05000122 (1) 42#define ANOMALY_05000122 (1)
45/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ 43/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
46#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) 44#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
45/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
46#define ANOMALY_05000167 (1)
47/* PPI_DELAY not functional in PPI modes with 0 frame syncs */ 47/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
48#define ANOMALY_05000180 (1) 48#define ANOMALY_05000180 (1)
49/* Instruction Cache Is Not Functional */ 49/* Instruction Cache Is Not Functional */
@@ -130,6 +130,12 @@
130#define ANOMALY_05000321 (__SILICON_REVISION__ < 3) 130#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
131/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ 131/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
132#define ANOMALY_05000322 (1) 132#define ANOMALY_05000322 (1)
133/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
134#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
135/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
136#define ANOMALY_05000357 (1)
137/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
138#define ANOMALY_05000359 (1)
133 139
134/* Anomalies that don't exist on this proc */ 140/* Anomalies that don't exist on this proc */
135#define ANOMALY_05000125 (0) 141#define ANOMALY_05000125 (0)
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
index 6fb328f5186a..86e45c379838 100644
--- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
@@ -146,7 +146,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
146 146
147 if (uart->rts_pin >= 0) { 147 if (uart->rts_pin >= 0) {
148 gpio_request(uart->rts_pin, DRIVER_NAME); 148 gpio_request(uart->rts_pin, DRIVER_NAME);
149 gpio_direction_output(uart->rts_pin); 149 gpio_direction_output(uart->rts_pin, 0);
150 } 150 }
151#endif 151#endif
152} 152}
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
index 36c44bc1a917..be6f2ff77f31 100644
--- a/include/asm-blackfin/mach-bf537/irq.h
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -162,11 +162,7 @@ Core Emulation **
162 162
163#define GPIO_IRQ_BASE IRQ_PF0 163#define GPIO_IRQ_BASE IRQ_PF0
164 164
165#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
166#define NR_IRQS (IRQ_PH15+1) 165#define NR_IRQS (IRQ_PH15+1)
167#else
168#define NR_IRQS (IRQ_UART1_ERROR+1)
169#endif
170 166
171#define IVG7 7 167#define IVG7 7
172#define IVG8 8 168#define IVG8 8
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h
index 18759e38eaae..5c6726d6f3b1 100644
--- a/include/asm-blackfin/mach-bf537/mem_map.h
+++ b/include/asm-blackfin/mach-bf537/mem_map.h
@@ -47,6 +47,7 @@
47/* Boot ROM Memory */ 47/* Boot ROM Memory */
48 48
49#define BOOT_ROM_START 0xEF000000 49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x800
50 51
51/* Level 1 Memory */ 52/* Level 1 Memory */
52 53
@@ -167,9 +168,7 @@
167 168
168/* Scratch Pad Memory */ 169/* Scratch Pad Memory */
169 170
170#if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
171#define L1_SCRATCH_START 0xFFB00000 171#define L1_SCRATCH_START 0xFFB00000
172#define L1_SCRATCH_LENGTH 0x1000 172#define L1_SCRATCH_LENGTH 0x1000
173#endif
174 173
175#endif /* _MEM_MAP_537_H_ */ 174#endif /* _MEM_MAP_537_H_ */
diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h
index 5a3f7d3bf73d..78fee6e0f237 100644
--- a/include/asm-blackfin/mach-bf537/portmux.h
+++ b/include/asm-blackfin/mach-bf537/portmux.h
@@ -1,6 +1,8 @@
1#ifndef _MACH_PORTMUX_H_ 1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_ 2#define _MACH_PORTMUX_H_
3 3
4#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
5
4#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) 6#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
5#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) 7#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
6#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) 8#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index c5b63759cdee..850dc12eb7f2 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List 10 * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -26,47 +26,59 @@
26/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 26/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
27#define ANOMALY_05000272 (1) 27#define ANOMALY_05000272 (1)
28/* False Hardware Error Exception when ISR context is not restored */ 28/* False Hardware Error Exception when ISR context is not restored */
29#define ANOMALY_05000281 (1) 29#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
30/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ 30/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
31#define ANOMALY_05000304 (1) 31#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
32/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 32/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
33#define ANOMALY_05000310 (1) 33#define ANOMALY_05000310 (1)
34/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 34/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
35#define ANOMALY_05000312 (1) 35#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
36/* TWI Slave Boot Mode Is Not Functional */ 36/* TWI Slave Boot Mode Is Not Functional */
37#define ANOMALY_05000324 (1) 37#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
38/* External FIFO Boot Mode Is Not Functional */ 38/* External FIFO Boot Mode Is Not Functional */
39#define ANOMALY_05000325 (1) 39#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
40/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ 40/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
41#define ANOMALY_05000327 (1) 41#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
42/* Incorrect Access of OTP_STATUS During otp_write() Function */ 42/* Incorrect Access of OTP_STATUS During otp_write() Function */
43#define ANOMALY_05000328 (1) 43#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
44/* Synchronous Burst Flash Boot Mode Is Not Functional */ 44/* Synchronous Burst Flash Boot Mode Is Not Functional */
45#define ANOMALY_05000329 (1) 45#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
46/* Host DMA Boot Mode Is Not Functional */ 46/* Host DMA Boot Mode Is Not Functional */
47#define ANOMALY_05000330 (1) 47#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
48/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ 48/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
49#define ANOMALY_05000334 (1) 49#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
50/* Inadequate Rotary Debounce Logic Duration */ 50/* Inadequate Rotary Debounce Logic Duration */
51#define ANOMALY_05000335 (1) 51#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
52/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ 52/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
53#define ANOMALY_05000336 (1) 53#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
54/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ 54/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
55#define ANOMALY_05000337 (1) 55#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
56/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ 56/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
57#define ANOMALY_05000338 (1) 57#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
58/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ 58/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
59#define ANOMALY_05000340 (1) 59#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
60/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ 60/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
61#define ANOMALY_05000344 (1) 61#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
62/* USB Calibration Value Is Not Intialized */ 62/* USB Calibration Value Is Not Intialized */
63#define ANOMALY_05000346 (1) 63#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
64/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ 64/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
65#define ANOMALY_05000347 (1) 65#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
66/* Data Lost when Core Reads SDH Data FIFO */ 66/* Data Lost when Core Reads SDH Data FIFO */
67#define ANOMALY_05000349 (1) 67#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
68/* PLL Status Register Is Inaccurate */ 68/* PLL Status Register Is Inaccurate */
69#define ANOMALY_05000351 (1) 69#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
70/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
71#define ANOMALY_05000357 (1)
72/* External Memory Read Access Hangs Core With PLL Bypass */
73#define ANOMALY_05000360 (1)
74/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
75#define ANOMALY_05000365 (1)
76/* Addressing Conflict between Boot ROM and Asynchronous Memory */
77#define ANOMALY_05000369 (1)
78/* Mobile DDR Operation Not Functional */
79#define ANOMALY_05000377 (1)
80/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
81#define ANOMALY_05000378 (1)
70 82
71/* Anomalies that don't exist on this proc */ 83/* Anomalies that don't exist on this proc */
72#define ANOMALY_05000125 (0) 84#define ANOMALY_05000125 (0)
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
index 7e6d349beb08..e748588e8930 100644
--- a/include/asm-blackfin/mach-bf548/bf548.h
+++ b/include/asm-blackfin/mach-bf548/bf548.h
@@ -106,24 +106,22 @@
106 106
107#define AMGCTLVAL (V_AMBEN | V_AMCKEN) 107#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
108 108
109#ifdef CONFIG_BF542 109#if defined(CONFIG_BF542)
110#define CPU "BF542" 110# define CPU "BF542"
111#define CPUID 0x027c8000 111# define CPUID 0x027c8000
112#endif 112#elif defined(CONFIG_BF544)
113#ifdef CONFIG_BF544 113# define CPU "BF544"
114#define CPU "BF544" 114# define CPUID 0x027c8000
115#define CPUID 0x027c8000 115#elif defined(CONFIG_BF547)
116#endif 116# define CPU "BF547"
117#ifdef CONFIG_BF548 117#elif defined(CONFIG_BF548)
118#define CPU "BF548" 118# define CPU "BF548"
119#define CPUID 0x027c6000 119# define CPUID 0x027c6000
120#endif 120#elif defined(CONFIG_BF549)
121#ifdef CONFIG_BF549 121# define CPU "BF549"
122#define CPU "BF549" 122#else
123#endif 123# define CPU "UNKNOWN"
124#ifndef CPU 124# define CPUID 0x0
125#define CPU "UNKNOWN"
126#define CPUID 0x0
127#endif 125#endif
128 126
129#endif /* __MACH_BF48_H__ */ 127#endif /* __MACH_BF48_H__ */
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
index f21a1620e6bd..3770aa38ee9f 100644
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -186,7 +186,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
186 186
187 if (uart->rts_pin >= 0) { 187 if (uart->rts_pin >= 0) {
188 gpio_request(uart->rts_pin, DRIVER_NAME); 188 gpio_request(uart->rts_pin, DRIVER_NAME);
189 gpio_direction_output(uart->rts_pin); 189 gpio_direction_output(uart->rts_pin, 0);
190 } 190 }
191#endif 191#endif
192} 192}
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index aefab3f618c1..19ddcd83c71f 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -244,39 +244,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
244#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) 244#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
245#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) 245#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
246 246
247#define bfin_read_TWI_CLKDIV() bfin_read16(TWI0_CLKDIV)
248#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
249#define bfin_read_TWI_CONTROL() bfin_read16(TWI0_CONTROL)
250#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
251#define bfin_read_TWI_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
252#define bfin_write_TWI_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
253#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
254#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
255#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
256#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
257#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI0_MASTER_CTRL)
258#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTRL, val)
259#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
260#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
261#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
262#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
263#define bfin_read_TWI_INT_STAT() bfin_read16(TWI0_INT_STAT)
264#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
265#define bfin_read_TWI_INT_MASK() bfin_read16(TWI0_INT_MASK)
266#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
267#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI0_FIFO_CTRL)
268#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTRL, val)
269#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
270#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
271#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
272#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
273#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
274#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
275#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
276#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
277#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
278#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
279
280/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ 247/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
281 248
282/* SPORT1 Registers */ 249/* SPORT1 Registers */
diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h
index 32d07130200c..a7c809f29ede 100644
--- a/include/asm-blackfin/mach-bf548/defBF542.h
+++ b/include/asm-blackfin/mach-bf548/defBF542.h
@@ -432,8 +432,8 @@
432 432
433#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ 433#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
434#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ 434#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
435#define CMD_TIMEOUT 0x4 /* CMD Time Out */ 435#define CMD_TIME_OUT 0x4 /* CMD Time Out */
436#define DAT_TIMEOUT 0x8 /* Data Time Out */ 436#define DAT_TIME_OUT 0x8 /* Data Time Out */
437#define TX_UNDERRUN 0x10 /* Transmit Underrun */ 437#define TX_UNDERRUN 0x10 /* Transmit Underrun */
438#define RX_OVERRUN 0x20 /* Receive Overrun */ 438#define RX_OVERRUN 0x20 /* Receive Overrun */
439#define CMD_RESP_END 0x40 /* CMD Response End */ 439#define CMD_RESP_END 0x40 /* CMD Response End */
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h
index 760307e34b9e..b8b9870e2697 100644
--- a/include/asm-blackfin/mach-bf548/defBF544.h
+++ b/include/asm-blackfin/mach-bf548/defBF544.h
@@ -645,7 +645,7 @@
645 645
646/* Bit masks for HOST_STATUS */ 646/* Bit masks for HOST_STATUS */
647 647
648#define READY 0x1 /* DMA Ready */ 648#define DMA_READY 0x1 /* DMA Ready */
649#define FIFOFULL 0x2 /* FIFO Full */ 649#define FIFOFULL 0x2 /* FIFO Full */
650#define FIFOEMPTY 0x4 /* FIFO Empty */ 650#define FIFOEMPTY 0x4 /* FIFO Empty */
651#define COMPLETE 0x8 /* DMA Complete */ 651#define COMPLETE 0x8 /* DMA Complete */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
index 70af33c963b0..e46f56891e6a 100644
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -1007,7 +1007,7 @@
1007 1007
1008/* Bit masks for HOST_STATUS */ 1008/* Bit masks for HOST_STATUS */
1009 1009
1010#define READY 0x1 /* DMA Ready */ 1010#define DMA_READY 0x1 /* DMA Ready */
1011#define FIFOFULL 0x2 /* FIFO Full */ 1011#define FIFOFULL 0x2 /* FIFO Full */
1012#define FIFOEMPTY 0x4 /* FIFO Empty */ 1012#define FIFOEMPTY 0x4 /* FIFO Empty */
1013#define COMPLETE 0x8 /* DMA Complete */ 1013#define COMPLETE 0x8 /* DMA Complete */
@@ -1095,8 +1095,8 @@
1095 1095
1096#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ 1096#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
1097#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ 1097#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
1098#define CMD_TIMEOUT 0x4 /* CMD Time Out */ 1098#define CMD_TIME_OUT 0x4 /* CMD Time Out */
1099#define DAT_TIMEOUT 0x8 /* Data Time Out */ 1099#define DAT_TIME_OUT 0x8 /* Data Time Out */
1100#define TX_UNDERRUN 0x10 /* Transmit Underrun */ 1100#define TX_UNDERRUN 0x10 /* Transmit Underrun */
1101#define RX_OVERRUN 0x20 /* Receive Overrun */ 1101#define RX_OVERRUN 0x20 /* Receive Overrun */
1102#define CMD_RESP_END 0x40 /* CMD Response End */ 1102#define CMD_RESP_END 0x40 /* CMD Response End */
diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h
index 4e46d657e50e..fcb72b41e007 100644
--- a/include/asm-blackfin/mach-bf548/defBF549.h
+++ b/include/asm-blackfin/mach-bf548/defBF549.h
@@ -1671,7 +1671,7 @@
1671/* Bit masks for MXVR_DMAx_CONFIG */ 1671/* Bit masks for MXVR_DMAx_CONFIG */
1672 1672
1673#define MDMAEN 0x1 /* DMA Channel Enable */ 1673#define MDMAEN 0x1 /* DMA Channel Enable */
1674#define DD 0x2 /* DMA Channel Direction */ 1674#define DMADD 0x2 /* DMA Channel Direction */
1675#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ 1675#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */
1676#define LCHAN 0x3c0 /* DMA Channel Logical Channel */ 1676#define LCHAN 0x3c0 /* DMA Channel Logical Channel */
1677#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ 1677#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index 1d365c844ffe..08f90c21fe8a 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -1644,8 +1644,25 @@
1644#define RESTART 0x20 /* Work Unit Transitions */ 1644#define RESTART 0x20 /* Work Unit Transitions */
1645#define DI_SEL 0x40 /* Data Interrupt Timing Select */ 1645#define DI_SEL 0x40 /* Data Interrupt Timing Select */
1646#define DI_EN 0x80 /* Data Interrupt Enable */ 1646#define DI_EN 0x80 /* Data Interrupt Enable */
1647
1647#define NDSIZE 0xf00 /* Flex Descriptor Size */ 1648#define NDSIZE 0xf00 /* Flex Descriptor Size */
1649#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1650#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1651#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1652#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1653#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1654#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1655#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1656#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1657#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1658#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1659
1648#define DMAFLOW 0xf000 /* Next Operation */ 1660#define DMAFLOW 0xf000 /* Next Operation */
1661#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1662#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1663#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1664#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1665#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1649 1666
1650/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ 1667/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1651 1668
@@ -1755,17 +1772,36 @@
1755#define TRP 0x3c0000 /* Pre charge-to-active command period */ 1772#define TRP 0x3c0000 /* Pre charge-to-active command period */
1756#define TRAS 0x3c00000 /* Min Active-to-pre charge time */ 1773#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
1757#define TRC 0x3c000000 /* Active-to-active time */ 1774#define TRC 0x3c000000 /* Active-to-active time */
1775#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */
1776#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */
1777#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */
1778#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */
1779#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */
1758 1780
1759/* Bit masks for EBIU_DDRCTL1 */ 1781/* Bit masks for EBIU_DDRCTL1 */
1760 1782
1761#define TRCD 0xf /* Active-to-Read/write delay */ 1783#define TRCD 0xf /* Active-to-Read/write delay */
1762#define MRD 0xf0 /* Mode register set to active */ 1784#define TMRD 0xf0 /* Mode register set to active */
1763#define TWR 0x300 /* Write Recovery time */ 1785#define TWR 0x300 /* Write Recovery time */
1764#define DDRDATWIDTH 0x3000 /* DDR data width */ 1786#define DDRDATWIDTH 0x3000 /* DDR data width */
1765#define EXTBANKS 0xc000 /* External banks */ 1787#define EXTBANKS 0xc000 /* External banks */
1766#define DDRDEVWIDTH 0x30000 /* DDR device width */ 1788#define DDRDEVWIDTH 0x30000 /* DDR device width */
1767#define DDRDEVSIZE 0xc0000 /* DDR device size */ 1789#define DDRDEVSIZE 0xc0000 /* DDR device size */
1768#define TWWTR 0xf0000000 /* Write-to-read delay */ 1790#define TWTR 0xf0000000 /* Write-to-read delay */
1791#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */
1792#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */
1793#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */
1794#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */
1795#define DDR_DATWIDTH 0x2000 /* DDR data width */
1796#define EXTBANK_1 0 /* 1 external bank */
1797#define EXTBANK_2 0x4000 /* 2 external banks */
1798#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */
1799#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */
1800#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */
1801#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */
1802#define DEVWD_4 0 /* DDR Device Width = 4 Bits */
1803#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */
1804#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */
1769 1805
1770/* Bit masks for EBIU_DDRCTL2 */ 1806/* Bit masks for EBIU_DDRCTL2 */
1771 1807
@@ -1773,6 +1809,10 @@
1773#define CASLATENCY 0x70 /* CAS latency */ 1809#define CASLATENCY 0x70 /* CAS latency */
1774#define DLLRESET 0x100 /* DLL Reset */ 1810#define DLLRESET 0x100 /* DLL Reset */
1775#define REGE 0x1000 /* Register mode enable */ 1811#define REGE 0x1000 /* Register mode enable */
1812#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */
1813#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */
1814#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */
1815#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */
1776 1816
1777/* Bit masks for EBIU_DDRCTL3 */ 1817/* Bit masks for EBIU_DDRCTL3 */
1778 1818
@@ -2240,6 +2280,10 @@
2240 2280
2241#define CSEL 0x30 /* Core Select */ 2281#define CSEL 0x30 /* Core Select */
2242#define SSEL 0xf /* System Select */ 2282#define SSEL 0xf /* System Select */
2283#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
2284#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
2285#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
2286#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
2243 2287
2244/* Bit masks for PLL_CTL */ 2288/* Bit masks for PLL_CTL */
2245 2289
@@ -2252,6 +2296,13 @@
2252#define PLL_OFF 0x2 /* Disable PLL */ 2296#define PLL_OFF 0x2 /* Disable PLL */
2253#define DF 0x1 /* Divide Frequency */ 2297#define DF 0x1 /* Divide Frequency */
2254 2298
2299/* SWRST Masks */
2300#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
2301#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
2302#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
2303#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
2304#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
2305
2255/* Bit masks for PLL_STAT */ 2306/* Bit masks for PLL_STAT */
2256 2307
2257#define PLL_LOCKED 0x20 /* PLL Locked Status */ 2308#define PLL_LOCKED 0x20 /* PLL Locked Status */
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
index 3b08cf9bd6f3..c34507a3f1df 100644
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -88,7 +88,7 @@ Events (highest priority) EMU 0
88#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ 88#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
89#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ 89#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
90#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ 90#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
91#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ 91#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
92#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ 92#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
93#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ 93#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
94#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ 94#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
@@ -338,11 +338,7 @@ Events (highest priority) EMU 0
338 338
339#define GPIO_IRQ_BASE IRQ_PA0 339#define GPIO_IRQ_BASE IRQ_PA0
340 340
341#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
342#define NR_IRQS (IRQ_PJ15+1) 341#define NR_IRQS (IRQ_PJ15+1)
343#else
344#define NR_IRQS (SYS_IRQS+1)
345#endif
346 342
347/* For compatibility reasons with existing code */ 343/* For compatibility reasons with existing code */
348 344
@@ -410,7 +406,7 @@ Events (highest priority) EMU 0
410#define IRQ_PINT1_POS 16 406#define IRQ_PINT1_POS 16
411#define IRQ_MDMAS0_POS 20 407#define IRQ_MDMAS0_POS 20
412#define IRQ_MDMAS1_POS 24 408#define IRQ_MDMAS1_POS 24
413#define IRQ_WATCHDOG_POS 28 409#define IRQ_WATCH_POS 28
414 410
415/* IAR3 BIT FIELDS */ 411/* IAR3 BIT FIELDS */
416#define IRQ_DMAC1_ERR_POS 0 412#define IRQ_DMAC1_ERR_POS 0
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
index 0cb279e973d7..befc2903d5a5 100644
--- a/include/asm-blackfin/mach-bf548/mem_init.h
+++ b/include/asm-blackfin/mach-bf548/mem_init.h
@@ -28,8 +28,68 @@
28 * If not, write to the Free Software Foundation, 28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */ 30 */
31#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
32
33#if (CONFIG_MEM_MT46V32M16_6T)
34#define DDR_SIZE DEVSZ_512
35#define DDR_WIDTH DEVWD_16
36
37#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
38#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
39#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
40#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
41#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800))
42
43#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
44#define DDR_tWTR DDR_TWTR(1)
45#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
46#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
47#endif
48
49#if (CONFIG_MEM_MT46V32M16_5B)
50#define DDR_SIZE DEVSZ_512
51#define DDR_WIDTH DEVWD_16
52
53#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
54#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
55#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
56#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
57#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800))
58
59#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
60#define DDR_tWTR DDR_TWTR(2)
61#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
62#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
63#endif
64
65#if (CONFIG_MEM_GENERIC_BOARD)
66#define DDR_SIZE DEVSZ_512
67#define DDR_WIDTH DEVWD_16
68
69#define DDR_tRCD DDR_TRCD(3)
70#define DDR_tWTR DDR_TWTR(2)
71#define DDR_tWR DDR_TWR(2)
72#define DDR_tMRD DDR_TMRD(2)
73#define DDR_tRP DDR_TRP(3)
74#define DDR_tRAS DDR_TRAS(7)
75#define DDR_tRC DDR_TRC(10)
76#define DDR_tRFC DDR_TRFC(12)
77#define DDR_tREFI DDR_TREFI(1288)
78#endif
79
80#if (CONFIG_SCLK_HZ <= 133333333)
81#define DDR_CL CL_2
82#elif (CONFIG_SCLK_HZ <= 166666666)
83#define DDR_CL CL_2_5
84#else
85#define DDR_CL CL_3
86#endif
87
88#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
89#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
90 | DDR_tMRD | DDR_tWR | DDR_tRCD)
91#define mem_DDRCTL2 DDR_CL
31 92
32#if (CONFIG_MEM_MT46V32M16)
33 93
34#if defined CONFIG_CLKIN_HALF 94#if defined CONFIG_CLKIN_HALF
35#define CLKIN_HALF 1 95#define CLKIN_HALF 1
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h
index ec1597e31831..f99f47bc3a07 100644
--- a/include/asm-blackfin/mach-bf548/mem_map.h
+++ b/include/asm-blackfin/mach-bf548/mem_map.h
@@ -47,6 +47,12 @@
47/* Boot ROM Memory */ 47/* Boot ROM Memory */
48 48
49#define BOOT_ROM_START 0xEF000000 49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x1000
51
52/* L1 Instruction ROM */
53
54#define L1_ROM_START 0xFFA14000
55#define L1_ROM_LENGTH 0x10000
50 56
51/* Level 1 Memory */ 57/* Level 1 Memory */
52 58
@@ -87,11 +93,19 @@
87#define BFIN_DSUPBANKS 0 93#define BFIN_DSUPBANKS 0
88#endif /*CONFIG_BFIN_DCACHE*/ 94#endif /*CONFIG_BFIN_DCACHE*/
89 95
96/* Level 2 Memory */
97#if !defined(CONFIG_BF542)
98# define L2_START 0xFEB00000
99# if defined(CONFIG_BF544)
100# define L2_LENGTH 0x10000
101# else
102# define L2_LENGTH 0x20000
103# endif
104#endif
105
90/* Scratch Pad Memory */ 106/* Scratch Pad Memory */
91 107
92#if defined(CONFIG_BF54x)
93#define L1_SCRATCH_START 0xFFB00000 108#define L1_SCRATCH_START 0xFFB00000
94#define L1_SCRATCH_LENGTH 0x1000 109#define L1_SCRATCH_LENGTH 0x1000
95#endif
96 110
97#endif/* _MEM_MAP_548_H_ */ 111#endif/* _MEM_MAP_548_H_ */
diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h
index b382deb501a7..8177a567dcdb 100644
--- a/include/asm-blackfin/mach-bf548/portmux.h
+++ b/include/asm-blackfin/mach-bf548/portmux.h
@@ -1,6 +1,8 @@
1#ifndef _MACH_PORTMUX_H_ 1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_ 2#define _MACH_PORTMUX_H_
3 3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
4#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) 6#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
5#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) 7#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
6#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) 8#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
@@ -267,4 +269,18 @@
267#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0)) 269#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
268#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0)) 270#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
269 271
272
273#define P_NAND_D0 (P_DONTCARE)
274#define P_NAND_D1 (P_DONTCARE)
275#define P_NAND_D2 (P_DONTCARE)
276#define P_NAND_D3 (P_DONTCARE)
277#define P_NAND_D4 (P_DONTCARE)
278#define P_NAND_D5 (P_DONTCARE)
279#define P_NAND_D6 (P_DONTCARE)
280#define P_NAND_D7 (P_DONTCARE)
281#define P_NAND_WE (P_DONTCARE)
282#define P_NAND_RE (P_DONTCARE)
283#define P_NAND_CLE (P_DONTCARE)
284#define P_NAND_ALE (P_DONTCARE)
285
270#endif /* _MACH_PORTMUX_H_ */ 286#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index bed956456884..0c1d46193939 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision N, March 28, 2007; ADSP-BF561 Silicon Anomaly List 10 * - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -15,7 +15,7 @@
15 15
16/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */ 16/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
17#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4 17#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
18# error Kernel will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 18# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
19#endif 19#endif
20 20
21/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ 21/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
@@ -208,6 +208,8 @@
208#define ANOMALY_05000275 (__SILICON_REVISION__ > 2) 208#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
209/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ 209/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
210#define ANOMALY_05000276 (__SILICON_REVISION__ < 5) 210#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
211/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
212#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
211/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 213/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
212#define ANOMALY_05000278 (__SILICON_REVISION__ < 5) 214#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
213/* False Hardware Error Exception When ISR Context Is Not Restored */ 215/* False Hardware Error Exception When ISR Context Is Not Restored */
@@ -246,6 +248,18 @@
246#define ANOMALY_05000332 (__SILICON_REVISION__ < 5) 248#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
247/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ 249/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
248#define ANOMALY_05000333 (__SILICON_REVISION__ < 5) 250#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
251/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
252#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
253/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
254#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
255/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
256#define ANOMALY_05000357 (1)
257/* Conflicting Column Address Widths Causes SDRAM Errors */
258#define ANOMALY_05000362 (1)
259/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
260#define ANOMALY_05000366 (1)
261/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
262#define ANOMALY_05000371 (1)
249 263
250/* Anomalies that don't exist on this proc */ 264/* Anomalies that don't exist on this proc */
251#define ANOMALY_05000158 (0) 265#define ANOMALY_05000158 (0)
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
index 17e1d5dcef02..3ef9e5f36136 100644
--- a/include/asm-blackfin/mach-bf561/bf561.h
+++ b/include/asm-blackfin/mach-bf561/bf561.h
@@ -33,25 +33,6 @@
33#define SUPPORTED_REVID 0x3 33#define SUPPORTED_REVID 0x3
34 34
35#define OFFSET_(x) ((x) & 0x0000FFFF) 35#define OFFSET_(x) ((x) & 0x0000FFFF)
36#define L1_ISRAM 0xFFA00000
37#define L1_ISRAM_END 0xFFA04000
38#define DATA_BANKA_SRAM 0xFF800000
39#define DATA_BANKA_SRAM_END 0xFF804000
40#define DATA_BANKB_SRAM 0xFF900000
41#define DATA_BANKB_SRAM_END 0xFF904000
42#define L1_DSRAMA 0xFF800000
43#define L1_DSRAMA_END 0xFF804000
44#define L1_DSRAMB 0xFF900000
45#define L1_DSRAMB_END 0xFF904000
46#define L2_SRAM 0xFEB00000
47#define L2_SRAM_END 0xFEB20000
48#define AMB_FLASH 0x20000000
49#define AMB_FLASH_END 0x21000000
50#define AMB_FLASH_LENGTH 0x01000000
51#define L1_ISRAM_LENGTH 0x4000
52#define L1_DSRAMA_LENGTH 0x4000
53#define L1_DSRAMB_LENGTH 0x4000
54#define L2_SRAM_LENGTH 0x20000
55 36
56/*some misc defines*/ 37/*some misc defines*/
57#define IMASK_IVG15 0x8000 38#define IMASK_IVG15 0x8000
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
index 69b9f8e120e9..7871d4313f49 100644
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -111,7 +111,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
111 } 111 }
112 if (uart->rts_pin >= 0) { 112 if (uart->rts_pin >= 0) {
113 gpio_request(uart->rts_pin, DRIVER_NAME); 113 gpio_request(uart->rts_pin, DRIVER_NAME);
114 gpio_direction_input(uart->rts_pin); 114 gpio_direction_input(uart->rts_pin, 0);
115 } 115 }
116#endif 116#endif
117} 117}
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index bf7dc4e00065..c3c0eb13c819 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -55,6 +55,10 @@
55/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ 55/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
56#define SWRST SICA_SWRST 56#define SWRST SICA_SWRST
57#define SYSCR SICA_SYSCR 57#define SYSCR SICA_SYSCR
58#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
59#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
60#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
61#define RESET_SOFTWARE (SWRST_OCCURRED)
58 62
59/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 63/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
60#define SICA_SWRST 0xFFC00100 /* Software Reset register */ 64#define SICA_SWRST 0xFFC00100 /* Software Reset register */
@@ -874,12 +878,14 @@
874#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ 878#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
875 879
876/* SWRST Mask */ 880/* SWRST Mask */
877#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ 881#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */
878#define SWRST_DBL_FAULT_B 0x00000800 /* SWRST Core B Double Fault */ 882#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */
879#define SWRST_DBL_FAULT_A 0x00001000 /* SWRST Core A Double Fault */ 883#define DOUBLE_FAULT_B 0x0010 /* Core B Double Fault Causes Reset */
880#define SWRST_WDT_B 0x00002000 /* SWRST Watchdog B */ 884#define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */
881#define SWRST_WDT_A 0x00004000 /* SWRST Watchdog A */ 885#define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */
882#define SWRST_OCCURRED 0x00008000 /* SWRST Status */ 886#define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */
887#define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */
888#define SWRST_OCCURRED 0x8000 /* SWRST Status */
883 889
884/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ 890/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
885 891
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h
index 12789927db3d..83f0383957d2 100644
--- a/include/asm-blackfin/mach-bf561/irq.h
+++ b/include/asm-blackfin/mach-bf561/irq.h
@@ -291,11 +291,7 @@
291 291
292#define GPIO_IRQ_BASE IRQ_PF0 292#define GPIO_IRQ_BASE IRQ_PF0
293 293
294#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
295#define NR_IRQS (IRQ_PF47 + 1) 294#define NR_IRQS (IRQ_PF47 + 1)
296#else
297#define NR_IRQS SYS_IRQS
298#endif
299 295
300#define IVG7 7 296#define IVG7 7
301#define IVG8 8 297#define IVG8 8
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h
index f7ac09cf2c3d..c26d8486cc4b 100644
--- a/include/asm-blackfin/mach-bf561/mem_map.h
+++ b/include/asm-blackfin/mach-bf561/mem_map.h
@@ -19,6 +19,11 @@
19#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ 19#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
20#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ 20#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
21 21
22/* Boot ROM Memory */
23
24#define BOOT_ROM_START 0xEF000000
25#define BOOT_ROM_LENGTH 0x800
26
22/* Level 1 Memory */ 27/* Level 1 Memory */
23 28
24#ifdef CONFIG_BFIN_ICACHE 29#ifdef CONFIG_BFIN_ICACHE
@@ -67,9 +72,7 @@
67 72
68/* Scratch Pad Memory */ 73/* Scratch Pad Memory */
69 74
70#if defined(CONFIG_BF561)
71#define L1_SCRATCH_START 0xFFB00000 75#define L1_SCRATCH_START 0xFFB00000
72#define L1_SCRATCH_LENGTH 0x1000 76#define L1_SCRATCH_LENGTH 0x1000
73#endif
74 77
75#endif /* _MEM_MAP_533_H_ */ 78#endif /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h
index 132ad31665e3..a6ee8206efb6 100644
--- a/include/asm-blackfin/mach-bf561/portmux.h
+++ b/include/asm-blackfin/mach-bf561/portmux.h
@@ -1,6 +1,8 @@
1#ifndef _MACH_PORTMUX_H_ 1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_ 2#define _MACH_PORTMUX_H_
3 3
4#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
5
4#define P_PPI0_CLK (P_DONTCARE) 6#define P_PPI0_CLK (P_DONTCARE)
5#define P_PPI0_FS1 (P_DONTCARE) 7#define P_PPI0_FS1 (P_DONTCARE)
6#define P_PPI0_FS2 (P_DONTCARE) 8#define P_PPI0_FS2 (P_DONTCARE)
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
index c1d8c4a78fcf..e8967f6124f7 100644
--- a/include/asm-blackfin/mach-common/def_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -46,7 +46,7 @@
46#endif 46#endif
47 47
48#define bfin_read8(addr) ({ \ 48#define bfin_read8(addr) ({ \
49 uint8_t __v; \ 49 uint32_t __v; \
50 __asm__ __volatile__( \ 50 __asm__ __volatile__( \
51 NOP_PAD_ANOMALY_05000198 \ 51 NOP_PAD_ANOMALY_05000198 \
52 "%0 = b[%1] (z);" \ 52 "%0 = b[%1] (z);" \
@@ -56,7 +56,7 @@
56 __v; }) 56 __v; })
57 57
58#define bfin_read16(addr) ({ \ 58#define bfin_read16(addr) ({ \
59 uint16_t __v; \ 59 uint32_t __v; \
60 __asm__ __volatile__( \ 60 __asm__ __volatile__( \
61 NOP_PAD_ANOMALY_05000198 \ 61 NOP_PAD_ANOMALY_05000198 \
62 "%0 = w[%1] (z);" \ 62 "%0 = w[%1] (z);" \
@@ -80,7 +80,7 @@
80 NOP_PAD_ANOMALY_05000198 \ 80 NOP_PAD_ANOMALY_05000198 \
81 "b[%0] = %1;" \ 81 "b[%0] = %1;" \
82 : \ 82 : \
83 : "a" (addr), "d" (val) \ 83 : "a" (addr), "d" ((uint8_t)(val)) \
84 : "memory" \ 84 : "memory" \
85 ) 85 )
86 86
@@ -89,7 +89,7 @@
89 NOP_PAD_ANOMALY_05000198 \ 89 NOP_PAD_ANOMALY_05000198 \
90 "w[%0] = %1;" \ 90 "w[%0] = %1;" \
91 : \ 91 : \
92 : "a" (addr), "d" (val) \ 92 : "a" (addr), "d" ((uint16_t)(val)) \
93 : "memory" \ 93 : "memory" \
94 ) 94 )
95 95
diff --git a/include/asm-blackfin/mmu.h b/include/asm-blackfin/mmu.h
index 11d52f1167d0..757e43906ed4 100644
--- a/include/asm-blackfin/mmu.h
+++ b/include/asm-blackfin/mmu.h
@@ -24,7 +24,9 @@ typedef struct {
24 unsigned long exec_fdpic_loadmap; 24 unsigned long exec_fdpic_loadmap;
25 unsigned long interp_fdpic_loadmap; 25 unsigned long interp_fdpic_loadmap;
26#endif 26#endif
27 27#ifdef CONFIG_MPU
28 unsigned long *page_rwx_mask;
29#endif
28} mm_context_t; 30} mm_context_t;
29 31
30#endif 32#endif
diff --git a/include/asm-blackfin/mmu_context.h b/include/asm-blackfin/mmu_context.h
index c5c71a6aaf19..b5eb67596ad5 100644
--- a/include/asm-blackfin/mmu_context.h
+++ b/include/asm-blackfin/mmu_context.h
@@ -30,9 +30,12 @@
30#ifndef __BLACKFIN_MMU_CONTEXT_H__ 30#ifndef __BLACKFIN_MMU_CONTEXT_H__
31#define __BLACKFIN_MMU_CONTEXT_H__ 31#define __BLACKFIN_MMU_CONTEXT_H__
32 32
33#include <linux/gfp.h>
34#include <linux/sched.h>
33#include <asm/setup.h> 35#include <asm/setup.h>
34#include <asm/page.h> 36#include <asm/page.h>
35#include <asm/pgalloc.h> 37#include <asm/pgalloc.h>
38#include <asm/cplbinit.h>
36 39
37extern void *current_l1_stack_save; 40extern void *current_l1_stack_save;
38extern int nr_l1stack_tasks; 41extern int nr_l1stack_tasks;
@@ -50,6 +53,12 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
50static inline int 53static inline int
51init_new_context(struct task_struct *tsk, struct mm_struct *mm) 54init_new_context(struct task_struct *tsk, struct mm_struct *mm)
52{ 55{
56#ifdef CONFIG_MPU
57 unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
58 mm->context.page_rwx_mask = (unsigned long *)p;
59 memset(mm->context.page_rwx_mask, 0,
60 page_mask_nelts * 3 * sizeof(long));
61#endif
53 return 0; 62 return 0;
54} 63}
55 64
@@ -73,6 +82,11 @@ static inline void destroy_context(struct mm_struct *mm)
73 sram_free(tmp->addr); 82 sram_free(tmp->addr);
74 kfree(tmp); 83 kfree(tmp);
75 } 84 }
85#ifdef CONFIG_MPU
86 if (current_rwx_mask == mm->context.page_rwx_mask)
87 current_rwx_mask = NULL;
88 free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
89#endif
76} 90}
77 91
78static inline unsigned long 92static inline unsigned long
@@ -106,9 +120,21 @@ activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
106 120
107#define deactivate_mm(tsk,mm) do { } while (0) 121#define deactivate_mm(tsk,mm) do { } while (0)
108 122
109static inline void activate_mm(struct mm_struct *prev_mm, 123#define activate_mm(prev, next) switch_mm(prev, next, NULL)
110 struct mm_struct *next_mm) 124
125static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
126 struct task_struct *tsk)
111{ 127{
128 if (prev_mm == next_mm)
129 return;
130#ifdef CONFIG_MPU
131 if (prev_mm->context.page_rwx_mask == current_rwx_mask) {
132 flush_switched_cplbs();
133 set_mask_dcplbs(next_mm->context.page_rwx_mask);
134 }
135#endif
136
137 /* L1 stack switching. */
112 if (!next_mm->context.l1_stack_save) 138 if (!next_mm->context.l1_stack_save)
113 return; 139 return;
114 if (next_mm->context.l1_stack_save == current_l1_stack_save) 140 if (next_mm->context.l1_stack_save == current_l1_stack_save)
@@ -120,10 +146,36 @@ static inline void activate_mm(struct mm_struct *prev_mm,
120 memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len); 146 memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
121} 147}
122 148
123static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 149#ifdef CONFIG_MPU
124 struct task_struct *tsk) 150static inline void protect_page(struct mm_struct *mm, unsigned long addr,
151 unsigned long flags)
152{
153 unsigned long *mask = mm->context.page_rwx_mask;
154 unsigned long page = addr >> 12;
155 unsigned long idx = page >> 5;
156 unsigned long bit = 1 << (page & 31);
157
158 if (flags & VM_MAYREAD)
159 mask[idx] |= bit;
160 else
161 mask[idx] &= ~bit;
162 mask += page_mask_nelts;
163 if (flags & VM_MAYWRITE)
164 mask[idx] |= bit;
165 else
166 mask[idx] &= ~bit;
167 mask += page_mask_nelts;
168 if (flags & VM_MAYEXEC)
169 mask[idx] |= bit;
170 else
171 mask[idx] &= ~bit;
172}
173
174static inline void update_protections(struct mm_struct *mm)
125{ 175{
126 activate_mm(prev, next); 176 flush_switched_cplbs();
177 set_mask_dcplbs(mm->context.page_rwx_mask);
127} 178}
179#endif
128 180
129#endif 181#endif
diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h
index 8bc86717021c..d5c9d1433781 100644
--- a/include/asm-blackfin/page.h
+++ b/include/asm-blackfin/page.h
@@ -11,8 +11,6 @@
11#endif 11#endif
12#define PAGE_MASK (~(PAGE_SIZE-1)) 12#define PAGE_MASK (~(PAGE_SIZE-1))
13 13
14#ifdef __KERNEL__
15
16#include <asm/setup.h> 14#include <asm/setup.h>
17 15
18#ifndef __ASSEMBLY__ 16#ifndef __ASSEMBLY__
@@ -88,6 +86,5 @@ extern unsigned long memory_end;
88#include <asm-generic/page.h> 86#include <asm-generic/page.h>
89 87
90#endif /* __ASSEMBLY__ */ 88#endif /* __ASSEMBLY__ */
91#endif /* __KERNEL__ */
92 89
93#endif /* _BLACKFIN_PAGE_H */ 90#endif /* _BLACKFIN_PAGE_H */
diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h
index 3b671d5fd70d..cbaff24b4b25 100644
--- a/include/asm-blackfin/page_offset.h
+++ b/include/asm-blackfin/page_offset.h
@@ -1,6 +1,6 @@
1 1
2/* This handles the memory map.. */ 2/* This handles the memory map.. */
3 3
4#ifdef CONFIG_BFIN 4#ifdef CONFIG_BLACKFIN
5#define PAGE_OFFSET_RAW 0x00000000 5#define PAGE_OFFSET_RAW 0x00000000
6#endif 6#endif
diff --git a/include/asm-blackfin/socket.h b/include/asm-blackfin/socket.h
index 5213c9652186..2ca702e44d47 100644
--- a/include/asm-blackfin/socket.h
+++ b/include/asm-blackfin/socket.h
@@ -50,4 +50,7 @@
50#define SO_PASSSEC 34 50#define SO_PASSSEC 34
51#define SO_TIMESTAMPNS 35 51#define SO_TIMESTAMPNS 35
52#define SCM_TIMESTAMPNS SO_TIMESTAMPNS 52#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
53
54#define SO_MARK 36
55
53#endif /* _ASM_SOCKET_H */ 56#endif /* _ASM_SOCKET_H */
diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
index e8ada91ab002..321f4d96e4ae 100644
--- a/include/asm-blackfin/string.h
+++ b/include/asm-blackfin/string.h
@@ -1,6 +1,8 @@
1#ifndef _BLACKFIN_STRING_H_ 1#ifndef _BLACKFIN_STRING_H_
2#define _BLACKFIN_STRING_H_ 2#define _BLACKFIN_STRING_H_
3 3
4#include <linux/types.h>
5
4#ifdef __KERNEL__ /* only set these up for kernel code */ 6#ifdef __KERNEL__ /* only set these up for kernel code */
5 7
6#define __HAVE_ARCH_STRCPY 8#define __HAVE_ARCH_STRCPY
diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h
index 4a927379ee1c..51494ef5bb41 100644
--- a/include/asm-blackfin/system.h
+++ b/include/asm-blackfin/system.h
@@ -183,55 +183,20 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
183 return tmp; 183 return tmp;
184} 184}
185 185
186#include <asm-generic/cmpxchg-local.h>
187
186/* 188/*
187 * Atomic compare and exchange. Compare OLD with MEM, if identical, 189 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
188 * store NEW in MEM. Return the initial value in MEM. Success is 190 * them available.
189 * indicated by comparing RETURN with OLD.
190 */ 191 */
191static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, 192#define cmpxchg_local(ptr, o, n) \
192 unsigned long new, int size) 193 ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
193{ 194 (unsigned long)(n), sizeof(*(ptr))))
194 unsigned long tmp = 0; 195#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
195 unsigned long flags = 0;
196
197 local_irq_save(flags);
198
199 switch (size) {
200 case 1:
201 __asm__ __volatile__
202 ("%0 = b%3 (z);\n\t"
203 "CC = %1 == %0;\n\t"
204 "IF !CC JUMP 1f;\n\t"
205 "b%3 = %2;\n\t"
206 "1:\n\t"
207 : "=&d" (tmp) : "d" (old), "d" (new), "m" (*__xg(ptr)) : "memory");
208 break;
209 case 2:
210 __asm__ __volatile__
211 ("%0 = w%3 (z);\n\t"
212 "CC = %1 == %0;\n\t"
213 "IF !CC JUMP 1f;\n\t"
214 "w%3 = %2;\n\t"
215 "1:\n\t"
216 : "=&d" (tmp) : "d" (old), "d" (new), "m" (*__xg(ptr)) : "memory");
217 break;
218 case 4:
219 __asm__ __volatile__
220 ("%0 = %3;\n\t"
221 "CC = %1 == %0;\n\t"
222 "IF !CC JUMP 1f;\n\t"
223 "%3 = %2;\n\t"
224 "1:\n\t"
225 : "=&d" (tmp) : "d" (old), "d" (new), "m" (*__xg(ptr)) : "memory");
226 break;
227 }
228 local_irq_restore(flags);
229 return tmp;
230}
231 196
232#define cmpxchg(ptr,o,n)\ 197#ifndef CONFIG_SMP
233 ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\ 198#include <asm-generic/cmpxchg.h>
234 (unsigned long)(n),sizeof(*(ptr)))) 199#endif
235 200
236#define prepare_to_switch() do { } while(0) 201#define prepare_to_switch() do { } while(0)
237 202
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
index fe365b1b7ca8..f0e5f940d9ca 100644
--- a/include/asm-blackfin/traps.h
+++ b/include/asm-blackfin/traps.h
@@ -45,31 +45,87 @@
45#define VEC_CPLB_I_M (44) 45#define VEC_CPLB_I_M (44)
46#define VEC_CPLB_I_MHIT (45) 46#define VEC_CPLB_I_MHIT (45)
47#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ 47#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
48/* The hardware reserves (63) for future use - we use it to tell our
49 * normal exception handling code we have a hardware error
50 */
51#define VEC_HWERR (63)
48 52
49#ifndef __ASSEMBLY__ 53#ifndef __ASSEMBLY__
50 54
51#define HWC_x2 "System MMR Error\nAn error occurred due to an invalid access to an System MMR location\nPossible reason: a 32-bit register is accessed with a 16-bit instruction,\nor a 16-bit register is accessed with a 32-bit instruction.\n" 55#define HWC_x2(level) \
52#define HWC_x3 "External Memory Addressing Error\n" 56 "System MMR Error\n" \
53#define HWC_x12 "Performance Monitor Overflow\n" 57 level " - An error occurred due to an invalid access to an System MMR location\n" \
54#define HWC_x18 "RAISE 5 instruction\n Software issued a RAISE 5 instruction to invoke the Hardware\n" 58 level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
55#define HWC_default "Reserved\n" 59 level " or a 16-bit register is accessed with a 32-bit instruction.\n"
56 60#define HWC_x3(level) \
57#define EXC_0x03 "Application stack overflow\n - Please increase the stack size of the application using elf2flt -s option,\n and/or reduce the stack use of the application.\n" 61 "External Memory Addressing Error\n"
58#define EXC_0x10 "Single step\n - When the processor is in single step mode, every instruction\n generates an exception. Primarily used for debugging.\n" 62#define HWC_x12(level) \
59#define EXC_0x11 "Exception caused by a trace buffer full condition\n - The processor takes this exception when the trace\n buffer overflows (only when enabled by the Trace Unit Control register).\n" 63 "Performance Monitor Overflow\n"
60#define EXC_0x21 "Undefined instruction\n - May be used to emulate instructions that are not defined for\n a particular processor implementation.\n" 64#define HWC_x18(level) \
61#define EXC_0x22 "Illegal instruction combination\n - See section for multi-issue rules in the ADSP-BF53x Blackfin\n Processor Instruction Set Reference.\n" 65 "RAISE 5 instruction\n" \
62#define EXC_0x23 "Data access CPLB protection violation\n - Attempted read or write to Supervisor resource,\n or illegal data memory access. \n" 66 level " Software issued a RAISE 5 instruction to invoke the Hardware\n"
63#define EXC_0x24 "Data access misaligned address violation\n - Attempted misaligned data memory or data cache access.\n" 67#define HWC_default(level) \
64#define EXC_0x25 "Unrecoverable event\n - For example, an exception generated while processing a previous exception.\n" 68 "Reserved\n"
65#define EXC_0x26 "Data access CPLB miss\n - Used by the MMU to signal a CPLB miss on a data access.\n" 69#define EXC_0x03(level) \
66#define EXC_0x27 "Data access multiple CPLB hits\n - More than one CPLB entry matches data fetch address.\n" 70 "Application stack overflow\n" \
67#define EXC_0x28 "Program Sequencer Exception caused by an emulation watchpoint match\n - There is a watchpoint match, and one of the EMUSW\n bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" 71 level " - Please increase the stack size of the application using elf2flt -s option,\n" \
68#define EXC_0x2A "Instruction fetch misaligned address violation\n - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch exception,\n the return address provided in RETX is the destination address which is misaligned, rather than the address of the offending instruction.\n" 72 level " and/or reduce the stack use of the application.\n"
69#define EXC_0x2B "CPLB protection violation\n - Illegal instruction fetch access (memory protection violation).\n" 73#define EXC_0x10(level) \
70#define EXC_0x2C "Instruction fetch CPLB miss\n - CPLB miss on an instruction fetch.\n" 74 "Single step\n" \
71#define EXC_0x2D "Instruction fetch multiple CPLB hits\n - More than one CPLB entry matches instruction fetch address.\n" 75 level " - When the processor is in single step mode, every instruction\n" \
72#define EXC_0x2E "Illegal use of supervisor resource\n - Attempted to use a Supervisor register or instruction from User mode.\n Supervisor resources are registers and instructions that are reserved\n for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n only instructions.\n" 76 level " generates an exception. Primarily used for debugging.\n"
77#define EXC_0x11(level) \
78 "Exception caused by a trace buffer full condition\n" \
79 level " - The processor takes this exception when the trace\n" \
80 level " buffer overflows (only when enabled by the Trace Unit Control register).\n"
81#define EXC_0x21(level) \
82 "Undefined instruction\n" \
83 level " - May be used to emulate instructions that are not defined for\n" \
84 level " a particular processor implementation.\n"
85#define EXC_0x22(level) \
86 "Illegal instruction combination\n" \
87 level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \
88 level " Processor Instruction Set Reference.\n"
89#define EXC_0x23(level) \
90 "Data access CPLB protection violation\n" \
91 level " - Attempted read or write to Supervisor resource,\n" \
92 level " or illegal data memory access. \n"
93#define EXC_0x24(level) \
94 "Data access misaligned address violation\n" \
95 level " - Attempted misaligned data memory or data cache access.\n"
96#define EXC_0x25(level) \
97 "Unrecoverable event\n" \
98 level " - For example, an exception generated while processing a previous exception.\n"
99#define EXC_0x26(level) \
100 "Data access CPLB miss\n" \
101 level " - Used by the MMU to signal a CPLB miss on a data access.\n"
102#define EXC_0x27(level) \
103 "Data access multiple CPLB hits\n" \
104 level " - More than one CPLB entry matches data fetch address.\n"
105#define EXC_0x28(level) \
106 "Program Sequencer Exception caused by an emulation watchpoint match\n" \
107 level " - There is a watchpoint match, and one of the EMUSW\n" \
108 level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
109#define EXC_0x2A(level) \
110 "Instruction fetch misaligned address violation\n" \
111 level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \
112 level " exception, the return address provided in RETX is the destination address which is\n" \
113 level " misaligned, rather than the address of the offending instruction.\n"
114#define EXC_0x2B(level) \
115 "CPLB protection violation\n" \
116 level " - Illegal instruction fetch access (memory protection violation).\n"
117#define EXC_0x2C(level) \
118 "Instruction fetch CPLB miss\n" \
119 level " - CPLB miss on an instruction fetch.\n"
120#define EXC_0x2D(level) \
121 "Instruction fetch multiple CPLB hits\n" \
122 level " - More than one CPLB entry matches instruction fetch address.\n"
123#define EXC_0x2E(level) \
124 "Illegal use of supervisor resource\n" \
125 level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
126 level " Supervisor resources are registers and instructions that are reserved\n" \
127 level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
128 level " only instructions.\n"
73 129
74#endif /* __ASSEMBLY__ */ 130#endif /* __ASSEMBLY__ */
75#endif /* _BFIN_TRAPS_H */ 131#endif /* _BFIN_TRAPS_H */
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
index 2233f8f9314d..22a410b8003b 100644
--- a/include/asm-blackfin/uaccess.h
+++ b/include/asm-blackfin/uaccess.h
@@ -31,7 +31,7 @@ static inline void set_fs(mm_segment_t fs)
31#define VERIFY_READ 0 31#define VERIFY_READ 0
32#define VERIFY_WRITE 1 32#define VERIFY_WRITE 1
33 33
34#define access_ok(type,addr,size) _access_ok((unsigned long)(addr),(size)) 34#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size))
35 35
36static inline int is_in_rom(unsigned long addr) 36static inline int is_in_rom(unsigned long addr)
37{ 37{
diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h
index 07ffe8b718c5..e98167358d26 100644
--- a/include/asm-blackfin/unistd.h
+++ b/include/asm-blackfin/unistd.h
@@ -369,8 +369,9 @@
369#define __NR_set_robust_list 354 369#define __NR_set_robust_list 354
370#define __NR_get_robust_list 355 370#define __NR_get_robust_list 355
371#define __NR_fallocate 356 371#define __NR_fallocate 356
372#define __NR_semtimedop 357
372 373
373#define __NR_syscall 357 374#define __NR_syscall 358
374#define NR_syscalls __NR_syscall 375#define NR_syscalls __NR_syscall
375 376
376/* Old optional stuff no one actually uses */ 377/* Old optional stuff no one actually uses */
diff --git a/include/asm-blackfin/user.h b/include/asm-blackfin/user.h
index abc34629bd59..afe6a0e1f7ce 100644
--- a/include/asm-blackfin/user.h
+++ b/include/asm-blackfin/user.h
@@ -75,7 +75,7 @@ struct user {
75 esp register. */ 75 esp register. */
76 long int signal; /* Signal that caused the core dump. */ 76 long int signal; /* Signal that caused the core dump. */
77 int reserved; /* No longer used */ 77 int reserved; /* No longer used */
78 struct user_regs_struct *u_ar0; 78 unsigned long u_ar0;
79 /* Used by gdb to help find the values for */ 79 /* Used by gdb to help find the values for */
80 /* the registers. */ 80 /* the registers. */
81 unsigned long magic; /* To uniquely identify a core file */ 81 unsigned long magic; /* To uniquely identify a core file */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 19:43:43 -0500