1 files changed, 78 insertions, 22 deletions
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
index fe365b1b7ca8..f0e5f940d9ca 100644
--- a/include/asm-blackfin/traps.h
+++ b/include/asm-blackfin/traps.h
@@ -45,31 +45,87 @@
 #define VEC_CPLB_I_M    (44)
 #define VEC_CPLB_I_MHIT (45)
 #define VEC_ILL_RES     (46)    /* including unvalid supervisor mode insn */
+/* The hardware reserves (63) for future use - we use it to tell our
+ * normal exception handling code we have a hardware error
+ */
+#define VEC_HWERR       (63)
 #ifndef __ASSEMBLY__
-#define HWC_x2 "System MMR Error\nAn error occurred due to an invalid access to an System MMR location\nPossible reason: a 32-bit register is accessed with a 16-bit instruction,\nor a 16-bit register is accessed with a 32-bit instruction.\n"
+#define HWC_x2(level) \
-#define HWC_x3 "External Memory Addressing Error\n"
+        "System MMR Error\n" \
-#define HWC_x12 "Performance Monitor Overflow\n"
+        level " - An error occurred due to an invalid access to an System MMR location\n" \
-#define HWC_x18 "RAISE 5 instruction\n Software issued a RAISE 5 instruction to invoke the Hardware\n"
+        level "   Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
-#define HWC_default "Reserved\n"
+        level "   or a 16-bit register is accessed with a 32-bit instruction.\n"
+#define HWC_x3(level) \
-#define EXC_0x03 "Application stack overflow\n - Please increase the stack size of the application using elf2flt -s option,\n and/or reduce the stack use of the application.\n"
+        "External Memory Addressing Error\n"
-#define EXC_0x10 "Single step\n - When the processor is in single step mode, every instruction\n generates an exception. Primarily used for debugging.\n"
+#define HWC_x12(level) \
-#define EXC_0x11 "Exception caused by a trace buffer full condition\n - The processor takes this exception when the trace\n buffer overflows (only when enabled by the Trace Unit Control register).\n"
+        "Performance Monitor Overflow\n"
-#define EXC_0x21 "Undefined instruction\n - May be used to emulate instructions that are not defined for\n a particular processor implementation.\n"
+#define HWC_x18(level) \
-#define EXC_0x22 "Illegal instruction combination\n - See section for multi-issue rules in the ADSP-BF53x Blackfin\n Processor Instruction Set Reference.\n"
+        "RAISE 5 instruction\n" \
-#define EXC_0x23 "Data access CPLB protection violation\n - Attempted read or write to Supervisor resource,\n or illegal data memory access. \n"
+        level "    Software issued a RAISE 5 instruction to invoke the Hardware\n"
-#define EXC_0x24 "Data access misaligned address violation\n - Attempted misaligned data memory or data cache access.\n"
+#define HWC_default(level) \
-#define EXC_0x25 "Unrecoverable event\n - For example, an exception generated while processing a previous exception.\n"
+         "Reserved\n"
-#define EXC_0x26 "Data access CPLB miss\n - Used by the MMU to signal a CPLB miss on a data access.\n"
+#define EXC_0x03(level) \
-#define EXC_0x27 "Data access multiple CPLB hits\n - More than one CPLB entry matches data fetch address.\n"
+        "Application stack overflow\n" \
-#define EXC_0x28 "Program Sequencer Exception caused by an emulation watchpoint match\n - There is a watchpoint match, and one of the EMUSW\n bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
+        level " - Please increase the stack size of the application using elf2flt -s option,\n" \
-#define EXC_0x2A "Instruction fetch misaligned address violation\n - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch exception,\n the return address provided in RETX is the destination address which is misaligned, rather than the address of the offending instruction.\n"
+        level "   and/or reduce the stack use of the application.\n"
-#define EXC_0x2B "CPLB protection violation\n - Illegal instruction fetch access (memory protection violation).\n"
+#define EXC_0x10(level) \
-#define EXC_0x2C "Instruction fetch CPLB miss\n - CPLB miss on an instruction fetch.\n"
+        "Single step\n" \
-#define EXC_0x2D "Instruction fetch multiple CPLB hits\n - More than one CPLB entry matches instruction fetch address.\n"
+        level " - When the processor is in single step mode, every instruction\n" \
-#define EXC_0x2E "Illegal use of supervisor resource\n - Attempted to use a Supervisor register or instruction from User mode.\n Supervisor resources are registers and instructions that are reserved\n for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n only instructions.\n"
+        level "   generates an exception. Primarily used for debugging.\n"
+#define EXC_0x11(level) \
+        "Exception caused by a trace buffer full condition\n" \
+        level " - The processor takes this exception when the trace\n" \
+        level "   buffer overflows (only when enabled by the Trace Unit Control register).\n"
+#define EXC_0x21(level) \
+        "Undefined instruction\n" \
+        level " - May be used to emulate instructions that are not defined for\n" \
+        level "   a particular processor implementation.\n"
+#define EXC_0x22(level) \
+        "Illegal instruction combination\n" \
+        level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \
+        level "   Processor Instruction Set Reference.\n"
+#define EXC_0x23(level) \
+        "Data access CPLB protection violation\n" \
+        level " - Attempted read or write to Supervisor resource,\n" \
+        level "   or illegal data memory access. \n"
+#define EXC_0x24(level) \
+        "Data access misaligned address violation\n" \
+        level " - Attempted misaligned data memory or data cache access.\n"
+#define EXC_0x25(level) \
+        "Unrecoverable event\n" \
+        level " - For example, an exception generated while processing a previous exception.\n"
+#define EXC_0x26(level) \
+        "Data access CPLB miss\n" \
+        level " - Used by the MMU to signal a CPLB miss on a data access.\n"
+#define EXC_0x27(level) \
+        "Data access multiple CPLB hits\n" \
+        level " - More than one CPLB entry matches data fetch address.\n"
+#define EXC_0x28(level) \
+        "Program Sequencer Exception caused by an emulation watchpoint match\n" \
+        level " - There is a watchpoint match, and one of the EMUSW\n" \
+        level "   bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
+#define EXC_0x2A(level) \
+        "Instruction fetch misaligned address violation\n" \
+        level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \
+        level "   exception, the return address provided in RETX is the destination address which is\n" \
+        level "   misaligned, rather than the address of the offending instruction.\n"
+#define EXC_0x2B(level) \
+        "CPLB protection violation\n" \
+        level " - Illegal instruction fetch access (memory protection violation).\n"
+#define EXC_0x2C(level) \
+        "Instruction fetch CPLB miss\n" \
+        level " - CPLB miss on an instruction fetch.\n"
+#define EXC_0x2D(level) \
+        "Instruction fetch multiple CPLB hits\n" \
+        level " - More than one CPLB entry matches instruction fetch address.\n"
+#define EXC_0x2E(level) \
+        "Illegal use of supervisor resource\n" \
+        level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
+        level "   Supervisor resources are registers and instructions that are reserved\n" \
+        level "   for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
+        level "   only instructions.\n"
 #endif                          /* __ASSEMBLY__ */
 #endif                          /* _BFIN_TRAPS_H */

diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h index fe365b1b7ca8..f0e5f940d9ca 100644 --- a/include/asm-blackfin/traps.h +++ b/include/asm-blackfin/traps.h
@@ -45,31 +45,87 @@
45	#define VEC_CPLB_I_M (44)	45	#define VEC_CPLB_I_M (44)
46	#define VEC_CPLB_I_MHIT (45)	46	#define VEC_CPLB_I_MHIT (45)
47	#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */	47	#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
		48	/* The hardware reserves (63) for future use - we use it to tell our
		49	* normal exception handling code we have a hardware error
		50	*/
		51	#define VEC_HWERR (63)
48		52
49	#ifndef __ASSEMBLY__	53	#ifndef __ASSEMBLY__
50		54
51	#define HWC_x2 "System MMR Error\nAn error occurred due to an invalid access to an System MMR location\nPossible reason: a 32-bit register is accessed with a 16-bit instruction,\nor a 16-bit register is accessed with a 32-bit instruction.\n"	55	#define HWC_x2(level) \
52	#define HWC_x3 "External Memory Addressing Error\n"	56	"System MMR Error\n" \
53	#define HWC_x12 "Performance Monitor Overflow\n"	57	level " - An error occurred due to an invalid access to an System MMR location\n" \
54	#define HWC_x18 "RAISE 5 instruction\n Software issued a RAISE 5 instruction to invoke the Hardware\n"	58	level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
55	#define HWC_default "Reserved\n"	59	level " or a 16-bit register is accessed with a 32-bit instruction.\n"
56		60	#define HWC_x3(level) \
57	#define EXC_0x03 "Application stack overflow\n - Please increase the stack size of the application using elf2flt -s option,\n and/or reduce the stack use of the application.\n"	61	"External Memory Addressing Error\n"
58	#define EXC_0x10 "Single step\n - When the processor is in single step mode, every instruction\n generates an exception. Primarily used for debugging.\n"	62	#define HWC_x12(level) \
59	#define EXC_0x11 "Exception caused by a trace buffer full condition\n - The processor takes this exception when the trace\n buffer overflows (only when enabled by the Trace Unit Control register).\n"	63	"Performance Monitor Overflow\n"
60	#define EXC_0x21 "Undefined instruction\n - May be used to emulate instructions that are not defined for\n a particular processor implementation.\n"	64	#define HWC_x18(level) \
61	#define EXC_0x22 "Illegal instruction combination\n - See section for multi-issue rules in the ADSP-BF53x Blackfin\n Processor Instruction Set Reference.\n"	65	"RAISE 5 instruction\n" \
62	#define EXC_0x23 "Data access CPLB protection violation\n - Attempted read or write to Supervisor resource,\n or illegal data memory access. \n"	66	level " Software issued a RAISE 5 instruction to invoke the Hardware\n"
63	#define EXC_0x24 "Data access misaligned address violation\n - Attempted misaligned data memory or data cache access.\n"	67	#define HWC_default(level) \
64	#define EXC_0x25 "Unrecoverable event\n - For example, an exception generated while processing a previous exception.\n"	68	"Reserved\n"
65	#define EXC_0x26 "Data access CPLB miss\n - Used by the MMU to signal a CPLB miss on a data access.\n"	69	#define EXC_0x03(level) \
66	#define EXC_0x27 "Data access multiple CPLB hits\n - More than one CPLB entry matches data fetch address.\n"	70	"Application stack overflow\n" \
67	#define EXC_0x28 "Program Sequencer Exception caused by an emulation watchpoint match\n - There is a watchpoint match, and one of the EMUSW\n bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"	71	level " - Please increase the stack size of the application using elf2flt -s option,\n" \
68	#define EXC_0x2A "Instruction fetch misaligned address violation\n - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch exception,\n the return address provided in RETX is the destination address which is misaligned, rather than the address of the offending instruction.\n"	72	level " and/or reduce the stack use of the application.\n"
69	#define EXC_0x2B "CPLB protection violation\n - Illegal instruction fetch access (memory protection violation).\n"	73	#define EXC_0x10(level) \
70	#define EXC_0x2C "Instruction fetch CPLB miss\n - CPLB miss on an instruction fetch.\n"	74	"Single step\n" \
71	#define EXC_0x2D "Instruction fetch multiple CPLB hits\n - More than one CPLB entry matches instruction fetch address.\n"	75	level " - When the processor is in single step mode, every instruction\n" \
72	#define EXC_0x2E "Illegal use of supervisor resource\n - Attempted to use a Supervisor register or instruction from User mode.\n Supervisor resources are registers and instructions that are reserved\n for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n only instructions.\n"	76	level " generates an exception. Primarily used for debugging.\n"
		77	#define EXC_0x11(level) \
		78	"Exception caused by a trace buffer full condition\n" \
		79	level " - The processor takes this exception when the trace\n" \
		80	level " buffer overflows (only when enabled by the Trace Unit Control register).\n"
		81	#define EXC_0x21(level) \
		82	"Undefined instruction\n" \
		83	level " - May be used to emulate instructions that are not defined for\n" \
		84	level " a particular processor implementation.\n"
		85	#define EXC_0x22(level) \
		86	"Illegal instruction combination\n" \
		87	level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \
		88	level " Processor Instruction Set Reference.\n"
		89	#define EXC_0x23(level) \
		90	"Data access CPLB protection violation\n" \
		91	level " - Attempted read or write to Supervisor resource,\n" \
		92	level " or illegal data memory access. \n"
		93	#define EXC_0x24(level) \
		94	"Data access misaligned address violation\n" \
		95	level " - Attempted misaligned data memory or data cache access.\n"
		96	#define EXC_0x25(level) \
		97	"Unrecoverable event\n" \
		98	level " - For example, an exception generated while processing a previous exception.\n"
		99	#define EXC_0x26(level) \
		100	"Data access CPLB miss\n" \
		101	level " - Used by the MMU to signal a CPLB miss on a data access.\n"
		102	#define EXC_0x27(level) \
		103	"Data access multiple CPLB hits\n" \
		104	level " - More than one CPLB entry matches data fetch address.\n"
		105	#define EXC_0x28(level) \
		106	"Program Sequencer Exception caused by an emulation watchpoint match\n" \
		107	level " - There is a watchpoint match, and one of the EMUSW\n" \
		108	level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
		109	#define EXC_0x2A(level) \
		110	"Instruction fetch misaligned address violation\n" \
		111	level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \
		112	level " exception, the return address provided in RETX is the destination address which is\n" \
		113	level " misaligned, rather than the address of the offending instruction.\n"
		114	#define EXC_0x2B(level) \
		115	"CPLB protection violation\n" \
		116	level " - Illegal instruction fetch access (memory protection violation).\n"
		117	#define EXC_0x2C(level) \
		118	"Instruction fetch CPLB miss\n" \
		119	level " - CPLB miss on an instruction fetch.\n"
		120	#define EXC_0x2D(level) \
		121	"Instruction fetch multiple CPLB hits\n" \
		122	level " - More than one CPLB entry matches instruction fetch address.\n"
		123	#define EXC_0x2E(level) \
		124	"Illegal use of supervisor resource\n" \
		125	level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
		126	level " Supervisor resources are registers and instructions that are reserved\n" \
		127	level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
		128	level " only instructions.\n"
73		129
74	#endif /* __ASSEMBLY__ */	130	#endif /* __ASSEMBLY__ */
75	#endif /* _BFIN_TRAPS_H */	131	#endif /* _BFIN_TRAPS_H */