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-rw-r--r--include/asm-blackfin/mach-common/cdef_LPBlackfin.h4
-rw-r--r--include/asm-blackfin/mach-common/clocks.h70
-rw-r--r--include/asm-blackfin/mach-common/def_LPBlackfin.h135
3 files changed, 139 insertions, 70 deletions
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
index 94ed381e5606..ede210eca4ec 100644
--- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
@@ -39,7 +39,7 @@
39#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS) 39#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
40#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) 40#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
41#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) 41#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
42#ifdef ANOMALY_05000125 42#if ANOMALY_05000125
43extern void bfin_write_DMEM_CONTROL(unsigned int val); 43extern void bfin_write_DMEM_CONTROL(unsigned int val);
44#else 44#else
45#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) 45#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
@@ -129,7 +129,7 @@ extern void bfin_write_DMEM_CONTROL(unsigned int val);
129#define DTEST_DATA3 0xFFE0040C 129#define DTEST_DATA3 0xFFE0040C
130*/ 130*/
131#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) 131#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
132#ifdef ANOMALY_05000125 132#if ANOMALY_05000125
133extern void bfin_write_IMEM_CONTROL(unsigned int val); 133extern void bfin_write_IMEM_CONTROL(unsigned int val);
134#else 134#else
135#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) 135#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
diff --git a/include/asm-blackfin/mach-common/clocks.h b/include/asm-blackfin/mach-common/clocks.h
new file mode 100644
index 000000000000..033bba92d61c
--- /dev/null
+++ b/include/asm-blackfin/mach-common/clocks.h
@@ -0,0 +1,70 @@
1/*
2 * File: include/asm-blackfin/mach-common/clocks.h
3 * Based on: include/asm-blackfin/mach-bf537/bf537.h
4 * Author: Robin Getz <rgetz@blackfin.uclinux.org>
5 *
6 * Created: 25Jul07
7 * Description: Common Clock definitions for various kernel files
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef _BFIN_CLOCKS_H
31#define _BFIN_CLOCKS_H
32
33#ifdef CONFIG_CCLK_DIV_1
34# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
35# define CONFIG_CCLK_DIV 1
36#endif
37
38#ifdef CONFIG_CCLK_DIV_2
39# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
40# define CONFIG_CCLK_DIV 2
41#endif
42
43#ifdef CONFIG_CCLK_DIV_4
44# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
45# define CONFIG_CCLK_DIV 4
46#endif
47
48#ifdef CONFIG_CCLK_DIV_8
49# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
50# define CONFIG_CCLK_DIV 8
51#endif
52
53#ifndef CONFIG_PLL_BYPASS
54# ifndef CONFIG_CLKIN_HALF
55# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
56# else
57# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
58# endif
59
60# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
61# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
62
63#else
64# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ)
65# define CONFIG_CCLK_HZ (CONFIG_CLKIN_HZ)
66# define CONFIG_SCLK_HZ (CONFIG_CLKIN_HZ)
67# define CONFIG_VCO_MULT 0
68#endif
69
70#endif
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
index be1ece8c0c27..c1d8c4a78fcf 100644
--- a/include/asm-blackfin/mach-common/def_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -33,81 +33,77 @@
33 33
34#include <asm/mach/anomaly.h> 34#include <asm/mach/anomaly.h>
35 35
36/*#if !defined(__ADSPLPBLACKFIN__)
37#warning def_LPBlackfin.h should only be included for 532 compatible chips.
38#endif
39*/
40
41#define MK_BMSK_(x) (1<<x) 36#define MK_BMSK_(x) (1<<x)
42 37
43#if defined(ANOMALY_05000198) 38#ifndef __ASSEMBLY__
44
45#define bfin_read8(addr) ({ unsigned char __v; \
46 __asm__ __volatile__ ("NOP;\n\t" \
47 "%0 = b[%1] (z);\n\t" \
48 : "=d"(__v) : "a"(addr)); \
49 __v; })
50
51#define bfin_read16(addr) ({ unsigned __v; \
52 __asm__ __volatile__ ("NOP;\n\t"\
53 "%0 = w[%1] (z);\n\t"\
54 : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
55
56#define bfin_read32(addr) ({ unsigned __v; \
57 __asm__ __volatile__ ("NOP;\n\t"\
58 "%0 = [%1];\n\t"\
59 : "=d"(__v) : "a"(addr)); __v; })
60
61#define bfin_write8(addr, val) ({ \
62 __asm__ __volatile__ ("NOP;\n\t" \
63 "b[%0] = %1;\n\t" \
64 : : "a"(addr), "d"(val) : "memory");})
65 39
66#define bfin_write16(addr,val) ({\ 40#include <linux/types.h>
67 __asm__ __volatile__ ("NOP;\n\t"\
68 "w[%0] = %1;\n\t"\
69 : : "a"(addr) , "d"(val) : "memory");})
70
71#define bfin_write32(addr,val) ({\
72 __asm__ __volatile__ ("NOP;\n\t"\
73 "[%0] = %1;\n\t"\
74 : : "a"(addr) , "d"(val) : "memory");})
75 41
42#if ANOMALY_05000198
43# define NOP_PAD_ANOMALY_05000198 "nop;"
76#else 44#else
77 45# define NOP_PAD_ANOMALY_05000198
78#define bfin_read8(addr) ({ unsigned char __v; \
79 __asm__ __volatile__ ( \
80 "%0 = b[%1] (z);\n\t" \
81 :"=d"(__v) : "a"(addr)); \
82 __v; })
83
84#define bfin_read16(addr) ({ unsigned __v; \
85 __asm__ __volatile__ (\
86 "%0 = w[%1] (z);\n\t"\
87 : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
88
89#define bfin_read32(addr) ({ unsigned __v; \
90 __asm__ __volatile__ (\
91 "%0 = [%1];\n\t"\
92 : "=d"(__v) : "a"(addr)); __v; })
93
94#define bfin_write8(addr, val) ({ \
95 __asm__ __volatile__ ( \
96 "b[%0] = %1; \n\t" \
97 ::"a"(addr), "d"(val) : "memory");})
98
99#define bfin_write16(addr,val) ({\
100 __asm__ __volatile__ (\
101 "w[%0] = %1;\n\t"\
102 : : "a"(addr) , "d"(val) : "memory");})
103
104#define bfin_write32(addr,val) ({\
105 __asm__ __volatile__ (\
106 "[%0] = %1;\n\t"\
107 : : "a"(addr) , "d"(val) : "memory");})
108
109#endif 46#endif
110 47
48#define bfin_read8(addr) ({ \
49 uint8_t __v; \
50 __asm__ __volatile__( \
51 NOP_PAD_ANOMALY_05000198 \
52 "%0 = b[%1] (z);" \
53 : "=d" (__v) \
54 : "a" (addr) \
55 ); \
56 __v; })
57
58#define bfin_read16(addr) ({ \
59 uint16_t __v; \
60 __asm__ __volatile__( \
61 NOP_PAD_ANOMALY_05000198 \
62 "%0 = w[%1] (z);" \
63 : "=d" (__v) \
64 : "a" (addr) \
65 ); \
66 __v; })
67
68#define bfin_read32(addr) ({ \
69 uint32_t __v; \
70 __asm__ __volatile__( \
71 NOP_PAD_ANOMALY_05000198 \
72 "%0 = [%1];" \
73 : "=d" (__v) \
74 : "a" (addr) \
75 ); \
76 __v; })
77
78#define bfin_write8(addr, val) \
79 __asm__ __volatile__( \
80 NOP_PAD_ANOMALY_05000198 \
81 "b[%0] = %1;" \
82 : \
83 : "a" (addr), "d" (val) \
84 : "memory" \
85 )
86
87#define bfin_write16(addr, val) \
88 __asm__ __volatile__( \
89 NOP_PAD_ANOMALY_05000198 \
90 "w[%0] = %1;" \
91 : \
92 : "a" (addr), "d" (val) \
93 : "memory" \
94 )
95
96#define bfin_write32(addr, val) \
97 __asm__ __volatile__( \
98 NOP_PAD_ANOMALY_05000198 \
99 "[%0] = %1;" \
100 : \
101 : "a" (addr), "d" (val) \
102 : "memory" \
103 )
104
105#endif /* __ASSEMBLY__ */
106
111/************************************************** 107/**************************************************
112 * System Register Bits 108 * System Register Bits
113 **************************************************/ 109 **************************************************/
@@ -643,6 +639,7 @@
643#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access 639#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
644 * allowed (user mode) 640 * allowed (user mode)
645 */ 641 */
642
646#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ 643#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
647#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ 644#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
648#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ 645#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
@@ -675,6 +672,8 @@
675 */ 672 */
676#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ 673#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
677 674
675#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
676
678/* TBUFCTL Masks */ 677/* TBUFCTL Masks */
679#define TBUFPWR 0x0001 678#define TBUFPWR 0x0001
680#define TBUFEN 0x0002 679#define TBUFEN 0x0002