aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-blackfin/mach-common
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-blackfin/mach-common')
-rw-r--r--include/asm-blackfin/mach-common/cdef_LPBlackfin.h471
-rw-r--r--include/asm-blackfin/mach-common/context.S350
-rw-r--r--include/asm-blackfin/mach-common/def_LPBlackfin.h691
3 files changed, 1512 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
new file mode 100644
index 000000000000..22aa5e637993
--- /dev/null
+++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
@@ -0,0 +1,471 @@
1 /*
2 * File: include/asm-blackfin/mach-common/cdef_LPBlackfin.h
3 * Based on:
4 * Author: unknown
5 * COPYRIGHT 2005 Analog Devices
6 * Created: ?
7 * Description:
8 *
9 * Modified:
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING.
25 * If not, write to the Free Software Foundation,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29#ifndef _CDEF_LPBLACKFIN_H
30#define _CDEF_LPBLACKFIN_H
31
32/*#if !defined(__ADSPLPBLACKFIN__)
33#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
34#endif
35*/
36#include <asm/mach-common/def_LPBlackfin.h>
37
38/*Cache & SRAM Memory*/
39#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
40#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
41#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
42#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
43#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
44#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
45#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
46#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
47#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
48#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
49#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
50#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val)
51/*
52#define MMR_TIMEOUT 0xFFE00010
53*/
54#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
55#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0)
56#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val)
57#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
58#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1)
59#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val)
60#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
61#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2)
62#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val)
63#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3)
64#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3)
65#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val)
66#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4)
67#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4)
68#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val)
69#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5)
70#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5)
71#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val)
72#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6)
73#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6)
74#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6,val)
75#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7)
76#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7)
77#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7,val)
78#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8)
79#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8)
80#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8,val)
81#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9)
82#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9)
83#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9,val)
84#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10)
85#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10)
86#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10,val)
87#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11)
88#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11)
89#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11,val)
90#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12)
91#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12)
92#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12,val)
93#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13)
94#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13)
95#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13,val)
96#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14)
97#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14)
98#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14,val)
99#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15)
100#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15)
101#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15,val)
102#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
103#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
104#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0,val)
105#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
106#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
107#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1,val)
108#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
109#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
110#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2,val)
111#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
112#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
113#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3,val)
114#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
115#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
116#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4,val)
117#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
118#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
119#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5,val)
120#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
121#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
122#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6,val)
123#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
124#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
125#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7,val)
126#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
127#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
128#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8,val)
129#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
130#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
131#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9,val)
132#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
133#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
134#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10,val)
135#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
136#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
137#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11,val)
138#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
139#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
140#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12,val)
141#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
142#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
143#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13,val)
144#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
145#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
146#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14,val)
147#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
148#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
149#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15,val)
150#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
151#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
152#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND,val)
153/*
154#define DTEST_INDEX 0xFFE00304
155*/
156#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
157#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
158#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0,val)
159#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
160#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
161#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1,val)
162/*
163#define DTEST_DATA2 0xFFE00408
164#define DTEST_DATA3 0xFFE0040C
165*/
166#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
167#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
168#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
169#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
170#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
171#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val)
172#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
173#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
174#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR,val)
175#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0)
176#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0)
177#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0,val)
178#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1)
179#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1)
180#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1,val)
181#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2)
182#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2)
183#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2,val)
184#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3)
185#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3)
186#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3,val)
187#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4)
188#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4)
189#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4,val)
190#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5)
191#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5)
192#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5,val)
193#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6)
194#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6)
195#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6,val)
196#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7)
197#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7)
198#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7,val)
199#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8)
200#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8)
201#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8,val)
202#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9)
203#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9)
204#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9,val)
205#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10)
206#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10)
207#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10,val)
208#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11)
209#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11)
210#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11,val)
211#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12)
212#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12)
213#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12,val)
214#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13)
215#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13)
216#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13,val)
217#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14)
218#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14)
219#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14,val)
220#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15)
221#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15)
222#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15,val)
223#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
224#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
225#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0,val)
226#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
227#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
228#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1,val)
229#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
230#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
231#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2,val)
232#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
233#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
234#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3,val)
235#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
236#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
237#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4,val)
238#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
239#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
240#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5,val)
241#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
242#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
243#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6,val)
244#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
245#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
246#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7,val)
247#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
248#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
249#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8,val)
250#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
251#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
252#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9,val)
253#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
254#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
255#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10,val)
256#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
257#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
258#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11,val)
259#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
260#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
261#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12,val)
262#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
263#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
264#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13,val)
265#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
266#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
267#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val)
268#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
269#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
270#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val)
271#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
272#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
273#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val)
274#if 0
275#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
276#endif
277#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
278#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
279#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val)
280#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
281#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
282#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val)
283
284/* Event/Interrupt Registers*/
285
286#define pEVT0 ((volatile void **)EVT0)
287#define bfin_read_EVT0() bfin_read32(EVT0)
288#define bfin_write_EVT0(val) bfin_write32(EVT0,val)
289#define pEVT1 ((volatile void **)EVT1)
290#define bfin_read_EVT1() bfin_read32(EVT1)
291#define bfin_write_EVT1(val) bfin_write32(EVT1,val)
292#define pEVT2 ((volatile void **)EVT2)
293#define bfin_read_EVT2() bfin_read32(EVT2)
294#define bfin_write_EVT2(val) bfin_write32(EVT2,val)
295#define pEVT3 ((volatile void **)EVT3)
296#define bfin_read_EVT3() bfin_read32(EVT3)
297#define bfin_write_EVT3(val) bfin_write32(EVT3,val)
298#define pEVT4 ((volatile void **)EVT4)
299#define bfin_read_EVT4() bfin_read32(EVT4)
300#define bfin_write_EVT4(val) bfin_write32(EVT4,val)
301#define pEVT5 ((volatile void **)EVT5)
302#define bfin_read_EVT5() bfin_read32(EVT5)
303#define bfin_write_EVT5(val) bfin_write32(EVT5,val)
304#define pEVT6 ((volatile void **)EVT6)
305#define bfin_read_EVT6() bfin_read32(EVT6)
306#define bfin_write_EVT6(val) bfin_write32(EVT6,val)
307#define pEVT7 ((volatile void **)EVT7)
308#define bfin_read_EVT7() bfin_read32(EVT7)
309#define bfin_write_EVT7(val) bfin_write32(EVT7,val)
310#define pEVT8 ((volatile void **)EVT8)
311#define bfin_read_EVT8() bfin_read32(EVT8)
312#define bfin_write_EVT8(val) bfin_write32(EVT8,val)
313#define pEVT9 ((volatile void **)EVT9)
314#define bfin_read_EVT9() bfin_read32(EVT9)
315#define bfin_write_EVT9(val) bfin_write32(EVT9,val)
316#define pEVT10 ((volatile void **)EVT10)
317#define bfin_read_EVT10() bfin_read32(EVT10)
318#define bfin_write_EVT10(val) bfin_write32(EVT10,val)
319#define pEVT11 ((volatile void **)EVT11)
320#define bfin_read_EVT11() bfin_read32(EVT11)
321#define bfin_write_EVT11(val) bfin_write32(EVT11,val)
322#define pEVT12 ((volatile void **)EVT12)
323#define bfin_read_EVT12() bfin_read32(EVT12)
324#define bfin_write_EVT12(val) bfin_write32(EVT12,val)
325#define pEVT13 ((volatile void **)EVT13)
326#define bfin_read_EVT13() bfin_read32(EVT13)
327#define bfin_write_EVT13(val) bfin_write32(EVT13,val)
328#define pEVT14 ((volatile void **)EVT14)
329#define bfin_read_EVT14() bfin_read32(EVT14)
330#define bfin_write_EVT14(val) bfin_write32(EVT14,val)
331#define pEVT15 ((volatile void **)EVT15)
332#define bfin_read_EVT15() bfin_read32(EVT15)
333#define bfin_write_EVT15(val) bfin_write32(EVT15,val)
334#define pIMASK ((volatile unsigned long *)IMASK)
335#define bfin_read_IMASK() bfin_read32(IMASK)
336#define bfin_write_IMASK(val) bfin_write32(IMASK,val)
337#define pIPEND ((volatile unsigned long *)IPEND)
338#define bfin_read_IPEND() bfin_read32(IPEND)
339#define bfin_write_IPEND(val) bfin_write32(IPEND,val)
340#define pILAT ((volatile unsigned long *)ILAT)
341#define bfin_read_ILAT() bfin_read32(ILAT)
342#define bfin_write_ILAT(val) bfin_write32(ILAT,val)
343
344/*Core Timer Registers*/
345#define pTCNTL ((volatile unsigned long *)TCNTL)
346#define bfin_read_TCNTL() bfin_read32(TCNTL)
347#define bfin_write_TCNTL(val) bfin_write32(TCNTL,val)
348#define pTPERIOD ((volatile unsigned long *)TPERIOD)
349#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
350#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD,val)
351#define pTSCALE ((volatile unsigned long *)TSCALE)
352#define bfin_read_TSCALE() bfin_read32(TSCALE)
353#define bfin_write_TSCALE(val) bfin_write32(TSCALE,val)
354#define pTCOUNT ((volatile unsigned long *)TCOUNT)
355#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
356#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT,val)
357
358/*Debug/MP/Emulation Registers*/
359#define pDSPID ((volatile unsigned long *)DSPID)
360#define bfin_read_DSPID() bfin_read32(DSPID)
361#define bfin_write_DSPID(val) bfin_write32(DSPID,val)
362#define pDBGCTL ((volatile unsigned long *)DBGCTL)
363#define bfin_read_DBGCTL() bfin_read32(DBGCTL)
364#define bfin_write_DBGCTL(val) bfin_write32(DBGCTL,val)
365#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
366#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
367#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT,val)
368#define pEMUDAT ((volatile unsigned long *)EMUDAT)
369#define bfin_read_EMUDAT() bfin_read32(EMUDAT)
370#define bfin_write_EMUDAT(val) bfin_write32(EMUDAT,val)
371
372/*Trace Buffer Registers*/
373#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
374#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
375#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL,val)
376#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
377#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
378#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT,val)
379#define pTBUF ((volatile void **)TBUF)
380#define bfin_read_TBUF() bfin_read32(TBUF)
381#define bfin_write_TBUF(val) bfin_write32(TBUF,val)
382
383/*Watch Point Control Registers*/
384#define pWPIACTL ((volatile unsigned long *)WPIACTL)
385#define bfin_read_WPIACTL() bfin_read32(WPIACTL)
386#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL,val)
387#define pWPIA0 ((volatile void **)WPIA0)
388#define bfin_read_WPIA0() bfin_read32(WPIA0)
389#define bfin_write_WPIA0(val) bfin_write32(WPIA0,val)
390#define pWPIA1 ((volatile void **)WPIA1)
391#define bfin_read_WPIA1() bfin_read32(WPIA1)
392#define bfin_write_WPIA1(val) bfin_write32(WPIA1,val)
393#define pWPIA2 ((volatile void **)WPIA2)
394#define bfin_read_WPIA2() bfin_read32(WPIA2)
395#define bfin_write_WPIA2(val) bfin_write32(WPIA2,val)
396#define pWPIA3 ((volatile void **)WPIA3)
397#define bfin_read_WPIA3() bfin_read32(WPIA3)
398#define bfin_write_WPIA3(val) bfin_write32(WPIA3,val)
399#define pWPIA4 ((volatile void **)WPIA4)
400#define bfin_read_WPIA4() bfin_read32(WPIA4)
401#define bfin_write_WPIA4(val) bfin_write32(WPIA4,val)
402#define pWPIA5 ((volatile void **)WPIA5)
403#define bfin_read_WPIA5() bfin_read32(WPIA5)
404#define bfin_write_WPIA5(val) bfin_write32(WPIA5,val)
405#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
406#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0)
407#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0,val)
408#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
409#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1)
410#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1,val)
411#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
412#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2)
413#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2,val)
414#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
415#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3)
416#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3,val)
417#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
418#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4)
419#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4,val)
420#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
421#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5)
422#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5,val)
423#define pWPDACTL ((volatile unsigned long *)WPDACTL)
424#define bfin_read_WPDACTL() bfin_read32(WPDACTL)
425#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL,val)
426#define pWPDA0 ((volatile void **)WPDA0)
427#define bfin_read_WPDA0() bfin_read32(WPDA0)
428#define bfin_write_WPDA0(val) bfin_write32(WPDA0,val)
429#define pWPDA1 ((volatile void **)WPDA1)
430#define bfin_read_WPDA1() bfin_read32(WPDA1)
431#define bfin_write_WPDA1(val) bfin_write32(WPDA1,val)
432#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
433#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0)
434#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0,val)
435#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
436#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1)
437#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1,val)
438#define pWPSTAT ((volatile unsigned long *)WPSTAT)
439#define bfin_read_WPSTAT() bfin_read32(WPSTAT)
440#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT,val)
441
442/*Performance Monitor Registers*/
443#define pPFCTL ((volatile unsigned long *)PFCTL)
444#define bfin_read_PFCTL() bfin_read32(PFCTL)
445#define bfin_write_PFCTL(val) bfin_write32(PFCTL,val)
446#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
447#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
448#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0,val)
449#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
450#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
451#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val)
452
453/*
454#define IPRIO 0xFFE02110
455*/
456
457#if defined(CONFIG_BFIN_ALIVE_LED)
458#define pCONFIG_BFIN_ALIVE_LED_DPORT \
459 (volatile unsigned short *)CONFIG_BFIN_ALIVE_LED_DPORT
460#define pCONFIG_BFIN_ALIVE_LED_PORT \
461 (volatile unsigned short *)CONFIG_BFIN_ALIVE_LED_PORT
462#endif
463
464#if defined(CONFIG_BFIN_IDLE_LED)
465#define pCONFIG_BFIN_IDLE_LED_DPORT \
466 (volatile unsigned short *)CONFIG_BFIN_IDLE_LED_DPORT
467#define pCONFIG_BFIN_IDLE_LED_PORT \
468 (volatile unsigned short *)CONFIG_BFIN_IDLE_LED_PORT
469#endif
470
471#endif /* _CDEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/mach-common/context.S b/include/asm-blackfin/mach-common/context.S
new file mode 100644
index 000000000000..fd0ebe1862b8
--- /dev/null
+++ b/include/asm-blackfin/mach-common/context.S
@@ -0,0 +1,350 @@
1/*
2 * File: arch/blackfin/kernel/context.S
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30/*
31 * Code to save processor context.
32 * We even save the register which are preserved by a function call
33 * - r4, r5, r6, r7, p3, p4, p5
34 */
35.macro save_context_with_interrupts
36 [--sp] = SYSCFG;
37
38 [--sp] = P0; /*orig_p0*/
39 [--sp] = R0; /*orig_r0*/
40
41 [--sp] = ( R7:0, P5:0 );
42 [--sp] = fp;
43 [--sp] = usp;
44
45 [--sp] = i0;
46 [--sp] = i1;
47 [--sp] = i2;
48 [--sp] = i3;
49
50 [--sp] = m0;
51 [--sp] = m1;
52 [--sp] = m2;
53 [--sp] = m3;
54
55 [--sp] = l0;
56 [--sp] = l1;
57 [--sp] = l2;
58 [--sp] = l3;
59
60 [--sp] = b0;
61 [--sp] = b1;
62 [--sp] = b2;
63 [--sp] = b3;
64 [--sp] = a0.x;
65 [--sp] = a0.w;
66 [--sp] = a1.x;
67 [--sp] = a1.w;
68
69 [--sp] = LC0;
70 [--sp] = LC1;
71 [--sp] = LT0;
72 [--sp] = LT1;
73 [--sp] = LB0;
74 [--sp] = LB1;
75
76 [--sp] = ASTAT;
77
78 [--sp] = r0; /* Skip reserved */
79 [--sp] = RETS;
80 r0 = RETI;
81 [--sp] = r0;
82 [--sp] = RETX;
83 [--sp] = RETN;
84 [--sp] = RETE;
85 [--sp] = SEQSTAT;
86 [--sp] = r0; /* Skip IPEND as well. */
87 /* Switch to other method of keeping interrupts disabled. */
88#ifdef CONFIG_DEBUG_HWERR
89 r0 = 0x3f;
90 sti r0;
91#else
92 cli r0;
93#endif
94 [--sp] = RETI; /*orig_pc*/
95 /* Clear all L registers. */
96 r0 = 0 (x);
97 l0 = r0;
98 l1 = r0;
99 l2 = r0;
100 l3 = r0;
101.endm
102
103.macro save_context_syscall
104 [--sp] = SYSCFG;
105
106 [--sp] = P0; /*orig_p0*/
107 [--sp] = R0; /*orig_r0*/
108 [--sp] = ( R7:0, P5:0 );
109 [--sp] = fp;
110 [--sp] = usp;
111
112 [--sp] = i0;
113 [--sp] = i1;
114 [--sp] = i2;
115 [--sp] = i3;
116
117 [--sp] = m0;
118 [--sp] = m1;
119 [--sp] = m2;
120 [--sp] = m3;
121
122 [--sp] = l0;
123 [--sp] = l1;
124 [--sp] = l2;
125 [--sp] = l3;
126
127 [--sp] = b0;
128 [--sp] = b1;
129 [--sp] = b2;
130 [--sp] = b3;
131 [--sp] = a0.x;
132 [--sp] = a0.w;
133 [--sp] = a1.x;
134 [--sp] = a1.w;
135
136 [--sp] = LC0;
137 [--sp] = LC1;
138 [--sp] = LT0;
139 [--sp] = LT1;
140 [--sp] = LB0;
141 [--sp] = LB1;
142
143 [--sp] = ASTAT;
144
145 [--sp] = r0; /* Skip reserved */
146 [--sp] = RETS;
147 r0 = RETI;
148 [--sp] = r0;
149 [--sp] = RETX;
150 [--sp] = RETN;
151 [--sp] = RETE;
152 [--sp] = SEQSTAT;
153 [--sp] = r0; /* Skip IPEND as well. */
154 [--sp] = RETI; /*orig_pc*/
155 /* Clear all L registers. */
156 r0 = 0 (x);
157 l0 = r0;
158 l1 = r0;
159 l2 = r0;
160 l3 = r0;
161.endm
162
163.macro save_context_no_interrupts
164 [--sp] = SYSCFG;
165 [--sp] = P0; /* orig_p0 */
166 [--sp] = R0; /* orig_r0 */
167 [--sp] = ( R7:0, P5:0 );
168 [--sp] = fp;
169 [--sp] = usp;
170
171 [--sp] = i0;
172 [--sp] = i1;
173 [--sp] = i2;
174 [--sp] = i3;
175
176 [--sp] = m0;
177 [--sp] = m1;
178 [--sp] = m2;
179 [--sp] = m3;
180
181 [--sp] = l0;
182 [--sp] = l1;
183 [--sp] = l2;
184 [--sp] = l3;
185
186 [--sp] = b0;
187 [--sp] = b1;
188 [--sp] = b2;
189 [--sp] = b3;
190 [--sp] = a0.x;
191 [--sp] = a0.w;
192 [--sp] = a1.x;
193 [--sp] = a1.w;
194
195 [--sp] = LC0;
196 [--sp] = LC1;
197 [--sp] = LT0;
198 [--sp] = LT1;
199 [--sp] = LB0;
200 [--sp] = LB1;
201
202 [--sp] = ASTAT;
203
204#ifdef CONFIG_KGDB
205 fp = 0(Z);
206 r1 = sp;
207 r1 += 60;
208 r1 += 60;
209 r1 += 60;
210 [--sp] = r1;
211#else
212 [--sp] = r0; /* Skip reserved */
213#endif
214 [--sp] = RETS;
215 r0 = RETI;
216 [--sp] = r0;
217 [--sp] = RETX;
218 [--sp] = RETN;
219 [--sp] = RETE;
220 [--sp] = SEQSTAT;
221#ifdef CONFIG_KGDB
222 r1.l = lo(IPEND);
223 r1.h = hi(IPEND);
224 [--sp] = r1;
225#else
226 [--sp] = r0; /* Skip IPEND as well. */
227#endif
228 [--sp] = r0; /*orig_pc*/
229 /* Clear all L registers. */
230 r0 = 0 (x);
231 l0 = r0;
232 l1 = r0;
233 l2 = r0;
234 l3 = r0;
235.endm
236
237.macro restore_context_no_interrupts
238 sp += 4; /* Skip orig_pc */
239 sp += 4; /* Skip IPEND */
240 SEQSTAT = [sp++];
241 RETE = [sp++];
242 RETN = [sp++];
243 RETX = [sp++];
244 r0 = [sp++];
245 RETI = r0; /* Restore RETI indirectly when in exception */
246 RETS = [sp++];
247
248 sp += 4; /* Skip Reserved */
249
250 ASTAT = [sp++];
251
252 LB1 = [sp++];
253 LB0 = [sp++];
254 LT1 = [sp++];
255 LT0 = [sp++];
256 LC1 = [sp++];
257 LC0 = [sp++];
258
259 a1.w = [sp++];
260 a1.x = [sp++];
261 a0.w = [sp++];
262 a0.x = [sp++];
263 b3 = [sp++];
264 b2 = [sp++];
265 b1 = [sp++];
266 b0 = [sp++];
267
268 l3 = [sp++];
269 l2 = [sp++];
270 l1 = [sp++];
271 l0 = [sp++];
272
273 m3 = [sp++];
274 m2 = [sp++];
275 m1 = [sp++];
276 m0 = [sp++];
277
278 i3 = [sp++];
279 i2 = [sp++];
280 i1 = [sp++];
281 i0 = [sp++];
282
283 sp += 4;
284 fp = [sp++];
285
286 ( R7 : 0, P5 : 0) = [ SP ++ ];
287 sp += 8; /* Skip orig_r0/orig_p0 */
288 SYSCFG = [sp++];
289.endm
290
291.macro restore_context_with_interrupts
292 sp += 4; /* Skip orig_pc */
293 sp += 4; /* Skip IPEND */
294 SEQSTAT = [sp++];
295 RETE = [sp++];
296 RETN = [sp++];
297 RETX = [sp++];
298 RETI = [sp++];
299 RETS = [sp++];
300
301 p0.h = _irq_flags;
302 p0.l = _irq_flags;
303 r0 = [p0];
304 sti r0;
305
306 sp += 4; /* Skip Reserved */
307
308 ASTAT = [sp++];
309
310 LB1 = [sp++];
311 LB0 = [sp++];
312 LT1 = [sp++];
313 LT0 = [sp++];
314 LC1 = [sp++];
315 LC0 = [sp++];
316
317 a1.w = [sp++];
318 a1.x = [sp++];
319 a0.w = [sp++];
320 a0.x = [sp++];
321 b3 = [sp++];
322 b2 = [sp++];
323 b1 = [sp++];
324 b0 = [sp++];
325
326 l3 = [sp++];
327 l2 = [sp++];
328 l1 = [sp++];
329 l0 = [sp++];
330
331 m3 = [sp++];
332 m2 = [sp++];
333 m1 = [sp++];
334 m0 = [sp++];
335
336 i3 = [sp++];
337 i2 = [sp++];
338 i1 = [sp++];
339 i0 = [sp++];
340
341 sp += 4;
342 fp = [sp++];
343
344 ( R7 : 0, P5 : 0) = [ SP ++ ];
345 sp += 8; /* Skip orig_r0/orig_p0 */
346 csync;
347 SYSCFG = [sp++];
348 csync;
349.endm
350
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
new file mode 100644
index 000000000000..76103526aec1
--- /dev/null
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -0,0 +1,691 @@
1 /*
2 * File: include/asm-blackfin/mach-common/def_LPBlackfin.h
3 * Based on:
4 * Author: unknown
5 * COPYRIGHT 2005 Analog Devices
6 * Created: ?
7 * Description:
8 *
9 * Modified:
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING.
25 * If not, write to the Free Software Foundation,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532/33 */
30
31#ifndef _DEF_LPBLACKFIN_H
32#define _DEF_LPBLACKFIN_H
33
34#include <asm/mach/anomaly.h>
35
36/*#if !defined(__ADSPLPBLACKFIN__)
37#warning def_LPBlackfin.h should only be included for 532 compatible chips.
38#endif
39*/
40
41#define MK_BMSK_(x) (1<<x)
42
43#if defined(ANOMALY_05000198)
44
45#define bfin_read16(addr) ({ unsigned __v; \
46 __asm__ __volatile__ ("NOP;\n\t"\
47 "%0 = w[%1] (z);\n\t"\
48 : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
49
50#define bfin_read32(addr) ({ unsigned __v; \
51 __asm__ __volatile__ ("NOP;\n\t"\
52 "%0 = [%1];\n\t"\
53 : "=d"(__v) : "a"(addr)); __v; })
54
55#define bfin_write16(addr,val) ({\
56 __asm__ __volatile__ ("NOP;\n\t"\
57 "w[%0] = %1;\n\t"\
58 : : "a"(addr) , "d"(val) : "memory");})
59
60#define bfin_write32(addr,val) ({\
61 __asm__ __volatile__ ("NOP;\n\t"\
62 "[%0] = %1;\n\t"\
63 : : "a"(addr) , "d"(val) : "memory");})
64
65#else
66
67#define bfin_read16(addr) ({ unsigned __v; \
68 __asm__ __volatile__ (\
69 "%0 = w[%1] (z);\n\t"\
70 : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
71
72#define bfin_read32(addr) ({ unsigned __v; \
73 __asm__ __volatile__ (\
74 "%0 = [%1];\n\t"\
75 : "=d"(__v) : "a"(addr)); __v; })
76
77#define bfin_write16(addr,val) ({\
78 __asm__ __volatile__ (\
79 "w[%0] = %1;\n\t"\
80 : : "a"(addr) , "d"(val) : "memory");})
81
82#define bfin_write32(addr,val) ({\
83 __asm__ __volatile__ (\
84 "[%0] = %1;\n\t"\
85 : : "a"(addr) , "d"(val) : "memory");})
86
87#endif
88
89/**************************************************
90 * System Register Bits
91 **************************************************/
92
93/**************************************************
94 * ASTAT register
95 **************************************************/
96
97/* definitions of ASTAT bit positions*/
98
99/*Result of last ALU0 or shifter operation is zero*/
100#define ASTAT_AZ_P 0x00000000
101/*Result of last ALU0 or shifter operation is negative*/
102#define ASTAT_AN_P 0x00000001
103/*Condition Code, used for holding comparison results*/
104#define ASTAT_CC_P 0x00000005
105/*Quotient Bit*/
106#define ASTAT_AQ_P 0x00000006
107/*Rounding mode, set for biased, clear for unbiased*/
108#define ASTAT_RND_MOD_P 0x00000008
109/*Result of last ALU0 operation generated a carry*/
110#define ASTAT_AC0_P 0x0000000C
111/*Result of last ALU0 operation generated a carry*/
112#define ASTAT_AC0_COPY_P 0x00000002
113/*Result of last ALU1 operation generated a carry*/
114#define ASTAT_AC1_P 0x0000000D
115/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
116#define ASTAT_AV0_P 0x00000010
117/*Sticky version of ASTAT_AV0 */
118#define ASTAT_AV0S_P 0x00000011
119/*Result of last MAC1 operation overflowed, sticky for MAC*/
120#define ASTAT_AV1_P 0x00000012
121/*Sticky version of ASTAT_AV1 */
122#define ASTAT_AV1S_P 0x00000013
123/*Result of last ALU0 or MAC0 operation overflowed*/
124#define ASTAT_V_P 0x00000018
125/*Result of last ALU0 or MAC0 operation overflowed*/
126#define ASTAT_V_COPY_P 0x00000003
127/*Sticky version of ASTAT_V*/
128#define ASTAT_VS_P 0x00000019
129
130/* Masks */
131
132/*Result of last ALU0 or shifter operation is zero*/
133#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
134/*Result of last ALU0 or shifter operation is negative*/
135#define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
136/*Result of last ALU0 operation generated a carry*/
137#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
138/*Result of last ALU0 operation generated a carry*/
139#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
140/*Result of last ALU0 operation generated a carry*/
141#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
142/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
143#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
144/*Result of last MAC1 operation overflowed, sticky for MAC*/
145#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
146/*Condition Code, used for holding comparison results*/
147#define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
148/*Quotient Bit*/
149#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
150/*Rounding mode, set for biased, clear for unbiased*/
151#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
152/*Overflow Bit*/
153#define ASTAT_V MK_BMSK_(ASTAT_V_P)
154/*Overflow Bit*/
155#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
156
157/**************************************************
158 * SEQSTAT register
159 **************************************************/
160
161/* Bit Positions */
162#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
163#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
164#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
165#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
166#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
167#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
168#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request,
169 * set by IDLE instruction.
170 */
171#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last
172 * reset was a software reset
173 * (=1)
174 */
175#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
176#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
177#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
178#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
179#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
180/* Masks */
181/* Exception cause */
182#define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
183 MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
184 MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
185 MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
186 MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
187 MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
188 0)
189
190/* Indicates whether the last reset was a software reset (=1) */
191#define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
192
193/* Last hw error cause */
194#define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
195 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
196 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
197 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
198 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
199 0)
200
201/* Translate bits to something useful */
202
203/* Last hw error cause */
204#define SEQSTAT_HWERRCAUSE_SHIFT (14)
205#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
206#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
207#define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
208#define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
209
210/**************************************************
211 * SYSCFG register
212 **************************************************/
213
214/* Bit Positions */
215#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when
216 * set it forces an exception
217 * for each instruction executed
218 */
219#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
220#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
221
222/* Masks */
223
224/* Supervisor single step, when set it forces an exception for each
225 *instruction executed
226 */
227#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
228/* Enable cycle counter (=1) */
229#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
230/* Self Nesting Interrupt Enable */
231#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
232/* Backward-compatibility for typos in prior releases */
233#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
234#define SYSCFG_CCCEN SYSCFG_CCEN
235
236/****************************************************
237 * Core MMR Register Map
238 ****************************************************/
239
240/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
241
242#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
243#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
244#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside
245 * Buffer Status
246 */
247#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
248#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside
249 * Buffer Fault Address
250 */
251#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside
252 * Buffer 0
253 */
254#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside
255 * Buffer 1
256 */
257#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside
258 * Buffer 2
259 */
260#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection
261 * Lookaside Buffer 3
262 */
263#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection
264 * Lookaside Buffer 4
265 */
266#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection
267 * Lookaside Buffer 5
268 */
269#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection
270 * Lookaside Buffer 6
271 */
272#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection
273 * Lookaside Buffer 7
274 */
275#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection
276 * Lookaside Buffer 8
277 */
278#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection
279 * Lookaside Buffer 9
280 */
281#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection
282 * Lookaside Buffer 10
283 */
284#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection
285 * Lookaside Buffer 11
286 */
287#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection
288 * Lookaside Buffer 12
289 */
290#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection
291 * Lookaside Buffer 13
292 */
293#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection
294 * Lookaside Buffer 14
295 */
296#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection
297 * Lookaside Buffer 15
298 */
299#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
300#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
301#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
302#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
303#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
304#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
305#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
306#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
307#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
308#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
309#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
310#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
311#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
312#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
313#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
314#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
315#define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */
316
317#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
318#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
319#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
320
321/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
322
323#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
324#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
325#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
326#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
327#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
328#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability
329 * Protection Lookaside Buffer 0
330 */
331#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability
332 * Protection Lookaside Buffer 1
333 */
334#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability
335 * Protection Lookaside Buffer 2
336 */
337#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability
338 * Protection Lookaside Buffer 3
339 */
340#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability
341 * Protection Lookaside Buffer 4
342 */
343#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability
344 * Protection Lookaside Buffer 5
345 */
346#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability
347 * Protection Lookaside Buffer 6
348 */
349#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability
350 * Protection Lookaside Buffer 7
351 */
352#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability
353 * Protection Lookaside Buffer 8
354 */
355#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability
356 * Protection Lookaside Buffer 9
357 */
358#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability
359 * Protection Lookaside Buffer 10
360 */
361#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability
362 * Protection Lookaside Buffer 11
363 */
364#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability
365 * Protection Lookaside Buffer 12
366 */
367#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability
368 * Protection Lookaside Buffer 13
369 */
370#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability
371 * Protection Lookaside Buffer 14
372 */
373#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability
374 * Protection Lookaside Buffer 15
375 */
376#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
377#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
378#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
379#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
380#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
381#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
382#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
383#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
384#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
385#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
386#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
387#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
388#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
389#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
390#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
391#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
392#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
393#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
394#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
395
396/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
397
398#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
399#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
400#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
401#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
402#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
403#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
404#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
405#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
406#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
407#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
408#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
409#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
410#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
411#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
412#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
413#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
414#define IMASK 0xFFE02104 /* Interrupt Mask Register */
415#define IPEND 0xFFE02108 /* Interrupt Pending Register */
416#define ILAT 0xFFE0210C /* Interrupt Latch Register */
417#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
418
419/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
420
421#define TCNTL 0xFFE03000 /* Core Timer Control Register */
422#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
423#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
424#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
425
426/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
427#define DSPID 0xFFE05000 /* DSP Processor ID Register for
428 * MP implementations
429 */
430
431#define DBGSTAT 0xFFE05008 /* Debug Status Register */
432
433/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
434
435#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
436#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
437#define TBUF 0xFFE06100 /* Trace Buffer */
438
439/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
440
441/* Watchpoint Instruction Address Control Register */
442#define WPIACTL 0xFFE07000
443/* Watchpoint Instruction Address Register 0 */
444#define WPIA0 0xFFE07040
445/* Watchpoint Instruction Address Register 1 */
446#define WPIA1 0xFFE07044
447/* Watchpoint Instruction Address Register 2 */
448#define WPIA2 0xFFE07048
449/* Watchpoint Instruction Address Register 3 */
450#define WPIA3 0xFFE0704C
451/* Watchpoint Instruction Address Register 4 */
452#define WPIA4 0xFFE07050
453/* Watchpoint Instruction Address Register 5 */
454#define WPIA5 0xFFE07054
455/* Watchpoint Instruction Address Count Register 0 */
456#define WPIACNT0 0xFFE07080
457/* Watchpoint Instruction Address Count Register 1 */
458#define WPIACNT1 0xFFE07084
459/* Watchpoint Instruction Address Count Register 2 */
460#define WPIACNT2 0xFFE07088
461/* Watchpoint Instruction Address Count Register 3 */
462#define WPIACNT3 0xFFE0708C
463/* Watchpoint Instruction Address Count Register 4 */
464#define WPIACNT4 0xFFE07090
465/* Watchpoint Instruction Address Count Register 5 */
466#define WPIACNT5 0xFFE07094
467/* Watchpoint Data Address Control Register */
468#define WPDACTL 0xFFE07100
469/* Watchpoint Data Address Register 0 */
470#define WPDA0 0xFFE07140
471/* Watchpoint Data Address Register 1 */
472#define WPDA1 0xFFE07144
473/* Watchpoint Data Address Count Value Register 0 */
474#define WPDACNT0 0xFFE07180
475/* Watchpoint Data Address Count Value Register 1 */
476#define WPDACNT1 0xFFE07184
477/* Watchpoint Status Register */
478#define WPSTAT 0xFFE07200
479
480/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
481
482/* Performance Monitor Control Register */
483#define PFCTL 0xFFE08000
484/* Performance Monitor Counter Register 0 */
485#define PFCNTR0 0xFFE08100
486/* Performance Monitor Counter Register 1 */
487#define PFCNTR1 0xFFE08104
488
489/****************************************************
490 * Core MMR Register Bits
491 ****************************************************/
492
493/**************************************************
494 * EVT registers (ILAT, IMASK, and IPEND).
495 **************************************************/
496
497/* Bit Positions */
498#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
499#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
500#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
501#define EVT_EVX_P 0x00000003 /* Exception bit position */
502#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
503#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
504#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
505#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
506#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
507#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
508#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
509#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
510#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
511#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
512#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
513#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
514
515/* Masks */
516#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
517#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
518#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
519#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
520#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
521#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
522#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
523#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
524#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
525#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
526#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
527#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
528#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
529#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
530#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
531#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
532
533/**************************************************
534 * DMEM_CONTROL Register
535 **************************************************/
536/* Bit Positions */
537#define ENDM_P 0x00 /* (doesn't really exist) Enable
538 *Data Memory L1
539 */
540#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
541
542#define ENDCPLB_P 0x01 /* Enable DCPLBS */
543#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
544#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
545#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
546#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
547#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
548#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
549#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
550#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
551
552/* Masks */
553#define ENDM 0x00000001 /* (doesn't really exist) Enable
554 * Data Memory L1
555 */
556#define ENDCPLB 0x00000002 /* Enable DCPLB */
557#define ASRAM_BSRAM 0x00000000
558#define ACACHE_BSRAM 0x00000008
559#define ACACHE_BCACHE 0x0000000C
560#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
561#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
562#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
563
564/* IMEM_CONTROL Register */
565/* Bit Positions */
566#define ENIM_P 0x00 /* Enable L1 Code Memory */
567#define IMCTL_ENIM_P 0x00 /* "" (older define) */
568#define ENICPLB_P 0x01 /* Enable ICPLB */
569#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
570#define IMC_P 0x02 /* Enable */
571#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as
572 * cache (0=SRAM)
573 */
574#define ILOC0_P 0x03 /* Lock Way 0 */
575#define ILOC1_P 0x04 /* Lock Way 1 */
576#define ILOC2_P 0x05 /* Lock Way 2 */
577#define ILOC3_P 0x06 /* Lock Way 3 */
578#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement
579 * Priority
580 */
581/* Masks */
582#define ENIM 0x00000001 /* Enable L1 Code Memory */
583#define ENICPLB 0x00000002 /* Enable ICPLB */
584#define IMC 0x00000004 /* Configure L1 code memory as
585 * cache (0=SRAM)
586 */
587#define ILOC0 0x00000008 /* Lock Way 0 */
588#define ILOC1 0x00000010 /* Lock Way 1 */
589#define ILOC2 0x00000020 /* Lock Way 2 */
590#define ILOC3 0x00000040 /* Lock Way 3 */
591#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement
592 * Priority
593 */
594
595/* TCNTL Masks */
596#define TMPWR 0x00000001 /* Timer Low Power Control,
597 * 0=low power mode, 1=active state
598 */
599#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
600#define TAUTORLD 0x00000004 /* Timer auto reload */
601#define TINT 0x00000008 /* Timer generated interrupt 0=no
602 * interrupt has been generated,
603 * 1=interrupt has been generated
604 * (sticky)
605 */
606
607/* DCPLB_DATA and ICPLB_DATA Registers */
608/* Bit Positions */
609#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
610#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry
611 * locked
612 */
613#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access
614 * allowed (user mode)
615 */
616/* Masks */
617#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
618#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry
619 * locked
620 */
621#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
622 * allowed (user mode)
623 */
624#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
625#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
626#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
627#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
628#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
629 * mapped to L1
630 */
631#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high
632 * priority port
633 */
634#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable
635 * in L1
636 */
637/* ICPLB_DATA only */
638#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line,
639 * 1=priority for non-replacement
640 */
641/* DCPLB_DATA only */
642#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write
643 * access allowed (user mode)
644 */
645#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write
646 * access allowed (supervisor mode)
647 */
648#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
649#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on
650 * write-through writes,
651 * 1= allocate cache lines on
652 * write-through writes.
653 */
654#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
655
656/* TBUFCTL Masks */
657#define TBUFPWR 0x0001
658#define TBUFEN 0x0002
659#define TBUFOVF 0x0004
660#define TBUFCMPLP_SINGLE 0x0008
661#define TBUFCMPLP_DOUBLE 0x0010
662#define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
663
664/* TBUFSTAT Masks */
665#define TBUFCNT 0x001F
666
667/* ITEST_COMMAND and DTEST_COMMAND Registers */
668/* Masks */
669#define TEST_READ 0x00000000 /* Read Access */
670#define TEST_WRITE 0x00000002 /* Write Access */
671#define TEST_TAG 0x00000000 /* Access TAG */
672#define TEST_DATA 0x00000004 /* Access DATA */
673#define TEST_DW0 0x00000000 /* Select Double Word 0 */
674#define TEST_DW1 0x00000008 /* Select Double Word 1 */
675#define TEST_DW2 0x00000010 /* Select Double Word 2 */
676#define TEST_DW3 0x00000018 /* Select Double Word 3 */
677#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
678#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
679#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
680#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
681#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
682#define TEST_WAY0 0x00000000 /* Access Way0 */
683#define TEST_WAY1 0x04000000 /* Access Way1 */
684/* ITEST_COMMAND only */
685#define TEST_WAY2 0x08000000 /* Access Way2 */
686#define TEST_WAY3 0x0C000000 /* Access Way3 */
687/* DTEST_COMMAND only */
688#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
689#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
690
691#endif /* _DEF_LPBLACKFIN_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 14:43:58 -0500