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-rw-r--r--include/asm-blackfin/mach-bf561/anomaly.h410
-rw-r--r--include/asm-blackfin/mach-bf561/bf561.h178
-rw-r--r--include/asm-blackfin/mach-bf561/blackfin.h2
-rw-r--r--include/asm-blackfin/mach-bf561/cdefBF561.h9
-rw-r--r--include/asm-blackfin/mach-bf561/defBF561.h1
-rw-r--r--include/asm-blackfin/mach-bf561/irq.h2
-rw-r--r--include/asm-blackfin/mach-bf561/mem_map.h24
-rw-r--r--include/asm-blackfin/mach-bf561/portmux.h2
8 files changed, 267 insertions, 361 deletions
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index f5b32d66517d..bed956456884 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -1,184 +1,256 @@
1
2/* 1/*
3 * File: include/asm-blackfin/mach-bf561/anomaly.h 2 * File: include/asm-blackfin/mach-bf561/anomaly.h
4 * Based on: 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
5 * Author:
6 *
7 * Created:
8 * Description:
9 *
10 * Rev:
11 *
12 * Modified:
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 * 4 *
16 * This program is free software; you can redistribute it and/or modify 5 * Copyright (C) 2004-2007 Analog Devices Inc.
17 * it under the terms of the GNU General Public License as published by 6 * Licensed under the GPL-2 or later.
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */ 7 */
31 8
32/* This file shoule be up to date with: 9/* This file shoule be up to date with:
33 * - Revision L, 10Aug2006; ADSP-BF561 Silicon Anomaly List 10 * - Revision N, March 28, 2007; ADSP-BF561 Silicon Anomaly List
34 */ 11 */
35 12
36#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
37#define _MACH_ANOMALY_H_ 14#define _MACH_ANOMALY_H_
38 15
39/* We do not support 0.1 or 0.4 silicon - sorry */ 16/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
40#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || defined(CONFIG_BF_REV_0_4)) 17#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
41#error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4 18# error Kernel will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
42#endif 19#endif
43 20
44/* Issues that are common to 0.5 and 0.3 silicon */ 21/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
45#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) 22#define ANOMALY_05000074 (1)
46#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in 23/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
47 slot1 and store of a P register in slot 2 is not 24#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
48 supported */ 25/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */
49#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not 26#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
50 updated at the same time. */ 27/* Testset instructions restricted to 32-bit aligned memory locations */
51#define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned 28#define ANOMALY_05000120 (1)
52 memory locations */ 29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
53#define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR 30#define ANOMALY_05000122 (1)
54 registers */ 31/* Erroneous exception when enabling cache */
55#define ANOMALY_05000127 /* Signbits instruction not functional under certain 32#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
56 conditions */ 33/* Signbits instruction not functional under certain conditions */
57#define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */ 34#define ANOMALY_05000127 (1)
58#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out 35/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
59 upper bits */ 36#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
60#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ 37/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
61#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame 38#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
62 syncs */ 39/* Stall in multi-unit DMA operations */
63#define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz 40#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
64 and higher devices */ 41/* Allowing the SPORT RX FIFO to fill will cause an overflow */
65#define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */ 42#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
66#define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */ 43/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
67#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not 44#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
68 functional */ 45/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
69#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the 46#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
70 shadow of a conditional branch */ 47/* DMA and TESTSET conflict when both are accessing external memory */
71#define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop 48#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
72 may cause bad instruction fetches */ 49/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
73#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on 50#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
74 external SPORT TX and RX clocks */ 51/* MDMA may lose the first few words of a descriptor chain */
75#define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */ 52#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
76#define ANOMALY_05000269 /* High I/O activity causes output voltage of internal 53/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
77 voltage regulator (VDDint) to increase */ 54#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
78#define ANOMALY_05000270 /* High I/O activity causes output voltage of internal 55/* IMDMA S1/D1 channel may stall */
79 voltage regulator (VDDint) to decrease */ 56#define ANOMALY_05000149 (1)
80#define ANOMALY_05000272 /* Certain data cache write through modes fail for 57/* DMA engine may lose data due to incorrect handshaking */
81 VDDint <=0.9V */ 58#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
82#define ANOMALY_05000274 /* Data cache write back to external synchronous memory 59/* DMA stalls when all three controllers read data from the same source */
83 may be lost */ 60#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
84#define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */ 61/* Execution stall when executing in L2 and doing external accesses */
85#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC 62#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
86 registers are interrupted */ 63/* Frame Delay in SPORT Multichannel Mode */
64#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
65/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
66#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
67/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
68#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
69/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
70#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
71/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
72#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
73/* A read from external memory may return a wrong value with data cache enabled */
74#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
75/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
76#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
77/* DMEM_CONTROL<12> is not set on Reset */
78#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
79/* SPORT transmit data is not gated by external frame sync in certain conditions */
80#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
81/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
82#define ANOMALY_05000166 (1)
83/* Turning Serial Ports on with External Frame Syncs */
84#define ANOMALY_05000167 (1)
85/* SDRAM auto-refresh and subsequent Power Ups */
86#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
87/* DATA CPLB page miss can result in lost write-through cache data writes */
88#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
89/* Boot-ROM code modifies SICA_IWRx wakeup registers */
90#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
91/* DSPID register values incorrect */
92#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
93/* DMA vs Core accesses to external memory */
94#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
95/* Cache Fill Buffer Data lost */
96#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
97/* Overlapping Sequencer and Memory Stalls */
98#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
99/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
100#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
101/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
102#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
103/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
104#define ANOMALY_05000180 (1)
105/* Disabling the PPI resets the PPI configuration registers */
106#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
107/* IMDMA does not operate to full speed for 600MHz and higher devices */
108#define ANOMALY_05000182 (1)
109/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */
110#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
111/* PPI TX Mode with 2 External Frame Syncs */
112#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
113/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */
114#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
115/* IMDMA Corrupted Data after a Halt */
116#define ANOMALY_05000187 (1)
117/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
118#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
119/* False Protection Exceptions */
120#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
121/* PPI not functional at core voltage < 1Volt */
122#define ANOMALY_05000190 (1)
123/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
124#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
125/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
126#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
127/* Restarting SPORT in Specific Modes May Cause Data Corruption */
128#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
129/* Failing MMR Accesses When Stalled by Preceding Memory Read */
130#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
131/* Current DMA Address Shows Wrong Value During Carry Fix */
132#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
133/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
134#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
135/* Possible Infinite Stall with Specific Dual-DAG Situation */
136#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
137/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
138#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
139/* Specific sequence that can cause DMA error or DMA stopping */
140#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
141/* Recovery from "Brown-Out" Condition */
142#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
143/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
144#define ANOMALY_05000208 (1)
145/* Speed Path in Computational Unit Affects Certain Instructions */
146#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
147/* UART TX Interrupt Masked Erroneously */
148#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
149/* NMI Event at Boot Time Results in Unpredictable State */
150#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
151/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
152#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
153/* Incorrect Pulse-Width of UART Start Bit */
154#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
155/* Scratchpad Memory Bank Reads May Return Incorrect Data */
156#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
157/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
158#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
159/* UART STB Bit Incorrectly Affects Receiver Setting */
160#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
161/* SPORT data transmit lines are incorrectly driven in multichannel mode */
162#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
163/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
164#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
165/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
166#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
167/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
168#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
169/* TESTSET operation forces stall on the other core */
170#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
171/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
172#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
173/* Exception Not Generated for MMR Accesses in Reserved Region */
174#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
175/* Maximum External Clock Speed for Timers */
176#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
177/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
178#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
179/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
180#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
181/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
182#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
183/* ICPLB_STATUS MMR Register May Be Corrupted */
184#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
185/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
186#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
187/* Stores To Data Cache May Be Lost */
188#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
189/* Hardware Loop Corrupted When Taking an ICPLB Exception */
190#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
191/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
192#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
193/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
194#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
195/* IMDMA destination IRQ status must be read prior to using IMDMA */
196#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
197/* IMDMA may corrupt data under certain conditions */
198#define ANOMALY_05000267 (1)
199/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
200#define ANOMALY_05000269 (1)
201/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
202#define ANOMALY_05000270 (1)
203/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
204#define ANOMALY_05000272 (1)
205/* Data cache write back to external synchronous memory may be lost */
206#define ANOMALY_05000274 (1)
207/* PPI Timing and Sampling Information Updates */
208#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
209/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
210#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
211/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
212#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
213/* False Hardware Error Exception When ISR Context Is Not Restored */
214#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
215/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
216#define ANOMALY_05000283 (1)
217/* A read will receive incorrect data under certain conditions */
218#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
219/* SPORTs May Receive Bad Data If FIFOs Fill Up */
220#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
221/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
222#define ANOMALY_05000301 (1)
223/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
224#define ANOMALY_05000302 (1)
225/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
226#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
227/* SCKELOW Bit Does Not Maintain State Through Hibernate */
228#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
229/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
230#define ANOMALY_05000310 (1)
231/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
232#define ANOMALY_05000312 (1)
233/* PPI Is Level-Sensitive on First Transfer */
234#define ANOMALY_05000313 (1)
235/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
236#define ANOMALY_05000315 (1)
237/* PF2 Output Remains Asserted After SPI Master Boot */
238#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
239/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */
240#define ANOMALY_05000323 (1)
241/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */
242#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
243/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */
244#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
245/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */
246#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
247/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
248#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
87 249
88#endif /* (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */ 250/* Anomalies that don't exist on this proc */
251#define ANOMALY_05000158 (0)
252#define ANOMALY_05000183 (0)
253#define ANOMALY_05000273 (0)
254#define ANOMALY_05000311 (0)
89 255
90#if (defined(CONFIG_BF_REV_0_5))
91#define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT
92 mode with external clock */
93#define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to
94 using IMDMA */
95#endif 256#endif
96
97#if (defined(CONFIG_BF_REV_0_3))
98#define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input)
99 Mode with 0 Frame Syncs */
100#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
101#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through
102 cache data writes */
103#define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */
104#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
105#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
106#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
107 accumulator saturation */
108#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
109 Purpose TX or RX modes */
110#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
111 registers */
112#define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with
113 External Frame Syncs */
114#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
115#define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits
116 (not a meaningful mode) */
117#define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer
118 Placement in Memory */
119#define ANOMALY_05000189 /* False Protection Exception */
120#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
121 when polarity setting is changed */
122#define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data
123 corruption */
124#define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding
125 memory read */
126#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
127 fix */
128#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
129 inactive channels in certain conditions */
130#define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG
131 situation */
132#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
133 allocate cache lines on reads only mode */
134#define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA
135 stopping */
136#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
137#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
138 instructions */
139#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
140#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
141 state */
142#define ANOMALY_05000220 /* Data Corruption with Cached External Memory and
143 Non-Cached On-Chip L2 Memory */
144#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
145#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
146 data */
147#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
148 Differences in certain Conditions */
149#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
150#define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in
151 multichannel mode */
152#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
153 hardware reset */
154#define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of
155 Control causes failures */
156#define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */
157#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
158 (TDM) mode in certain conditions */
159#define ANOMALY_05000251 /* Exception not generated for MMR accesses in
160 reserved region */
161#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
162#define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12
163 of the ICPLB Data registers differ */
164#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
165#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
166#define ANOMALY_05000262 /* Stores to data cache may be lost */
167#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB
168 exception */
169#define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second
170 to last instruction in hardware loop */
171#define ANOMALY_05000276 /* Timing requirements change for External Frame
172 Sync PPI Modes with non-zero PPI_DELAY */
173#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
174 DMA system instability */
175#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
176 not restored */
177#define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed
178 in a particular stage */
179#define ANOMALY_05000287 /* A read will receive incorrect data under certain
180 conditions */
181#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
182#endif
183
184#endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
index 96a5d3a47e45..17e1d5dcef02 100644
--- a/include/asm-blackfin/mach-bf561/bf561.h
+++ b/include/asm-blackfin/mach-bf561/bf561.h
@@ -73,13 +73,13 @@
73 */ 73 */
74 74
75 75
76#define BLKFIN_ISUBBANKS 4 76#define BFIN_ISUBBANKS 4
77#define BLKFIN_IWAYS 4 77#define BFIN_IWAYS 4
78#define BLKFIN_ILINES 32 78#define BFIN_ILINES 32
79 79
80#define BLKFIN_DSUBBANKS 4 80#define BFIN_DSUBBANKS 4
81#define BLKFIN_DWAYS 2 81#define BFIN_DWAYS 2
82#define BLKFIN_DLINES 64 82#define BFIN_DLINES 64
83 83
84#define WAY0_L 0x1 84#define WAY0_L 0x1
85#define WAY1_L 0x2 85#define WAY1_L 0x2
@@ -230,93 +230,6 @@
230 230
231#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002) 231#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
232 232
233#define MAX_VC 600000000
234#define MIN_VC 50000000
235
236/******************************* PLL Settings ********************************/
237#ifdef CONFIG_BFIN_KERNEL_CLOCK
238#if (CONFIG_VCO_MULT < 0)
239#error "VCO Multiplier is less than 0. Please select a different value"
240#endif
241
242#if (CONFIG_VCO_MULT == 0)
243#error "VCO Multiplier should be greater than 0. Please select a different value"
244#endif
245
246#ifndef CONFIG_CLKIN_HALF
247#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
248#else
249#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
250#endif
251
252#ifndef CONFIG_PLL_BYPASS
253#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
254#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
255#else
256#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
257#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
258#endif
259
260#if (CONFIG_SCLK_DIV < 1)
261#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
262#endif
263
264#if (CONFIG_SCLK_DIV > 15)
265#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
266#endif
267
268#if (CONFIG_CCLK_DIV != 1)
269#if (CONFIG_CCLK_DIV != 2)
270#if (CONFIG_CCLK_DIV != 4)
271#if (CONFIG_CCLK_DIV != 8)
272#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
273#endif
274#endif
275#endif
276#endif
277
278#if (CONFIG_VCO_HZ > MAX_VC)
279#error "VCO selected is more than maximum value. Please change the VCO multipler"
280#endif
281
282#if (CONFIG_SCLK_HZ > 133000000)
283#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
284#endif
285
286#if (CONFIG_SCLK_HZ < 27000000)
287#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
288#endif
289
290#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
291#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
292#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
293#error "Please select sclk less than cclk"
294#endif
295#endif
296#endif
297
298#if (CONFIG_CCLK_DIV == 1)
299#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
300#endif
301#if (CONFIG_CCLK_DIV == 2)
302#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
303#endif
304#if (CONFIG_CCLK_DIV == 4)
305#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
306#endif
307#if (CONFIG_CCLK_DIV == 8)
308#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
309#endif
310#ifndef CONFIG_CCLK_ACT_DIV
311#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
312#endif
313
314#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1)
315#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
316#endif
317
318#endif /* CONFIG_BFIN_KERNEL_CLOCK */
319
320#ifdef CONFIG_BF561 233#ifdef CONFIG_BF561
321#define CPU "BF561" 234#define CPU "BF561"
322#define CPUID 0x027bb000 235#define CPUID 0x027bb000
@@ -326,83 +239,4 @@
326#define CPUID 0x0 239#define CPUID 0x0
327#endif 240#endif
328 241
329#if (CONFIG_MEM_SIZE % 4)
330#error "SDRAM memory size must be a multiple of 4MB!"
331#endif
332#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
333#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
334#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
335#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
336
337/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
338
339#define ANOMALY_05000158_WORKAROUND 0x200
340#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
341#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
342 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
343#else /*Write Through */
344#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \
345 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
346#endif
347
348
349#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
350#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
351#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
352#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
353
354#define L2_MEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
355
356#define SIZE_1K 0x00000400 /* 1K */
357#define SIZE_4K 0x00001000 /* 4K */
358#define SIZE_1M 0x00100000 /* 1M */
359#define SIZE_4M 0x00400000 /* 4M */
360
361#define MAX_CPLBS (16 * 2)
362
363/*
364* Number of required data CPLB switchtable entries
365* MEMSIZE / 4 (we mostly install 4M page size CPLBs
366* approx 16 for smaller 1MB page size CPLBs for allignment purposes
367* 1 for L1 Data Memory
368* 1 for L2 Data Memory
369* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
370* 64 for ASYNC Memory
371*/
372
373
374#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 + 64) * 2)
375
376/*
377* Number of required instruction CPLB switchtable entries
378* MEMSIZE / 4 (we mostly install 4M page size CPLBs
379* approx 12 for smaller 1MB page size CPLBs for allignment purposes
380* 1 for L1 Instruction Memory
381* 1 for L2 Instruction Memory
382* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
383*/
384
385#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
386
387#if 0 /* comment by mhfan */
388/* Event Vector Table Address */
389#define EVT_EMULATION_ADDR 0xffe02000
390#define EVT_RESET_ADDR 0xffe02004
391#define EVT_NMI_ADDR 0xffe02008
392#define EVT_EXCEPTION_ADDR 0xffe0200c
393#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
394#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
395#define EVT_TIMER_ADDR 0xffe02018
396#define EVT_IVG7_ADDR 0xffe0201c
397#define EVT_IVG8_ADDR 0xffe02020
398#define EVT_IVG9_ADDR 0xffe02024
399#define EVT_IVG10_ADDR 0xffe02028
400#define EVT_IVG11_ADDR 0xffe0202c
401#define EVT_IVG12_ADDR 0xffe02030
402#define EVT_IVG13_ADDR 0xffe02034
403#define EVT_IVG14_ADDR 0xffe02038
404#define EVT_IVG15_ADDR 0xffe0203c
405#define EVT_OVERRIDE_ADDR 0xffe02100
406#endif /* comment by mhfan */
407
408#endif /* __MACH_BF561_H__ */ 242#endif /* __MACH_BF561_H__ */
diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h
index 2537c845e8b0..562aee39895c 100644
--- a/include/asm-blackfin/mach-bf561/blackfin.h
+++ b/include/asm-blackfin/mach-bf561/blackfin.h
@@ -38,7 +38,7 @@
38#include "defBF561.h" 38#include "defBF561.h"
39#include "anomaly.h" 39#include "anomaly.h"
40 40
41#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) 41#if !defined(__ASSEMBLY__)
42#include "cdefBF561.h" 42#include "cdefBF561.h"
43#endif 43#endif
44 44
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
index 73d4d65249cd..d667816486c0 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -31,11 +31,8 @@
31#ifndef _CDEF_BF561_H 31#ifndef _CDEF_BF561_H
32#define _CDEF_BF561_H 32#define _CDEF_BF561_H
33 33
34/* 34#include <asm/blackfin.h>
35#if !defined(__ADSPBF561__) 35
36#warning cdefBF561.h should only be included for BF561 chip.
37#endif
38*/
39/* include all Core registers and bit definitions */ 36/* include all Core registers and bit definitions */
40#include "defBF561.h" 37#include "defBF561.h"
41 38
@@ -67,7 +64,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
67 bfin_write32(SICA_IWR1, 0); 64 bfin_write32(SICA_IWR1, 0);
68 65
69 bfin_write16(VR_CTL, val); 66 bfin_write16(VR_CTL, val);
70 __builtin_bfin_ssync(); 67 SSYNC();
71 68
72 local_irq_save(flags); 69 local_irq_save(flags);
73 asm("IDLE;"); 70 asm("IDLE;");
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 0f2dc6e6335b..bf7dc4e00065 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -120,6 +120,7 @@
120#define UART_GCTL 0xFFC00424 /* Global Control Register */ 120#define UART_GCTL 0xFFC00424 /* Global Control Register */
121 121
122/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ 122/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
123#define SPI0_REGBASE 0xFFC00500
123#define SPI_CTL 0xFFC00500 /* SPI Control Register */ 124#define SPI_CTL 0xFFC00500 /* SPI Control Register */
124#define SPI_FLG 0xFFC00504 /* SPI Flag register */ 125#define SPI_FLG 0xFFC00504 /* SPI Flag register */
125#define SPI_STAT 0xFFC00508 /* SPI Status register */ 126#define SPI_STAT 0xFFC00508 /* SPI Status register */
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h
index a753ce720d74..12789927db3d 100644
--- a/include/asm-blackfin/mach-bf561/irq.h
+++ b/include/asm-blackfin/mach-bf561/irq.h
@@ -289,6 +289,8 @@
289#define IRQ_PF46 119 289#define IRQ_PF46 119
290#define IRQ_PF47 120 290#define IRQ_PF47 120
291 291
292#define GPIO_IRQ_BASE IRQ_PF0
293
292#ifdef CONFIG_IRQCHIP_DEMUX_GPIO 294#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
293#define NR_IRQS (IRQ_PF47 + 1) 295#define NR_IRQS (IRQ_PF47 + 1)
294#else 296#else
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h
index ebac9a8d838d..f7ac09cf2c3d 100644
--- a/include/asm-blackfin/mach-bf561/mem_map.h
+++ b/include/asm-blackfin/mach-bf561/mem_map.h
@@ -21,10 +21,10 @@
21 21
22/* Level 1 Memory */ 22/* Level 1 Memory */
23 23
24#ifdef CONFIG_BLKFIN_CACHE 24#ifdef CONFIG_BFIN_ICACHE
25#define BLKFIN_ICACHESIZE (16*1024) 25#define BFIN_ICACHESIZE (16*1024)
26#else 26#else
27#define BLKFIN_ICACHESIZE (0*1024) 27#define BFIN_ICACHESIZE (0*1024)
28#endif 28#endif
29 29
30/* Memory Map for ADSP-BF561 processors */ 30/* Memory Map for ADSP-BF561 processors */
@@ -36,29 +36,29 @@
36 36
37#define L1_CODE_LENGTH 0x4000 37#define L1_CODE_LENGTH 0x4000
38 38
39#ifdef CONFIG_BLKFIN_DCACHE 39#ifdef CONFIG_BFIN_DCACHE
40 40
41#ifdef CONFIG_BLKFIN_DCACHE_BANKA 41#ifdef CONFIG_BFIN_DCACHE_BANKA
42#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 42#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
43#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 43#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
44#define L1_DATA_B_LENGTH 0x8000 44#define L1_DATA_B_LENGTH 0x8000
45#define BLKFIN_DCACHESIZE (16*1024) 45#define BFIN_DCACHESIZE (16*1024)
46#define BLKFIN_DSUPBANKS 1 46#define BFIN_DSUPBANKS 1
47#else 47#else
48#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 48#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
49#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 49#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
50#define L1_DATA_B_LENGTH (0x8000 - 0x4000) 50#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
51#define BLKFIN_DCACHESIZE (32*1024) 51#define BFIN_DCACHESIZE (32*1024)
52#define BLKFIN_DSUPBANKS 2 52#define BFIN_DSUPBANKS 2
53#endif 53#endif
54 54
55#else 55#else
56#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 56#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
57#define L1_DATA_A_LENGTH 0x8000 57#define L1_DATA_A_LENGTH 0x8000
58#define L1_DATA_B_LENGTH 0x8000 58#define L1_DATA_B_LENGTH 0x8000
59#define BLKFIN_DCACHESIZE (0*1024) 59#define BFIN_DCACHESIZE (0*1024)
60#define BLKFIN_DSUPBANKS 0 60#define BFIN_DSUPBANKS 0
61#endif /*CONFIG_BLKFIN_DCACHE*/ 61#endif /*CONFIG_BFIN_DCACHE*/
62#endif 62#endif
63 63
64/* Level 2 Memory */ 64/* Level 2 Memory */
diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h
index 10d11d5ffe23..132ad31665e3 100644
--- a/include/asm-blackfin/mach-bf561/portmux.h
+++ b/include/asm-blackfin/mach-bf561/portmux.h
@@ -81,7 +81,7 @@
81#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1)) 81#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
82#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0)) 82#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
83#define P_SPI0_MOSI (P_DONTCARE) 83#define P_SPI0_MOSI (P_DONTCARE)
84#define P_SPI0_MIS0 (P_DONTCARE) 84#define P_SPI0_MISO (P_DONTCARE)
85#define P_SPI0_SCK (P_DONTCARE) 85#define P_SPI0_SCK (P_DONTCARE)
86 86
87#endif /* _MACH_PORTMUX_H_ */ 87#endif /* _MACH_PORTMUX_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 21:08:10 -0500