diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf561')
| -rw-r--r-- | include/asm-blackfin/mach-bf561/anomaly.h | 184 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf561/bf561.h | 408 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf561/bfin_serial_5xx.h | 108 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf561/blackfin.h | 52 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf561/cdefBF561.h | 1543 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf561/defBF561.h | 1717 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf561/dma.h | 35 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf561/irq.h | 450 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf561/mem_init.h | 322 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf561/mem_map.h | 75 |
10 files changed, 4894 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h new file mode 100644 index 000000000000..f5b32d66517d --- /dev/null +++ b/include/asm-blackfin/mach-bf561/anomaly.h | |||
| @@ -0,0 +1,184 @@ | |||
| 1 | |||
| 2 | /* | ||
| 3 | * File: include/asm-blackfin/mach-bf561/anomaly.h | ||
| 4 | * Based on: | ||
| 5 | * Author: | ||
| 6 | * | ||
| 7 | * Created: | ||
| 8 | * Description: | ||
| 9 | * | ||
| 10 | * Rev: | ||
| 11 | * | ||
| 12 | * Modified: | ||
| 13 | * | ||
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License as published by | ||
| 18 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; see the file COPYING. | ||
| 28 | * If not, write to the Free Software Foundation, | ||
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 30 | */ | ||
| 31 | |||
| 32 | /* This file shoule be up to date with: | ||
| 33 | * - Revision L, 10Aug2006; ADSP-BF561 Silicon Anomaly List | ||
| 34 | */ | ||
| 35 | |||
| 36 | #ifndef _MACH_ANOMALY_H_ | ||
| 37 | #define _MACH_ANOMALY_H_ | ||
| 38 | |||
| 39 | /* We do not support 0.1 or 0.4 silicon - sorry */ | ||
| 40 | #if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || defined(CONFIG_BF_REV_0_4)) | ||
| 41 | #error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4 | ||
| 42 | #endif | ||
| 43 | |||
| 44 | /* Issues that are common to 0.5 and 0.3 silicon */ | ||
| 45 | #if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) | ||
| 46 | #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in | ||
| 47 | slot1 and store of a P register in slot 2 is not | ||
| 48 | supported */ | ||
| 49 | #define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not | ||
| 50 | updated at the same time. */ | ||
| 51 | #define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned | ||
| 52 | memory locations */ | ||
| 53 | #define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR | ||
| 54 | registers */ | ||
| 55 | #define ANOMALY_05000127 /* Signbits instruction not functional under certain | ||
| 56 | conditions */ | ||
| 57 | #define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */ | ||
| 58 | #define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out | ||
| 59 | upper bits */ | ||
| 60 | #define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ | ||
| 61 | #define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame | ||
| 62 | syncs */ | ||
| 63 | #define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz | ||
| 64 | and higher devices */ | ||
| 65 | #define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */ | ||
| 66 | #define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */ | ||
| 67 | #define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not | ||
| 68 | functional */ | ||
| 69 | #define ANOMALY_05000245 /* Spurious Hardware Error from an access in the | ||
| 70 | shadow of a conditional branch */ | ||
| 71 | #define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop | ||
| 72 | may cause bad instruction fetches */ | ||
| 73 | #define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on | ||
| 74 | external SPORT TX and RX clocks */ | ||
| 75 | #define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */ | ||
| 76 | #define ANOMALY_05000269 /* High I/O activity causes output voltage of internal | ||
| 77 | voltage regulator (VDDint) to increase */ | ||
| 78 | #define ANOMALY_05000270 /* High I/O activity causes output voltage of internal | ||
| 79 | voltage regulator (VDDint) to decrease */ | ||
| 80 | #define ANOMALY_05000272 /* Certain data cache write through modes fail for | ||
| 81 | VDDint <=0.9V */ | ||
| 82 | #define ANOMALY_05000274 /* Data cache write back to external synchronous memory | ||
| 83 | may be lost */ | ||
| 84 | #define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */ | ||
| 85 | #define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC | ||
| 86 | registers are interrupted */ | ||
| 87 | |||
| 88 | #endif /* (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */ | ||
| 89 | |||
| 90 | #if (defined(CONFIG_BF_REV_0_5)) | ||
| 91 | #define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT | ||
| 92 | mode with external clock */ | ||
| 93 | #define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to | ||
| 94 | using IMDMA */ | ||
| 95 | #endif | ||
| 96 | |||
| 97 | #if (defined(CONFIG_BF_REV_0_3)) | ||
| 98 | #define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input) | ||
| 99 | Mode with 0 Frame Syncs */ | ||
| 100 | #define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */ | ||
| 101 | #define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through | ||
| 102 | cache data writes */ | ||
| 103 | #define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */ | ||
| 104 | #define ANOMALY_05000174 /* Cache Fill Buffer Data lost */ | ||
| 105 | #define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */ | ||
| 106 | #define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an | ||
| 107 | accumulator saturation */ | ||
| 108 | #define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General | ||
| 109 | Purpose TX or RX modes */ | ||
| 110 | #define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration | ||
| 111 | registers */ | ||
| 112 | #define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with | ||
| 113 | External Frame Syncs */ | ||
| 114 | #define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */ | ||
| 115 | #define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits | ||
| 116 | (not a meaningful mode) */ | ||
| 117 | #define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer | ||
| 118 | Placement in Memory */ | ||
| 119 | #define ANOMALY_05000189 /* False Protection Exception */ | ||
| 120 | #define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs | ||
| 121 | when polarity setting is changed */ | ||
| 122 | #define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data | ||
| 123 | corruption */ | ||
| 124 | #define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding | ||
| 125 | memory read */ | ||
| 126 | #define ANOMALY_05000199 /* DMA current address shows wrong value during carry | ||
| 127 | fix */ | ||
| 128 | #define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during | ||
| 129 | inactive channels in certain conditions */ | ||
| 130 | #define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG | ||
| 131 | situation */ | ||
| 132 | #define ANOMALY_05000204 /* Incorrect data read with write-through cache and | ||
| 133 | allocate cache lines on reads only mode */ | ||
| 134 | #define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA | ||
| 135 | stopping */ | ||
| 136 | #define ANOMALY_05000207 /* Recovery from "brown-out" condition */ | ||
| 137 | #define ANOMALY_05000209 /* Speed-Path in computational unit affects certain | ||
| 138 | instructions */ | ||
| 139 | #define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ | ||
| 140 | #define ANOMALY_05000219 /* NMI event at boot time results in unpredictable | ||
| 141 | state */ | ||
| 142 | #define ANOMALY_05000220 /* Data Corruption with Cached External Memory and | ||
| 143 | Non-Cached On-Chip L2 Memory */ | ||
| 144 | #define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ | ||
| 145 | #define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect | ||
| 146 | data */ | ||
| 147 | #define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate | ||
| 148 | Differences in certain Conditions */ | ||
| 149 | #define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ | ||
| 150 | #define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in | ||
| 151 | multichannel mode */ | ||
| 152 | #define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to | ||
| 153 | hardware reset */ | ||
| 154 | #define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of | ||
| 155 | Control causes failures */ | ||
| 156 | #define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */ | ||
| 157 | #define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel | ||
| 158 | (TDM) mode in certain conditions */ | ||
| 159 | #define ANOMALY_05000251 /* Exception not generated for MMR accesses in | ||
| 160 | reserved region */ | ||
| 161 | #define ANOMALY_05000253 /* Maximum external clock speed for Timers */ | ||
| 162 | #define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12 | ||
| 163 | of the ICPLB Data registers differ */ | ||
| 164 | #define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ | ||
| 165 | #define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ | ||
| 166 | #define ANOMALY_05000262 /* Stores to data cache may be lost */ | ||
| 167 | #define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB | ||
| 168 | exception */ | ||
| 169 | #define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second | ||
| 170 | to last instruction in hardware loop */ | ||
| 171 | #define ANOMALY_05000276 /* Timing requirements change for External Frame | ||
| 172 | Sync PPI Modes with non-zero PPI_DELAY */ | ||
| 173 | #define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause | ||
| 174 | DMA system instability */ | ||
| 175 | #define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is | ||
| 176 | not restored */ | ||
| 177 | #define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed | ||
| 178 | in a particular stage */ | ||
| 179 | #define ANOMALY_05000287 /* A read will receive incorrect data under certain | ||
| 180 | conditions */ | ||
| 181 | #define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */ | ||
| 182 | #endif | ||
| 183 | |||
| 184 | #endif /* _MACH_ANOMALY_H_ */ | ||
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h new file mode 100644 index 000000000000..96a5d3a47e45 --- /dev/null +++ b/include/asm-blackfin/mach-bf561/bf561.h | |||
| @@ -0,0 +1,408 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf561/bf561.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #ifndef __MACH_BF561_H__ | ||
| 31 | #define __MACH_BF561_H__ | ||
| 32 | |||
| 33 | #define SUPPORTED_REVID 0x3 | ||
| 34 | |||
| 35 | #define OFFSET_(x) ((x) & 0x0000FFFF) | ||
| 36 | #define L1_ISRAM 0xFFA00000 | ||
| 37 | #define L1_ISRAM_END 0xFFA04000 | ||
| 38 | #define DATA_BANKA_SRAM 0xFF800000 | ||
| 39 | #define DATA_BANKA_SRAM_END 0xFF804000 | ||
| 40 | #define DATA_BANKB_SRAM 0xFF900000 | ||
| 41 | #define DATA_BANKB_SRAM_END 0xFF904000 | ||
| 42 | #define L1_DSRAMA 0xFF800000 | ||
| 43 | #define L1_DSRAMA_END 0xFF804000 | ||
| 44 | #define L1_DSRAMB 0xFF900000 | ||
| 45 | #define L1_DSRAMB_END 0xFF904000 | ||
| 46 | #define L2_SRAM 0xFEB00000 | ||
| 47 | #define L2_SRAM_END 0xFEB20000 | ||
| 48 | #define AMB_FLASH 0x20000000 | ||
| 49 | #define AMB_FLASH_END 0x21000000 | ||
| 50 | #define AMB_FLASH_LENGTH 0x01000000 | ||
| 51 | #define L1_ISRAM_LENGTH 0x4000 | ||
| 52 | #define L1_DSRAMA_LENGTH 0x4000 | ||
| 53 | #define L1_DSRAMB_LENGTH 0x4000 | ||
| 54 | #define L2_SRAM_LENGTH 0x20000 | ||
| 55 | |||
| 56 | /*some misc defines*/ | ||
| 57 | #define IMASK_IVG15 0x8000 | ||
| 58 | #define IMASK_IVG14 0x4000 | ||
| 59 | #define IMASK_IVG13 0x2000 | ||
| 60 | #define IMASK_IVG12 0x1000 | ||
| 61 | |||
| 62 | #define IMASK_IVG11 0x0800 | ||
| 63 | #define IMASK_IVG10 0x0400 | ||
| 64 | #define IMASK_IVG9 0x0200 | ||
| 65 | #define IMASK_IVG8 0x0100 | ||
| 66 | |||
| 67 | #define IMASK_IVG7 0x0080 | ||
| 68 | #define IMASK_IVGTMR 0x0040 | ||
| 69 | #define IMASK_IVGHW 0x0020 | ||
| 70 | |||
| 71 | /*************************** | ||
| 72 | * Blackfin Cache setup | ||
| 73 | */ | ||
| 74 | |||
| 75 | |||
| 76 | #define BLKFIN_ISUBBANKS 4 | ||
| 77 | #define BLKFIN_IWAYS 4 | ||
| 78 | #define BLKFIN_ILINES 32 | ||
| 79 | |||
| 80 | #define BLKFIN_DSUBBANKS 4 | ||
| 81 | #define BLKFIN_DWAYS 2 | ||
| 82 | #define BLKFIN_DLINES 64 | ||
| 83 | |||
| 84 | #define WAY0_L 0x1 | ||
| 85 | #define WAY1_L 0x2 | ||
| 86 | #define WAY01_L 0x3 | ||
| 87 | #define WAY2_L 0x4 | ||
| 88 | #define WAY02_L 0x5 | ||
| 89 | #define WAY12_L 0x6 | ||
| 90 | #define WAY012_L 0x7 | ||
| 91 | |||
| 92 | #define WAY3_L 0x8 | ||
| 93 | #define WAY03_L 0x9 | ||
| 94 | #define WAY13_L 0xA | ||
| 95 | #define WAY013_L 0xB | ||
| 96 | |||
| 97 | #define WAY32_L 0xC | ||
| 98 | #define WAY320_L 0xD | ||
| 99 | #define WAY321_L 0xE | ||
| 100 | #define WAYALL_L 0xF | ||
| 101 | |||
| 102 | #define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ | ||
| 103 | |||
| 104 | /* IAR0 BIT FIELDS */ | ||
| 105 | #define PLL_WAKEUP_BIT 0xFFFFFFFF | ||
| 106 | #define DMA1_ERROR_BIT 0xFFFFFF0F | ||
| 107 | #define DMA2_ERROR_BIT 0xFFFFF0FF | ||
| 108 | #define IMDMA_ERROR_BIT 0xFFFF0FFF | ||
| 109 | #define PPI1_ERROR_BIT 0xFFF0FFFF | ||
| 110 | #define PPI2_ERROR_BIT 0xFF0FFFFF | ||
| 111 | #define SPORT0_ERROR_BIT 0xF0FFFFFF | ||
| 112 | #define SPORT1_ERROR_BIT 0x0FFFFFFF | ||
| 113 | /* IAR1 BIT FIELDS */ | ||
| 114 | #define SPI_ERROR_BIT 0xFFFFFFFF | ||
| 115 | #define UART_ERROR_BIT 0xFFFFFF0F | ||
| 116 | #define RESERVED_ERROR_BIT 0xFFFFF0FF | ||
| 117 | #define DMA1_0_BIT 0xFFFF0FFF | ||
| 118 | #define DMA1_1_BIT 0xFFF0FFFF | ||
| 119 | #define DMA1_2_BIT 0xFF0FFFFF | ||
| 120 | #define DMA1_3_BIT 0xF0FFFFFF | ||
| 121 | #define DMA1_4_BIT 0x0FFFFFFF | ||
| 122 | /* IAR2 BIT FIELDS */ | ||
| 123 | #define DMA1_5_BIT 0xFFFFFFFF | ||
| 124 | #define DMA1_6_BIT 0xFFFFFF0F | ||
| 125 | #define DMA1_7_BIT 0xFFFFF0FF | ||
| 126 | #define DMA1_8_BIT 0xFFFF0FFF | ||
| 127 | #define DMA1_9_BIT 0xFFF0FFFF | ||
| 128 | #define DMA1_10_BIT 0xFF0FFFFF | ||
| 129 | #define DMA1_11_BIT 0xF0FFFFFF | ||
| 130 | #define DMA2_0_BIT 0x0FFFFFFF | ||
| 131 | /* IAR3 BIT FIELDS */ | ||
| 132 | #define DMA2_1_BIT 0xFFFFFFFF | ||
| 133 | #define DMA2_2_BIT 0xFFFFFF0F | ||
| 134 | #define DMA2_3_BIT 0xFFFFF0FF | ||
| 135 | #define DMA2_4_BIT 0xFFFF0FFF | ||
| 136 | #define DMA2_5_BIT 0xFFF0FFFF | ||
| 137 | #define DMA2_6_BIT 0xFF0FFFFF | ||
| 138 | #define DMA2_7_BIT 0xF0FFFFFF | ||
| 139 | #define DMA2_8_BIT 0x0FFFFFFF | ||
| 140 | /* IAR4 BIT FIELDS */ | ||
| 141 | #define DMA2_9_BIT 0xFFFFFFFF | ||
| 142 | #define DMA2_10_BIT 0xFFFFFF0F | ||
| 143 | #define DMA2_11_BIT 0xFFFFF0FF | ||
| 144 | #define TIMER0_BIT 0xFFFF0FFF | ||
| 145 | #define TIMER1_BIT 0xFFF0FFFF | ||
| 146 | #define TIMER2_BIT 0xFF0FFFFF | ||
| 147 | #define TIMER3_BIT 0xF0FFFFFF | ||
| 148 | #define TIMER4_BIT 0x0FFFFFFF | ||
| 149 | /* IAR5 BIT FIELDS */ | ||
| 150 | #define TIMER5_BIT 0xFFFFFFFF | ||
| 151 | #define TIMER6_BIT 0xFFFFFF0F | ||
| 152 | #define TIMER7_BIT 0xFFFFF0FF | ||
| 153 | #define TIMER8_BIT 0xFFFF0FFF | ||
| 154 | #define TIMER9_BIT 0xFFF0FFFF | ||
| 155 | #define TIMER10_BIT 0xFF0FFFFF | ||
| 156 | #define TIMER11_BIT 0xF0FFFFFF | ||
| 157 | #define PROG0_INTA_BIT 0x0FFFFFFF | ||
| 158 | /* IAR6 BIT FIELDS */ | ||
| 159 | #define PROG0_INTB_BIT 0xFFFFFFFF | ||
| 160 | #define PROG1_INTA_BIT 0xFFFFFF0F | ||
| 161 | #define PROG1_INTB_BIT 0xFFFFF0FF | ||
| 162 | #define PROG2_INTA_BIT 0xFFFF0FFF | ||
| 163 | #define PROG2_INTB_BIT 0xFFF0FFFF | ||
| 164 | #define DMA1_WRRD0_BIT 0xFF0FFFFF | ||
| 165 | #define DMA1_WRRD1_BIT 0xF0FFFFFF | ||
| 166 | #define DMA2_WRRD0_BIT 0x0FFFFFFF | ||
| 167 | /* IAR7 BIT FIELDS */ | ||
| 168 | #define DMA2_WRRD1_BIT 0xFFFFFFFF | ||
| 169 | #define IMDMA_WRRD0_BIT 0xFFFFFF0F | ||
| 170 | #define IMDMA_WRRD1_BIT 0xFFFFF0FF | ||
| 171 | #define WATCH_BIT 0xFFFF0FFF | ||
| 172 | #define RESERVED_1_BIT 0xFFF0FFFF | ||
| 173 | #define RESERVED_2_BIT 0xFF0FFFFF | ||
| 174 | #define SUPPLE_0_BIT 0xF0FFFFFF | ||
| 175 | #define SUPPLE_1_BIT 0x0FFFFFFF | ||
| 176 | |||
| 177 | /* Miscellaneous Values */ | ||
| 178 | |||
| 179 | /****************************** EBIU Settings ********************************/ | ||
| 180 | #define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) | ||
| 181 | #define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) | ||
| 182 | |||
| 183 | #if defined(CONFIG_C_AMBEN_ALL) | ||
| 184 | #define V_AMBEN AMBEN_ALL | ||
| 185 | #elif defined(CONFIG_C_AMBEN) | ||
| 186 | #define V_AMBEN 0x0 | ||
| 187 | #elif defined(CONFIG_C_AMBEN_B0) | ||
| 188 | #define V_AMBEN AMBEN_B0 | ||
| 189 | #elif defined(CONFIG_C_AMBEN_B0_B1) | ||
| 190 | #define V_AMBEN AMBEN_B0_B1 | ||
| 191 | #elif defined(CONFIG_C_AMBEN_B0_B1_B2) | ||
| 192 | #define V_AMBEN AMBEN_B0_B1_B2 | ||
| 193 | #endif | ||
| 194 | |||
| 195 | #ifdef CONFIG_C_AMCKEN | ||
| 196 | #define V_AMCKEN AMCKEN | ||
| 197 | #else | ||
| 198 | #define V_AMCKEN 0x0 | ||
| 199 | #endif | ||
| 200 | |||
| 201 | #ifdef CONFIG_C_B0PEN | ||
| 202 | #define V_B0PEN 0x10 | ||
| 203 | #else | ||
| 204 | #define V_B0PEN 0x00 | ||
| 205 | #endif | ||
| 206 | |||
| 207 | #ifdef CONFIG_C_B1PEN | ||
| 208 | #define V_B1PEN 0x20 | ||
| 209 | #else | ||
| 210 | #define V_B1PEN 0x00 | ||
| 211 | #endif | ||
| 212 | |||
| 213 | #ifdef CONFIG_C_B2PEN | ||
| 214 | #define V_B2PEN 0x40 | ||
| 215 | #else | ||
| 216 | #define V_B2PEN 0x00 | ||
| 217 | #endif | ||
| 218 | |||
| 219 | #ifdef CONFIG_C_B3PEN | ||
| 220 | #define V_B3PEN 0x80 | ||
| 221 | #else | ||
| 222 | #define V_B3PEN 0x00 | ||
| 223 | #endif | ||
| 224 | |||
| 225 | #ifdef CONFIG_C_CDPRIO | ||
| 226 | #define V_CDPRIO 0x100 | ||
| 227 | #else | ||
| 228 | #define V_CDPRIO 0x0 | ||
| 229 | #endif | ||
| 230 | |||
| 231 | #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002) | ||
| 232 | |||
| 233 | #define MAX_VC 600000000 | ||
| 234 | #define MIN_VC 50000000 | ||
| 235 | |||
| 236 | /******************************* PLL Settings ********************************/ | ||
| 237 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | ||
| 238 | #if (CONFIG_VCO_MULT < 0) | ||
| 239 | #error "VCO Multiplier is less than 0. Please select a different value" | ||
| 240 | #endif | ||
| 241 | |||
| 242 | #if (CONFIG_VCO_MULT == 0) | ||
| 243 | #error "VCO Multiplier should be greater than 0. Please select a different value" | ||
| 244 | #endif | ||
| 245 | |||
| 246 | #ifndef CONFIG_CLKIN_HALF | ||
| 247 | #define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) | ||
| 248 | #else | ||
| 249 | #define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) | ||
| 250 | #endif | ||
| 251 | |||
| 252 | #ifndef CONFIG_PLL_BYPASS | ||
| 253 | #define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) | ||
| 254 | #define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) | ||
| 255 | #else | ||
| 256 | #define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ | ||
| 257 | #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ | ||
| 258 | #endif | ||
| 259 | |||
| 260 | #if (CONFIG_SCLK_DIV < 1) | ||
| 261 | #error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" | ||
| 262 | #endif | ||
| 263 | |||
| 264 | #if (CONFIG_SCLK_DIV > 15) | ||
| 265 | #error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" | ||
| 266 | #endif | ||
| 267 | |||
| 268 | #if (CONFIG_CCLK_DIV != 1) | ||
| 269 | #if (CONFIG_CCLK_DIV != 2) | ||
| 270 | #if (CONFIG_CCLK_DIV != 4) | ||
| 271 | #if (CONFIG_CCLK_DIV != 8) | ||
| 272 | #error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value" | ||
| 273 | #endif | ||
| 274 | #endif | ||
| 275 | #endif | ||
| 276 | #endif | ||
| 277 | |||
| 278 | #if (CONFIG_VCO_HZ > MAX_VC) | ||
| 279 | #error "VCO selected is more than maximum value. Please change the VCO multipler" | ||
| 280 | #endif | ||
| 281 | |||
| 282 | #if (CONFIG_SCLK_HZ > 133000000) | ||
| 283 | #error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" | ||
| 284 | #endif | ||
| 285 | |||
| 286 | #if (CONFIG_SCLK_HZ < 27000000) | ||
| 287 | #error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" | ||
| 288 | #endif | ||
| 289 | |||
| 290 | #if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ) | ||
| 291 | #if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) | ||
| 292 | #if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) | ||
| 293 | #error "Please select sclk less than cclk" | ||
| 294 | #endif | ||
| 295 | #endif | ||
| 296 | #endif | ||
| 297 | |||
| 298 | #if (CONFIG_CCLK_DIV == 1) | ||
| 299 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV1 | ||
| 300 | #endif | ||
| 301 | #if (CONFIG_CCLK_DIV == 2) | ||
| 302 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV2 | ||
| 303 | #endif | ||
| 304 | #if (CONFIG_CCLK_DIV == 4) | ||
| 305 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV4 | ||
| 306 | #endif | ||
| 307 | #if (CONFIG_CCLK_DIV == 8) | ||
| 308 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV8 | ||
| 309 | #endif | ||
| 310 | #ifndef CONFIG_CCLK_ACT_DIV | ||
| 311 | #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly | ||
| 312 | #endif | ||
| 313 | |||
| 314 | #if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1) | ||
| 315 | #error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK | ||
| 316 | #endif | ||
| 317 | |||
| 318 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ | ||
| 319 | |||
| 320 | #ifdef CONFIG_BF561 | ||
| 321 | #define CPU "BF561" | ||
| 322 | #define CPUID 0x027bb000 | ||
| 323 | #endif | ||
| 324 | #ifndef CPU | ||
| 325 | #define CPU "UNKNOWN" | ||
| 326 | #define CPUID 0x0 | ||
| 327 | #endif | ||
| 328 | |||
| 329 | #if (CONFIG_MEM_SIZE % 4) | ||
| 330 | #error "SDRAM memory size must be a multiple of 4MB!" | ||
| 331 | #endif | ||
| 332 | #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) | ||
| 333 | #define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) | ||
| 334 | #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) | ||
| 335 | #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) | ||
| 336 | |||
| 337 | /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ | ||
| 338 | |||
| 339 | #define ANOMALY_05000158_WORKAROUND 0x200 | ||
| 340 | #ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ | ||
| 341 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ | ||
| 342 | | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) | ||
| 343 | #else /*Write Through */ | ||
| 344 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \ | ||
| 345 | | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) | ||
| 346 | #endif | ||
| 347 | |||
| 348 | |||
| 349 | #define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) | ||
| 350 | #define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY) | ||
| 351 | #define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY) | ||
| 352 | #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) | ||
| 353 | |||
| 354 | #define L2_MEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY) | ||
| 355 | |||
| 356 | #define SIZE_1K 0x00000400 /* 1K */ | ||
| 357 | #define SIZE_4K 0x00001000 /* 4K */ | ||
| 358 | #define SIZE_1M 0x00100000 /* 1M */ | ||
| 359 | #define SIZE_4M 0x00400000 /* 4M */ | ||
| 360 | |||
| 361 | #define MAX_CPLBS (16 * 2) | ||
| 362 | |||
| 363 | /* | ||
| 364 | * Number of required data CPLB switchtable entries | ||
| 365 | * MEMSIZE / 4 (we mostly install 4M page size CPLBs | ||
| 366 | * approx 16 for smaller 1MB page size CPLBs for allignment purposes | ||
| 367 | * 1 for L1 Data Memory | ||
| 368 | * 1 for L2 Data Memory | ||
| 369 | * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO | ||
| 370 | * 64 for ASYNC Memory | ||
| 371 | */ | ||
| 372 | |||
| 373 | |||
| 374 | #define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 + 64) * 2) | ||
| 375 | |||
| 376 | /* | ||
| 377 | * Number of required instruction CPLB switchtable entries | ||
| 378 | * MEMSIZE / 4 (we mostly install 4M page size CPLBs | ||
| 379 | * approx 12 for smaller 1MB page size CPLBs for allignment purposes | ||
| 380 | * 1 for L1 Instruction Memory | ||
| 381 | * 1 for L2 Instruction Memory | ||
| 382 | * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO | ||
| 383 | */ | ||
| 384 | |||
| 385 | #define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2) | ||
| 386 | |||
| 387 | #if 0 /* comment by mhfan */ | ||
| 388 | /* Event Vector Table Address */ | ||
| 389 | #define EVT_EMULATION_ADDR 0xffe02000 | ||
| 390 | #define EVT_RESET_ADDR 0xffe02004 | ||
| 391 | #define EVT_NMI_ADDR 0xffe02008 | ||
| 392 | #define EVT_EXCEPTION_ADDR 0xffe0200c | ||
| 393 | #define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 | ||
| 394 | #define EVT_HARDWARE_ERROR_ADDR 0xffe02014 | ||
| 395 | #define EVT_TIMER_ADDR 0xffe02018 | ||
| 396 | #define EVT_IVG7_ADDR 0xffe0201c | ||
| 397 | #define EVT_IVG8_ADDR 0xffe02020 | ||
| 398 | #define EVT_IVG9_ADDR 0xffe02024 | ||
| 399 | #define EVT_IVG10_ADDR 0xffe02028 | ||
| 400 | #define EVT_IVG11_ADDR 0xffe0202c | ||
| 401 | #define EVT_IVG12_ADDR 0xffe02030 | ||
| 402 | #define EVT_IVG13_ADDR 0xffe02034 | ||
| 403 | #define EVT_IVG14_ADDR 0xffe02038 | ||
| 404 | #define EVT_IVG15_ADDR 0xffe0203c | ||
| 405 | #define EVT_OVERRIDE_ADDR 0xffe02100 | ||
| 406 | #endif /* comment by mhfan */ | ||
| 407 | |||
| 408 | #endif /* __MACH_BF561_H__ */ | ||
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h new file mode 100644 index 000000000000..23bf76aa3451 --- /dev/null +++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h | |||
| @@ -0,0 +1,108 @@ | |||
| 1 | #include <linux/serial.h> | ||
| 2 | #include <asm/dma.h> | ||
| 3 | |||
| 4 | #define NR_PORTS 1 | ||
| 5 | |||
| 6 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | ||
| 7 | #define OFFSET_RBR 0x00 /* Receive Buffer register */ | ||
| 8 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ | ||
| 9 | #define OFFSET_IER 0x04 /* Interrupt Enable Register */ | ||
| 10 | #define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ | ||
| 11 | #define OFFSET_IIR 0x08 /* Interrupt Identification Register */ | ||
| 12 | #define OFFSET_LCR 0x0C /* Line Control Register */ | ||
| 13 | #define OFFSET_MCR 0x10 /* Modem Control Register */ | ||
| 14 | #define OFFSET_LSR 0x14 /* Line Status Register */ | ||
| 15 | #define OFFSET_MSR 0x18 /* Modem Status Register */ | ||
| 16 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | ||
| 17 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | ||
| 18 | |||
| 19 | #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) | ||
| 20 | #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) | ||
| 21 | #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) | ||
| 22 | #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) | ||
| 23 | #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) | ||
| 24 | #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) | ||
| 25 | #define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) | ||
| 26 | #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) | ||
| 27 | |||
| 28 | #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) | ||
| 29 | #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) | ||
| 30 | #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) | ||
| 31 | #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) | ||
| 32 | #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) | ||
| 33 | #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) | ||
| 34 | |||
| 35 | #ifdef CONFIG_BFIN_UART0_CTSRTS | ||
| 36 | # define CONFIG_SERIAL_BFIN_CTSRTS | ||
| 37 | # ifndef CONFIG_UART0_CTS_PIN | ||
| 38 | # define CONFIG_UART0_CTS_PIN -1 | ||
| 39 | # endif | ||
| 40 | # ifndef CONFIG_UART0_RTS_PIN | ||
| 41 | # define CONFIG_UART0_RTS_PIN -1 | ||
| 42 | # endif | ||
| 43 | #endif | ||
| 44 | |||
| 45 | struct bfin_serial_port { | ||
| 46 | struct uart_port port; | ||
| 47 | unsigned int old_status; | ||
| 48 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
| 49 | int tx_done; | ||
| 50 | int tx_count; | ||
| 51 | struct circ_buf rx_dma_buf; | ||
| 52 | struct timer_list rx_dma_timer; | ||
| 53 | int rx_dma_nrows; | ||
| 54 | unsigned int tx_dma_channel; | ||
| 55 | unsigned int rx_dma_channel; | ||
| 56 | struct work_struct tx_dma_workqueue; | ||
| 57 | #else | ||
| 58 | struct work_struct cts_workqueue; | ||
| 59 | #endif | ||
| 60 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | ||
| 61 | int cts_pin; | ||
| 62 | int rts_pin; | ||
| 63 | #endif | ||
| 64 | }; | ||
| 65 | |||
| 66 | struct bfin_serial_port bfin_serial_ports[NR_PORTS]; | ||
| 67 | struct bfin_serial_res { | ||
| 68 | unsigned long uart_base_addr; | ||
| 69 | int uart_irq; | ||
| 70 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
| 71 | unsigned int uart_tx_dma_channel; | ||
| 72 | unsigned int uart_rx_dma_channel; | ||
| 73 | #endif | ||
| 74 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | ||
| 75 | int uart_cts_pin; | ||
| 76 | int uart_rts_pin; | ||
| 77 | #endif | ||
| 78 | }; | ||
| 79 | |||
| 80 | struct bfin_serial_res bfin_serial_resource[] = { | ||
| 81 | 0xFFC00400, | ||
| 82 | IRQ_UART_RX, | ||
| 83 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
| 84 | CH_UART_TX, | ||
| 85 | CH_UART_RX, | ||
| 86 | #endif | ||
| 87 | #ifdef CONFIG_BFIN_UART0_CTSRTS | ||
| 88 | CONFIG_UART0_CTS_PIN, | ||
| 89 | CONFIG_UART0_RTS_PIN, | ||
| 90 | #endif | ||
| 91 | }; | ||
| 92 | |||
| 93 | |||
| 94 | int nr_ports = NR_PORTS; | ||
| 95 | static void bfin_serial_hw_init(struct bfin_serial_port *uart) | ||
| 96 | { | ||
| 97 | |||
| 98 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | ||
| 99 | if (uart->cts_pin >= 0) { | ||
| 100 | gpio_request(uart->cts_pin, NULL); | ||
| 101 | gpio_direction_input(uart->cts_pin); | ||
| 102 | } | ||
| 103 | if (uart->rts_pin >= 0) { | ||
| 104 | gpio_request(uart->rts_pin, NULL); | ||
| 105 | gpio_direction_input(uart->rts_pin); | ||
| 106 | } | ||
| 107 | #endif | ||
| 108 | } | ||
diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h new file mode 100644 index 000000000000..2537c845e8b0 --- /dev/null +++ b/include/asm-blackfin/mach-bf561/blackfin.h | |||
| @@ -0,0 +1,52 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf561/blackfin.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef _MACH_BLACKFIN_H_ | ||
| 32 | #define _MACH_BLACKFIN_H_ | ||
| 33 | |||
| 34 | #define BF561_FAMILY | ||
| 35 | |||
| 36 | #include "bf561.h" | ||
| 37 | #include "mem_map.h" | ||
| 38 | #include "defBF561.h" | ||
| 39 | #include "anomaly.h" | ||
| 40 | |||
| 41 | #if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) | ||
| 42 | #include "cdefBF561.h" | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D() | ||
| 46 | #define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val) | ||
| 47 | #define bfin_read_FIO_DIR() bfin_read_FIO0_DIR() | ||
| 48 | #define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val) | ||
| 49 | #define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() | ||
| 50 | #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) | ||
| 51 | |||
| 52 | #endif /* _MACH_BLACKFIN_H_ */ | ||
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h new file mode 100644 index 000000000000..5dc0ed835447 --- /dev/null +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h | |||
| @@ -0,0 +1,1543 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf561/cdefBF561.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef _CDEF_BF561_H | ||
| 32 | #define _CDEF_BF561_H | ||
| 33 | |||
| 34 | /* | ||
| 35 | #if !defined(__ADSPBF561__) | ||
| 36 | #warning cdefBF561.h should only be included for BF561 chip. | ||
| 37 | #endif | ||
| 38 | */ | ||
| 39 | /* include all Core registers and bit definitions */ | ||
| 40 | #include "defBF561.h" | ||
| 41 | |||
| 42 | /*include core specific register pointer definitions*/ | ||
| 43 | #include <asm/mach-common/cdef_LPBlackfin.h> | ||
| 44 | |||
| 45 | #include <asm/system.h> | ||
| 46 | |||
| 47 | /*********************************************************************************** */ | ||
| 48 | /* System MMR Register Map */ | ||
| 49 | /*********************************************************************************** */ | ||
| 50 | |||
| 51 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | ||
| 52 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | ||
| 53 | #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) | ||
| 54 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) | ||
| 55 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) | ||
| 56 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | ||
| 57 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| 58 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| 59 | { | ||
| 60 | unsigned long flags, iwr; | ||
| 61 | |||
| 62 | bfin_write16(VR_CTL, val); | ||
| 63 | __builtin_bfin_ssync(); | ||
| 64 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 65 | iwr = bfin_read32(SICA_IWR0); | ||
| 66 | /* Only allow PPL Wakeup) */ | ||
| 67 | bfin_write32(SICA_IWR0, IWR_ENABLE(0)); | ||
| 68 | local_irq_save(flags); | ||
| 69 | asm("IDLE;"); | ||
| 70 | local_irq_restore(flags); | ||
| 71 | bfin_write32(SICA_IWR0, iwr); | ||
| 72 | } | ||
| 73 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) | ||
| 74 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) | ||
| 75 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | ||
| 76 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) | ||
| 77 | #define bfin_read_CHIPID() bfin_read32(CHIPID) | ||
| 78 | |||
| 79 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ | ||
| 80 | #define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) | ||
| 81 | #define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) | ||
| 82 | #define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR) | ||
| 83 | #define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val) | ||
| 84 | #define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT) | ||
| 85 | #define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val) | ||
| 86 | #define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK) | ||
| 87 | #define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val) | ||
| 88 | #define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0) | ||
| 89 | #define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val) | ||
| 90 | #define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1) | ||
| 91 | #define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val) | ||
| 92 | #define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0) | ||
| 93 | #define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val) | ||
| 94 | #define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1) | ||
| 95 | #define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val) | ||
| 96 | #define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2) | ||
| 97 | #define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val) | ||
| 98 | #define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3) | ||
| 99 | #define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val) | ||
| 100 | #define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4) | ||
| 101 | #define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val) | ||
| 102 | #define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5) | ||
| 103 | #define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val) | ||
| 104 | #define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6) | ||
| 105 | #define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val) | ||
| 106 | #define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7) | ||
| 107 | #define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val) | ||
| 108 | #define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0) | ||
| 109 | #define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val) | ||
| 110 | #define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1) | ||
| 111 | #define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val) | ||
| 112 | #define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0) | ||
| 113 | #define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val) | ||
| 114 | #define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1) | ||
| 115 | #define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val) | ||
| 116 | |||
| 117 | /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ | ||
| 118 | #define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) | ||
| 119 | #define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST,val) | ||
| 120 | #define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR) | ||
| 121 | #define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR,val) | ||
| 122 | #define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT) | ||
| 123 | #define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT,val) | ||
| 124 | #define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0) | ||
| 125 | #define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val) | ||
| 126 | #define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1) | ||
| 127 | #define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1,val) | ||
| 128 | #define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0) | ||
| 129 | #define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0,val) | ||
| 130 | #define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1) | ||
| 131 | #define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1,val) | ||
| 132 | #define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2) | ||
| 133 | #define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2,val) | ||
| 134 | #define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3) | ||
| 135 | #define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3,val) | ||
| 136 | #define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4) | ||
| 137 | #define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4,val) | ||
| 138 | #define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5) | ||
| 139 | #define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5,val) | ||
| 140 | #define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6) | ||
| 141 | #define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6,val) | ||
| 142 | #define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7) | ||
| 143 | #define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7,val) | ||
| 144 | #define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0) | ||
| 145 | #define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0,val) | ||
| 146 | #define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1) | ||
| 147 | #define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1,val) | ||
| 148 | #define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0) | ||
| 149 | #define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0,val) | ||
| 150 | #define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1) | ||
| 151 | #define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1,val) | ||
| 152 | /* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ | ||
| 153 | #define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL) | ||
| 154 | #define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL,val) | ||
| 155 | #define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT) | ||
| 156 | #define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT,val) | ||
| 157 | #define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT) | ||
| 158 | #define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT,val) | ||
| 159 | |||
| 160 | /* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */ | ||
| 161 | #define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL) | ||
| 162 | #define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL,val) | ||
| 163 | #define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT) | ||
| 164 | #define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT,val) | ||
| 165 | #define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT) | ||
| 166 | #define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT,val) | ||
| 167 | |||
| 168 | /* UART Controller (0xFFC00400 - 0xFFC004FF) */ | ||
| 169 | #define bfin_read_UART_THR() bfin_read16(UART_THR) | ||
| 170 | #define bfin_write_UART_THR(val) bfin_write16(UART_THR,val) | ||
| 171 | #define bfin_read_UART_RBR() bfin_read16(UART_RBR) | ||
| 172 | #define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val) | ||
| 173 | #define bfin_read_UART_DLL() bfin_read16(UART_DLL) | ||
| 174 | #define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val) | ||
| 175 | #define bfin_read_UART_IER() bfin_read16(UART_IER) | ||
| 176 | #define bfin_write_UART_IER(val) bfin_write16(UART_IER,val) | ||
| 177 | #define bfin_read_UART_DLH() bfin_read16(UART_DLH) | ||
| 178 | #define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val) | ||
| 179 | #define bfin_read_UART_IIR() bfin_read16(UART_IIR) | ||
| 180 | #define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val) | ||
| 181 | #define bfin_read_UART_LCR() bfin_read16(UART_LCR) | ||
| 182 | #define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val) | ||
| 183 | #define bfin_read_UART_MCR() bfin_read16(UART_MCR) | ||
| 184 | #define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val) | ||
| 185 | #define bfin_read_UART_LSR() bfin_read16(UART_LSR) | ||
| 186 | #define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val) | ||
| 187 | #define bfin_read_UART_MSR() bfin_read16(UART_MSR) | ||
| 188 | #define bfin_write_UART_MSR(val) bfin_write16(UART_MSR,val) | ||
| 189 | #define bfin_read_UART_SCR() bfin_read16(UART_SCR) | ||
| 190 | #define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val) | ||
| 191 | #define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) | ||
| 192 | #define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val) | ||
| 193 | |||
| 194 | /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ | ||
| 195 | #define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) | ||
| 196 | #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val) | ||
| 197 | #define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) | ||
| 198 | #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val) | ||
| 199 | #define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) | ||
| 200 | #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val) | ||
| 201 | #define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) | ||
| 202 | #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val) | ||
| 203 | #define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) | ||
| 204 | #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val) | ||
| 205 | #define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) | ||
| 206 | #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val) | ||
| 207 | #define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) | ||
| 208 | #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val) | ||
| 209 | |||
| 210 | /* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */ | ||
| 211 | #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) | ||
| 212 | #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val) | ||
| 213 | #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) | ||
| 214 | #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val) | ||
| 215 | #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) | ||
| 216 | #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val) | ||
| 217 | #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) | ||
| 218 | #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val) | ||
| 219 | #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) | ||
| 220 | #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val) | ||
| 221 | #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) | ||
| 222 | #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val) | ||
| 223 | #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) | ||
| 224 | #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val) | ||
| 225 | #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) | ||
| 226 | #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val) | ||
| 227 | #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) | ||
| 228 | #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val) | ||
| 229 | #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) | ||
| 230 | #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val) | ||
| 231 | #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) | ||
| 232 | #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val) | ||
| 233 | #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) | ||
| 234 | #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val) | ||
| 235 | #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) | ||
| 236 | #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val) | ||
| 237 | #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) | ||
| 238 | #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val) | ||
| 239 | #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) | ||
| 240 | #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val) | ||
| 241 | #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) | ||
| 242 | #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val) | ||
| 243 | #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) | ||
| 244 | #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val) | ||
| 245 | #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) | ||
| 246 | #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val) | ||
| 247 | #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) | ||
| 248 | #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val) | ||
| 249 | #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) | ||
| 250 | #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val) | ||
| 251 | #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) | ||
| 252 | #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val) | ||
| 253 | #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) | ||
| 254 | #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val) | ||
| 255 | #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) | ||
| 256 | #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val) | ||
| 257 | #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) | ||
| 258 | #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val) | ||
| 259 | #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) | ||
| 260 | #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val) | ||
| 261 | #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) | ||
| 262 | #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val) | ||
| 263 | #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) | ||
| 264 | #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val) | ||
| 265 | #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) | ||
| 266 | #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val) | ||
| 267 | #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) | ||
| 268 | #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val) | ||
| 269 | #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) | ||
| 270 | #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val) | ||
| 271 | #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) | ||
| 272 | #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val) | ||
| 273 | #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) | ||
| 274 | #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val) | ||
| 275 | |||
| 276 | /* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */ | ||
| 277 | #define bfin_read_TMRS8_ENABLE() bfin_read16(TMRS8_ENABLE) | ||
| 278 | #define bfin_write_TMRS8_ENABLE(val) bfin_write16(TMRS8_ENABLE,val) | ||
| 279 | #define bfin_read_TMRS8_DISABLE() bfin_read16(TMRS8_DISABLE) | ||
| 280 | #define bfin_write_TMRS8_DISABLE(val) bfin_write16(TMRS8_DISABLE,val) | ||
| 281 | #define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS) | ||
| 282 | #define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS,val) | ||
| 283 | #define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) | ||
| 284 | #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG,val) | ||
| 285 | #define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) | ||
| 286 | #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER,val) | ||
| 287 | #define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) | ||
| 288 | #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD,val) | ||
| 289 | #define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) | ||
| 290 | #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH,val) | ||
| 291 | #define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) | ||
| 292 | #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG,val) | ||
| 293 | #define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) | ||
| 294 | #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER,val) | ||
| 295 | #define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) | ||
| 296 | #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD,val) | ||
| 297 | #define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) | ||
| 298 | #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH,val) | ||
| 299 | #define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) | ||
| 300 | #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG,val) | ||
| 301 | #define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) | ||
| 302 | #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER,val) | ||
| 303 | #define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) | ||
| 304 | #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD,val) | ||
| 305 | #define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) | ||
| 306 | #define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH,val) | ||
| 307 | #define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG) | ||
| 308 | #define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG,val) | ||
| 309 | #define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER) | ||
| 310 | #define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER,val) | ||
| 311 | #define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD) | ||
| 312 | #define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD,val) | ||
| 313 | #define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH) | ||
| 314 | #define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH,val) | ||
| 315 | #define bfin_read_TMRS4_ENABLE() bfin_read16(TMRS4_ENABLE) | ||
| 316 | #define bfin_write_TMRS4_ENABLE(val) bfin_write16(TMRS4_ENABLE,val) | ||
| 317 | #define bfin_read_TMRS4_DISABLE() bfin_read16(TMRS4_DISABLE) | ||
| 318 | #define bfin_write_TMRS4_DISABLE(val) bfin_write16(TMRS4_DISABLE,val) | ||
| 319 | #define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS) | ||
| 320 | #define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS,val) | ||
| 321 | |||
| 322 | /* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ | ||
| 323 | #define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D) | ||
| 324 | #define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D,val) | ||
| 325 | #define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C) | ||
| 326 | #define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C,val) | ||
| 327 | #define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S) | ||
| 328 | #define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S,val) | ||
| 329 | #define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T) | ||
| 330 | #define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T,val) | ||
| 331 | #define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D) | ||
| 332 | #define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D,val) | ||
| 333 | #define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C) | ||
| 334 | #define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C,val) | ||
| 335 | #define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S) | ||
| 336 | #define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S,val) | ||
| 337 | #define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T) | ||
| 338 | #define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T,val) | ||
| 339 | #define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D) | ||
| 340 | #define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D,val) | ||
| 341 | #define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C) | ||
| 342 | #define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C,val) | ||
| 343 | #define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S) | ||
| 344 | #define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S,val) | ||
| 345 | #define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T) | ||
| 346 | #define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T,val) | ||
| 347 | #define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR) | ||
| 348 | #define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR,val) | ||
| 349 | #define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR) | ||
| 350 | #define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR,val) | ||
| 351 | #define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE) | ||
| 352 | #define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE,val) | ||
| 353 | #define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH) | ||
| 354 | #define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH,val) | ||
| 355 | #define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN) | ||
| 356 | #define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN,val) | ||
| 357 | /* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */ | ||
| 358 | #define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D) | ||
| 359 | #define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D,val) | ||
| 360 | #define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C) | ||
| 361 | #define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C,val) | ||
| 362 | #define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S) | ||
| 363 | #define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S,val) | ||
| 364 | #define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T) | ||
| 365 | #define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T,val) | ||
| 366 | #define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D) | ||
| 367 | #define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D,val) | ||
| 368 | #define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C) | ||
| 369 | #define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C,val) | ||
| 370 | #define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S) | ||
| 371 | #define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S,val) | ||
| 372 | #define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T) | ||
| 373 | #define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T,val) | ||
| 374 | #define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D) | ||
| 375 | #define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D,val) | ||
| 376 | #define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C) | ||
| 377 | #define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C,val) | ||
| 378 | #define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S) | ||
| 379 | #define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S,val) | ||
| 380 | #define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T) | ||
| 381 | #define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T,val) | ||
| 382 | #define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR) | ||
| 383 | #define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR,val) | ||
| 384 | #define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR) | ||
| 385 | #define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR,val) | ||
| 386 | #define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE) | ||
| 387 | #define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE,val) | ||
| 388 | #define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH) | ||
| 389 | #define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH,val) | ||
| 390 | #define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN) | ||
| 391 | #define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN,val) | ||
| 392 | /* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */ | ||
| 393 | #define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D) | ||
| 394 | #define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D,val) | ||
| 395 | #define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C) | ||
| 396 | #define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C,val) | ||
| 397 | #define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S) | ||
| 398 | #define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S,val) | ||
| 399 | #define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T) | ||
| 400 | #define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T,val) | ||
| 401 | #define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D) | ||
| 402 | #define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D,val) | ||
| 403 | #define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C) | ||
| 404 | #define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C,val) | ||
| 405 | #define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S) | ||
| 406 | #define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S,val) | ||
| 407 | #define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T) | ||
| 408 | #define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T,val) | ||
| 409 | #define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D) | ||
| 410 | #define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D,val) | ||
| 411 | #define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C) | ||
| 412 | #define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C,val) | ||
| 413 | #define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S) | ||
| 414 | #define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S,val) | ||
| 415 | #define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T) | ||
| 416 | #define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T,val) | ||
| 417 | #define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR) | ||
| 418 | #define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR,val) | ||
| 419 | #define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR) | ||
| 420 | #define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR,val) | ||
| 421 | #define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE) | ||
| 422 | #define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE,val) | ||
| 423 | #define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH) | ||
| 424 | #define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH,val) | ||
| 425 | #define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN) | ||
| 426 | #define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN,val) | ||
| 427 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ | ||
| 428 | #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) | ||
| 429 | #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val) | ||
| 430 | #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) | ||
| 431 | #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val) | ||
| 432 | #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) | ||
| 433 | #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val) | ||
| 434 | #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) | ||
| 435 | #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val) | ||
| 436 | #define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) | ||
| 437 | #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val) | ||
| 438 | #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) | ||
| 439 | #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val) | ||
| 440 | #define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) | ||
| 441 | #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val) | ||
| 442 | #define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) | ||
| 443 | #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val) | ||
| 444 | #define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) | ||
| 445 | #define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val) | ||
| 446 | #define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) | ||
| 447 | #define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val) | ||
| 448 | #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) | ||
| 449 | #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val) | ||
| 450 | #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) | ||
| 451 | #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val) | ||
| 452 | #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) | ||
| 453 | #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val) | ||
| 454 | #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) | ||
| 455 | #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val) | ||
| 456 | #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) | ||
| 457 | #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val) | ||
| 458 | #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) | ||
| 459 | #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val) | ||
| 460 | #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) | ||
| 461 | #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val) | ||
| 462 | #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) | ||
| 463 | #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val) | ||
| 464 | #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) | ||
| 465 | #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val) | ||
| 466 | #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) | ||
| 467 | #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val) | ||
| 468 | #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) | ||
| 469 | #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val) | ||
| 470 | #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) | ||
| 471 | #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val) | ||
| 472 | #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) | ||
| 473 | #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val) | ||
| 474 | #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) | ||
| 475 | #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val) | ||
| 476 | #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) | ||
| 477 | #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val) | ||
| 478 | #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) | ||
| 479 | #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val) | ||
| 480 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ | ||
| 481 | #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) | ||
| 482 | #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val) | ||
| 483 | #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) | ||
| 484 | #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val) | ||
| 485 | #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) | ||
| 486 | #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val) | ||
| 487 | #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) | ||
| 488 | #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val) | ||
| 489 | #define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) | ||
| 490 | #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val) | ||
| 491 | #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) | ||
| 492 | #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val) | ||
| 493 | #define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) | ||
| 494 | #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val) | ||
| 495 | #define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) | ||
| 496 | #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val) | ||
| 497 | #define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) | ||
| 498 | #define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val) | ||
| 499 | #define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) | ||
| 500 | #define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val) | ||
| 501 | #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) | ||
| 502 | #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val) | ||
| 503 | #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) | ||
| 504 | #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val) | ||
| 505 | #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) | ||
| 506 | #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val) | ||
| 507 | #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) | ||
| 508 | #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val) | ||
| 509 | #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) | ||
| 510 | #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val) | ||
| 511 | #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) | ||
| 512 | #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val) | ||
| 513 | #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) | ||
| 514 | #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val) | ||
| 515 | #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) | ||
| 516 | #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val) | ||
| 517 | #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) | ||
| 518 | #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val) | ||
| 519 | #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) | ||
| 520 | #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val) | ||
| 521 | #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) | ||
| 522 | #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val) | ||
| 523 | #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) | ||
| 524 | #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val) | ||
| 525 | #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) | ||
| 526 | #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val) | ||
| 527 | #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) | ||
| 528 | #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val) | ||
| 529 | #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) | ||
| 530 | #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val) | ||
| 531 | #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) | ||
| 532 | #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val) | ||
| 533 | /* Asynchronous Memory Controller - External Bus Interface Unit */ | ||
| 534 | #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) | ||
| 535 | #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val) | ||
| 536 | #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) | ||
| 537 | #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val) | ||
| 538 | #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) | ||
| 539 | #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val) | ||
| 540 | /* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ | ||
| 541 | #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) | ||
| 542 | #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val) | ||
| 543 | #define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL) | ||
| 544 | #define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val) | ||
| 545 | #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) | ||
| 546 | #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val) | ||
| 547 | #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) | ||
| 548 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) | ||
| 549 | /* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */ | ||
| 550 | #define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL) | ||
| 551 | #define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val) | ||
| 552 | #define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS) | ||
| 553 | #define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val) | ||
| 554 | #define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT) | ||
| 555 | #define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val) | ||
| 556 | #define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY) | ||
| 557 | #define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY,val) | ||
| 558 | #define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME) | ||
| 559 | #define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME,val) | ||
| 560 | /* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */ | ||
| 561 | #define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL) | ||
| 562 | #define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val) | ||
| 563 | #define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS) | ||
| 564 | #define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val) | ||
| 565 | #define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT) | ||
| 566 | #define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val) | ||
| 567 | #define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY) | ||
| 568 | #define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY,val) | ||
| 569 | #define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME) | ||
| 570 | #define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val) | ||
| 571 | /*DMA traffic control registers */ | ||
| 572 | #define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER) | ||
| 573 | #define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER,val) | ||
| 574 | #define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT) | ||
| 575 | #define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT,val) | ||
| 576 | #define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER) | ||
| 577 | #define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER,val) | ||
| 578 | #define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT) | ||
| 579 | #define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT,val) | ||
| 580 | /* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ | ||
| 581 | #define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG) | ||
| 582 | #define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val) | ||
| 583 | #define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_read32(DMA1_0_NEXT_DESC_PTR) | ||
| 584 | #define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_write32(DMA1_0_NEXT_DESC_PTR,val) | ||
| 585 | #define bfin_read_DMA1_0_START_ADDR() bfin_read32(DMA1_0_START_ADDR) | ||
| 586 | #define bfin_write_DMA1_0_START_ADDR(val) bfin_write32(DMA1_0_START_ADDR,val) | ||
| 587 | #define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT) | ||
| 588 | #define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT,val) | ||
| 589 | #define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT) | ||
| 590 | #define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT,val) | ||
| 591 | #define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY) | ||
| 592 | #define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY,val) | ||
| 593 | #define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY) | ||
| 594 | #define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY,val) | ||
| 595 | #define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_read32(DMA1_0_CURR_DESC_PTR) | ||
| 596 | #define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_write32(DMA1_0_CURR_DESC_PTR,val) | ||
| 597 | #define bfin_read_DMA1_0_CURR_ADDR() bfin_read32(DMA1_0_CURR_ADDR) | ||
| 598 | #define bfin_write_DMA1_0_CURR_ADDR(val) bfin_write32(DMA1_0_CURR_ADDR,val) | ||
| 599 | #define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT) | ||
| 600 | #define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT,val) | ||
| 601 | #define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT) | ||
| 602 | #define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT,val) | ||
| 603 | #define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS) | ||
| 604 | #define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS,val) | ||
| 605 | #define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP) | ||
| 606 | #define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP,val) | ||
| 607 | #define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG) | ||
| 608 | #define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG,val) | ||
| 609 | #define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_read32(DMA1_1_NEXT_DESC_PTR) | ||
| 610 | #define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_write32(DMA1_1_NEXT_DESC_PTR,val) | ||
| 611 | #define bfin_read_DMA1_1_START_ADDR() bfin_read32(DMA1_1_START_ADDR) | ||
| 612 | #define bfin_write_DMA1_1_START_ADDR(val) bfin_write32(DMA1_1_START_ADDR,val) | ||
| 613 | #define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT) | ||
| 614 | #define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT,val) | ||
| 615 | #define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT) | ||
| 616 | #define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT,val) | ||
| 617 | #define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY) | ||
| 618 | #define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY,val) | ||
| 619 | #define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY) | ||
| 620 | #define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY,val) | ||
| 621 | #define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_read32(DMA1_1_CURR_DESC_PTR) | ||
| 622 | #define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_write32(DMA1_1_CURR_DESC_PTR,val) | ||
| 623 | #define bfin_read_DMA1_1_CURR_ADDR() bfin_read32(DMA1_1_CURR_ADDR) | ||
| 624 | #define bfin_write_DMA1_1_CURR_ADDR(val) bfin_write32(DMA1_1_CURR_ADDR,val) | ||
| 625 | #define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT) | ||
| 626 | #define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT,val) | ||
| 627 | #define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT) | ||
| 628 | #define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT,val) | ||
| 629 | #define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS) | ||
| 630 | #define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS,val) | ||
| 631 | #define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP) | ||
| 632 | #define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP,val) | ||
| 633 | #define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG) | ||
| 634 | #define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG,val) | ||
| 635 | #define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_read32(DMA1_2_NEXT_DESC_PTR) | ||
| 636 | #define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_write32(DMA1_2_NEXT_DESC_PTR,val) | ||
| 637 | #define bfin_read_DMA1_2_START_ADDR() bfin_read32(DMA1_2_START_ADDR) | ||
| 638 | #define bfin_write_DMA1_2_START_ADDR(val) bfin_write32(DMA1_2_START_ADDR,val) | ||
| 639 | #define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT) | ||
| 640 | #define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT,val) | ||
| 641 | #define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT) | ||
| 642 | #define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT,val) | ||
| 643 | #define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY) | ||
| 644 | #define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY,val) | ||
| 645 | #define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY) | ||
| 646 | #define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY,val) | ||
| 647 | #define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_read32(DMA1_2_CURR_DESC_PTR) | ||
| 648 | #define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_write32(DMA1_2_CURR_DESC_PTR,val) | ||
| 649 | #define bfin_read_DMA1_2_CURR_ADDR() bfin_read32(DMA1_2_CURR_ADDR) | ||
| 650 | #define bfin_write_DMA1_2_CURR_ADDR(val) bfin_write32(DMA1_2_CURR_ADDR,val) | ||
| 651 | #define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT) | ||
| 652 | #define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT,val) | ||
| 653 | #define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT) | ||
| 654 | #define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT,val) | ||
| 655 | #define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS) | ||
| 656 | #define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS,val) | ||
| 657 | #define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP) | ||
| 658 | #define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP,val) | ||
| 659 | #define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG) | ||
| 660 | #define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG,val) | ||
| 661 | #define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_read32(DMA1_3_NEXT_DESC_PTR) | ||
| 662 | #define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_write32(DMA1_3_NEXT_DESC_PTR,val) | ||
| 663 | #define bfin_read_DMA1_3_START_ADDR() bfin_read32(DMA1_3_START_ADDR) | ||
| 664 | #define bfin_write_DMA1_3_START_ADDR(val) bfin_write32(DMA1_3_START_ADDR,val) | ||
| 665 | #define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT) | ||
| 666 | #define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT,val) | ||
| 667 | #define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT) | ||
| 668 | #define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT,val) | ||
| 669 | #define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY) | ||
| 670 | #define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY,val) | ||
| 671 | #define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY) | ||
| 672 | #define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY,val) | ||
| 673 | #define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_read32(DMA1_3_CURR_DESC_PTR) | ||
| 674 | #define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_write32(DMA1_3_CURR_DESC_PTR,val) | ||
| 675 | #define bfin_read_DMA1_3_CURR_ADDR() bfin_read32(DMA1_3_CURR_ADDR) | ||
| 676 | #define bfin_write_DMA1_3_CURR_ADDR(val) bfin_write32(DMA1_3_CURR_ADDR,val) | ||
| 677 | #define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT) | ||
| 678 | #define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT,val) | ||
| 679 | #define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT) | ||
| 680 | #define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT,val) | ||
| 681 | #define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS) | ||
| 682 | #define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS,val) | ||
| 683 | #define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP) | ||
| 684 | #define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP,val) | ||
| 685 | #define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG) | ||
| 686 | #define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG,val) | ||
| 687 | #define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_read32(DMA1_4_NEXT_DESC_PTR) | ||
| 688 | #define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_write32(DMA1_4_NEXT_DESC_PTR,val) | ||
| 689 | #define bfin_read_DMA1_4_START_ADDR() bfin_read32(DMA1_4_START_ADDR) | ||
| 690 | #define bfin_write_DMA1_4_START_ADDR(val) bfin_write32(DMA1_4_START_ADDR,val) | ||
| 691 | #define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT) | ||
| 692 | #define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT,val) | ||
| 693 | #define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT) | ||
| 694 | #define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT,val) | ||
| 695 | #define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY) | ||
| 696 | #define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY,val) | ||
| 697 | #define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY) | ||
| 698 | #define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY,val) | ||
| 699 | #define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_read32(DMA1_4_CURR_DESC_PTR) | ||
| 700 | #define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_write32(DMA1_4_CURR_DESC_PTR,val) | ||
| 701 | #define bfin_read_DMA1_4_CURR_ADDR() bfin_read32(DMA1_4_CURR_ADDR) | ||
| 702 | #define bfin_write_DMA1_4_CURR_ADDR(val) bfin_write32(DMA1_4_CURR_ADDR,val) | ||
| 703 | #define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT) | ||
| 704 | #define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT,val) | ||
| 705 | #define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT) | ||
| 706 | #define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT,val) | ||
| 707 | #define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS) | ||
| 708 | #define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS,val) | ||
| 709 | #define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP) | ||
| 710 | #define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP,val) | ||
| 711 | #define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG) | ||
| 712 | #define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG,val) | ||
| 713 | #define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_read32(DMA1_5_NEXT_DESC_PTR) | ||
| 714 | #define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_write32(DMA1_5_NEXT_DESC_PTR,val) | ||
| 715 | #define bfin_read_DMA1_5_START_ADDR() bfin_read32(DMA1_5_START_ADDR) | ||
| 716 | #define bfin_write_DMA1_5_START_ADDR(val) bfin_write32(DMA1_5_START_ADDR,val) | ||
| 717 | #define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT) | ||
| 718 | #define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT,val) | ||
| 719 | #define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT) | ||
| 720 | #define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT,val) | ||
| 721 | #define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY) | ||
| 722 | #define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY,val) | ||
| 723 | #define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY) | ||
| 724 | #define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY,val) | ||
| 725 | #define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_read32(DMA1_5_CURR_DESC_PTR) | ||
| 726 | #define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_write32(DMA1_5_CURR_DESC_PTR,val) | ||
| 727 | #define bfin_read_DMA1_5_CURR_ADDR() bfin_read32(DMA1_5_CURR_ADDR) | ||
| 728 | #define bfin_write_DMA1_5_CURR_ADDR(val) bfin_write32(DMA1_5_CURR_ADDR,val) | ||
| 729 | #define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT) | ||
| 730 | #define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT,val) | ||
| 731 | #define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT) | ||
| 732 | #define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT,val) | ||
| 733 | #define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS) | ||
| 734 | #define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS,val) | ||
| 735 | #define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP) | ||
| 736 | #define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP,val) | ||
| 737 | #define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG) | ||
| 738 | #define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG,val) | ||
| 739 | #define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_read32(DMA1_6_NEXT_DESC_PTR) | ||
| 740 | #define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_write32(DMA1_6_NEXT_DESC_PTR,val) | ||
| 741 | #define bfin_read_DMA1_6_START_ADDR() bfin_read32(DMA1_6_START_ADDR) | ||
| 742 | #define bfin_write_DMA1_6_START_ADDR(val) bfin_write32(DMA1_6_START_ADDR,val) | ||
| 743 | #define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT) | ||
| 744 | #define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT,val) | ||
| 745 | #define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT) | ||
| 746 | #define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT,val) | ||
| 747 | #define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY) | ||
| 748 | #define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY,val) | ||
| 749 | #define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY) | ||
| 750 | #define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY,val) | ||
| 751 | #define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_read32(DMA1_6_CURR_DESC_PTR) | ||
| 752 | #define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_write32(DMA1_6_CURR_DESC_PTR,val) | ||
| 753 | #define bfin_read_DMA1_6_CURR_ADDR() bfin_read32(DMA1_6_CURR_ADDR) | ||
| 754 | #define bfin_write_DMA1_6_CURR_ADDR(val) bfin_write32(DMA1_6_CURR_ADDR,val) | ||
| 755 | #define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT) | ||
| 756 | #define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT,val) | ||
| 757 | #define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT) | ||
| 758 | #define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT,val) | ||
| 759 | #define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS) | ||
| 760 | #define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS,val) | ||
| 761 | #define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP) | ||
| 762 | #define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP,val) | ||
| 763 | #define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG) | ||
| 764 | #define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG,val) | ||
| 765 | #define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_read32(DMA1_7_NEXT_DESC_PTR) | ||
| 766 | #define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_write32(DMA1_7_NEXT_DESC_PTR,val) | ||
| 767 | #define bfin_read_DMA1_7_START_ADDR() bfin_read32(DMA1_7_START_ADDR) | ||
| 768 | #define bfin_write_DMA1_7_START_ADDR(val) bfin_write32(DMA1_7_START_ADDR,val) | ||
| 769 | #define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT) | ||
| 770 | #define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT,val) | ||
| 771 | #define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT) | ||
| 772 | #define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT,val) | ||
| 773 | #define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY) | ||
| 774 | #define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY,val) | ||
| 775 | #define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY) | ||
| 776 | #define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY,val) | ||
| 777 | #define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_read32(DMA1_7_CURR_DESC_PTR) | ||
| 778 | #define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_write32(DMA1_7_CURR_DESC_PTR,val) | ||
| 779 | #define bfin_read_DMA1_7_CURR_ADDR() bfin_read32(DMA1_7_CURR_ADDR) | ||
| 780 | #define bfin_write_DMA1_7_CURR_ADDR(val) bfin_write32(DMA1_7_CURR_ADDR,val) | ||
| 781 | #define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT) | ||
| 782 | #define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT,val) | ||
| 783 | #define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT) | ||
| 784 | #define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT,val) | ||
| 785 | #define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS) | ||
| 786 | #define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS,val) | ||
| 787 | #define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP) | ||
| 788 | #define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP,val) | ||
| 789 | #define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG) | ||
| 790 | #define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG,val) | ||
| 791 | #define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_read32(DMA1_8_NEXT_DESC_PTR) | ||
| 792 | #define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_write32(DMA1_8_NEXT_DESC_PTR,val) | ||
| 793 | #define bfin_read_DMA1_8_START_ADDR() bfin_read32(DMA1_8_START_ADDR) | ||
| 794 | #define bfin_write_DMA1_8_START_ADDR(val) bfin_write32(DMA1_8_START_ADDR,val) | ||
| 795 | #define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT) | ||
| 796 | #define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT,val) | ||
| 797 | #define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT) | ||
| 798 | #define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT,val) | ||
| 799 | #define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY) | ||
| 800 | #define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY,val) | ||
| 801 | #define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY) | ||
| 802 | #define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY,val) | ||
| 803 | #define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_read32(DMA1_8_CURR_DESC_PTR) | ||
| 804 | #define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_write32(DMA1_8_CURR_DESC_PTR,val) | ||
| 805 | #define bfin_read_DMA1_8_CURR_ADDR() bfin_read32(DMA1_8_CURR_ADDR) | ||
| 806 | #define bfin_write_DMA1_8_CURR_ADDR(val) bfin_write32(DMA1_8_CURR_ADDR,val) | ||
| 807 | #define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT) | ||
| 808 | #define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT,val) | ||
| 809 | #define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT) | ||
| 810 | #define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT,val) | ||
| 811 | #define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS) | ||
| 812 | #define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS,val) | ||
| 813 | #define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP) | ||
| 814 | #define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP,val) | ||
| 815 | #define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG) | ||
| 816 | #define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG,val) | ||
| 817 | #define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_read32(DMA1_9_NEXT_DESC_PTR) | ||
| 818 | #define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_write32(DMA1_9_NEXT_DESC_PTR,val) | ||
| 819 | #define bfin_read_DMA1_9_START_ADDR() bfin_read32(DMA1_9_START_ADDR) | ||
| 820 | #define bfin_write_DMA1_9_START_ADDR(val) bfin_write32(DMA1_9_START_ADDR,val) | ||
| 821 | #define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT) | ||
| 822 | #define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT,val) | ||
| 823 | #define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT) | ||
| 824 | #define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT,val) | ||
| 825 | #define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY) | ||
| 826 | #define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY,val) | ||
| 827 | #define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY) | ||
| 828 | #define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY,val) | ||
| 829 | #define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_read32(DMA1_9_CURR_DESC_PTR) | ||
| 830 | #define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_write32(DMA1_9_CURR_DESC_PTR,val) | ||
| 831 | #define bfin_read_DMA1_9_CURR_ADDR() bfin_read32(DMA1_9_CURR_ADDR) | ||
| 832 | #define bfin_write_DMA1_9_CURR_ADDR(val) bfin_write32(DMA1_9_CURR_ADDR,val) | ||
| 833 | #define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT) | ||
| 834 | #define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT,val) | ||
| 835 | #define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT) | ||
| 836 | #define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT,val) | ||
| 837 | #define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS) | ||
| 838 | #define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS,val) | ||
| 839 | #define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP) | ||
| 840 | #define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP,val) | ||
| 841 | #define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG) | ||
| 842 | #define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG,val) | ||
| 843 | #define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_read32(DMA1_10_NEXT_DESC_PTR) | ||
| 844 | #define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_write32(DMA1_10_NEXT_DESC_PTR,val) | ||
| 845 | #define bfin_read_DMA1_10_START_ADDR() bfin_read32(DMA1_10_START_ADDR) | ||
| 846 | #define bfin_write_DMA1_10_START_ADDR(val) bfin_write32(DMA1_10_START_ADDR,val) | ||
| 847 | #define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT) | ||
| 848 | #define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT,val) | ||
| 849 | #define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT) | ||
| 850 | #define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT,val) | ||
| 851 | #define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY) | ||
| 852 | #define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY,val) | ||
| 853 | #define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY) | ||
| 854 | #define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY,val) | ||
| 855 | #define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_read32(DMA1_10_CURR_DESC_PTR) | ||
| 856 | #define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_write32(DMA1_10_CURR_DESC_PTR,val) | ||
| 857 | #define bfin_read_DMA1_10_CURR_ADDR() bfin_read32(DMA1_10_CURR_ADDR) | ||
| 858 | #define bfin_write_DMA1_10_CURR_ADDR(val) bfin_write32(DMA1_10_CURR_ADDR,val) | ||
| 859 | #define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT) | ||
| 860 | #define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT,val) | ||
| 861 | #define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT) | ||
| 862 | #define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT,val) | ||
| 863 | #define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS) | ||
| 864 | #define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS,val) | ||
| 865 | #define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP) | ||
| 866 | #define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP,val) | ||
| 867 | #define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG) | ||
| 868 | #define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG,val) | ||
| 869 | #define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_read32(DMA1_11_NEXT_DESC_PTR) | ||
| 870 | #define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_write32(DMA1_11_NEXT_DESC_PTR,val) | ||
| 871 | #define bfin_read_DMA1_11_START_ADDR() bfin_read32(DMA1_11_START_ADDR) | ||
| 872 | #define bfin_write_DMA1_11_START_ADDR(val) bfin_write32(DMA1_11_START_ADDR,val) | ||
| 873 | #define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT) | ||
| 874 | #define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT,val) | ||
| 875 | #define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT) | ||
| 876 | #define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT,val) | ||
| 877 | #define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY) | ||
| 878 | #define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY,val) | ||
| 879 | #define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY) | ||
| 880 | #define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY,val) | ||
| 881 | #define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_read32(DMA1_11_CURR_DESC_PTR) | ||
| 882 | #define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_write32(DMA1_11_CURR_DESC_PTR,val) | ||
| 883 | #define bfin_read_DMA1_11_CURR_ADDR() bfin_read32(DMA1_11_CURR_ADDR) | ||
| 884 | #define bfin_write_DMA1_11_CURR_ADDR(val) bfin_write32(DMA1_11_CURR_ADDR,val) | ||
| 885 | #define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT) | ||
| 886 | #define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT,val) | ||
| 887 | #define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT) | ||
| 888 | #define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT,val) | ||
| 889 | #define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS) | ||
| 890 | #define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS,val) | ||
| 891 | #define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP) | ||
| 892 | #define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val) | ||
| 893 | /* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ | ||
| 894 | #define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG) | ||
| 895 | #define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG,val) | ||
| 896 | #define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_read32(MDMA1_D0_NEXT_DESC_PTR) | ||
| 897 | #define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D0_NEXT_DESC_PTR,val) | ||
| 898 | #define bfin_read_MDMA1_D0_START_ADDR() bfin_read32(MDMA1_D0_START_ADDR) | ||
| 899 | #define bfin_write_MDMA1_D0_START_ADDR(val) bfin_write32(MDMA1_D0_START_ADDR,val) | ||
| 900 | #define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT) | ||
| 901 | #define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT,val) | ||
| 902 | #define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT) | ||
| 903 | #define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT,val) | ||
| 904 | #define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY) | ||
| 905 | #define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY,val) | ||
| 906 | #define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY) | ||
| 907 | #define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY,val) | ||
| 908 | #define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_read32(MDMA1_D0_CURR_DESC_PTR) | ||
| 909 | #define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_write32(MDMA1_D0_CURR_DESC_PTR,val) | ||
| 910 | #define bfin_read_MDMA1_D0_CURR_ADDR() bfin_read32(MDMA1_D0_CURR_ADDR) | ||
| 911 | #define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_write32(MDMA1_D0_CURR_ADDR,val) | ||
| 912 | #define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT) | ||
| 913 | #define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT,val) | ||
| 914 | #define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT) | ||
| 915 | #define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT,val) | ||
| 916 | #define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS) | ||
| 917 | #define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS,val) | ||
| 918 | #define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP) | ||
| 919 | #define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP,val) | ||
| 920 | #define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG) | ||
| 921 | #define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG,val) | ||
| 922 | #define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_read32(MDMA1_S0_NEXT_DESC_PTR) | ||
| 923 | #define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S0_NEXT_DESC_PTR,val) | ||
| 924 | #define bfin_read_MDMA1_S0_START_ADDR() bfin_read32(MDMA1_S0_START_ADDR) | ||
| 925 | #define bfin_write_MDMA1_S0_START_ADDR(val) bfin_write32(MDMA1_S0_START_ADDR,val) | ||
| 926 | #define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT) | ||
| 927 | #define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT,val) | ||
| 928 | #define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT) | ||
| 929 | #define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT,val) | ||
| 930 | #define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY) | ||
| 931 | #define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY,val) | ||
| 932 | #define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY) | ||
| 933 | #define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY,val) | ||
| 934 | #define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_read32(MDMA1_S0_CURR_DESC_PTR) | ||
| 935 | #define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_write32(MDMA1_S0_CURR_DESC_PTR,val) | ||
| 936 | #define bfin_read_MDMA1_S0_CURR_ADDR() bfin_read32(MDMA1_S0_CURR_ADDR) | ||
| 937 | #define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_write32(MDMA1_S0_CURR_ADDR,val) | ||
| 938 | #define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT) | ||
| 939 | #define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT,val) | ||
| 940 | #define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT) | ||
| 941 | #define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT,val) | ||
| 942 | #define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS) | ||
| 943 | #define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS,val) | ||
| 944 | #define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP) | ||
| 945 | #define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP,val) | ||
| 946 | #define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG) | ||
| 947 | #define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG,val) | ||
| 948 | #define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_read32(MDMA1_D1_NEXT_DESC_PTR) | ||
| 949 | #define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D1_NEXT_DESC_PTR,val) | ||
| 950 | #define bfin_read_MDMA1_D1_START_ADDR() bfin_read32(MDMA1_D1_START_ADDR) | ||
| 951 | #define bfin_write_MDMA1_D1_START_ADDR(val) bfin_write32(MDMA1_D1_START_ADDR,val) | ||
| 952 | #define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT) | ||
| 953 | #define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT,val) | ||
| 954 | #define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT) | ||
| 955 | #define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT,val) | ||
| 956 | #define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY) | ||
| 957 | #define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY,val) | ||
| 958 | #define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY) | ||
| 959 | #define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY,val) | ||
| 960 | #define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_read32(MDMA1_D1_CURR_DESC_PTR) | ||
| 961 | #define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_write32(MDMA1_D1_CURR_DESC_PTR,val) | ||
| 962 | #define bfin_read_MDMA1_D1_CURR_ADDR() bfin_read32(MDMA1_D1_CURR_ADDR) | ||
| 963 | #define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_write32(MDMA1_D1_CURR_ADDR,val) | ||
| 964 | #define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT) | ||
| 965 | #define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT,val) | ||
| 966 | #define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT) | ||
| 967 | #define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT,val) | ||
| 968 | #define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS) | ||
| 969 | #define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS,val) | ||
| 970 | #define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP) | ||
| 971 | #define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP,val) | ||
| 972 | #define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG) | ||
| 973 | #define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG,val) | ||
| 974 | #define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_read32(MDMA1_S1_NEXT_DESC_PTR) | ||
| 975 | #define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S1_NEXT_DESC_PTR,val) | ||
| 976 | #define bfin_read_MDMA1_S1_START_ADDR() bfin_read32(MDMA1_S1_START_ADDR) | ||
| 977 | #define bfin_write_MDMA1_S1_START_ADDR(val) bfin_write32(MDMA1_S1_START_ADDR,val) | ||
| 978 | #define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT) | ||
| 979 | #define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT,val) | ||
| 980 | #define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT) | ||
| 981 | #define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT,val) | ||
| 982 | #define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY) | ||
| 983 | #define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY,val) | ||
| 984 | #define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY) | ||
| 985 | #define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY,val) | ||
| 986 | #define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_read32(MDMA1_S1_CURR_DESC_PTR) | ||
| 987 | #define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_write32(MDMA1_S1_CURR_DESC_PTR,val) | ||
| 988 | #define bfin_read_MDMA1_S1_CURR_ADDR() bfin_read32(MDMA1_S1_CURR_ADDR) | ||
| 989 | #define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_write32(MDMA1_S1_CURR_ADDR,val) | ||
| 990 | #define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT) | ||
| 991 | #define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT,val) | ||
| 992 | #define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) | ||
| 993 | #define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT,val) | ||
| 994 | #define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS) | ||
| 995 | #define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS,val) | ||
| 996 | #define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP) | ||
| 997 | #define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP,val) | ||
| 998 | /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ | ||
| 999 | #define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG) | ||
| 1000 | #define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val) | ||
| 1001 | #define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_read32(DMA2_0_NEXT_DESC_PTR) | ||
| 1002 | #define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_write32(DMA2_0_NEXT_DESC_PTR,val) | ||
| 1003 | #define bfin_read_DMA2_0_START_ADDR() bfin_read32(DMA2_0_START_ADDR) | ||
| 1004 | #define bfin_write_DMA2_0_START_ADDR(val) bfin_write32(DMA2_0_START_ADDR,val) | ||
| 1005 | #define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT) | ||
| 1006 | #define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT,val) | ||
| 1007 | #define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT) | ||
| 1008 | #define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT,val) | ||
| 1009 | #define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY) | ||
| 1010 | #define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY,val) | ||
| 1011 | #define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY) | ||
| 1012 | #define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY,val) | ||
| 1013 | #define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_read32(DMA2_0_CURR_DESC_PTR) | ||
| 1014 | #define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_write32(DMA2_0_CURR_DESC_PTR,val) | ||
| 1015 | #define bfin_read_DMA2_0_CURR_ADDR() bfin_read32(DMA2_0_CURR_ADDR) | ||
| 1016 | #define bfin_write_DMA2_0_CURR_ADDR(val) bfin_write32(DMA2_0_CURR_ADDR,val) | ||
| 1017 | #define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT) | ||
| 1018 | #define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT,val) | ||
| 1019 | #define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT) | ||
| 1020 | #define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT,val) | ||
| 1021 | #define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS) | ||
| 1022 | #define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS,val) | ||
| 1023 | #define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP) | ||
| 1024 | #define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP,val) | ||
| 1025 | #define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG) | ||
| 1026 | #define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG,val) | ||
| 1027 | #define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_read32(DMA2_1_NEXT_DESC_PTR) | ||
| 1028 | #define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_write32(DMA2_1_NEXT_DESC_PTR,val) | ||
| 1029 | #define bfin_read_DMA2_1_START_ADDR() bfin_read32(DMA2_1_START_ADDR) | ||
| 1030 | #define bfin_write_DMA2_1_START_ADDR(val) bfin_write32(DMA2_1_START_ADDR,val) | ||
| 1031 | #define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT) | ||
| 1032 | #define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT,val) | ||
| 1033 | #define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT) | ||
| 1034 | #define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT,val) | ||
| 1035 | #define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY) | ||
| 1036 | #define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY,val) | ||
| 1037 | #define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY) | ||
| 1038 | #define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY,val) | ||
| 1039 | #define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_read32(DMA2_1_CURR_DESC_PTR) | ||
| 1040 | #define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_write32(DMA2_1_CURR_DESC_PTR,val) | ||
| 1041 | #define bfin_read_DMA2_1_CURR_ADDR() bfin_read32(DMA2_1_CURR_ADDR) | ||
| 1042 | #define bfin_write_DMA2_1_CURR_ADDR(val) bfin_write32(DMA2_1_CURR_ADDR,val) | ||
| 1043 | #define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT) | ||
| 1044 | #define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT,val) | ||
| 1045 | #define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT) | ||
| 1046 | #define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT,val) | ||
| 1047 | #define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS) | ||
| 1048 | #define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS,val) | ||
| 1049 | #define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP) | ||
| 1050 | #define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP,val) | ||
| 1051 | #define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG) | ||
| 1052 | #define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG,val) | ||
| 1053 | #define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_read32(DMA2_2_NEXT_DESC_PTR) | ||
| 1054 | #define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_write32(DMA2_2_NEXT_DESC_PTR,val) | ||
| 1055 | #define bfin_read_DMA2_2_START_ADDR() bfin_read32(DMA2_2_START_ADDR) | ||
| 1056 | #define bfin_write_DMA2_2_START_ADDR(val) bfin_write32(DMA2_2_START_ADDR,val) | ||
| 1057 | #define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT) | ||
| 1058 | #define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT,val) | ||
| 1059 | #define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT) | ||
| 1060 | #define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT,val) | ||
| 1061 | #define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY) | ||
| 1062 | #define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY,val) | ||
| 1063 | #define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY) | ||
| 1064 | #define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY,val) | ||
| 1065 | #define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_read32(DMA2_2_CURR_DESC_PTR) | ||
| 1066 | #define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_write32(DMA2_2_CURR_DESC_PTR,val) | ||
| 1067 | #define bfin_read_DMA2_2_CURR_ADDR() bfin_read32(DMA2_2_CURR_ADDR) | ||
| 1068 | #define bfin_write_DMA2_2_CURR_ADDR(val) bfin_write32(DMA2_2_CURR_ADDR,val) | ||
| 1069 | #define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT) | ||
| 1070 | #define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT,val) | ||
| 1071 | #define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT) | ||
| 1072 | #define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT,val) | ||
| 1073 | #define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS) | ||
| 1074 | #define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS,val) | ||
| 1075 | #define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP) | ||
| 1076 | #define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP,val) | ||
| 1077 | #define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG) | ||
| 1078 | #define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG,val) | ||
| 1079 | #define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_read32(DMA2_3_NEXT_DESC_PTR) | ||
| 1080 | #define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_write32(DMA2_3_NEXT_DESC_PTR,val) | ||
| 1081 | #define bfin_read_DMA2_3_START_ADDR() bfin_read32(DMA2_3_START_ADDR) | ||
| 1082 | #define bfin_write_DMA2_3_START_ADDR(val) bfin_write32(DMA2_3_START_ADDR,val) | ||
| 1083 | #define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT) | ||
| 1084 | #define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT,val) | ||
| 1085 | #define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT) | ||
| 1086 | #define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT,val) | ||
| 1087 | #define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY) | ||
| 1088 | #define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY,val) | ||
| 1089 | #define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY) | ||
| 1090 | #define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY,val) | ||
| 1091 | #define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_read32(DMA2_3_CURR_DESC_PTR) | ||
| 1092 | #define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_write32(DMA2_3_CURR_DESC_PTR,val) | ||
| 1093 | #define bfin_read_DMA2_3_CURR_ADDR() bfin_read32(DMA2_3_CURR_ADDR) | ||
| 1094 | #define bfin_write_DMA2_3_CURR_ADDR(val) bfin_write32(DMA2_3_CURR_ADDR,val) | ||
| 1095 | #define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT) | ||
| 1096 | #define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT,val) | ||
| 1097 | #define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT) | ||
| 1098 | #define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT,val) | ||
| 1099 | #define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS) | ||
| 1100 | #define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS,val) | ||
| 1101 | #define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP) | ||
| 1102 | #define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP,val) | ||
| 1103 | #define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG) | ||
| 1104 | #define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG,val) | ||
| 1105 | #define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_read32(DMA2_4_NEXT_DESC_PTR) | ||
| 1106 | #define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_write32(DMA2_4_NEXT_DESC_PTR,val) | ||
| 1107 | #define bfin_read_DMA2_4_START_ADDR() bfin_read32(DMA2_4_START_ADDR) | ||
| 1108 | #define bfin_write_DMA2_4_START_ADDR(val) bfin_write32(DMA2_4_START_ADDR,val) | ||
| 1109 | #define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT) | ||
| 1110 | #define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT,val) | ||
| 1111 | #define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT) | ||
| 1112 | #define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT,val) | ||
| 1113 | #define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY) | ||
| 1114 | #define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY,val) | ||
| 1115 | #define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY) | ||
| 1116 | #define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY,val) | ||
| 1117 | #define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_read32(DMA2_4_CURR_DESC_PTR) | ||
| 1118 | #define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_write32(DMA2_4_CURR_DESC_PTR,val) | ||
| 1119 | #define bfin_read_DMA2_4_CURR_ADDR() bfin_read32(DMA2_4_CURR_ADDR) | ||
| 1120 | #define bfin_write_DMA2_4_CURR_ADDR(val) bfin_write32(DMA2_4_CURR_ADDR,val) | ||
| 1121 | #define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT) | ||
| 1122 | #define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT,val) | ||
| 1123 | #define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT) | ||
| 1124 | #define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT,val) | ||
| 1125 | #define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS) | ||
| 1126 | #define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS,val) | ||
| 1127 | #define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP) | ||
| 1128 | #define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP,val) | ||
| 1129 | #define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG) | ||
| 1130 | #define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG,val) | ||
| 1131 | #define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_read32(DMA2_5_NEXT_DESC_PTR) | ||
| 1132 | #define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_write32(DMA2_5_NEXT_DESC_PTR,val) | ||
| 1133 | #define bfin_read_DMA2_5_START_ADDR() bfin_read32(DMA2_5_START_ADDR) | ||
| 1134 | #define bfin_write_DMA2_5_START_ADDR(val) bfin_write32(DMA2_5_START_ADDR,val) | ||
| 1135 | #define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT) | ||
| 1136 | #define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT,val) | ||
| 1137 | #define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT) | ||
| 1138 | #define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT,val) | ||
| 1139 | #define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY) | ||
| 1140 | #define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY,val) | ||
| 1141 | #define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY) | ||
| 1142 | #define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY,val) | ||
| 1143 | #define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_read32(DMA2_5_CURR_DESC_PTR) | ||
| 1144 | #define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_write32(DMA2_5_CURR_DESC_PTR,val) | ||
| 1145 | #define bfin_read_DMA2_5_CURR_ADDR() bfin_read32(DMA2_5_CURR_ADDR) | ||
| 1146 | #define bfin_write_DMA2_5_CURR_ADDR(val) bfin_write32(DMA2_5_CURR_ADDR,val) | ||
| 1147 | #define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT) | ||
| 1148 | #define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT,val) | ||
| 1149 | #define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT) | ||
| 1150 | #define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT,val) | ||
| 1151 | #define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS) | ||
| 1152 | #define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS,val) | ||
| 1153 | #define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP) | ||
| 1154 | #define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP,val) | ||
| 1155 | #define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG) | ||
| 1156 | #define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG,val) | ||
| 1157 | #define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_read32(DMA2_6_NEXT_DESC_PTR) | ||
| 1158 | #define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_write32(DMA2_6_NEXT_DESC_PTR,val) | ||
| 1159 | #define bfin_read_DMA2_6_START_ADDR() bfin_read32(DMA2_6_START_ADDR) | ||
| 1160 | #define bfin_write_DMA2_6_START_ADDR(val) bfin_write32(DMA2_6_START_ADDR,val) | ||
| 1161 | #define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT) | ||
| 1162 | #define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT,val) | ||
| 1163 | #define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT) | ||
| 1164 | #define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT,val) | ||
| 1165 | #define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY) | ||
| 1166 | #define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY,val) | ||
| 1167 | #define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY) | ||
| 1168 | #define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY,val) | ||
| 1169 | #define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_read32(DMA2_6_CURR_DESC_PTR) | ||
| 1170 | #define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_write32(DMA2_6_CURR_DESC_PTR,val) | ||
| 1171 | #define bfin_read_DMA2_6_CURR_ADDR() bfin_read32(DMA2_6_CURR_ADDR) | ||
| 1172 | #define bfin_write_DMA2_6_CURR_ADDR(val) bfin_write32(DMA2_6_CURR_ADDR,val) | ||
| 1173 | #define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT) | ||
| 1174 | #define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT,val) | ||
| 1175 | #define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT) | ||
| 1176 | #define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT,val) | ||
| 1177 | #define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS) | ||
| 1178 | #define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS,val) | ||
| 1179 | #define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP) | ||
| 1180 | #define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP,val) | ||
| 1181 | #define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG) | ||
| 1182 | #define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG,val) | ||
| 1183 | #define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_read32(DMA2_7_NEXT_DESC_PTR) | ||
| 1184 | #define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_write32(DMA2_7_NEXT_DESC_PTR,val) | ||
| 1185 | #define bfin_read_DMA2_7_START_ADDR() bfin_read32(DMA2_7_START_ADDR) | ||
| 1186 | #define bfin_write_DMA2_7_START_ADDR(val) bfin_write32(DMA2_7_START_ADDR,val) | ||
| 1187 | #define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT) | ||
| 1188 | #define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT,val) | ||
| 1189 | #define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT) | ||
| 1190 | #define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT,val) | ||
| 1191 | #define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY) | ||
| 1192 | #define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY,val) | ||
| 1193 | #define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY) | ||
| 1194 | #define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY,val) | ||
| 1195 | #define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_read32(DMA2_7_CURR_DESC_PTR) | ||
| 1196 | #define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_write32(DMA2_7_CURR_DESC_PTR,val) | ||
| 1197 | #define bfin_read_DMA2_7_CURR_ADDR() bfin_read32(DMA2_7_CURR_ADDR) | ||
| 1198 | #define bfin_write_DMA2_7_CURR_ADDR(val) bfin_write32(DMA2_7_CURR_ADDR,val) | ||
| 1199 | #define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT) | ||
| 1200 | #define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT,val) | ||
| 1201 | #define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT) | ||
| 1202 | #define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT,val) | ||
| 1203 | #define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS) | ||
| 1204 | #define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS,val) | ||
| 1205 | #define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP) | ||
| 1206 | #define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP,val) | ||
| 1207 | #define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG) | ||
| 1208 | #define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG,val) | ||
| 1209 | #define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_read32(DMA2_8_NEXT_DESC_PTR) | ||
| 1210 | #define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_write32(DMA2_8_NEXT_DESC_PTR,val) | ||
| 1211 | #define bfin_read_DMA2_8_START_ADDR() bfin_read32(DMA2_8_START_ADDR) | ||
| 1212 | #define bfin_write_DMA2_8_START_ADDR(val) bfin_write32(DMA2_8_START_ADDR,val) | ||
| 1213 | #define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT) | ||
| 1214 | #define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT,val) | ||
| 1215 | #define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT) | ||
| 1216 | #define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT,val) | ||
| 1217 | #define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY) | ||
| 1218 | #define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY,val) | ||
| 1219 | #define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY) | ||
| 1220 | #define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY,val) | ||
| 1221 | #define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_read32(DMA2_8_CURR_DESC_PTR) | ||
| 1222 | #define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_write32(DMA2_8_CURR_DESC_PTR,val) | ||
| 1223 | #define bfin_read_DMA2_8_CURR_ADDR() bfin_read32(DMA2_8_CURR_ADDR) | ||
| 1224 | #define bfin_write_DMA2_8_CURR_ADDR(val) bfin_write32(DMA2_8_CURR_ADDR,val) | ||
| 1225 | #define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT) | ||
| 1226 | #define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT,val) | ||
| 1227 | #define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT) | ||
| 1228 | #define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT,val) | ||
| 1229 | #define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS) | ||
| 1230 | #define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS,val) | ||
| 1231 | #define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP) | ||
| 1232 | #define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP,val) | ||
| 1233 | #define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG) | ||
| 1234 | #define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG,val) | ||
| 1235 | #define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_read32(DMA2_9_NEXT_DESC_PTR) | ||
| 1236 | #define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_write32(DMA2_9_NEXT_DESC_PTR,val) | ||
| 1237 | #define bfin_read_DMA2_9_START_ADDR() bfin_read32(DMA2_9_START_ADDR) | ||
| 1238 | #define bfin_write_DMA2_9_START_ADDR(val) bfin_write32(DMA2_9_START_ADDR,val) | ||
| 1239 | #define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT) | ||
| 1240 | #define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT,val) | ||
| 1241 | #define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT) | ||
| 1242 | #define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT,val) | ||
| 1243 | #define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY) | ||
| 1244 | #define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY,val) | ||
| 1245 | #define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY) | ||
| 1246 | #define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY,val) | ||
| 1247 | #define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_read32(DMA2_9_CURR_DESC_PTR) | ||
| 1248 | #define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_write32(DMA2_9_CURR_DESC_PTR,val) | ||
| 1249 | #define bfin_read_DMA2_9_CURR_ADDR() bfin_read32(DMA2_9_CURR_ADDR) | ||
| 1250 | #define bfin_write_DMA2_9_CURR_ADDR(val) bfin_write32(DMA2_9_CURR_ADDR,val) | ||
| 1251 | #define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT) | ||
| 1252 | #define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT,val) | ||
| 1253 | #define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT) | ||
| 1254 | #define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT,val) | ||
| 1255 | #define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS) | ||
| 1256 | #define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS,val) | ||
| 1257 | #define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP) | ||
| 1258 | #define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP,val) | ||
| 1259 | #define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG) | ||
| 1260 | #define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG,val) | ||
| 1261 | #define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_read32(DMA2_10_NEXT_DESC_PTR) | ||
| 1262 | #define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_write32(DMA2_10_NEXT_DESC_PTR,val) | ||
| 1263 | #define bfin_read_DMA2_10_START_ADDR() bfin_read32(DMA2_10_START_ADDR) | ||
| 1264 | #define bfin_write_DMA2_10_START_ADDR(val) bfin_write32(DMA2_10_START_ADDR,val) | ||
| 1265 | #define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT) | ||
| 1266 | #define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT,val) | ||
| 1267 | #define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT) | ||
| 1268 | #define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT,val) | ||
| 1269 | #define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY) | ||
| 1270 | #define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY,val) | ||
| 1271 | #define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY) | ||
| 1272 | #define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY,val) | ||
| 1273 | #define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_read32(DMA2_10_CURR_DESC_PTR) | ||
| 1274 | #define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_write32(DMA2_10_CURR_DESC_PTR,val) | ||
| 1275 | #define bfin_read_DMA2_10_CURR_ADDR() bfin_read32(DMA2_10_CURR_ADDR) | ||
| 1276 | #define bfin_write_DMA2_10_CURR_ADDR(val) bfin_write32(DMA2_10_CURR_ADDR,val) | ||
| 1277 | #define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT) | ||
| 1278 | #define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT,val) | ||
| 1279 | #define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT) | ||
| 1280 | #define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT,val) | ||
| 1281 | #define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS) | ||
| 1282 | #define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS,val) | ||
| 1283 | #define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP) | ||
| 1284 | #define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP,val) | ||
| 1285 | #define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG) | ||
| 1286 | #define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG,val) | ||
| 1287 | #define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_read32(DMA2_11_NEXT_DESC_PTR) | ||
| 1288 | #define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_write32(DMA2_11_NEXT_DESC_PTR,val) | ||
| 1289 | #define bfin_read_DMA2_11_START_ADDR() bfin_read32(DMA2_11_START_ADDR) | ||
| 1290 | #define bfin_write_DMA2_11_START_ADDR(val) bfin_write32(DMA2_11_START_ADDR,val) | ||
| 1291 | #define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT) | ||
| 1292 | #define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT,val) | ||
| 1293 | #define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT) | ||
| 1294 | #define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT,val) | ||
| 1295 | #define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY) | ||
| 1296 | #define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY,val) | ||
| 1297 | #define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY) | ||
| 1298 | #define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY,val) | ||
| 1299 | #define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_read32(DMA2_11_CURR_DESC_PTR) | ||
| 1300 | #define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_write32(DMA2_11_CURR_DESC_PTR,val) | ||
| 1301 | #define bfin_read_DMA2_11_CURR_ADDR() bfin_read32(DMA2_11_CURR_ADDR) | ||
| 1302 | #define bfin_write_DMA2_11_CURR_ADDR(val) bfin_write32(DMA2_11_CURR_ADDR,val) | ||
| 1303 | #define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT) | ||
| 1304 | #define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT,val) | ||
| 1305 | #define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT) | ||
| 1306 | #define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT,val) | ||
| 1307 | #define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS) | ||
| 1308 | #define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS,val) | ||
| 1309 | #define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP) | ||
| 1310 | #define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val) | ||
| 1311 | /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ | ||
| 1312 | #define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG) | ||
| 1313 | #define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG,val) | ||
| 1314 | #define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_read32(MDMA2_D0_NEXT_DESC_PTR) | ||
| 1315 | #define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D0_NEXT_DESC_PTR,val) | ||
| 1316 | #define bfin_read_MDMA2_D0_START_ADDR() bfin_read32(MDMA2_D0_START_ADDR) | ||
| 1317 | #define bfin_write_MDMA2_D0_START_ADDR(val) bfin_write32(MDMA2_D0_START_ADDR,val) | ||
| 1318 | #define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT) | ||
| 1319 | #define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT,val) | ||
| 1320 | #define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT) | ||
| 1321 | #define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT,val) | ||
| 1322 | #define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY) | ||
| 1323 | #define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY,val) | ||
| 1324 | #define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY) | ||
| 1325 | #define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY,val) | ||
| 1326 | #define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_read32(MDMA2_D0_CURR_DESC_PTR) | ||
| 1327 | #define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_write32(MDMA2_D0_CURR_DESC_PTR,val) | ||
| 1328 | #define bfin_read_MDMA2_D0_CURR_ADDR() bfin_read32(MDMA2_D0_CURR_ADDR) | ||
| 1329 | #define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_write32(MDMA2_D0_CURR_ADDR,val) | ||
| 1330 | #define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT) | ||
| 1331 | #define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT,val) | ||
| 1332 | #define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT) | ||
| 1333 | #define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT,val) | ||
| 1334 | #define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS) | ||
| 1335 | #define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS,val) | ||
| 1336 | #define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP) | ||
| 1337 | #define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP,val) | ||
| 1338 | #define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG) | ||
| 1339 | #define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG,val) | ||
| 1340 | #define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_read32(MDMA2_S0_NEXT_DESC_PTR) | ||
| 1341 | #define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S0_NEXT_DESC_PTR,val) | ||
| 1342 | #define bfin_read_MDMA2_S0_START_ADDR() bfin_read32(MDMA2_S0_START_ADDR) | ||
| 1343 | #define bfin_write_MDMA2_S0_START_ADDR(val) bfin_write32(MDMA2_S0_START_ADDR,val) | ||
| 1344 | #define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT) | ||
| 1345 | #define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT,val) | ||
| 1346 | #define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT) | ||
| 1347 | #define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT,val) | ||
| 1348 | #define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY) | ||
| 1349 | #define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY,val) | ||
| 1350 | #define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY) | ||
| 1351 | #define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY,val) | ||
| 1352 | #define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_read32(MDMA2_S0_CURR_DESC_PTR) | ||
| 1353 | #define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_write32(MDMA2_S0_CURR_DESC_PTR,val) | ||
| 1354 | #define bfin_read_MDMA2_S0_CURR_ADDR() bfin_read32(MDMA2_S0_CURR_ADDR) | ||
| 1355 | #define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_write32(MDMA2_S0_CURR_ADDR,val) | ||
| 1356 | #define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT) | ||
| 1357 | #define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT,val) | ||
| 1358 | #define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT) | ||
| 1359 | #define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT,val) | ||
| 1360 | #define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS) | ||
| 1361 | #define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS,val) | ||
| 1362 | #define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP) | ||
| 1363 | #define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP,val) | ||
| 1364 | #define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG) | ||
| 1365 | #define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG,val) | ||
| 1366 | #define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_read32(MDMA2_D1_NEXT_DESC_PTR) | ||
| 1367 | #define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D1_NEXT_DESC_PTR,val) | ||
| 1368 | #define bfin_read_MDMA2_D1_START_ADDR() bfin_read32(MDMA2_D1_START_ADDR) | ||
| 1369 | #define bfin_write_MDMA2_D1_START_ADDR(val) bfin_write32(MDMA2_D1_START_ADDR,val) | ||
| 1370 | #define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT) | ||
| 1371 | #define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT,val) | ||
| 1372 | #define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT) | ||
| 1373 | #define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT,val) | ||
| 1374 | #define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY) | ||
| 1375 | #define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY,val) | ||
| 1376 | #define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY) | ||
| 1377 | #define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY,val) | ||
| 1378 | #define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_read32(MDMA2_D1_CURR_DESC_PTR) | ||
| 1379 | #define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_write32(MDMA2_D1_CURR_DESC_PTR,val) | ||
| 1380 | #define bfin_read_MDMA2_D1_CURR_ADDR() bfin_read32(MDMA2_D1_CURR_ADDR) | ||
| 1381 | #define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_write32(MDMA2_D1_CURR_ADDR,val) | ||
| 1382 | #define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT) | ||
| 1383 | #define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT,val) | ||
| 1384 | #define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT) | ||
| 1385 | #define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT,val) | ||
| 1386 | #define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS) | ||
| 1387 | #define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS,val) | ||
| 1388 | #define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP) | ||
| 1389 | #define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP,val) | ||
| 1390 | #define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG) | ||
| 1391 | #define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG,val) | ||
| 1392 | #define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_read32(MDMA2_S1_NEXT_DESC_PTR) | ||
| 1393 | #define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S1_NEXT_DESC_PTR,val) | ||
| 1394 | #define bfin_read_MDMA2_S1_START_ADDR() bfin_read32(MDMA2_S1_START_ADDR) | ||
| 1395 | #define bfin_write_MDMA2_S1_START_ADDR(val) bfin_write32(MDMA2_S1_START_ADDR,val) | ||
| 1396 | #define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT) | ||
| 1397 | #define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT,val) | ||
| 1398 | #define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT) | ||
| 1399 | #define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT,val) | ||
| 1400 | #define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY) | ||
| 1401 | #define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY,val) | ||
| 1402 | #define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY) | ||
| 1403 | #define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY,val) | ||
| 1404 | #define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_read32(MDMA2_S1_CURR_DESC_PTR) | ||
| 1405 | #define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_write32(MDMA2_S1_CURR_DESC_PTR,val) | ||
| 1406 | #define bfin_read_MDMA2_S1_CURR_ADDR() bfin_read32(MDMA2_S1_CURR_ADDR) | ||
| 1407 | #define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_write32(MDMA2_S1_CURR_ADDR,val) | ||
| 1408 | #define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT) | ||
| 1409 | #define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT,val) | ||
| 1410 | #define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT) | ||
| 1411 | #define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT,val) | ||
| 1412 | #define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS) | ||
| 1413 | #define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS,val) | ||
| 1414 | #define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP) | ||
| 1415 | #define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP,val) | ||
| 1416 | /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ | ||
| 1417 | #define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG) | ||
| 1418 | #define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val) | ||
| 1419 | #define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_read32(IMDMA_D0_NEXT_DESC_PTR) | ||
| 1420 | #define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D0_NEXT_DESC_PTR,val) | ||
| 1421 | #define bfin_read_IMDMA_D0_START_ADDR() bfin_read32(IMDMA_D0_START_ADDR) | ||
| 1422 | #define bfin_write_IMDMA_D0_START_ADDR(val) bfin_write32(IMDMA_D0_START_ADDR,val) | ||
| 1423 | #define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT) | ||
| 1424 | #define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT,val) | ||
| 1425 | #define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT) | ||
| 1426 | #define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT,val) | ||
| 1427 | #define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY) | ||
| 1428 | #define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY,val) | ||
| 1429 | #define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY) | ||
| 1430 | #define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY,val) | ||
| 1431 | #define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_read32(IMDMA_D0_CURR_DESC_PTR) | ||
| 1432 | #define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_write32(IMDMA_D0_CURR_DESC_PTR,val) | ||
| 1433 | #define bfin_read_IMDMA_D0_CURR_ADDR() bfin_read32(IMDMA_D0_CURR_ADDR) | ||
| 1434 | #define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_write32(IMDMA_D0_CURR_ADDR,val) | ||
| 1435 | #define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT) | ||
| 1436 | #define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT,val) | ||
| 1437 | #define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT) | ||
| 1438 | #define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT,val) | ||
| 1439 | #define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS) | ||
| 1440 | #define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS,val) | ||
| 1441 | #define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG) | ||
| 1442 | #define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG,val) | ||
| 1443 | #define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_read32(IMDMA_S0_NEXT_DESC_PTR) | ||
| 1444 | #define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S0_NEXT_DESC_PTR,val) | ||
| 1445 | #define bfin_read_IMDMA_S0_START_ADDR() bfin_read32(IMDMA_S0_START_ADDR) | ||
| 1446 | #define bfin_write_IMDMA_S0_START_ADDR(val) bfin_write32(IMDMA_S0_START_ADDR,val) | ||
| 1447 | #define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT) | ||
| 1448 | #define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT,val) | ||
| 1449 | #define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT) | ||
| 1450 | #define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT,val) | ||
| 1451 | #define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY) | ||
| 1452 | #define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY,val) | ||
| 1453 | #define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY) | ||
| 1454 | #define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY,val) | ||
| 1455 | #define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_read32(IMDMA_S0_CURR_DESC_PTR) | ||
| 1456 | #define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_write32(IMDMA_S0_CURR_DESC_PTR,val) | ||
| 1457 | #define bfin_read_IMDMA_S0_CURR_ADDR() bfin_read32(IMDMA_S0_CURR_ADDR) | ||
| 1458 | #define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_write32(IMDMA_S0_CURR_ADDR,val) | ||
| 1459 | #define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT) | ||
| 1460 | #define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT,val) | ||
| 1461 | #define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT) | ||
| 1462 | #define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT,val) | ||
| 1463 | #define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS) | ||
| 1464 | #define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS,val) | ||
| 1465 | #define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG) | ||
| 1466 | #define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG,val) | ||
| 1467 | #define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_read32(IMDMA_D1_NEXT_DESC_PTR) | ||
| 1468 | #define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D1_NEXT_DESC_PTR,val) | ||
| 1469 | #define bfin_read_IMDMA_D1_START_ADDR() bfin_read32(IMDMA_D1_START_ADDR) | ||
| 1470 | #define bfin_write_IMDMA_D1_START_ADDR(val) bfin_write32(IMDMA_D1_START_ADDR,val) | ||
| 1471 | #define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT) | ||
| 1472 | #define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT,val) | ||
| 1473 | #define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT) | ||
| 1474 | #define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT,val) | ||
| 1475 | #define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY) | ||
| 1476 | #define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY,val) | ||
| 1477 | #define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY) | ||
| 1478 | #define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY,val) | ||
| 1479 | #define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_read32(IMDMA_D1_CURR_DESC_PTR) | ||
| 1480 | #define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_write32(IMDMA_D1_CURR_DESC_PTR,val) | ||
| 1481 | #define bfin_read_IMDMA_D1_CURR_ADDR() bfin_read32(IMDMA_D1_CURR_ADDR) | ||
| 1482 | #define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_write32(IMDMA_D1_CURR_ADDR,val) | ||
| 1483 | #define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT) | ||
| 1484 | #define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT,val) | ||
| 1485 | #define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT) | ||
| 1486 | #define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT,val) | ||
| 1487 | #define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS) | ||
| 1488 | #define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS,val) | ||
| 1489 | #define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG) | ||
| 1490 | #define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG,val) | ||
| 1491 | #define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_read32(IMDMA_S1_NEXT_DESC_PTR) | ||
| 1492 | #define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S1_NEXT_DESC_PTR,val) | ||
| 1493 | #define bfin_read_IMDMA_S1_START_ADDR() bfin_read32(IMDMA_S1_START_ADDR) | ||
| 1494 | #define bfin_write_IMDMA_S1_START_ADDR(val) bfin_write32(IMDMA_S1_START_ADDR,val) | ||
| 1495 | #define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT) | ||
| 1496 | #define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT,val) | ||
| 1497 | #define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT) | ||
| 1498 | #define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT,val) | ||
| 1499 | #define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY) | ||
| 1500 | #define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY,val) | ||
| 1501 | #define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY) | ||
| 1502 | #define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY,val) | ||
| 1503 | #define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_read32(IMDMA_S1_CURR_DESC_PTR) | ||
| 1504 | #define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_write32(IMDMA_S1_CURR_DESC_PTR,val) | ||
| 1505 | #define bfin_read_IMDMA_S1_CURR_ADDR() bfin_read32(IMDMA_S1_CURR_ADDR) | ||
| 1506 | #define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_write32(IMDMA_S1_CURR_ADDR,val) | ||
| 1507 | #define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT) | ||
| 1508 | #define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT,val) | ||
| 1509 | #define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT) | ||
| 1510 | #define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT,val) | ||
| 1511 | #define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS) | ||
| 1512 | #define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val) | ||
| 1513 | |||
| 1514 | #define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA1_S0_CONFIG() | ||
| 1515 | #define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA1_S0_CONFIG(val) | ||
| 1516 | #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA1_S0_IRQ_STATUS() | ||
| 1517 | #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA1_S0_IRQ_STATUS(val) | ||
| 1518 | #define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA1_S0_X_MODIFY() | ||
| 1519 | #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA1_S0_X_MODIFY(val) | ||
| 1520 | #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA1_S0_Y_MODIFY() | ||
| 1521 | #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA1_S0_Y_MODIFY(val) | ||
| 1522 | #define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA1_S0_X_COUNT() | ||
| 1523 | #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA1_S0_X_COUNT(val) | ||
| 1524 | #define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA1_S0_Y_COUNT() | ||
| 1525 | #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA1_S0_Y_COUNT(val) | ||
| 1526 | #define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA1_S0_START_ADDR() | ||
| 1527 | #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA1_S0_START_ADDR(val) | ||
| 1528 | #define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA1_D0_CONFIG() | ||
| 1529 | #define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA1_D0_CONFIG(val) | ||
| 1530 | #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA1_D0_IRQ_STATUS() | ||
| 1531 | #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA1_D0_IRQ_STATUS(val) | ||
| 1532 | #define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA1_D0_X_MODIFY() | ||
| 1533 | #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA1_D0_X_MODIFY(val) | ||
| 1534 | #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA1_D0_Y_MODIFY() | ||
| 1535 | #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA1_D0_Y_MODIFY(val) | ||
| 1536 | #define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA1_D0_X_COUNT() | ||
| 1537 | #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA1_D0_X_COUNT(val) | ||
| 1538 | #define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA1_D0_Y_COUNT() | ||
| 1539 | #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA1_D0_Y_COUNT(val) | ||
| 1540 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR() | ||
| 1541 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val) | ||
| 1542 | |||
| 1543 | #endif /* _CDEF_BF561_H */ | ||
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h new file mode 100644 index 000000000000..a6de4c69ba55 --- /dev/null +++ b/include/asm-blackfin/mach-bf561/defBF561.h | |||
| @@ -0,0 +1,1717 @@ | |||
| 1 | |||
| 2 | /* | ||
| 3 | * File: include/asm-blackfin/mach-bf561/defBF561.h | ||
| 4 | * Based on: | ||
| 5 | * Author: | ||
| 6 | * | ||
| 7 | * Created: | ||
| 8 | * Description: | ||
| 9 | * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 | ||
| 10 | * Rev: | ||
| 11 | * | ||
| 12 | * Modified: | ||
| 13 | * | ||
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License as published by | ||
| 18 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; see the file COPYING. | ||
| 28 | * If not, write to the Free Software Foundation, | ||
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #ifndef _DEF_BF561_H | ||
| 33 | #define _DEF_BF561_H | ||
| 34 | /* | ||
| 35 | #if !defined(__ADSPBF561__) | ||
| 36 | #warning defBF561.h should only be included for BF561 chip. | ||
| 37 | #endif | ||
| 38 | */ | ||
| 39 | /* include all Core registers and bit definitions */ | ||
| 40 | #include <asm/mach-common/def_LPBlackfin.h> | ||
| 41 | |||
| 42 | /*********************************************************************************** */ | ||
| 43 | /* System MMR Register Map */ | ||
| 44 | /*********************************************************************************** */ | ||
| 45 | |||
| 46 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | ||
| 47 | |||
| 48 | #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ | ||
| 49 | #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ | ||
| 50 | #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ | ||
| 51 | #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ | ||
| 52 | #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ | ||
| 53 | #define CHIPID 0xFFC00014 /* Chip ID Register */ | ||
| 54 | |||
| 55 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ | ||
| 56 | #define SICA_SWRST 0xFFC00100 /* Software Reset register */ | ||
| 57 | #define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ | ||
| 58 | #define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ | ||
| 59 | #define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */ | ||
| 60 | #define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ | ||
| 61 | #define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ | ||
| 62 | #define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ | ||
| 63 | #define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ | ||
| 64 | #define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ | ||
| 65 | #define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ | ||
| 66 | #define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ | ||
| 67 | #define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ | ||
| 68 | #define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ | ||
| 69 | #define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ | ||
| 70 | #define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ | ||
| 71 | #define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ | ||
| 72 | #define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ | ||
| 73 | #define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ | ||
| 74 | |||
| 75 | /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ | ||
| 76 | #define SICB_SWRST 0xFFC01100 /* reserved */ | ||
| 77 | #define SICB_SYSCR 0xFFC01104 /* reserved */ | ||
| 78 | #define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */ | ||
| 79 | #define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */ | ||
| 80 | #define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */ | ||
| 81 | #define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */ | ||
| 82 | #define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */ | ||
| 83 | #define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */ | ||
| 84 | #define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */ | ||
| 85 | #define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */ | ||
| 86 | #define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */ | ||
| 87 | #define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */ | ||
| 88 | #define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */ | ||
| 89 | #define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */ | ||
| 90 | #define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */ | ||
| 91 | #define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */ | ||
| 92 | #define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */ | ||
| 93 | |||
| 94 | /* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ | ||
| 95 | #define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */ | ||
| 96 | #define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */ | ||
| 97 | #define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */ | ||
| 98 | |||
| 99 | /* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */ | ||
| 100 | #define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */ | ||
| 101 | #define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */ | ||
| 102 | #define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */ | ||
| 103 | |||
| 104 | /* UART Controller (0xFFC00400 - 0xFFC004FF) */ | ||
| 105 | #define UART_THR 0xFFC00400 /* Transmit Holding register */ | ||
| 106 | #define UART_RBR 0xFFC00400 /* Receive Buffer register */ | ||
| 107 | #define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ | ||
| 108 | #define UART_IER 0xFFC00404 /* Interrupt Enable Register */ | ||
| 109 | #define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ | ||
| 110 | #define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ | ||
| 111 | #define UART_LCR 0xFFC0040C /* Line Control Register */ | ||
| 112 | #define UART_MCR 0xFFC00410 /* Modem Control Register */ | ||
| 113 | #define UART_LSR 0xFFC00414 /* Line Status Register */ | ||
| 114 | #define UART_MSR 0xFFC00418 /* Modem Status Register */ | ||
| 115 | #define UART_SCR 0xFFC0041C /* SCR Scratch Register */ | ||
| 116 | #define UART_GCTL 0xFFC00424 /* Global Control Register */ | ||
| 117 | |||
| 118 | /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ | ||
| 119 | #define SPI_CTL 0xFFC00500 /* SPI Control Register */ | ||
| 120 | #define SPI_FLG 0xFFC00504 /* SPI Flag register */ | ||
| 121 | #define SPI_STAT 0xFFC00508 /* SPI Status register */ | ||
| 122 | #define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ | ||
| 123 | #define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ | ||
| 124 | #define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ | ||
| 125 | #define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ | ||
| 126 | |||
| 127 | /* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */ | ||
| 128 | #define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */ | ||
| 129 | #define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */ | ||
| 130 | #define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */ | ||
| 131 | #define TIMER0_WIDTH 0xFFC0060C /* Timer0 Width register */ | ||
| 132 | |||
| 133 | #define TIMER1_CONFIG 0xFFC00610 /* Timer1 Configuration register */ | ||
| 134 | #define TIMER1_COUNTER 0xFFC00614 /* Timer1 Counter register */ | ||
| 135 | #define TIMER1_PERIOD 0xFFC00618 /* Timer1 Period register */ | ||
| 136 | #define TIMER1_WIDTH 0xFFC0061C /* Timer1 Width register */ | ||
| 137 | |||
| 138 | #define TIMER2_CONFIG 0xFFC00620 /* Timer2 Configuration register */ | ||
| 139 | #define TIMER2_COUNTER 0xFFC00624 /* Timer2 Counter register */ | ||
| 140 | #define TIMER2_PERIOD 0xFFC00628 /* Timer2 Period register */ | ||
| 141 | #define TIMER2_WIDTH 0xFFC0062C /* Timer2 Width register */ | ||
| 142 | |||
| 143 | #define TIMER3_CONFIG 0xFFC00630 /* Timer3 Configuration register */ | ||
| 144 | #define TIMER3_COUNTER 0xFFC00634 /* Timer3 Counter register */ | ||
| 145 | #define TIMER3_PERIOD 0xFFC00638 /* Timer3 Period register */ | ||
| 146 | #define TIMER3_WIDTH 0xFFC0063C /* Timer3 Width register */ | ||
| 147 | |||
| 148 | #define TIMER4_CONFIG 0xFFC00640 /* Timer4 Configuration register */ | ||
| 149 | #define TIMER4_COUNTER 0xFFC00644 /* Timer4 Counter register */ | ||
| 150 | #define TIMER4_PERIOD 0xFFC00648 /* Timer4 Period register */ | ||
| 151 | #define TIMER4_WIDTH 0xFFC0064C /* Timer4 Width register */ | ||
| 152 | |||
| 153 | #define TIMER5_CONFIG 0xFFC00650 /* Timer5 Configuration register */ | ||
| 154 | #define TIMER5_COUNTER 0xFFC00654 /* Timer5 Counter register */ | ||
| 155 | #define TIMER5_PERIOD 0xFFC00658 /* Timer5 Period register */ | ||
| 156 | #define TIMER5_WIDTH 0xFFC0065C /* Timer5 Width register */ | ||
| 157 | |||
| 158 | #define TIMER6_CONFIG 0xFFC00660 /* Timer6 Configuration register */ | ||
| 159 | #define TIMER6_COUNTER 0xFFC00664 /* Timer6 Counter register */ | ||
| 160 | #define TIMER6_PERIOD 0xFFC00668 /* Timer6 Period register */ | ||
| 161 | #define TIMER6_WIDTH 0xFFC0066C /* Timer6 Width register */ | ||
| 162 | |||
| 163 | #define TIMER7_CONFIG 0xFFC00670 /* Timer7 Configuration register */ | ||
| 164 | #define TIMER7_COUNTER 0xFFC00674 /* Timer7 Counter register */ | ||
| 165 | #define TIMER7_PERIOD 0xFFC00678 /* Timer7 Period register */ | ||
| 166 | #define TIMER7_WIDTH 0xFFC0067C /* Timer7 Width register */ | ||
| 167 | |||
| 168 | #define TMRS8_ENABLE 0xFFC00680 /* Timer Enable Register */ | ||
| 169 | #define TMRS8_DISABLE 0xFFC00684 /* Timer Disable register */ | ||
| 170 | #define TMRS8_STATUS 0xFFC00688 /* Timer Status register */ | ||
| 171 | |||
| 172 | /* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */ | ||
| 173 | #define TIMER8_CONFIG 0xFFC01600 /* Timer8 Configuration register */ | ||
| 174 | #define TIMER8_COUNTER 0xFFC01604 /* Timer8 Counter register */ | ||
| 175 | #define TIMER8_PERIOD 0xFFC01608 /* Timer8 Period register */ | ||
| 176 | #define TIMER8_WIDTH 0xFFC0160C /* Timer8 Width register */ | ||
| 177 | |||
| 178 | #define TIMER9_CONFIG 0xFFC01610 /* Timer9 Configuration register */ | ||
| 179 | #define TIMER9_COUNTER 0xFFC01614 /* Timer9 Counter register */ | ||
| 180 | #define TIMER9_PERIOD 0xFFC01618 /* Timer9 Period register */ | ||
| 181 | #define TIMER9_WIDTH 0xFFC0161C /* Timer9 Width register */ | ||
| 182 | |||
| 183 | #define TIMER10_CONFIG 0xFFC01620 /* Timer10 Configuration register */ | ||
| 184 | #define TIMER10_COUNTER 0xFFC01624 /* Timer10 Counter register */ | ||
| 185 | #define TIMER10_PERIOD 0xFFC01628 /* Timer10 Period register */ | ||
| 186 | #define TIMER10_WIDTH 0xFFC0162C /* Timer10 Width register */ | ||
| 187 | |||
| 188 | #define TIMER11_CONFIG 0xFFC01630 /* Timer11 Configuration register */ | ||
| 189 | #define TIMER11_COUNTER 0xFFC01634 /* Timer11 Counter register */ | ||
| 190 | #define TIMER11_PERIOD 0xFFC01638 /* Timer11 Period register */ | ||
| 191 | #define TIMER11_WIDTH 0xFFC0163C /* Timer11 Width register */ | ||
| 192 | |||
| 193 | #define TMRS4_ENABLE 0xFFC01640 /* Timer Enable Register */ | ||
| 194 | #define TMRS4_DISABLE 0xFFC01644 /* Timer Disable register */ | ||
| 195 | #define TMRS4_STATUS 0xFFC01648 /* Timer Status register */ | ||
| 196 | |||
| 197 | /* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ | ||
| 198 | #define FIO0_FLAG_D 0xFFC00700 /* Flag Data register */ | ||
| 199 | #define FIO0_FLAG_C 0xFFC00704 /* Flag Clear register */ | ||
| 200 | #define FIO0_FLAG_S 0xFFC00708 /* Flag Set register */ | ||
| 201 | #define FIO0_FLAG_T 0xFFC0070C /* Flag Toggle register */ | ||
| 202 | #define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */ | ||
| 203 | #define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */ | ||
| 204 | #define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */ | ||
| 205 | #define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */ | ||
| 206 | #define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */ | ||
| 207 | #define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */ | ||
| 208 | #define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */ | ||
| 209 | #define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */ | ||
| 210 | #define FIO0_DIR 0xFFC00730 /* Flag Direction register */ | ||
| 211 | #define FIO0_POLAR 0xFFC00734 /* Flag Polarity register */ | ||
| 212 | #define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */ | ||
| 213 | #define FIO0_BOTH 0xFFC0073C /* Flag Set on Both Edges register */ | ||
| 214 | #define FIO0_INEN 0xFFC00740 /* Flag Input Enable register */ | ||
| 215 | |||
| 216 | /* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */ | ||
| 217 | #define FIO1_FLAG_D 0xFFC01500 /* Flag Data register (mask used to directly */ | ||
| 218 | #define FIO1_FLAG_C 0xFFC01504 /* Flag Clear register */ | ||
| 219 | #define FIO1_FLAG_S 0xFFC01508 /* Flag Set register */ | ||
| 220 | #define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register (mask used to */ | ||
| 221 | #define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */ | ||
| 222 | #define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */ | ||
| 223 | #define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */ | ||
| 224 | #define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */ | ||
| 225 | #define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */ | ||
| 226 | #define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */ | ||
| 227 | #define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */ | ||
| 228 | #define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */ | ||
| 229 | #define FIO1_DIR 0xFFC01530 /* Flag Direction register */ | ||
| 230 | #define FIO1_POLAR 0xFFC01534 /* Flag Polarity register */ | ||
| 231 | #define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */ | ||
| 232 | #define FIO1_BOTH 0xFFC0153C /* Flag Set on Both Edges register */ | ||
| 233 | #define FIO1_INEN 0xFFC01540 /* Flag Input Enable register */ | ||
| 234 | |||
| 235 | /* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */ | ||
| 236 | #define FIO2_FLAG_D 0xFFC01700 /* Flag Data register (mask used to directly */ | ||
| 237 | #define FIO2_FLAG_C 0xFFC01704 /* Flag Clear register */ | ||
| 238 | #define FIO2_FLAG_S 0xFFC01708 /* Flag Set register */ | ||
| 239 | #define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register (mask used to */ | ||
| 240 | #define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */ | ||
| 241 | #define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */ | ||
| 242 | #define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */ | ||
| 243 | #define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */ | ||
| 244 | #define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */ | ||
| 245 | #define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */ | ||
| 246 | #define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */ | ||
| 247 | #define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */ | ||
| 248 | #define FIO2_DIR 0xFFC01730 /* Flag Direction register */ | ||
| 249 | #define FIO2_POLAR 0xFFC01734 /* Flag Polarity register */ | ||
| 250 | #define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */ | ||
| 251 | #define FIO2_BOTH 0xFFC0173C /* Flag Set on Both Edges register */ | ||
| 252 | #define FIO2_INEN 0xFFC01740 /* Flag Input Enable register */ | ||
| 253 | |||
| 254 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ | ||
| 255 | #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ | ||
| 256 | #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ | ||
| 257 | #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ | ||
| 258 | #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ | ||
| 259 | #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ | ||
| 260 | #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ | ||
| 261 | #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ | ||
| 262 | #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ | ||
| 263 | #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ | ||
| 264 | #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ | ||
| 265 | #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ | ||
| 266 | #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ | ||
| 267 | #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ | ||
| 268 | #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ | ||
| 269 | #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ | ||
| 270 | #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ | ||
| 271 | #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ | ||
| 272 | #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ | ||
| 273 | #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ | ||
| 274 | #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ | ||
| 275 | #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ | ||
| 276 | #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ | ||
| 277 | |||
| 278 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ | ||
| 279 | #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ | ||
| 280 | #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ | ||
| 281 | #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ | ||
| 282 | #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ | ||
| 283 | #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ | ||
| 284 | #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ | ||
| 285 | #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ | ||
| 286 | #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ | ||
| 287 | #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ | ||
| 288 | #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ | ||
| 289 | #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ | ||
| 290 | #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ | ||
| 291 | #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ | ||
| 292 | #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ | ||
| 293 | #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ | ||
| 294 | #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ | ||
| 295 | #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ | ||
| 296 | #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ | ||
| 297 | #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ | ||
| 298 | #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ | ||
| 299 | #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ | ||
| 300 | #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ | ||
| 301 | |||
| 302 | /* Asynchronous Memory Controller - External Bus Interface Unit */ | ||
| 303 | #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ | ||
| 304 | #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ | ||
| 305 | #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ | ||
| 306 | |||
| 307 | /* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ | ||
| 308 | #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ | ||
| 309 | #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ | ||
| 310 | #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ | ||
| 311 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ | ||
| 312 | |||
| 313 | /* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */ | ||
| 314 | #define PPI0_CONTROL 0xFFC01000 /* PPI0 Control register */ | ||
| 315 | #define PPI0_STATUS 0xFFC01004 /* PPI0 Status register */ | ||
| 316 | #define PPI0_COUNT 0xFFC01008 /* PPI0 Transfer Count register */ | ||
| 317 | #define PPI0_DELAY 0xFFC0100C /* PPI0 Delay Count register */ | ||
| 318 | #define PPI0_FRAME 0xFFC01010 /* PPI0 Frame Length register */ | ||
| 319 | |||
| 320 | /*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */ | ||
| 321 | #define PPI1_CONTROL 0xFFC01300 /* PPI1 Control register */ | ||
| 322 | #define PPI1_STATUS 0xFFC01304 /* PPI1 Status register */ | ||
| 323 | #define PPI1_COUNT 0xFFC01308 /* PPI1 Transfer Count register */ | ||
| 324 | #define PPI1_DELAY 0xFFC0130C /* PPI1 Delay Count register */ | ||
| 325 | #define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */ | ||
| 326 | |||
| 327 | /*DMA traffic control registers */ | ||
| 328 | #define DMA1_TC_PER 0xFFC01B0C /* Traffic control periods */ | ||
| 329 | #define DMA1_TC_CNT 0xFFC01B10 /* Traffic control current counts */ | ||
| 330 | #define DMA2_TC_PER 0xFFC00B0C /* Traffic control periods */ | ||
| 331 | #define DMA2_TC_CNT 0xFFC00B10 /* Traffic control current counts */ | ||
| 332 | |||
| 333 | /* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ | ||
| 334 | #define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */ | ||
| 335 | #define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */ | ||
| 336 | #define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */ | ||
| 337 | #define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */ | ||
| 338 | #define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */ | ||
| 339 | #define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */ | ||
| 340 | #define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */ | ||
| 341 | #define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */ | ||
| 342 | #define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */ | ||
| 343 | #define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */ | ||
| 344 | #define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */ | ||
| 345 | #define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */ | ||
| 346 | #define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */ | ||
| 347 | |||
| 348 | #define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */ | ||
| 349 | #define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */ | ||
| 350 | #define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */ | ||
| 351 | #define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */ | ||
| 352 | #define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */ | ||
| 353 | #define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */ | ||
| 354 | #define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */ | ||
| 355 | #define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */ | ||
| 356 | #define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */ | ||
| 357 | #define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */ | ||
| 358 | #define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */ | ||
| 359 | #define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt/Status Register */ | ||
| 360 | #define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */ | ||
| 361 | |||
| 362 | #define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */ | ||
| 363 | #define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */ | ||
| 364 | #define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */ | ||
| 365 | #define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */ | ||
| 366 | #define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */ | ||
| 367 | #define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */ | ||
| 368 | #define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */ | ||
| 369 | #define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */ | ||
| 370 | #define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */ | ||
| 371 | #define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */ | ||
| 372 | #define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */ | ||
| 373 | #define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */ | ||
| 374 | #define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */ | ||
| 375 | |||
| 376 | #define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */ | ||
| 377 | #define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */ | ||
| 378 | #define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */ | ||
| 379 | #define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */ | ||
| 380 | #define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */ | ||
| 381 | #define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */ | ||
| 382 | #define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */ | ||
| 383 | #define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */ | ||
| 384 | #define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */ | ||
| 385 | #define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */ | ||
| 386 | #define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */ | ||
| 387 | #define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt/Status Register */ | ||
| 388 | #define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */ | ||
| 389 | |||
| 390 | #define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */ | ||
| 391 | #define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */ | ||
| 392 | #define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */ | ||
| 393 | #define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */ | ||
| 394 | #define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */ | ||
| 395 | #define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */ | ||
| 396 | #define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */ | ||
| 397 | #define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */ | ||
| 398 | #define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */ | ||
| 399 | #define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */ | ||
| 400 | #define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */ | ||
| 401 | #define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt/Status Register */ | ||
| 402 | #define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */ | ||
| 403 | |||
| 404 | #define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */ | ||
| 405 | #define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */ | ||
| 406 | #define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */ | ||
| 407 | #define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */ | ||
| 408 | #define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */ | ||
| 409 | #define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */ | ||
| 410 | #define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */ | ||
| 411 | #define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */ | ||
| 412 | #define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */ | ||
| 413 | #define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */ | ||
| 414 | #define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */ | ||
| 415 | #define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt/Status Register */ | ||
| 416 | #define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */ | ||
| 417 | |||
| 418 | #define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */ | ||
| 419 | #define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */ | ||
| 420 | #define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */ | ||
| 421 | #define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */ | ||
| 422 | #define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */ | ||
| 423 | #define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */ | ||
| 424 | #define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */ | ||
| 425 | #define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */ | ||
| 426 | #define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */ | ||
| 427 | #define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */ | ||
| 428 | #define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */ | ||
| 429 | #define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt/Status Register */ | ||
| 430 | #define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */ | ||
| 431 | |||
| 432 | #define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */ | ||
| 433 | #define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */ | ||
| 434 | #define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */ | ||
| 435 | #define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */ | ||
| 436 | #define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */ | ||
| 437 | #define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */ | ||
| 438 | #define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */ | ||
| 439 | #define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */ | ||
| 440 | #define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */ | ||
| 441 | #define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */ | ||
| 442 | #define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */ | ||
| 443 | #define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt/Status Register */ | ||
| 444 | #define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */ | ||
| 445 | |||
| 446 | #define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */ | ||
| 447 | #define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */ | ||
| 448 | #define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */ | ||
| 449 | #define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */ | ||
| 450 | #define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */ | ||
| 451 | #define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */ | ||
| 452 | #define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */ | ||
| 453 | #define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */ | ||
| 454 | #define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */ | ||
| 455 | #define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */ | ||
| 456 | #define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */ | ||
| 457 | #define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt/Status Register */ | ||
| 458 | #define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */ | ||
| 459 | |||
| 460 | #define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */ | ||
| 461 | #define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */ | ||
| 462 | #define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */ | ||
| 463 | #define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */ | ||
| 464 | #define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */ | ||
| 465 | #define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */ | ||
| 466 | #define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */ | ||
| 467 | #define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */ | ||
| 468 | #define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */ | ||
| 469 | #define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */ | ||
| 470 | #define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */ | ||
| 471 | #define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt/Status Register */ | ||
| 472 | #define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */ | ||
| 473 | |||
| 474 | #define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */ | ||
| 475 | #define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */ | ||
| 476 | #define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */ | ||
| 477 | #define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */ | ||
| 478 | #define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */ | ||
| 479 | #define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */ | ||
| 480 | #define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */ | ||
| 481 | #define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */ | ||
| 482 | #define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */ | ||
| 483 | #define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */ | ||
| 484 | #define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */ | ||
| 485 | #define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt/Status Register */ | ||
| 486 | #define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */ | ||
| 487 | |||
| 488 | #define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */ | ||
| 489 | #define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */ | ||
| 490 | #define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */ | ||
| 491 | #define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */ | ||
| 492 | #define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */ | ||
| 493 | #define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */ | ||
| 494 | #define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */ | ||
| 495 | #define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */ | ||
| 496 | #define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */ | ||
| 497 | #define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */ | ||
| 498 | #define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */ | ||
| 499 | #define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt/Status Register */ | ||
| 500 | #define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */ | ||
| 501 | |||
| 502 | /* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ | ||
| 503 | #define MDMA1_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */ | ||
| 504 | #define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */ | ||
| 505 | #define MDMA1_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */ | ||
| 506 | #define MDMA1_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */ | ||
| 507 | #define MDMA1_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */ | ||
| 508 | #define MDMA1_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */ | ||
| 509 | #define MDMA1_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */ | ||
| 510 | #define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ | ||
| 511 | #define MDMA1_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */ | ||
| 512 | #define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */ | ||
| 513 | #define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */ | ||
| 514 | #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */ | ||
| 515 | #define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */ | ||
| 516 | |||
| 517 | #define MDMA1_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */ | ||
| 518 | #define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */ | ||
| 519 | #define MDMA1_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */ | ||
| 520 | #define MDMA1_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */ | ||
| 521 | #define MDMA1_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */ | ||
| 522 | #define MDMA1_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */ | ||
| 523 | #define MDMA1_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */ | ||
| 524 | #define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ | ||
| 525 | #define MDMA1_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */ | ||
| 526 | #define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */ | ||
| 527 | #define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */ | ||
| 528 | #define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */ | ||
| 529 | #define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */ | ||
| 530 | |||
| 531 | #define MDMA1_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */ | ||
| 532 | #define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */ | ||
| 533 | #define MDMA1_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */ | ||
| 534 | #define MDMA1_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */ | ||
| 535 | #define MDMA1_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */ | ||
| 536 | #define MDMA1_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */ | ||
| 537 | #define MDMA1_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */ | ||
| 538 | #define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ | ||
| 539 | #define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */ | ||
| 540 | #define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */ | ||
| 541 | #define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */ | ||
| 542 | #define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */ | ||
| 543 | #define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */ | ||
| 544 | |||
| 545 | #define MDMA1_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */ | ||
| 546 | #define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */ | ||
| 547 | #define MDMA1_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */ | ||
| 548 | #define MDMA1_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */ | ||
| 549 | #define MDMA1_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */ | ||
| 550 | #define MDMA1_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */ | ||
| 551 | #define MDMA1_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */ | ||
| 552 | #define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ | ||
| 553 | #define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */ | ||
| 554 | #define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */ | ||
| 555 | #define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */ | ||
| 556 | #define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */ | ||
| 557 | #define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */ | ||
| 558 | |||
| 559 | /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ | ||
| 560 | #define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */ | ||
| 561 | #define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */ | ||
| 562 | #define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */ | ||
| 563 | #define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */ | ||
| 564 | #define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */ | ||
| 565 | #define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */ | ||
| 566 | #define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */ | ||
| 567 | #define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */ | ||
| 568 | #define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */ | ||
| 569 | #define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */ | ||
| 570 | #define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */ | ||
| 571 | #define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */ | ||
| 572 | #define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */ | ||
| 573 | |||
| 574 | #define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */ | ||
| 575 | #define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */ | ||
| 576 | #define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */ | ||
| 577 | #define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */ | ||
| 578 | #define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */ | ||
| 579 | #define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */ | ||
| 580 | #define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */ | ||
| 581 | #define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */ | ||
| 582 | #define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */ | ||
| 583 | #define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */ | ||
| 584 | #define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */ | ||
| 585 | #define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */ | ||
| 586 | #define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */ | ||
| 587 | |||
| 588 | #define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */ | ||
| 589 | #define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */ | ||
| 590 | #define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */ | ||
| 591 | #define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */ | ||
| 592 | #define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */ | ||
| 593 | #define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */ | ||
| 594 | #define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */ | ||
| 595 | #define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */ | ||
| 596 | #define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */ | ||
| 597 | #define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */ | ||
| 598 | #define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */ | ||
| 599 | #define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */ | ||
| 600 | #define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */ | ||
| 601 | |||
| 602 | #define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */ | ||
| 603 | #define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */ | ||
| 604 | #define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */ | ||
| 605 | #define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */ | ||
| 606 | #define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */ | ||
| 607 | #define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */ | ||
| 608 | #define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */ | ||
| 609 | #define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */ | ||
| 610 | #define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */ | ||
| 611 | #define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */ | ||
| 612 | #define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */ | ||
| 613 | #define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */ | ||
| 614 | #define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */ | ||
| 615 | |||
| 616 | #define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */ | ||
| 617 | #define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */ | ||
| 618 | #define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */ | ||
| 619 | #define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */ | ||
| 620 | #define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */ | ||
| 621 | #define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */ | ||
| 622 | #define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */ | ||
| 623 | #define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */ | ||
| 624 | #define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */ | ||
| 625 | #define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */ | ||
| 626 | #define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */ | ||
| 627 | #define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */ | ||
| 628 | #define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */ | ||
| 629 | |||
| 630 | #define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */ | ||
| 631 | #define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */ | ||
| 632 | #define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */ | ||
| 633 | #define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */ | ||
| 634 | #define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */ | ||
| 635 | #define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */ | ||
| 636 | #define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */ | ||
| 637 | #define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */ | ||
| 638 | #define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */ | ||
| 639 | #define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */ | ||
| 640 | #define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */ | ||
| 641 | #define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */ | ||
| 642 | #define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */ | ||
| 643 | |||
| 644 | #define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */ | ||
| 645 | #define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */ | ||
| 646 | #define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */ | ||
| 647 | #define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */ | ||
| 648 | #define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */ | ||
| 649 | #define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */ | ||
| 650 | #define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */ | ||
| 651 | #define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */ | ||
| 652 | #define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */ | ||
| 653 | #define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */ | ||
| 654 | #define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */ | ||
| 655 | #define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */ | ||
| 656 | #define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */ | ||
| 657 | |||
| 658 | #define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */ | ||
| 659 | #define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */ | ||
| 660 | #define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */ | ||
| 661 | #define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */ | ||
| 662 | #define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */ | ||
| 663 | #define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */ | ||
| 664 | #define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */ | ||
| 665 | #define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */ | ||
| 666 | #define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */ | ||
| 667 | #define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */ | ||
| 668 | #define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */ | ||
| 669 | #define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */ | ||
| 670 | #define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */ | ||
| 671 | |||
| 672 | #define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */ | ||
| 673 | #define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */ | ||
| 674 | #define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */ | ||
| 675 | #define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */ | ||
| 676 | #define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */ | ||
| 677 | #define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */ | ||
| 678 | #define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */ | ||
| 679 | #define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */ | ||
| 680 | #define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */ | ||
| 681 | #define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */ | ||
| 682 | #define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */ | ||
| 683 | #define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */ | ||
| 684 | #define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */ | ||
| 685 | |||
| 686 | #define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */ | ||
| 687 | #define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */ | ||
| 688 | #define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */ | ||
| 689 | #define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */ | ||
| 690 | #define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */ | ||
| 691 | #define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */ | ||
| 692 | #define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */ | ||
| 693 | #define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */ | ||
| 694 | #define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */ | ||
| 695 | #define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */ | ||
| 696 | #define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */ | ||
| 697 | #define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */ | ||
| 698 | #define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */ | ||
| 699 | |||
| 700 | #define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */ | ||
| 701 | #define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */ | ||
| 702 | #define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */ | ||
| 703 | #define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */ | ||
| 704 | #define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */ | ||
| 705 | #define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */ | ||
| 706 | #define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */ | ||
| 707 | #define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */ | ||
| 708 | #define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */ | ||
| 709 | #define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */ | ||
| 710 | #define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */ | ||
| 711 | #define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */ | ||
| 712 | #define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */ | ||
| 713 | |||
| 714 | #define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */ | ||
| 715 | #define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */ | ||
| 716 | #define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */ | ||
| 717 | #define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */ | ||
| 718 | #define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */ | ||
| 719 | #define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */ | ||
| 720 | #define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */ | ||
| 721 | #define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */ | ||
| 722 | #define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */ | ||
| 723 | #define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */ | ||
| 724 | #define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */ | ||
| 725 | #define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */ | ||
| 726 | #define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */ | ||
| 727 | |||
| 728 | /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ | ||
| 729 | #define MDMA2_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */ | ||
| 730 | #define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */ | ||
| 731 | #define MDMA2_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */ | ||
| 732 | #define MDMA2_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */ | ||
| 733 | #define MDMA2_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */ | ||
| 734 | #define MDMA2_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */ | ||
| 735 | #define MDMA2_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */ | ||
| 736 | #define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */ | ||
| 737 | #define MDMA2_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */ | ||
| 738 | #define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */ | ||
| 739 | #define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */ | ||
| 740 | #define MDMA2_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */ | ||
| 741 | #define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */ | ||
| 742 | |||
| 743 | #define MDMA2_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */ | ||
| 744 | #define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */ | ||
| 745 | #define MDMA2_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */ | ||
| 746 | #define MDMA2_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */ | ||
| 747 | #define MDMA2_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */ | ||
| 748 | #define MDMA2_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */ | ||
| 749 | #define MDMA2_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */ | ||
| 750 | #define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */ | ||
| 751 | #define MDMA2_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */ | ||
| 752 | #define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */ | ||
| 753 | #define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */ | ||
| 754 | #define MDMA2_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */ | ||
| 755 | #define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */ | ||
| 756 | |||
| 757 | #define MDMA2_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */ | ||
| 758 | #define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */ | ||
| 759 | #define MDMA2_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */ | ||
| 760 | #define MDMA2_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */ | ||
| 761 | #define MDMA2_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */ | ||
| 762 | #define MDMA2_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */ | ||
| 763 | #define MDMA2_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */ | ||
| 764 | #define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */ | ||
| 765 | #define MDMA2_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */ | ||
| 766 | #define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */ | ||
| 767 | #define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */ | ||
| 768 | #define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */ | ||
| 769 | #define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */ | ||
| 770 | |||
| 771 | #define MDMA2_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */ | ||
| 772 | #define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */ | ||
| 773 | #define MDMA2_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */ | ||
| 774 | #define MDMA2_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */ | ||
| 775 | #define MDMA2_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */ | ||
| 776 | #define MDMA2_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */ | ||
| 777 | #define MDMA2_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */ | ||
| 778 | #define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */ | ||
| 779 | #define MDMA2_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */ | ||
| 780 | #define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */ | ||
| 781 | #define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */ | ||
| 782 | #define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ | ||
| 783 | #define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ | ||
| 784 | |||
| 785 | /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ | ||
| 786 | #define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */ | ||
| 787 | #define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */ | ||
| 788 | #define IMDMA_D0_START_ADDR 0xFFC01804 /*IMDMA Stream 0 Destination Start Address */ | ||
| 789 | #define IMDMA_D0_X_COUNT 0xFFC01810 /*IMDMA Stream 0 Destination Inner-Loop Count */ | ||
| 790 | #define IMDMA_D0_Y_COUNT 0xFFC01818 /*IMDMA Stream 0 Destination Outer-Loop Count */ | ||
| 791 | #define IMDMA_D0_X_MODIFY 0xFFC01814 /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */ | ||
| 792 | #define IMDMA_D0_Y_MODIFY 0xFFC0181C /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */ | ||
| 793 | #define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /*IMDMA Stream 0 Destination Current Descriptor Ptr */ | ||
| 794 | #define IMDMA_D0_CURR_ADDR 0xFFC01824 /*IMDMA Stream 0 Destination Current Address */ | ||
| 795 | #define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */ | ||
| 796 | #define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */ | ||
| 797 | #define IMDMA_D0_IRQ_STATUS 0xFFC01828 /*IMDMA Stream 0 Destination Interrupt/Status */ | ||
| 798 | |||
| 799 | #define IMDMA_S0_CONFIG 0xFFC01848 /*IMDMA Stream 0 Source Configuration */ | ||
| 800 | #define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */ | ||
| 801 | #define IMDMA_S0_START_ADDR 0xFFC01844 /*IMDMA Stream 0 Source Start Address */ | ||
| 802 | #define IMDMA_S0_X_COUNT 0xFFC01850 /*IMDMA Stream 0 Source Inner-Loop Count */ | ||
| 803 | #define IMDMA_S0_Y_COUNT 0xFFC01858 /*IMDMA Stream 0 Source Outer-Loop Count */ | ||
| 804 | #define IMDMA_S0_X_MODIFY 0xFFC01854 /*IMDMA Stream 0 Source Inner-Loop Address-Increment */ | ||
| 805 | #define IMDMA_S0_Y_MODIFY 0xFFC0185C /*IMDMA Stream 0 Source Outer-Loop Address-Increment */ | ||
| 806 | #define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /*IMDMA Stream 0 Source Current Descriptor Ptr reg */ | ||
| 807 | #define IMDMA_S0_CURR_ADDR 0xFFC01864 /*IMDMA Stream 0 Source Current Address */ | ||
| 808 | #define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */ | ||
| 809 | #define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */ | ||
| 810 | #define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */ | ||
| 811 | |||
| 812 | #define IMDMA_D1_CONFIG 0xFFC01888 /*IMDMA Stream 1 Destination Configuration */ | ||
| 813 | #define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */ | ||
| 814 | #define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */ | ||
| 815 | #define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */ | ||
| 816 | #define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */ | ||
| 817 | #define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */ | ||
| 818 | #define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */ | ||
| 819 | #define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */ | ||
| 820 | #define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */ | ||
| 821 | #define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */ | ||
| 822 | #define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */ | ||
| 823 | #define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */ | ||
| 824 | |||
| 825 | #define IMDMA_S1_CONFIG 0xFFC018C8 /*IMDMA Stream 1 Source Configuration */ | ||
| 826 | #define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */ | ||
| 827 | #define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */ | ||
| 828 | #define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */ | ||
| 829 | #define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */ | ||
| 830 | #define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */ | ||
| 831 | #define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */ | ||
| 832 | #define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */ | ||
| 833 | #define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */ | ||
| 834 | #define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */ | ||
| 835 | #define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */ | ||
| 836 | #define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */ | ||
| 837 | |||
| 838 | /*********************************************************************************** */ | ||
| 839 | /* System MMR Register Bits */ | ||
| 840 | /******************************************************************************* */ | ||
| 841 | |||
| 842 | /* ********************* PLL AND RESET MASKS ************************ */ | ||
| 843 | |||
| 844 | /* PLL_CTL Masks */ | ||
| 845 | #define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ | ||
| 846 | #define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ | ||
| 847 | #define PLL_OFF 0x00000002 /* Shut off PLL clocks */ | ||
| 848 | #define STOPCK_OFF 0x00000008 /* Core clock off */ | ||
| 849 | #define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ | ||
| 850 | #define BYPASS 0x00000100 /* Bypass the PLL */ | ||
| 851 | |||
| 852 | /* CHIPID Masks */ | ||
| 853 | #define CHIPID_VERSION 0xF0000000 | ||
| 854 | #define CHIPID_FAMILY 0x0FFFF000 | ||
| 855 | #define CHIPID_MANUFACTURE 0x00000FFE | ||
| 856 | |||
| 857 | /* PLL_DIV Masks */ | ||
| 858 | #define SCLK_DIV(x) (x) /* SCLK = VCO / x */ | ||
| 859 | |||
| 860 | #define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ | ||
| 861 | #define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ | ||
| 862 | #define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ | ||
| 863 | #define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ | ||
| 864 | |||
| 865 | /* PLL_STAT Masks */ | ||
| 866 | #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ | ||
| 867 | #define FULL_ON 0x0002 /* Processor In Full On Mode */ | ||
| 868 | #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ | ||
| 869 | #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ | ||
| 870 | |||
| 871 | /* SWRST Mask */ | ||
| 872 | #define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ | ||
| 873 | #define SWRST_DBL_FAULT_B 0x00000800 /* SWRST Core B Double Fault */ | ||
| 874 | #define SWRST_DBL_FAULT_A 0x00001000 /* SWRST Core A Double Fault */ | ||
| 875 | #define SWRST_WDT_B 0x00002000 /* SWRST Watchdog B */ | ||
| 876 | #define SWRST_WDT_A 0x00004000 /* SWRST Watchdog A */ | ||
| 877 | #define SWRST_OCCURRED 0x00008000 /* SWRST Status */ | ||
| 878 | |||
| 879 | /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ | ||
| 880 | |||
| 881 | /* SICu_IARv Masks */ | ||
| 882 | /* u = A or B */ | ||
| 883 | /* v = 0 to 7 */ | ||
| 884 | /* w = 0 or 1 */ | ||
| 885 | |||
| 886 | /* Per_number = 0 to 63 */ | ||
| 887 | /* IVG_number = 7 to 15 */ | ||
| 888 | #define Peripheral_IVG(Per_number, IVG_number) \ | ||
| 889 | ((IVG_number) - 7) << (((Per_number) % 8) * 4) /* Peripheral #Per_number assigned IVG #IVG_number */ | ||
| 890 | /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */ | ||
| 891 | /* r0.h = hi(Peripheral_IVG(62, 10)); */ | ||
| 892 | |||
| 893 | /* SICx_IMASKw Masks */ | ||
| 894 | /* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */ | ||
| 895 | #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ | ||
| 896 | #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ | ||
| 897 | #define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ | ||
| 898 | #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ | ||
| 899 | |||
| 900 | /* SIC_IWR Masks */ | ||
| 901 | #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ | ||
| 902 | #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ | ||
| 903 | /* x = pos 0 to 31, for 32-63 use value-32 */ | ||
| 904 | #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ | ||
| 905 | #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ | ||
| 906 | |||
| 907 | /* ********* WATCHDOG TIMER MASKS ********************8 */ | ||
| 908 | |||
| 909 | /* Watchdog Timer WDOG_CTL Register */ | ||
| 910 | #define ICTL(x) ((x<<1) & 0x0006) | ||
| 911 | #define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */ | ||
| 912 | #define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */ | ||
| 913 | #define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */ | ||
| 914 | #define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */ | ||
| 915 | |||
| 916 | #define TMR_EN 0x0000 | ||
| 917 | #define TMR_DIS 0x0AD0 | ||
| 918 | #define TRO 0x8000 | ||
| 919 | |||
| 920 | #define ICTL_P0 0x01 | ||
| 921 | #define ICTL_P1 0x02 | ||
| 922 | #define TRO_P 0x0F | ||
| 923 | |||
| 924 | /* ***************************** UART CONTROLLER MASKS ********************** */ | ||
| 925 | |||
| 926 | /* UART_LCR Register */ | ||
| 927 | |||
| 928 | #define DLAB 0x80 | ||
| 929 | #define SB 0x40 | ||
| 930 | #define STP 0x20 | ||
| 931 | #define EPS 0x10 | ||
| 932 | #define PEN 0x08 | ||
| 933 | #define STB 0x04 | ||
| 934 | #define WLS(x) ((x-5) & 0x03) | ||
| 935 | |||
| 936 | #define DLAB_P 0x07 | ||
| 937 | #define SB_P 0x06 | ||
| 938 | #define STP_P 0x05 | ||
| 939 | #define EPS_P 0x04 | ||
| 940 | #define PEN_P 0x03 | ||
| 941 | #define STB_P 0x02 | ||
| 942 | #define WLS_P1 0x01 | ||
| 943 | #define WLS_P0 0x00 | ||
| 944 | |||
| 945 | /* UART_MCR Register */ | ||
| 946 | #define LOOP_ENA 0x10 | ||
| 947 | #define LOOP_ENA_P 0x04 | ||
| 948 | |||
| 949 | /* UART_LSR Register */ | ||
| 950 | #define TEMT 0x40 | ||
| 951 | #define THRE 0x20 | ||
| 952 | #define BI 0x10 | ||
| 953 | #define FE 0x08 | ||
| 954 | #define PE 0x04 | ||
| 955 | #define OE 0x02 | ||
| 956 | #define DR 0x01 | ||
| 957 | |||
| 958 | #define TEMP_P 0x06 | ||
| 959 | #define THRE_P 0x05 | ||
| 960 | #define BI_P 0x04 | ||
| 961 | #define FE_P 0x03 | ||
| 962 | #define PE_P 0x02 | ||
| 963 | #define OE_P 0x01 | ||
| 964 | #define DR_P 0x00 | ||
| 965 | |||
| 966 | /* UART_IER Register */ | ||
| 967 | #define ELSI 0x04 | ||
| 968 | #define ETBEI 0x02 | ||
| 969 | #define ERBFI 0x01 | ||
| 970 | |||
| 971 | #define ELSI_P 0x02 | ||
| 972 | #define ETBEI_P 0x01 | ||
| 973 | #define ERBFI_P 0x00 | ||
| 974 | |||
| 975 | /* UART_IIR Register */ | ||
| 976 | #define STATUS(x) ((x << 1) & 0x06) | ||
| 977 | #define NINT 0x01 | ||
| 978 | #define STATUS_P1 0x02 | ||
| 979 | #define STATUS_P0 0x01 | ||
| 980 | #define NINT_P 0x00 | ||
| 981 | #define IIR_TX_READY 0x02 /* UART_THR empty */ | ||
| 982 | #define IIR_RX_READY 0x04 /* Receive data ready */ | ||
| 983 | #define IIR_LINE_CHANGE 0x06 /* Receive line status */ | ||
| 984 | #define IIR_STATUS 0x06 | ||
| 985 | |||
| 986 | /* UART_GCTL Register */ | ||
| 987 | #define FFE 0x20 | ||
| 988 | #define FPE 0x10 | ||
| 989 | #define RPOLC 0x08 | ||
| 990 | #define TPOLC 0x04 | ||
| 991 | #define IREN 0x02 | ||
| 992 | #define UCEN 0x01 | ||
| 993 | |||
| 994 | #define FFE_P 0x05 | ||
| 995 | #define FPE_P 0x04 | ||
| 996 | #define RPOLC_P 0x03 | ||
| 997 | #define TPOLC_P 0x02 | ||
| 998 | #define IREN_P 0x01 | ||
| 999 | #define UCEN_P 0x00 | ||
| 1000 | |||
| 1001 | /* ********** SERIAL PORT MASKS ********************** */ | ||
| 1002 | |||
| 1003 | /* SPORTx_TCR1 Masks */ | ||
| 1004 | #define TSPEN 0x0001 /* TX enable */ | ||
| 1005 | #define ITCLK 0x0002 /* Internal TX Clock Select */ | ||
| 1006 | #define TDTYPE 0x000C /* TX Data Formatting Select */ | ||
| 1007 | #define TLSBIT 0x0010 /* TX Bit Order */ | ||
| 1008 | #define ITFS 0x0200 /* Internal TX Frame Sync Select */ | ||
| 1009 | #define TFSR 0x0400 /* TX Frame Sync Required Select */ | ||
| 1010 | #define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ | ||
| 1011 | #define LTFS 0x1000 /* Low TX Frame Sync Select */ | ||
| 1012 | #define LATFS 0x2000 /* Late TX Frame Sync Select */ | ||
| 1013 | #define TCKFE 0x4000 /* TX Clock Falling Edge Select */ | ||
| 1014 | |||
| 1015 | /* SPORTx_TCR2 Masks */ | ||
| 1016 | #define SLEN 0x001F /*TX Word Length */ | ||
| 1017 | #define TXSE 0x0100 /*TX Secondary Enable */ | ||
| 1018 | #define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ | ||
| 1019 | #define TRFST 0x0400 /*TX Right-First Data Order */ | ||
| 1020 | |||
| 1021 | /* SPORTx_RCR1 Masks */ | ||
| 1022 | #define RSPEN 0x0001 /* RX enable */ | ||
| 1023 | #define IRCLK 0x0002 /* Internal RX Clock Select */ | ||
| 1024 | #define RDTYPE 0x000C /* RX Data Formatting Select */ | ||
| 1025 | #define RULAW 0x0008 /* u-Law enable */ | ||
| 1026 | #define RALAW 0x000C /* A-Law enable */ | ||
| 1027 | #define RLSBIT 0x0010 /* RX Bit Order */ | ||
| 1028 | #define IRFS 0x0200 /* Internal RX Frame Sync Select */ | ||
| 1029 | #define RFSR 0x0400 /* RX Frame Sync Required Select */ | ||
| 1030 | #define LRFS 0x1000 /* Low RX Frame Sync Select */ | ||
| 1031 | #define LARFS 0x2000 /* Late RX Frame Sync Select */ | ||
| 1032 | #define RCKFE 0x4000 /* RX Clock Falling Edge Select */ | ||
| 1033 | |||
| 1034 | /* SPORTx_RCR2 Masks */ | ||
| 1035 | #define SLEN 0x001F /*RX Word Length */ | ||
| 1036 | #define RXSE 0x0100 /*RX Secondary Enable */ | ||
| 1037 | #define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */ | ||
| 1038 | #define RRFST 0x0400 /*Right-First Data Order */ | ||
| 1039 | |||
| 1040 | /*SPORTx_STAT Masks */ | ||
| 1041 | #define RXNE 0x0001 /*RX FIFO Not Empty Status */ | ||
| 1042 | #define RUVF 0x0002 /*RX Underflow Status */ | ||
| 1043 | #define ROVF 0x0004 /*RX Overflow Status */ | ||
| 1044 | #define TXF 0x0008 /*TX FIFO Full Status */ | ||
| 1045 | #define TUVF 0x0010 /*TX Underflow Status */ | ||
| 1046 | #define TOVF 0x0020 /*TX Overflow Status */ | ||
| 1047 | #define TXHRE 0x0040 /*TX Hold Register Empty */ | ||
| 1048 | |||
| 1049 | /*SPORTx_MCMC1 Masks */ | ||
| 1050 | #define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */ | ||
| 1051 | #define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */ | ||
| 1052 | |||
| 1053 | /*SPORTx_MCMC2 Masks */ | ||
| 1054 | #define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */ | ||
| 1055 | #define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */ | ||
| 1056 | #define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */ | ||
| 1057 | #define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */ | ||
| 1058 | #define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */ | ||
| 1059 | #define MFD 0x0000F000 /*Multichannel Frame Delay */ | ||
| 1060 | |||
| 1061 | /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ | ||
| 1062 | |||
| 1063 | /* PPI_CONTROL Masks */ | ||
| 1064 | #define PORT_EN 0x00000001 /* PPI Port Enable */ | ||
| 1065 | #define PORT_DIR 0x00000002 /* PPI Port Direction */ | ||
| 1066 | #define XFR_TYPE 0x0000000C /* PPI Transfer Type */ | ||
| 1067 | #define PORT_CFG 0x00000030 /* PPI Port Configuration */ | ||
| 1068 | #define FLD_SEL 0x00000040 /* PPI Active Field Select */ | ||
| 1069 | #define PACK_EN 0x00000080 /* PPI Packing Mode */ | ||
| 1070 | #define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ | ||
| 1071 | #define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ | ||
| 1072 | #define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ | ||
| 1073 | #define DLENGTH 0x00003800 /* PPI Data Length */ | ||
| 1074 | #define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ | ||
| 1075 | #define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ | ||
| 1076 | #define POL 0x0000C000 /* PPI Signal Polarities */ | ||
| 1077 | |||
| 1078 | /* PPI_STATUS Masks */ | ||
| 1079 | #define FLD 0x00000400 /* Field Indicator */ | ||
| 1080 | #define FT_ERR 0x00000800 /* Frame Track Error */ | ||
| 1081 | #define OVR 0x00001000 /* FIFO Overflow Error */ | ||
| 1082 | #define UNDR 0x00002000 /* FIFO Underrun Error */ | ||
| 1083 | #define ERR_DET 0x00004000 /* Error Detected Indicator */ | ||
| 1084 | #define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ | ||
| 1085 | |||
| 1086 | /* ********** DMA CONTROLLER MASKS *********************8 */ | ||
| 1087 | |||
| 1088 | /* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */ | ||
| 1089 | #define DMAEN 0x00000001 /* Channel Enable */ | ||
| 1090 | #define WNR 0x00000002 /* Channel Direction (W/R*) */ | ||
| 1091 | #define WDSIZE_8 0x00000000 /* Word Size 8 bits */ | ||
| 1092 | #define WDSIZE_16 0x00000004 /* Word Size 16 bits */ | ||
| 1093 | #define WDSIZE_32 0x00000008 /* Word Size 32 bits */ | ||
| 1094 | #define DMA2D 0x00000010 /* 2D/1D* Mode */ | ||
| 1095 | #define RESTART 0x00000020 /* Restart */ | ||
| 1096 | #define DI_SEL 0x00000040 /* Data Interrupt Select */ | ||
| 1097 | #define DI_EN 0x00000080 /* Data Interrupt Enable */ | ||
| 1098 | #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ | ||
| 1099 | #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ | ||
| 1100 | #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ | ||
| 1101 | #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ | ||
| 1102 | #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ | ||
| 1103 | #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ | ||
| 1104 | #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ | ||
| 1105 | #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ | ||
| 1106 | #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ | ||
| 1107 | #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ | ||
| 1108 | #define NDSIZE 0x00000900 /* Next Descriptor Size */ | ||
| 1109 | #define DMAFLOW 0x00007000 /* Flow Control */ | ||
| 1110 | #define DMAFLOW_STOP 0x0000 /* Stop Mode */ | ||
| 1111 | #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ | ||
| 1112 | #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ | ||
| 1113 | #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ | ||
| 1114 | #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ | ||
| 1115 | |||
| 1116 | #define DMAEN_P 0 /* Channel Enable */ | ||
| 1117 | #define WNR_P 1 /* Channel Direction (W/R*) */ | ||
| 1118 | #define DMA2D_P 4 /* 2D/1D* Mode */ | ||
| 1119 | #define RESTART_P 5 /* Restart */ | ||
| 1120 | #define DI_SEL_P 6 /* Data Interrupt Select */ | ||
| 1121 | #define DI_EN_P 7 /* Data Interrupt Enable */ | ||
| 1122 | |||
| 1123 | /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */ | ||
| 1124 | |||
| 1125 | #define DMA_DONE 0x00000001 /* DMA Done Indicator */ | ||
| 1126 | #define DMA_ERR 0x00000002 /* DMA Error Indicator */ | ||
| 1127 | #define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ | ||
| 1128 | #define DMA_RUN 0x00000008 /* DMA Running Indicator */ | ||
| 1129 | |||
| 1130 | #define DMA_DONE_P 0 /* DMA Done Indicator */ | ||
| 1131 | #define DMA_ERR_P 1 /* DMA Error Indicator */ | ||
| 1132 | #define DFETCH_P 2 /* Descriptor Fetch Indicator */ | ||
| 1133 | #define DMA_RUN_P 3 /* DMA Running Indicator */ | ||
| 1134 | |||
| 1135 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */ | ||
| 1136 | |||
| 1137 | #define CTYPE 0x00000040 /* DMA Channel Type Indicator */ | ||
| 1138 | #define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ | ||
| 1139 | #define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ | ||
| 1140 | #define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ | ||
| 1141 | #define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ | ||
| 1142 | #define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ | ||
| 1143 | #define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ | ||
| 1144 | #define PMAP 0x00007000 /* DMA Peripheral Map Field */ | ||
| 1145 | |||
| 1146 | /* ************* GENERAL PURPOSE TIMER MASKS ******************** */ | ||
| 1147 | |||
| 1148 | /* PWM Timer bit definitions */ | ||
| 1149 | |||
| 1150 | /* TIMER_ENABLE Register */ | ||
| 1151 | #define TIMEN0 0x0001 | ||
| 1152 | #define TIMEN1 0x0002 | ||
| 1153 | #define TIMEN2 0x0004 | ||
| 1154 | #define TIMEN3 0x0008 | ||
| 1155 | #define TIMEN4 0x0010 | ||
| 1156 | #define TIMEN5 0x0020 | ||
| 1157 | #define TIMEN6 0x0040 | ||
| 1158 | #define TIMEN7 0x0080 | ||
| 1159 | #define TIMEN8 0x0001 | ||
| 1160 | #define TIMEN9 0x0002 | ||
| 1161 | #define TIMEN10 0x0004 | ||
| 1162 | #define TIMEN11 0x0008 | ||
| 1163 | |||
| 1164 | #define TIMEN0_P 0x00 | ||
| 1165 | #define TIMEN1_P 0x01 | ||
| 1166 | #define TIMEN2_P 0x02 | ||
| 1167 | #define TIMEN3_P 0x03 | ||
| 1168 | #define TIMEN4_P 0x04 | ||
| 1169 | #define TIMEN5_P 0x05 | ||
| 1170 | #define TIMEN6_P 0x06 | ||
| 1171 | #define TIMEN7_P 0x07 | ||
| 1172 | #define TIMEN8_P 0x00 | ||
| 1173 | #define TIMEN9_P 0x01 | ||
| 1174 | #define TIMEN10_P 0x02 | ||
| 1175 | #define TIMEN11_P 0x03 | ||
| 1176 | |||
| 1177 | /* TIMER_DISABLE Register */ | ||
| 1178 | #define TIMDIS0 0x0001 | ||
| 1179 | #define TIMDIS1 0x0002 | ||
| 1180 | #define TIMDIS2 0x0004 | ||
| 1181 | #define TIMDIS3 0x0008 | ||
| 1182 | #define TIMDIS4 0x0010 | ||
| 1183 | #define TIMDIS5 0x0020 | ||
| 1184 | #define TIMDIS6 0x0040 | ||
| 1185 | #define TIMDIS7 0x0080 | ||
| 1186 | #define TIMDIS8 0x0001 | ||
| 1187 | #define TIMDIS9 0x0002 | ||
| 1188 | #define TIMDIS10 0x0004 | ||
| 1189 | #define TIMDIS11 0x0008 | ||
| 1190 | |||
| 1191 | #define TIMDIS0_P 0x00 | ||
| 1192 | #define TIMDIS1_P 0x01 | ||
| 1193 | #define TIMDIS2_P 0x02 | ||
| 1194 | #define TIMDIS3_P 0x03 | ||
| 1195 | #define TIMDIS4_P 0x04 | ||
| 1196 | #define TIMDIS5_P 0x05 | ||
| 1197 | #define TIMDIS6_P 0x06 | ||
| 1198 | #define TIMDIS7_P 0x07 | ||
| 1199 | #define TIMDIS8_P 0x00 | ||
| 1200 | #define TIMDIS9_P 0x01 | ||
| 1201 | #define TIMDIS10_P 0x02 | ||
| 1202 | #define TIMDIS11_P 0x03 | ||
| 1203 | |||
| 1204 | /* TIMER_STATUS Register */ | ||
| 1205 | #define TIMIL0 0x00000001 | ||
| 1206 | #define TIMIL1 0x00000002 | ||
| 1207 | #define TIMIL2 0x00000004 | ||
| 1208 | #define TIMIL3 0x00000008 | ||
| 1209 | #define TIMIL4 0x00010000 | ||
| 1210 | #define TIMIL5 0x00020000 | ||
| 1211 | #define TIMIL6 0x00040000 | ||
| 1212 | #define TIMIL7 0x00080000 | ||
| 1213 | #define TIMIL8 0x0001 | ||
| 1214 | #define TIMIL9 0x0002 | ||
| 1215 | #define TIMIL10 0x0004 | ||
| 1216 | #define TIMIL11 0x0008 | ||
| 1217 | #define TOVL_ERR0 0x00000010 | ||
| 1218 | #define TOVL_ERR1 0x00000020 | ||
| 1219 | #define TOVL_ERR2 0x00000040 | ||
| 1220 | #define TOVL_ERR3 0x00000080 | ||
| 1221 | #define TOVL_ERR4 0x00100000 | ||
| 1222 | #define TOVL_ERR5 0x00200000 | ||
| 1223 | #define TOVL_ERR6 0x00400000 | ||
| 1224 | #define TOVL_ERR7 0x00800000 | ||
| 1225 | #define TOVL_ERR8 0x0010 | ||
| 1226 | #define TOVL_ERR9 0x0020 | ||
| 1227 | #define TOVL_ERR10 0x0040 | ||
| 1228 | #define TOVL_ERR11 0x0080 | ||
| 1229 | #define TRUN0 0x00001000 | ||
| 1230 | #define TRUN1 0x00002000 | ||
| 1231 | #define TRUN2 0x00004000 | ||
| 1232 | #define TRUN3 0x00008000 | ||
| 1233 | #define TRUN4 0x10000000 | ||
| 1234 | #define TRUN5 0x20000000 | ||
| 1235 | #define TRUN6 0x40000000 | ||
| 1236 | #define TRUN7 0x80000000 | ||
| 1237 | #define TRUN8 0x1000 | ||
| 1238 | #define TRUN9 0x2000 | ||
| 1239 | #define TRUN10 0x4000 | ||
| 1240 | #define TRUN11 0x8000 | ||
| 1241 | |||
| 1242 | #define TIMIL0_P 0x00 | ||
| 1243 | #define TIMIL1_P 0x01 | ||
| 1244 | #define TIMIL2_P 0x02 | ||
| 1245 | #define TIMIL3_P 0x03 | ||
| 1246 | #define TIMIL4_P 0x10 | ||
| 1247 | #define TIMIL5_P 0x11 | ||
| 1248 | #define TIMIL6_P 0x12 | ||
| 1249 | #define TIMIL7_P 0x13 | ||
| 1250 | #define TIMIL8_P 0x00 | ||
| 1251 | #define TIMIL9_P 0x01 | ||
| 1252 | #define TIMIL10_P 0x02 | ||
| 1253 | #define TIMIL11_P 0x03 | ||
| 1254 | #define TOVL_ERR0_P 0x04 | ||
| 1255 | #define TOVL_ERR1_P 0x05 | ||
| 1256 | #define TOVL_ERR2_P 0x06 | ||
| 1257 | #define TOVL_ERR3_P 0x07 | ||
| 1258 | #define TOVL_ERR4_P 0x14 | ||
| 1259 | #define TOVL_ERR5_P 0x15 | ||
| 1260 | #define TOVL_ERR6_P 0x16 | ||
| 1261 | #define TOVL_ERR7_P 0x17 | ||
| 1262 | #define TOVL_ERR8_P 0x04 | ||
| 1263 | #define TOVL_ERR9_P 0x05 | ||
| 1264 | #define TOVL_ERR10_P 0x06 | ||
| 1265 | #define TOVL_ERR11_P 0x07 | ||
| 1266 | #define TRUN0_P 0x0C | ||
| 1267 | #define TRUN1_P 0x0D | ||
| 1268 | #define TRUN2_P 0x0E | ||
| 1269 | #define TRUN3_P 0x0F | ||
| 1270 | #define TRUN4_P 0x1C | ||
| 1271 | #define TRUN5_P 0x1D | ||
| 1272 | #define TRUN6_P 0x1E | ||
| 1273 | #define TRUN7_P 0x1F | ||
| 1274 | #define TRUN8_P 0x0C | ||
| 1275 | #define TRUN9_P 0x0D | ||
| 1276 | #define TRUN10_P 0x0E | ||
| 1277 | #define TRUN11_P 0x0F | ||
| 1278 | |||
| 1279 | /* TIMERx_CONFIG Registers */ | ||
| 1280 | #define PWM_OUT 0x0001 | ||
| 1281 | #define WDTH_CAP 0x0002 | ||
| 1282 | #define EXT_CLK 0x0003 | ||
| 1283 | #define PULSE_HI 0x0004 | ||
| 1284 | #define PERIOD_CNT 0x0008 | ||
| 1285 | #define IRQ_ENA 0x0010 | ||
| 1286 | #define TIN_SEL 0x0020 | ||
| 1287 | #define OUT_DIS 0x0040 | ||
| 1288 | #define CLK_SEL 0x0080 | ||
| 1289 | #define TOGGLE_HI 0x0100 | ||
| 1290 | #define EMU_RUN 0x0200 | ||
| 1291 | #define ERR_TYP(x) ((x & 0x03) << 14) | ||
| 1292 | |||
| 1293 | #define TMODE_P0 0x00 | ||
| 1294 | #define TMODE_P1 0x01 | ||
| 1295 | #define PULSE_HI_P 0x02 | ||
| 1296 | #define PERIOD_CNT_P 0x03 | ||
| 1297 | #define IRQ_ENA_P 0x04 | ||
| 1298 | #define TIN_SEL_P 0x05 | ||
| 1299 | #define OUT_DIS_P 0x06 | ||
| 1300 | #define CLK_SEL_P 0x07 | ||
| 1301 | #define TOGGLE_HI_P 0x08 | ||
| 1302 | #define EMU_RUN_P 0x09 | ||
| 1303 | #define ERR_TYP_P0 0x0E | ||
| 1304 | #define ERR_TYP_P1 0x0F | ||
| 1305 | |||
| 1306 | /*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */ | ||
| 1307 | |||
| 1308 | /* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ | ||
| 1309 | #define PF0 0x0001 | ||
| 1310 | #define PF1 0x0002 | ||
| 1311 | #define PF2 0x0004 | ||
| 1312 | #define PF3 0x0008 | ||
| 1313 | #define PF4 0x0010 | ||
| 1314 | #define PF5 0x0020 | ||
| 1315 | #define PF6 0x0040 | ||
| 1316 | #define PF7 0x0080 | ||
| 1317 | #define PF8 0x0100 | ||
| 1318 | #define PF9 0x0200 | ||
| 1319 | #define PF10 0x0400 | ||
| 1320 | #define PF11 0x0800 | ||
| 1321 | #define PF12 0x1000 | ||
| 1322 | #define PF13 0x2000 | ||
| 1323 | #define PF14 0x4000 | ||
| 1324 | #define PF15 0x8000 | ||
| 1325 | |||
| 1326 | /* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ | ||
| 1327 | #define PF0_P 0 | ||
| 1328 | #define PF1_P 1 | ||
| 1329 | #define PF2_P 2 | ||
| 1330 | #define PF3_P 3 | ||
| 1331 | #define PF4_P 4 | ||
| 1332 | #define PF5_P 5 | ||
| 1333 | #define PF6_P 6 | ||
| 1334 | #define PF7_P 7 | ||
| 1335 | #define PF8_P 8 | ||
| 1336 | #define PF9_P 9 | ||
| 1337 | #define PF10_P 10 | ||
| 1338 | #define PF11_P 11 | ||
| 1339 | #define PF12_P 12 | ||
| 1340 | #define PF13_P 13 | ||
| 1341 | #define PF14_P 14 | ||
| 1342 | #define PF15_P 15 | ||
| 1343 | |||
| 1344 | /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ | ||
| 1345 | |||
| 1346 | /* SPI_CTL Masks */ | ||
| 1347 | #define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ | ||
| 1348 | #define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ | ||
| 1349 | #define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ | ||
| 1350 | #define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ | ||
| 1351 | #define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ | ||
| 1352 | #define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ | ||
| 1353 | #define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ | ||
| 1354 | #define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ | ||
| 1355 | #define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ | ||
| 1356 | #define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ | ||
| 1357 | #define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ | ||
| 1358 | #define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ | ||
| 1359 | |||
| 1360 | /* SPI_FLG Masks */ | ||
| 1361 | #define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 1362 | #define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 1363 | #define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 1364 | #define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 1365 | #define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 1366 | #define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 1367 | #define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 1368 | #define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 1369 | #define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 1370 | #define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 1371 | #define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 1372 | #define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 1373 | #define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 1374 | #define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 1375 | |||
| 1376 | /* SPI_FLG Bit Positions */ | ||
| 1377 | #define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 1378 | #define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 1379 | #define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 1380 | #define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 1381 | #define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 1382 | #define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 1383 | #define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 1384 | #define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 1385 | #define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 1386 | #define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 1387 | #define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 1388 | #define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 1389 | #define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 1390 | #define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 1391 | |||
| 1392 | /* SPI_STAT Masks */ | ||
| 1393 | #define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ | ||
| 1394 | #define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */ | ||
| 1395 | #define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ | ||
| 1396 | #define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ | ||
| 1397 | #define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ | ||
| 1398 | #define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ | ||
| 1399 | #define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ | ||
| 1400 | |||
| 1401 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ | ||
| 1402 | |||
| 1403 | /* AMGCTL Masks */ | ||
| 1404 | #define AMCKEN 0x0001 /* Enable CLKOUT */ | ||
| 1405 | #define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */ | ||
| 1406 | #define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */ | ||
| 1407 | #define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ | ||
| 1408 | #define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ | ||
| 1409 | #define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */ | ||
| 1410 | #define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */ | ||
| 1411 | #define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */ | ||
| 1412 | #define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */ | ||
| 1413 | |||
| 1414 | /* AMGCTL Bit Positions */ | ||
| 1415 | #define AMCKEN_P 0x00000000 /* Enable CLKOUT */ | ||
| 1416 | #define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ | ||
| 1417 | #define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ | ||
| 1418 | #define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ | ||
| 1419 | #define B0_PEN_P 0x004 /* Enable 16-bit packing Bank 0 */ | ||
| 1420 | #define B1_PEN_P 0x005 /* Enable 16-bit packing Bank 1 */ | ||
| 1421 | #define B2_PEN_P 0x006 /* Enable 16-bit packing Bank 2 */ | ||
| 1422 | #define B3_PEN_P 0x007 /* Enable 16-bit packing Bank 3 */ | ||
| 1423 | |||
| 1424 | /* AMBCTL0 Masks */ | ||
| 1425 | #define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ | ||
| 1426 | #define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ | ||
| 1427 | #define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ | ||
| 1428 | #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ | ||
| 1429 | #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ | ||
| 1430 | #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ | ||
| 1431 | #define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ | ||
| 1432 | #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ | ||
| 1433 | #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ | ||
| 1434 | #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ | ||
| 1435 | #define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ | ||
| 1436 | #define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ | ||
| 1437 | #define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ | ||
| 1438 | #define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ | ||
| 1439 | #define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ | ||
| 1440 | #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ | ||
| 1441 | #define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ | ||
| 1442 | #define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ | ||
| 1443 | #define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ | ||
| 1444 | #define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ | ||
| 1445 | #define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ | ||
| 1446 | #define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ | ||
| 1447 | #define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ | ||
| 1448 | #define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ | ||
| 1449 | #define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ | ||
| 1450 | #define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ | ||
| 1451 | #define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ | ||
| 1452 | #define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ | ||
| 1453 | #define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ | ||
| 1454 | #define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ | ||
| 1455 | #define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ | ||
| 1456 | #define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ | ||
| 1457 | #define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ | ||
| 1458 | #define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ | ||
| 1459 | #define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ | ||
| 1460 | #define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ | ||
| 1461 | #define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ | ||
| 1462 | #define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ | ||
| 1463 | #define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ | ||
| 1464 | #define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ | ||
| 1465 | #define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ | ||
| 1466 | #define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ | ||
| 1467 | #define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ | ||
| 1468 | #define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ | ||
| 1469 | #define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ | ||
| 1470 | #define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ | ||
| 1471 | #define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ | ||
| 1472 | #define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ | ||
| 1473 | #define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ | ||
| 1474 | #define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ | ||
| 1475 | #define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ | ||
| 1476 | #define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ | ||
| 1477 | #define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ | ||
| 1478 | #define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ | ||
| 1479 | #define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ | ||
| 1480 | #define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ | ||
| 1481 | #define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ | ||
| 1482 | #define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ | ||
| 1483 | #define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ | ||
| 1484 | #define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ | ||
| 1485 | #define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ | ||
| 1486 | #define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ | ||
| 1487 | #define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ | ||
| 1488 | #define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ | ||
| 1489 | #define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ | ||
| 1490 | #define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ | ||
| 1491 | #define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ | ||
| 1492 | #define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ | ||
| 1493 | #define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ | ||
| 1494 | #define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ | ||
| 1495 | #define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ | ||
| 1496 | #define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ | ||
| 1497 | #define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ | ||
| 1498 | #define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ | ||
| 1499 | #define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ | ||
| 1500 | #define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ | ||
| 1501 | #define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ | ||
| 1502 | #define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ | ||
| 1503 | #define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ | ||
| 1504 | #define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ | ||
| 1505 | #define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ | ||
| 1506 | #define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ | ||
| 1507 | #define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ | ||
| 1508 | #define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ | ||
| 1509 | #define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ | ||
| 1510 | #define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ | ||
| 1511 | #define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ | ||
| 1512 | #define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ | ||
| 1513 | |||
| 1514 | /* AMBCTL1 Masks */ | ||
| 1515 | #define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ | ||
| 1516 | #define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ | ||
| 1517 | #define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ | ||
| 1518 | #define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ | ||
| 1519 | #define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ | ||
| 1520 | #define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ | ||
| 1521 | #define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ | ||
| 1522 | #define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ | ||
| 1523 | #define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ | ||
| 1524 | #define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ | ||
| 1525 | #define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ | ||
| 1526 | #define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ | ||
| 1527 | #define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ | ||
| 1528 | #define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ | ||
| 1529 | #define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ | ||
| 1530 | #define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ | ||
| 1531 | #define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ | ||
| 1532 | #define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ | ||
| 1533 | #define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ | ||
| 1534 | #define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ | ||
| 1535 | #define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ | ||
| 1536 | #define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ | ||
| 1537 | #define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ | ||
| 1538 | #define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ | ||
| 1539 | #define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ | ||
| 1540 | #define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ | ||
| 1541 | #define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ | ||
| 1542 | #define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ | ||
| 1543 | #define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ | ||
| 1544 | #define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ | ||
| 1545 | #define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ | ||
| 1546 | #define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ | ||
| 1547 | #define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ | ||
| 1548 | #define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ | ||
| 1549 | #define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ | ||
| 1550 | #define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ | ||
| 1551 | #define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ | ||
| 1552 | #define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ | ||
| 1553 | #define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ | ||
| 1554 | #define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ | ||
| 1555 | #define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ | ||
| 1556 | #define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ | ||
| 1557 | #define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ | ||
| 1558 | #define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ | ||
| 1559 | #define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ | ||
| 1560 | #define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ | ||
| 1561 | #define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ | ||
| 1562 | #define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ | ||
| 1563 | #define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ | ||
| 1564 | #define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ | ||
| 1565 | #define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ | ||
| 1566 | #define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ | ||
| 1567 | #define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ | ||
| 1568 | #define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ | ||
| 1569 | #define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ | ||
| 1570 | #define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ | ||
| 1571 | #define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ | ||
| 1572 | #define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ | ||
| 1573 | #define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ | ||
| 1574 | #define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ | ||
| 1575 | #define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ | ||
| 1576 | #define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ | ||
| 1577 | #define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ | ||
| 1578 | #define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ | ||
| 1579 | #define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ | ||
| 1580 | #define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ | ||
| 1581 | #define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ | ||
| 1582 | #define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ | ||
| 1583 | #define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ | ||
| 1584 | #define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ | ||
| 1585 | #define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ | ||
| 1586 | #define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ | ||
| 1587 | #define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ | ||
| 1588 | #define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ | ||
| 1589 | #define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ | ||
| 1590 | #define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ | ||
| 1591 | #define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ | ||
| 1592 | #define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ | ||
| 1593 | #define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ | ||
| 1594 | #define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ | ||
| 1595 | #define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ | ||
| 1596 | #define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ | ||
| 1597 | #define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ | ||
| 1598 | #define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ | ||
| 1599 | #define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ | ||
| 1600 | #define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ | ||
| 1601 | #define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ | ||
| 1602 | #define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ | ||
| 1603 | |||
| 1604 | /* ********************** SDRAM CONTROLLER MASKS *************************** */ | ||
| 1605 | |||
| 1606 | /* EBIU_SDGCTL Masks */ | ||
| 1607 | #define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ | ||
| 1608 | #define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ | ||
| 1609 | #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ | ||
| 1610 | #define PFE 0x00000010 /* Enable SDRAM prefetch */ | ||
| 1611 | #define PFP 0x00000020 /* Prefetch has priority over AMC requests */ | ||
| 1612 | #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ | ||
| 1613 | #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ | ||
| 1614 | #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ | ||
| 1615 | #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ | ||
| 1616 | #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ | ||
| 1617 | #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ | ||
| 1618 | #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ | ||
| 1619 | #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ | ||
| 1620 | #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ | ||
| 1621 | #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ | ||
| 1622 | #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ | ||
| 1623 | #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ | ||
| 1624 | #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ | ||
| 1625 | #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ | ||
| 1626 | #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ | ||
| 1627 | #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ | ||
| 1628 | #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ | ||
| 1629 | #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ | ||
| 1630 | #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ | ||
| 1631 | #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ | ||
| 1632 | #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ | ||
| 1633 | #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ | ||
| 1634 | #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ | ||
| 1635 | #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ | ||
| 1636 | #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ | ||
| 1637 | #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ | ||
| 1638 | #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ | ||
| 1639 | #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ | ||
| 1640 | #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ | ||
| 1641 | #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ | ||
| 1642 | #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ | ||
| 1643 | #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ | ||
| 1644 | #define PUPSD 0x00200000 /*Power-up start delay */ | ||
| 1645 | #define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ | ||
| 1646 | #define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ | ||
| 1647 | #define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ | ||
| 1648 | #define EBUFE 0x02000000 /* Enable external buffering timing */ | ||
| 1649 | #define FBBRW 0x04000000 /* Fast back-to-back read write enable */ | ||
| 1650 | #define EMREN 0x10000000 /* Extended mode register enable */ | ||
| 1651 | #define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ | ||
| 1652 | #define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ | ||
| 1653 | |||
| 1654 | /* EBIU_SDBCTL Masks */ | ||
| 1655 | #define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */ | ||
| 1656 | #define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ | ||
| 1657 | #define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */ | ||
| 1658 | #define EB0_SZ_64 0x00000004 /* SDRAM external bank size = 64MB */ | ||
| 1659 | #define EB0_SZ_128 0x00000006 /* SDRAM external bank size = 128MB */ | ||
| 1660 | #define EB0_CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ | ||
| 1661 | #define EB0_CAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ | ||
| 1662 | #define EB0_CAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ | ||
| 1663 | #define EB0_CAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ | ||
| 1664 | |||
| 1665 | #define EB1_E 0x00000100 /* Enable SDRAM external bank 1 */ | ||
| 1666 | #define EB1__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ | ||
| 1667 | #define EB1__SZ_32 0x00000200 /* SDRAM external bank size = 32MB */ | ||
| 1668 | #define EB1__SZ_64 0x00000400 /* SDRAM external bank size = 64MB */ | ||
| 1669 | #define EB1__SZ_128 0x00000600 /* SDRAM external bank size = 128MB */ | ||
| 1670 | #define EB1__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ | ||
| 1671 | #define EB1__CAW_9 0x00001000 /* SDRAM external bank column address width = 9 bits */ | ||
| 1672 | #define EB1__CAW_10 0x00002000 /* SDRAM external bank column address width = 9 bits */ | ||
| 1673 | #define EB1__CAW_11 0x00003000 /* SDRAM external bank column address width = 9 bits */ | ||
| 1674 | |||
| 1675 | #define EB2__E 0x00010000 /* Enable SDRAM external bank 2 */ | ||
| 1676 | #define EB2__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ | ||
| 1677 | #define EB2__SZ_32 0x00020000 /* SDRAM external bank size = 32MB */ | ||
| 1678 | #define EB2__SZ_64 0x00040000 /* SDRAM external bank size = 64MB */ | ||
| 1679 | #define EB2__SZ_128 0x00060000 /* SDRAM external bank size = 128MB */ | ||
| 1680 | #define EB2__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ | ||
| 1681 | #define EB2__CAW_9 0x00100000 /* SDRAM external bank column address width = 9 bits */ | ||
| 1682 | #define EB2__CAW_10 0x00200000 /* SDRAM external bank column address width = 9 bits */ | ||
| 1683 | #define EB2__CAW_11 0x00300000 /* SDRAM external bank column address width = 9 bits */ | ||
| 1684 | |||
| 1685 | #define EB3__E 0x01000000 /* Enable SDRAM external bank 3 */ | ||
| 1686 | #define EB3__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */ | ||
| 1687 | #define EB3__SZ_32 0x02000000 /* SDRAM external bank size = 32MB */ | ||
| 1688 | #define EB3__SZ_64 0x04000000 /* SDRAM external bank size = 64MB */ | ||
| 1689 | #define EB3__SZ_128 0x06000000 /* SDRAM external bank size = 128MB */ | ||
| 1690 | #define EB3__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ | ||
| 1691 | #define EB3__CAW_9 0x10000000 /* SDRAM external bank column address width = 9 bits */ | ||
| 1692 | #define EB3__CAW_10 0x20000000 /* SDRAM external bank column address width = 9 bits */ | ||
| 1693 | #define EB3__CAW_11 0x30000000 /* SDRAM external bank column address width = 9 bits */ | ||
| 1694 | |||
| 1695 | /* EBIU_SDSTAT Masks */ | ||
| 1696 | #define SDCI 0x00000001 /* SDRAM controller is idle */ | ||
| 1697 | #define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ | ||
| 1698 | #define SDPUA 0x00000004 /* SDRAM power up active */ | ||
| 1699 | #define SDRS 0x00000008 /* SDRAM is in reset state */ | ||
| 1700 | #define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ | ||
| 1701 | #define BGSTAT 0x00000020 /* Bus granted */ | ||
| 1702 | |||
| 1703 | /*VR_CTL Masks*/ | ||
| 1704 | #define WAKE 0x100 | ||
| 1705 | #define VLEV_6 0x60 | ||
| 1706 | #define VLEV_7 0x70 | ||
| 1707 | #define VLEV_8 0x80 | ||
| 1708 | #define VLEV_9 0x90 | ||
| 1709 | #define VLEV_10 0xA0 | ||
| 1710 | #define VLEV_11 0xB0 | ||
| 1711 | #define VLEV_12 0xC0 | ||
| 1712 | #define VLEV_13 0xD0 | ||
| 1713 | #define VLEV_14 0xE0 | ||
| 1714 | #define VLEV_15 0xF0 | ||
| 1715 | #define FREQ_3 0x03 | ||
| 1716 | |||
| 1717 | #endif /* _DEF_BF561_H */ | ||
diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h new file mode 100644 index 000000000000..21d982003e75 --- /dev/null +++ b/include/asm-blackfin/mach-bf561/dma.h | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * | ||
| 3 | * BF-533/2/1 Specific Declarations | ||
| 4 | * | ||
| 5 | ****************************************************************************/ | ||
| 6 | |||
| 7 | #ifndef _MACH_DMA_H_ | ||
| 8 | #define _MACH_DMA_H_ | ||
| 9 | |||
| 10 | #define MAX_BLACKFIN_DMA_CHANNEL 36 | ||
| 11 | |||
| 12 | #define CH_PPI0 0 | ||
| 13 | #define CH_PPI (CH_PPI0) | ||
| 14 | #define CH_PPI1 1 | ||
| 15 | #define CH_SPORT0_RX 12 | ||
| 16 | #define CH_SPORT0_TX 13 | ||
| 17 | #define CH_SPORT1_RX 14 | ||
| 18 | #define CH_SPORT1_TX 15 | ||
| 19 | #define CH_SPI 16 | ||
| 20 | #define CH_UART_RX 17 | ||
| 21 | #define CH_UART_TX 18 | ||
| 22 | #define CH_MEM_STREAM0_DEST 24 /* TX */ | ||
| 23 | #define CH_MEM_STREAM0_SRC 25 /* RX */ | ||
| 24 | #define CH_MEM_STREAM1_DEST 26 /* TX */ | ||
| 25 | #define CH_MEM_STREAM1_SRC 27 /* RX */ | ||
| 26 | #define CH_MEM_STREAM2_DEST 28 | ||
| 27 | #define CH_MEM_STREAM2_SRC 29 | ||
| 28 | #define CH_MEM_STREAM3_SRC 30 | ||
| 29 | #define CH_MEM_STREAM3_DEST 31 | ||
| 30 | #define CH_IMEM_STREAM0_DEST 32 | ||
| 31 | #define CH_IMEM_STREAM0_SRC 33 | ||
| 32 | #define CH_IMEM_STREAM1_SRC 34 | ||
| 33 | #define CH_IMEM_STREAM1_DEST 35 | ||
| 34 | |||
| 35 | #endif | ||
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h new file mode 100644 index 000000000000..a753ce720d74 --- /dev/null +++ b/include/asm-blackfin/mach-bf561/irq.h | |||
| @@ -0,0 +1,450 @@ | |||
| 1 | |||
| 2 | /* | ||
| 3 | * File: include/asm-blackfin/mach-bf561/irq.h | ||
| 4 | * Based on: | ||
| 5 | * Author: | ||
| 6 | * | ||
| 7 | * Created: | ||
| 8 | * Description: | ||
| 9 | * | ||
| 10 | * Rev: | ||
| 11 | * | ||
| 12 | * Modified: | ||
| 13 | * | ||
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License as published by | ||
| 18 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; see the file COPYING. | ||
| 28 | * If not, write to the Free Software Foundation, | ||
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #ifndef _BF561_IRQ_H_ | ||
| 33 | #define _BF561_IRQ_H_ | ||
| 34 | |||
| 35 | /*********************************************************************** | ||
| 36 | * Interrupt source definitions: | ||
| 37 | Event Source Core Event Name IRQ No | ||
| 38 | (highest priority) | ||
| 39 | Emulation Events EMU 0 | ||
| 40 | Reset RST 1 | ||
| 41 | NMI NMI 2 | ||
| 42 | Exception EVX 3 | ||
| 43 | Reserved -- 4 | ||
| 44 | Hardware Error IVHW 5 | ||
| 45 | Core Timer IVTMR 6 * | ||
| 46 | |||
| 47 | PLL Wakeup Interrupt IVG7 7 | ||
| 48 | DMA1 Error (generic) IVG7 8 | ||
| 49 | DMA2 Error (generic) IVG7 9 | ||
| 50 | IMDMA Error (generic) IVG7 10 | ||
| 51 | PPI1 Error Interrupt IVG7 11 | ||
| 52 | PPI2 Error Interrupt IVG7 12 | ||
| 53 | SPORT0 Error Interrupt IVG7 13 | ||
| 54 | SPORT1 Error Interrupt IVG7 14 | ||
| 55 | SPI Error Interrupt IVG7 15 | ||
| 56 | UART Error Interrupt IVG7 16 | ||
| 57 | Reserved Interrupt IVG7 17 | ||
| 58 | |||
| 59 | DMA1 0 Interrupt(PPI1) IVG8 18 | ||
| 60 | DMA1 1 Interrupt(PPI2) IVG8 19 | ||
| 61 | DMA1 2 Interrupt IVG8 20 | ||
| 62 | DMA1 3 Interrupt IVG8 21 | ||
| 63 | DMA1 4 Interrupt IVG8 22 | ||
| 64 | DMA1 5 Interrupt IVG8 23 | ||
| 65 | DMA1 6 Interrupt IVG8 24 | ||
| 66 | DMA1 7 Interrupt IVG8 25 | ||
| 67 | DMA1 8 Interrupt IVG8 26 | ||
| 68 | DMA1 9 Interrupt IVG8 27 | ||
| 69 | DMA1 10 Interrupt IVG8 28 | ||
| 70 | DMA1 11 Interrupt IVG8 29 | ||
| 71 | |||
| 72 | DMA2 0 (SPORT0 RX) IVG9 30 | ||
| 73 | DMA2 1 (SPORT0 TX) IVG9 31 | ||
| 74 | DMA2 2 (SPORT1 RX) IVG9 32 | ||
| 75 | DMA2 3 (SPORT2 TX) IVG9 33 | ||
| 76 | DMA2 4 (SPI) IVG9 34 | ||
| 77 | DMA2 5 (UART RX) IVG9 35 | ||
| 78 | DMA2 6 (UART TX) IVG9 36 | ||
| 79 | DMA2 7 Interrupt IVG9 37 | ||
| 80 | DMA2 8 Interrupt IVG9 38 | ||
| 81 | DMA2 9 Interrupt IVG9 39 | ||
| 82 | DMA2 10 Interrupt IVG9 40 | ||
| 83 | DMA2 11 Interrupt IVG9 41 | ||
| 84 | |||
| 85 | TIMER 0 Interrupt IVG10 42 | ||
| 86 | TIMER 1 Interrupt IVG10 43 | ||
| 87 | TIMER 2 Interrupt IVG10 44 | ||
| 88 | TIMER 3 Interrupt IVG10 45 | ||
| 89 | TIMER 4 Interrupt IVG10 46 | ||
| 90 | TIMER 5 Interrupt IVG10 47 | ||
| 91 | TIMER 6 Interrupt IVG10 48 | ||
| 92 | TIMER 7 Interrupt IVG10 49 | ||
| 93 | TIMER 8 Interrupt IVG10 50 | ||
| 94 | TIMER 9 Interrupt IVG10 51 | ||
| 95 | TIMER 10 Interrupt IVG10 52 | ||
| 96 | TIMER 11 Interrupt IVG10 53 | ||
| 97 | |||
| 98 | Programmable Flags0 A (8) IVG11 54 | ||
| 99 | Programmable Flags0 B (8) IVG11 55 | ||
| 100 | Programmable Flags1 A (8) IVG11 56 | ||
| 101 | Programmable Flags1 B (8) IVG11 57 | ||
| 102 | Programmable Flags2 A (8) IVG11 58 | ||
| 103 | Programmable Flags2 B (8) IVG11 59 | ||
| 104 | |||
| 105 | MDMA1 0 write/read INT IVG8 60 | ||
| 106 | MDMA1 1 write/read INT IVG8 61 | ||
| 107 | |||
| 108 | MDMA2 0 write/read INT IVG9 62 | ||
| 109 | MDMA2 1 write/read INT IVG9 63 | ||
| 110 | |||
| 111 | IMDMA 0 write/read INT IVG12 64 | ||
| 112 | IMDMA 1 write/read INT IVG12 65 | ||
| 113 | |||
| 114 | Watch Dog Timer IVG13 66 | ||
| 115 | |||
| 116 | Reserved interrupt IVG7 67 | ||
| 117 | Reserved interrupt IVG7 68 | ||
| 118 | Supplemental interrupt 0 IVG7 69 | ||
| 119 | supplemental interrupt 1 IVG7 70 | ||
| 120 | |||
| 121 | Software Interrupt 1 IVG14 71 | ||
| 122 | Software Interrupt 2 IVG15 72 * | ||
| 123 | (lowest priority) | ||
| 124 | **********************************************************************/ | ||
| 125 | |||
| 126 | #define SYS_IRQS 72 | ||
| 127 | #define NR_PERI_INTS 64 | ||
| 128 | |||
| 129 | /* | ||
| 130 | * The ABSTRACT IRQ definitions | ||
| 131 | * the first seven of the following are fixed, | ||
| 132 | * the rest you change if you need to. | ||
| 133 | */ | ||
| 134 | /* IVG 0-6*/ | ||
| 135 | #define IRQ_EMU 0 /* Emulation */ | ||
| 136 | #define IRQ_RST 1 /* Reset */ | ||
| 137 | #define IRQ_NMI 2 /* Non Maskable Interrupt */ | ||
| 138 | #define IRQ_EVX 3 /* Exception */ | ||
| 139 | #define IRQ_UNUSED 4 /* Reserved interrupt */ | ||
| 140 | #define IRQ_HWERR 5 /* Hardware Error */ | ||
| 141 | #define IRQ_CORETMR 6 /* Core timer */ | ||
| 142 | |||
| 143 | #define IVG_BASE 7 | ||
| 144 | /* IVG 7 */ | ||
| 145 | #define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */ | ||
| 146 | #define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */ | ||
| 147 | #define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */ | ||
| 148 | #define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */ | ||
| 149 | #define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */ | ||
| 150 | #define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */ | ||
| 151 | #define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */ | ||
| 152 | #define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */ | ||
| 153 | #define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */ | ||
| 154 | #define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */ | ||
| 155 | #define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */ | ||
| 156 | #define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */ | ||
| 157 | #define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */ | ||
| 158 | /* IVG 8 */ | ||
| 159 | #define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */ | ||
| 160 | #define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ | ||
| 161 | #define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ | ||
| 162 | #define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */ | ||
| 163 | #define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */ | ||
| 164 | #define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */ | ||
| 165 | #define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */ | ||
| 166 | #define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */ | ||
| 167 | #define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */ | ||
| 168 | #define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */ | ||
| 169 | #define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */ | ||
| 170 | #define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */ | ||
| 171 | #define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */ | ||
| 172 | #define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */ | ||
| 173 | #define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */ | ||
| 174 | /* IVG 9 */ | ||
| 175 | #define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */ | ||
| 176 | #define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */ | ||
| 177 | #define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */ | ||
| 178 | #define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */ | ||
| 179 | #define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */ | ||
| 180 | #define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */ | ||
| 181 | #define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */ | ||
| 182 | #define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */ | ||
| 183 | #define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */ | ||
| 184 | #define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */ | ||
| 185 | #define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */ | ||
| 186 | #define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */ | ||
| 187 | #define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */ | ||
| 188 | #define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */ | ||
| 189 | #define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */ | ||
| 190 | #define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */ | ||
| 191 | #define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */ | ||
| 192 | #define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */ | ||
| 193 | #define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */ | ||
| 194 | /* IVG 10 */ | ||
| 195 | #define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */ | ||
| 196 | #define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */ | ||
| 197 | #define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */ | ||
| 198 | #define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */ | ||
| 199 | #define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */ | ||
| 200 | #define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */ | ||
| 201 | #define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */ | ||
| 202 | #define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */ | ||
| 203 | #define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */ | ||
| 204 | #define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */ | ||
| 205 | #define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */ | ||
| 206 | #define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */ | ||
| 207 | /* IVG 11 */ | ||
| 208 | #define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */ | ||
| 209 | #define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */ | ||
| 210 | #define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */ | ||
| 211 | #define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */ | ||
| 212 | #define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */ | ||
| 213 | #define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */ | ||
| 214 | #define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */ | ||
| 215 | #define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */ | ||
| 216 | /* IVG 8 */ | ||
| 217 | #define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */ | ||
| 218 | #define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */ | ||
| 219 | #define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0 | ||
| 220 | #define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */ | ||
| 221 | #define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */ | ||
| 222 | #define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1 | ||
| 223 | /* IVG 9 */ | ||
| 224 | #define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */ | ||
| 225 | #define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0 | ||
| 226 | #define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */ | ||
| 227 | #define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1 | ||
| 228 | /* IVG 12 */ | ||
| 229 | #define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */ | ||
| 230 | #define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0 | ||
| 231 | #define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */ | ||
| 232 | #define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1 | ||
| 233 | /* IVG 13 */ | ||
| 234 | #define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */ | ||
| 235 | /* IVG 7 */ | ||
| 236 | #define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */ | ||
| 237 | #define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */ | ||
| 238 | #define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */ | ||
| 239 | #define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */ | ||
| 240 | #define IRQ_SW_INT1 71 /* Software Interrupt 1 */ | ||
| 241 | #define IRQ_SW_INT2 72 /* Software Interrupt 2 */ | ||
| 242 | /* reserved for SYSCALL */ | ||
| 243 | #define IRQ_PF0 73 | ||
| 244 | #define IRQ_PF1 74 | ||
| 245 | #define IRQ_PF2 75 | ||
| 246 | #define IRQ_PF3 76 | ||
| 247 | #define IRQ_PF4 77 | ||
| 248 | #define IRQ_PF5 78 | ||
| 249 | #define IRQ_PF6 79 | ||
| 250 | #define IRQ_PF7 80 | ||
| 251 | #define IRQ_PF8 81 | ||
| 252 | #define IRQ_PF9 82 | ||
| 253 | #define IRQ_PF10 83 | ||
| 254 | #define IRQ_PF11 84 | ||
| 255 | #define IRQ_PF12 85 | ||
| 256 | #define IRQ_PF13 86 | ||
| 257 | #define IRQ_PF14 87 | ||
| 258 | #define IRQ_PF15 88 | ||
| 259 | #define IRQ_PF16 89 | ||
| 260 | #define IRQ_PF17 90 | ||
| 261 | #define IRQ_PF18 91 | ||
| 262 | #define IRQ_PF19 92 | ||
| 263 | #define IRQ_PF20 93 | ||
| 264 | #define IRQ_PF21 94 | ||
| 265 | #define IRQ_PF22 95 | ||
| 266 | #define IRQ_PF23 96 | ||
| 267 | #define IRQ_PF24 97 | ||
| 268 | #define IRQ_PF25 98 | ||
| 269 | #define IRQ_PF26 99 | ||
| 270 | #define IRQ_PF27 100 | ||
| 271 | #define IRQ_PF28 101 | ||
| 272 | #define IRQ_PF29 102 | ||
| 273 | #define IRQ_PF30 103 | ||
| 274 | #define IRQ_PF31 104 | ||
| 275 | #define IRQ_PF32 105 | ||
| 276 | #define IRQ_PF33 106 | ||
| 277 | #define IRQ_PF34 107 | ||
| 278 | #define IRQ_PF35 108 | ||
| 279 | #define IRQ_PF36 109 | ||
| 280 | #define IRQ_PF37 110 | ||
| 281 | #define IRQ_PF38 111 | ||
| 282 | #define IRQ_PF39 112 | ||
| 283 | #define IRQ_PF40 113 | ||
| 284 | #define IRQ_PF41 114 | ||
| 285 | #define IRQ_PF42 115 | ||
| 286 | #define IRQ_PF43 116 | ||
| 287 | #define IRQ_PF44 117 | ||
| 288 | #define IRQ_PF45 118 | ||
| 289 | #define IRQ_PF46 119 | ||
| 290 | #define IRQ_PF47 120 | ||
| 291 | |||
| 292 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO | ||
| 293 | #define NR_IRQS (IRQ_PF47 + 1) | ||
| 294 | #else | ||
| 295 | #define NR_IRQS SYS_IRQS | ||
| 296 | #endif | ||
| 297 | |||
| 298 | #define IVG7 7 | ||
| 299 | #define IVG8 8 | ||
| 300 | #define IVG9 9 | ||
| 301 | #define IVG10 10 | ||
| 302 | #define IVG11 11 | ||
| 303 | #define IVG12 12 | ||
| 304 | #define IVG13 13 | ||
| 305 | #define IVG14 14 | ||
| 306 | #define IVG15 15 | ||
| 307 | |||
| 308 | /* | ||
| 309 | * DEFAULT PRIORITIES: | ||
| 310 | */ | ||
| 311 | |||
| 312 | #define CONFIG_DEF_PLL_WAKEUP 7 | ||
| 313 | #define CONFIG_DEF_DMA1_ERROR 7 | ||
| 314 | #define CONFIG_DEF_DMA2_ERROR 7 | ||
| 315 | #define CONFIG_DEF_IMDMA_ERROR 7 | ||
| 316 | #define CONFIG_DEF_PPI1_ERROR 7 | ||
| 317 | #define CONFIG_DEF_PPI2_ERROR 7 | ||
| 318 | #define CONFIG_DEF_SPORT0_ERROR 7 | ||
| 319 | #define CONFIG_DEF_SPORT1_ERROR 7 | ||
| 320 | #define CONFIG_DEF_SPI_ERROR 7 | ||
| 321 | #define CONFIG_DEF_UART_ERROR 7 | ||
| 322 | #define CONFIG_DEF_RESERVED_ERROR 7 | ||
| 323 | #define CONFIG_DEF_DMA1_0 8 | ||
| 324 | #define CONFIG_DEF_DMA1_1 8 | ||
| 325 | #define CONFIG_DEF_DMA1_2 8 | ||
| 326 | #define CONFIG_DEF_DMA1_3 8 | ||
| 327 | #define CONFIG_DEF_DMA1_4 8 | ||
| 328 | #define CONFIG_DEF_DMA1_5 8 | ||
| 329 | #define CONFIG_DEF_DMA1_6 8 | ||
| 330 | #define CONFIG_DEF_DMA1_7 8 | ||
| 331 | #define CONFIG_DEF_DMA1_8 8 | ||
| 332 | #define CONFIG_DEF_DMA1_9 8 | ||
| 333 | #define CONFIG_DEF_DMA1_10 8 | ||
| 334 | #define CONFIG_DEF_DMA1_11 8 | ||
| 335 | #define CONFIG_DEF_DMA2_0 9 | ||
| 336 | #define CONFIG_DEF_DMA2_1 9 | ||
| 337 | #define CONFIG_DEF_DMA2_2 9 | ||
| 338 | #define CONFIG_DEF_DMA2_3 9 | ||
| 339 | #define CONFIG_DEF_DMA2_4 9 | ||
| 340 | #define CONFIG_DEF_DMA2_5 9 | ||
| 341 | #define CONFIG_DEF_DMA2_6 9 | ||
| 342 | #define CONFIG_DEF_DMA2_7 9 | ||
| 343 | #define CONFIG_DEF_DMA2_8 9 | ||
| 344 | #define CONFIG_DEF_DMA2_9 9 | ||
| 345 | #define CONFIG_DEF_DMA2_10 9 | ||
| 346 | #define CONFIG_DEF_DMA2_11 9 | ||
| 347 | #define CONFIG_DEF_TIMER0 10 | ||
| 348 | #define CONFIG_DEF_TIMER1 10 | ||
| 349 | #define CONFIG_DEF_TIMER2 10 | ||
| 350 | #define CONFIG_DEF_TIMER3 10 | ||
| 351 | #define CONFIG_DEF_TIMER4 10 | ||
| 352 | #define CONFIG_DEF_TIMER5 10 | ||
| 353 | #define CONFIG_DEF_TIMER6 10 | ||
| 354 | #define CONFIG_DEF_TIMER7 10 | ||
| 355 | #define CONFIG_DEF_TIMER8 10 | ||
| 356 | #define CONFIG_DEF_TIMER9 10 | ||
| 357 | #define CONFIG_DEF_TIMER10 10 | ||
| 358 | #define CONFIG_DEF_TIMER11 10 | ||
| 359 | #define CONFIG_DEF_PROG0_INTA 11 | ||
| 360 | #define CONFIG_DEF_PROG0_INTB 11 | ||
| 361 | #define CONFIG_DEF_PROG1_INTA 11 | ||
| 362 | #define CONFIG_DEF_PROG1_INTB 11 | ||
| 363 | #define CONFIG_DEF_PROG2_INTA 11 | ||
| 364 | #define CONFIG_DEF_PROG2_INTB 11 | ||
| 365 | #define CONFIG_DEF_DMA1_WRRD0 8 | ||
| 366 | #define CONFIG_DEF_DMA1_WRRD1 8 | ||
| 367 | #define CONFIG_DEF_DMA2_WRRD0 9 | ||
| 368 | #define CONFIG_DEF_DMA2_WRRD1 9 | ||
| 369 | #define CONFIG_DEF_IMDMA_WRRD0 12 | ||
| 370 | #define CONFIG_DEF_IMDMA_WRRD1 12 | ||
| 371 | #define CONFIG_DEF_WATCH 13 | ||
| 372 | #define CONFIG_DEF_RESERVED_1 7 | ||
| 373 | #define CONFIG_DEF_RESERVED_2 7 | ||
| 374 | #define CONFIG_DEF_SUPPLE_0 7 | ||
| 375 | #define CONFIG_DEF_SUPPLE_1 7 | ||
| 376 | |||
| 377 | /* IAR0 BIT FIELDS */ | ||
| 378 | #define IRQ_PLL_WAKEUP_POS 0 | ||
| 379 | #define IRQ_DMA1_ERROR_POS 4 | ||
| 380 | #define IRQ_DMA2_ERROR_POS 8 | ||
| 381 | #define IRQ_IMDMA_ERROR_POS 12 | ||
| 382 | #define IRQ_PPI0_ERROR_POS 16 | ||
| 383 | #define IRQ_PPI1_ERROR_POS 20 | ||
| 384 | #define IRQ_SPORT0_ERROR_POS 24 | ||
| 385 | #define IRQ_SPORT1_ERROR_POS 28 | ||
| 386 | /* IAR1 BIT FIELDS */ | ||
| 387 | #define IRQ_SPI_ERROR_POS 0 | ||
| 388 | #define IRQ_UART_ERROR_POS 4 | ||
| 389 | #define IRQ_RESERVED_ERROR_POS 8 | ||
| 390 | #define IRQ_DMA1_0_POS 12 | ||
| 391 | #define IRQ_DMA1_1_POS 16 | ||
| 392 | #define IRQ_DMA1_2_POS 20 | ||
| 393 | #define IRQ_DMA1_3_POS 24 | ||
| 394 | #define IRQ_DMA1_4_POS 28 | ||
| 395 | /* IAR2 BIT FIELDS */ | ||
| 396 | #define IRQ_DMA1_5_POS 0 | ||
| 397 | #define IRQ_DMA1_6_POS 4 | ||
| 398 | #define IRQ_DMA1_7_POS 8 | ||
| 399 | #define IRQ_DMA1_8_POS 12 | ||
| 400 | #define IRQ_DMA1_9_POS 16 | ||
| 401 | #define IRQ_DMA1_10_POS 20 | ||
| 402 | #define IRQ_DMA1_11_POS 24 | ||
| 403 | #define IRQ_DMA2_0_POS 28 | ||
| 404 | /* IAR3 BIT FIELDS */ | ||
| 405 | #define IRQ_DMA2_1_POS 0 | ||
| 406 | #define IRQ_DMA2_2_POS 4 | ||
| 407 | #define IRQ_DMA2_3_POS 8 | ||
| 408 | #define IRQ_DMA2_4_POS 12 | ||
| 409 | #define IRQ_DMA2_5_POS 16 | ||
| 410 | #define IRQ_DMA2_6_POS 20 | ||
| 411 | #define IRQ_DMA2_7_POS 24 | ||
| 412 | #define IRQ_DMA2_8_POS 28 | ||
| 413 | /* IAR4 BIT FIELDS */ | ||
| 414 | #define IRQ_DMA2_9_POS 0 | ||
| 415 | #define IRQ_DMA2_10_POS 4 | ||
| 416 | #define IRQ_DMA2_11_POS 8 | ||
| 417 | #define IRQ_TIMER0_POS 12 | ||
| 418 | #define IRQ_TIMER1_POS 16 | ||
| 419 | #define IRQ_TIMER2_POS 20 | ||
| 420 | #define IRQ_TIMER3_POS 24 | ||
| 421 | #define IRQ_TIMER4_POS 28 | ||
| 422 | /* IAR5 BIT FIELDS */ | ||
| 423 | #define IRQ_TIMER5_POS 0 | ||
| 424 | #define IRQ_TIMER6_POS 4 | ||
| 425 | #define IRQ_TIMER7_POS 8 | ||
| 426 | #define IRQ_TIMER8_POS 12 | ||
| 427 | #define IRQ_TIMER9_POS 16 | ||
| 428 | #define IRQ_TIMER10_POS 20 | ||
| 429 | #define IRQ_TIMER11_POS 24 | ||
| 430 | #define IRQ_PROG0_INTA_POS 28 | ||
| 431 | /* IAR6 BIT FIELDS */ | ||
| 432 | #define IRQ_PROG0_INTB_POS 0 | ||
| 433 | #define IRQ_PROG1_INTA_POS 4 | ||
| 434 | #define IRQ_PROG1_INTB_POS 8 | ||
| 435 | #define IRQ_PROG2_INTA_POS 12 | ||
| 436 | #define IRQ_PROG2_INTB_POS 16 | ||
| 437 | #define IRQ_DMA1_WRRD0_POS 20 | ||
| 438 | #define IRQ_DMA1_WRRD1_POS 24 | ||
| 439 | #define IRQ_DMA2_WRRD0_POS 28 | ||
| 440 | /* IAR7 BIT FIELDS */ | ||
| 441 | #define IRQ_DMA2_WRRD1_POS 0 | ||
| 442 | #define IRQ_IMDMA_WRRD0_POS 4 | ||
| 443 | #define IRQ_IMDMA_WRRD1_POS 8 | ||
| 444 | #define IRQ_WDTIMER_POS 12 | ||
| 445 | #define IRQ_RESERVED_1_POS 16 | ||
| 446 | #define IRQ_RESERVED_2_POS 20 | ||
| 447 | #define IRQ_SUPPLE_0_POS 24 | ||
| 448 | #define IRQ_SUPPLE_1_POS 28 | ||
| 449 | |||
| 450 | #endif /* _BF561_IRQ_H_ */ | ||
diff --git a/include/asm-blackfin/mach-bf561/mem_init.h b/include/asm-blackfin/mach-bf561/mem_init.h new file mode 100644 index 000000000000..439a5895b346 --- /dev/null +++ b/include/asm-blackfin/mach-bf561/mem_init.h | |||
| @@ -0,0 +1,322 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf561/mem_init.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC8M32B2B5_7) | ||
| 32 | #if (CONFIG_SCLK_HZ > 119402985) | ||
| 33 | #define SDRAM_tRP TRP_2 | ||
| 34 | #define SDRAM_tRP_num 2 | ||
| 35 | #define SDRAM_tRAS TRAS_7 | ||
| 36 | #define SDRAM_tRAS_num 7 | ||
| 37 | #define SDRAM_tRCD TRCD_2 | ||
| 38 | #define SDRAM_tWR TWR_2 | ||
| 39 | #endif | ||
| 40 | #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) | ||
| 41 | #define SDRAM_tRP TRP_2 | ||
| 42 | #define SDRAM_tRP_num 2 | ||
| 43 | #define SDRAM_tRAS TRAS_6 | ||
| 44 | #define SDRAM_tRAS_num 6 | ||
| 45 | #define SDRAM_tRCD TRCD_2 | ||
| 46 | #define SDRAM_tWR TWR_2 | ||
| 47 | #endif | ||
| 48 | #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) | ||
| 49 | #define SDRAM_tRP TRP_2 | ||
| 50 | #define SDRAM_tRP_num 2 | ||
| 51 | #define SDRAM_tRAS TRAS_5 | ||
| 52 | #define SDRAM_tRAS_num 5 | ||
| 53 | #define SDRAM_tRCD TRCD_2 | ||
| 54 | #define SDRAM_tWR TWR_2 | ||
| 55 | #endif | ||
| 56 | #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) | ||
| 57 | #define SDRAM_tRP TRP_2 | ||
| 58 | #define SDRAM_tRP_num 2 | ||
| 59 | #define SDRAM_tRAS TRAS_4 | ||
| 60 | #define SDRAM_tRAS_num 4 | ||
| 61 | #define SDRAM_tRCD TRCD_2 | ||
| 62 | #define SDRAM_tWR TWR_2 | ||
| 63 | #endif | ||
| 64 | #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) | ||
| 65 | #define SDRAM_tRP TRP_2 | ||
| 66 | #define SDRAM_tRP_num 2 | ||
| 67 | #define SDRAM_tRAS TRAS_3 | ||
| 68 | #define SDRAM_tRAS_num 3 | ||
| 69 | #define SDRAM_tRCD TRCD_2 | ||
| 70 | #define SDRAM_tWR TWR_2 | ||
| 71 | #endif | ||
| 72 | #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) | ||
| 73 | #define SDRAM_tRP TRP_1 | ||
| 74 | #define SDRAM_tRP_num 1 | ||
| 75 | #define SDRAM_tRAS TRAS_4 | ||
| 76 | #define SDRAM_tRAS_num 3 | ||
| 77 | #define SDRAM_tRCD TRCD_1 | ||
| 78 | #define SDRAM_tWR TWR_2 | ||
| 79 | #endif | ||
| 80 | #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) | ||
| 81 | #define SDRAM_tRP TRP_1 | ||
| 82 | #define SDRAM_tRP_num 1 | ||
| 83 | #define SDRAM_tRAS TRAS_3 | ||
| 84 | #define SDRAM_tRAS_num 3 | ||
| 85 | #define SDRAM_tRCD TRCD_1 | ||
| 86 | #define SDRAM_tWR TWR_2 | ||
| 87 | #endif | ||
| 88 | #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) | ||
| 89 | #define SDRAM_tRP TRP_1 | ||
| 90 | #define SDRAM_tRP_num 1 | ||
| 91 | #define SDRAM_tRAS TRAS_2 | ||
| 92 | #define SDRAM_tRAS_num 2 | ||
| 93 | #define SDRAM_tRCD TRCD_1 | ||
| 94 | #define SDRAM_tWR TWR_2 | ||
| 95 | #endif | ||
| 96 | #if (CONFIG_SCLK_HZ <= 29850746) | ||
| 97 | #define SDRAM_tRP TRP_1 | ||
| 98 | #define SDRAM_tRP_num 1 | ||
| 99 | #define SDRAM_tRAS TRAS_1 | ||
| 100 | #define SDRAM_tRAS_num 1 | ||
| 101 | #define SDRAM_tRCD TRCD_1 | ||
| 102 | #define SDRAM_tWR TWR_2 | ||
| 103 | #endif | ||
| 104 | #endif | ||
| 105 | |||
| 106 | #if (CONFIG_MEM_MT48LC16M16A2TG_75) | ||
| 107 | /*SDRAM INFORMATION: */ | ||
| 108 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 109 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 110 | #define SDRAM_CL CL_3 | ||
| 111 | #endif | ||
| 112 | |||
| 113 | #if (CONFIG_MEM_MT48LC64M4A2FB_7E) | ||
| 114 | /*SDRAM INFORMATION: */ | ||
| 115 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 116 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 117 | #define SDRAM_CL CL_3 | ||
| 118 | #endif | ||
| 119 | |||
| 120 | #if (CONFIG_MEM_MT48LC8M32B2B5_7) | ||
| 121 | /*SDRAM INFORMATION: */ | ||
| 122 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 123 | #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ | ||
| 124 | #define SDRAM_CL CL_3 | ||
| 125 | #endif | ||
| 126 | |||
| 127 | #if (CONFIG_MEM_GENERIC_BOARD) | ||
| 128 | /*SDRAM INFORMATION: Modify this for your board */ | ||
| 129 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 130 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 131 | #define SDRAM_CL CL_3 | ||
| 132 | #endif | ||
| 133 | |||
| 134 | #if (CONFIG_MEM_SIZE == 128) | ||
| 135 | #define SDRAM_SIZE EB0_SZ_128 | ||
| 136 | #endif | ||
| 137 | #if (CONFIG_MEM_SIZE == 64) | ||
| 138 | #define SDRAM_SIZE EB0_SZ_64 | ||
| 139 | #endif | ||
| 140 | #if ( CONFIG_MEM_SIZE == 32) | ||
| 141 | #define SDRAM_SIZE EB0_SZ_32 | ||
| 142 | #endif | ||
| 143 | #if (CONFIG_MEM_SIZE == 16) | ||
| 144 | #define SDRAM_SIZE EB0_SZ_16 | ||
| 145 | #endif | ||
| 146 | #if (CONFIG_MEM_ADD_WIDTH == 11) | ||
| 147 | #define SDRAM_WIDTH EB0_CAW_11 | ||
| 148 | #endif | ||
| 149 | #if (CONFIG_MEM_ADD_WIDTH == 10) | ||
| 150 | #define SDRAM_WIDTH EB0_CAW_10 | ||
| 151 | #endif | ||
| 152 | #if (CONFIG_MEM_ADD_WIDTH == 9) | ||
| 153 | #define SDRAM_WIDTH EB0_CAW_9 | ||
| 154 | #endif | ||
| 155 | #if (CONFIG_MEM_ADD_WIDTH == 8) | ||
| 156 | #define SDRAM_WIDTH EB0_CAW_8 | ||
| 157 | #endif | ||
| 158 | |||
| 159 | #define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EB0_E) | ||
| 160 | |||
| 161 | /* Equation from section 17 (p17-46) of BF533 HRM */ | ||
| 162 | #define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) | ||
| 163 | |||
| 164 | /* Enable SCLK Out */ | ||
| 165 | #define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) | ||
| 166 | |||
| 167 | #if defined CONFIG_CLKIN_HALF | ||
| 168 | #define CLKIN_HALF 1 | ||
| 169 | #else | ||
| 170 | #define CLKIN_HALF 0 | ||
| 171 | #endif | ||
| 172 | |||
| 173 | #if defined CONFIG_PLL_BYPASS | ||
| 174 | #define PLL_BYPASS 1 | ||
| 175 | #else | ||
| 176 | #define PLL_BYPASS 0 | ||
| 177 | #endif | ||
| 178 | |||
| 179 | /***************************************Currently Not Being Used *********************************/ | ||
| 180 | #define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 181 | #define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 182 | #define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) | ||
| 183 | #define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 184 | #define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 185 | |||
| 186 | #if (flash_EBIU_AMBCTL_TT > 3) | ||
| 187 | #define flash_EBIU_AMBCTL0_TT B0TT_4 | ||
| 188 | #endif | ||
| 189 | #if (flash_EBIU_AMBCTL_TT == 3) | ||
| 190 | #define flash_EBIU_AMBCTL0_TT B0TT_3 | ||
| 191 | #endif | ||
| 192 | #if (flash_EBIU_AMBCTL_TT == 2) | ||
| 193 | #define flash_EBIU_AMBCTL0_TT B0TT_2 | ||
| 194 | #endif | ||
| 195 | #if (flash_EBIU_AMBCTL_TT < 2) | ||
| 196 | #define flash_EBIU_AMBCTL0_TT B0TT_1 | ||
| 197 | #endif | ||
| 198 | |||
| 199 | #if (flash_EBIU_AMBCTL_ST > 3) | ||
| 200 | #define flash_EBIU_AMBCTL0_ST B0ST_4 | ||
| 201 | #endif | ||
| 202 | #if (flash_EBIU_AMBCTL_ST == 3) | ||
| 203 | #define flash_EBIU_AMBCTL0_ST B0ST_3 | ||
| 204 | #endif | ||
| 205 | #if (flash_EBIU_AMBCTL_ST == 2) | ||
| 206 | #define flash_EBIU_AMBCTL0_ST B0ST_2 | ||
| 207 | #endif | ||
| 208 | #if (flash_EBIU_AMBCTL_ST < 2) | ||
| 209 | #define flash_EBIU_AMBCTL0_ST B0ST_1 | ||
| 210 | #endif | ||
| 211 | |||
| 212 | #if (flash_EBIU_AMBCTL_HT > 2) | ||
| 213 | #define flash_EBIU_AMBCTL0_HT B0HT_3 | ||
| 214 | #endif | ||
| 215 | #if (flash_EBIU_AMBCTL_HT == 2) | ||
| 216 | #define flash_EBIU_AMBCTL0_HT B0HT_2 | ||
| 217 | #endif | ||
| 218 | #if (flash_EBIU_AMBCTL_HT == 1) | ||
| 219 | #define flash_EBIU_AMBCTL0_HT B0HT_1 | ||
| 220 | #endif | ||
| 221 | #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) | ||
| 222 | #define flash_EBIU_AMBCTL0_HT B0HT_0 | ||
| 223 | #endif | ||
| 224 | #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) | ||
| 225 | #define flash_EBIU_AMBCTL0_HT B0HT_1 | ||
| 226 | #endif | ||
| 227 | |||
| 228 | #if (flash_EBIU_AMBCTL_WAT > 14) | ||
| 229 | #define flash_EBIU_AMBCTL0_WAT B0WAT_15 | ||
| 230 | #endif | ||
| 231 | #if (flash_EBIU_AMBCTL_WAT == 14) | ||
| 232 | #define flash_EBIU_AMBCTL0_WAT B0WAT_14 | ||
| 233 | #endif | ||
| 234 | #if (flash_EBIU_AMBCTL_WAT == 13) | ||
| 235 | #define flash_EBIU_AMBCTL0_WAT B0WAT_13 | ||
| 236 | #endif | ||
| 237 | #if (flash_EBIU_AMBCTL_WAT == 12) | ||
| 238 | #define flash_EBIU_AMBCTL0_WAT B0WAT_12 | ||
| 239 | #endif | ||
| 240 | #if (flash_EBIU_AMBCTL_WAT == 11) | ||
| 241 | #define flash_EBIU_AMBCTL0_WAT B0WAT_11 | ||
| 242 | #endif | ||
| 243 | #if (flash_EBIU_AMBCTL_WAT == 10) | ||
| 244 | #define flash_EBIU_AMBCTL0_WAT B0WAT_10 | ||
| 245 | #endif | ||
| 246 | #if (flash_EBIU_AMBCTL_WAT == 9) | ||
| 247 | #define flash_EBIU_AMBCTL0_WAT B0WAT_9 | ||
| 248 | #endif | ||
| 249 | #if (flash_EBIU_AMBCTL_WAT == 8) | ||
| 250 | #define flash_EBIU_AMBCTL0_WAT B0WAT_8 | ||
| 251 | #endif | ||
| 252 | #if (flash_EBIU_AMBCTL_WAT == 7) | ||
| 253 | #define flash_EBIU_AMBCTL0_WAT B0WAT_7 | ||
| 254 | #endif | ||
| 255 | #if (flash_EBIU_AMBCTL_WAT == 6) | ||
| 256 | #define flash_EBIU_AMBCTL0_WAT B0WAT_6 | ||
| 257 | #endif | ||
| 258 | #if (flash_EBIU_AMBCTL_WAT == 5) | ||
| 259 | #define flash_EBIU_AMBCTL0_WAT B0WAT_5 | ||
| 260 | #endif | ||
| 261 | #if (flash_EBIU_AMBCTL_WAT == 4) | ||
| 262 | #define flash_EBIU_AMBCTL0_WAT B0WAT_4 | ||
| 263 | #endif | ||
| 264 | #if (flash_EBIU_AMBCTL_WAT == 3) | ||
| 265 | #define flash_EBIU_AMBCTL0_WAT B0WAT_3 | ||
| 266 | #endif | ||
| 267 | #if (flash_EBIU_AMBCTL_WAT == 2) | ||
| 268 | #define flash_EBIU_AMBCTL0_WAT B0WAT_2 | ||
| 269 | #endif | ||
| 270 | #if (flash_EBIU_AMBCTL_WAT == 1) | ||
| 271 | #define flash_EBIU_AMBCTL0_WAT B0WAT_1 | ||
| 272 | #endif | ||
| 273 | |||
| 274 | #if (flash_EBIU_AMBCTL_RAT > 14) | ||
| 275 | #define flash_EBIU_AMBCTL0_RAT B0RAT_15 | ||
| 276 | #endif | ||
| 277 | #if (flash_EBIU_AMBCTL_RAT == 14) | ||
| 278 | #define flash_EBIU_AMBCTL0_RAT B0RAT_14 | ||
| 279 | #endif | ||
| 280 | #if (flash_EBIU_AMBCTL_RAT == 13) | ||
| 281 | #define flash_EBIU_AMBCTL0_RAT B0RAT_13 | ||
| 282 | #endif | ||
| 283 | #if (flash_EBIU_AMBCTL_RAT == 12) | ||
| 284 | #define flash_EBIU_AMBCTL0_RAT B0RAT_12 | ||
| 285 | #endif | ||
| 286 | #if (flash_EBIU_AMBCTL_RAT == 11) | ||
| 287 | #define flash_EBIU_AMBCTL0_RAT B0RAT_11 | ||
| 288 | #endif | ||
| 289 | #if (flash_EBIU_AMBCTL_RAT == 10) | ||
| 290 | #define flash_EBIU_AMBCTL0_RAT B0RAT_10 | ||
| 291 | #endif | ||
| 292 | #if (flash_EBIU_AMBCTL_RAT == 9) | ||
| 293 | #define flash_EBIU_AMBCTL0_RAT B0RAT_9 | ||
| 294 | #endif | ||
| 295 | #if (flash_EBIU_AMBCTL_RAT == 8) | ||
| 296 | #define flash_EBIU_AMBCTL0_RAT B0RAT_8 | ||
| 297 | #endif | ||
| 298 | #if (flash_EBIU_AMBCTL_RAT == 7) | ||
| 299 | #define flash_EBIU_AMBCTL0_RAT B0RAT_7 | ||
| 300 | #endif | ||
| 301 | #if (flash_EBIU_AMBCTL_RAT == 6) | ||
| 302 | #define flash_EBIU_AMBCTL0_RAT B0RAT_6 | ||
| 303 | #endif | ||
| 304 | #if (flash_EBIU_AMBCTL_RAT == 5) | ||
| 305 | #define flash_EBIU_AMBCTL0_RAT B0RAT_5 | ||
| 306 | #endif | ||
| 307 | #if (flash_EBIU_AMBCTL_RAT == 4) | ||
| 308 | #define flash_EBIU_AMBCTL0_RAT B0RAT_4 | ||
| 309 | #endif | ||
| 310 | #if (flash_EBIU_AMBCTL_RAT == 3) | ||
| 311 | #define flash_EBIU_AMBCTL0_RAT B0RAT_3 | ||
| 312 | #endif | ||
| 313 | #if (flash_EBIU_AMBCTL_RAT == 2) | ||
| 314 | #define flash_EBIU_AMBCTL0_RAT B0RAT_2 | ||
| 315 | #endif | ||
| 316 | #if (flash_EBIU_AMBCTL_RAT == 1) | ||
| 317 | #define flash_EBIU_AMBCTL0_RAT B0RAT_1 | ||
| 318 | #endif | ||
| 319 | |||
| 320 | #define flash_EBIU_AMBCTL0 \ | ||
| 321 | (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ | ||
| 322 | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) | ||
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h new file mode 100644 index 000000000000..ebac9a8d838d --- /dev/null +++ b/include/asm-blackfin/mach-bf561/mem_map.h | |||
| @@ -0,0 +1,75 @@ | |||
| 1 | /* | ||
| 2 | * Memory MAP | ||
| 3 | * Common header file for blackfin BF561 of processors. | ||
| 4 | */ | ||
| 5 | |||
| 6 | #ifndef _MEM_MAP_561_H_ | ||
| 7 | #define _MEM_MAP_561_H_ | ||
| 8 | |||
| 9 | #define COREMMR_BASE 0xFFE00000 /* Core MMRs */ | ||
| 10 | #define SYSMMR_BASE 0xFFC00000 /* System MMRs */ | ||
| 11 | |||
| 12 | /* Async Memory Banks */ | ||
| 13 | #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ | ||
| 14 | #define ASYNC_BANK3_SIZE 0x04000000 /* 64M */ | ||
| 15 | #define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */ | ||
| 16 | #define ASYNC_BANK2_SIZE 0x04000000 /* 64M */ | ||
| 17 | #define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */ | ||
| 18 | #define ASYNC_BANK1_SIZE 0x04000000 /* 64M */ | ||
| 19 | #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ | ||
| 20 | #define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ | ||
| 21 | |||
| 22 | /* Level 1 Memory */ | ||
| 23 | |||
| 24 | #ifdef CONFIG_BLKFIN_CACHE | ||
| 25 | #define BLKFIN_ICACHESIZE (16*1024) | ||
| 26 | #else | ||
| 27 | #define BLKFIN_ICACHESIZE (0*1024) | ||
| 28 | #endif | ||
| 29 | |||
| 30 | /* Memory Map for ADSP-BF561 processors */ | ||
| 31 | |||
| 32 | #ifdef CONFIG_BF561 | ||
| 33 | #define L1_CODE_START 0xFFA00000 | ||
| 34 | #define L1_DATA_A_START 0xFF800000 | ||
| 35 | #define L1_DATA_B_START 0xFF900000 | ||
| 36 | |||
| 37 | #define L1_CODE_LENGTH 0x4000 | ||
| 38 | |||
| 39 | #ifdef CONFIG_BLKFIN_DCACHE | ||
| 40 | |||
| 41 | #ifdef CONFIG_BLKFIN_DCACHE_BANKA | ||
| 42 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) | ||
| 43 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | ||
| 44 | #define L1_DATA_B_LENGTH 0x8000 | ||
| 45 | #define BLKFIN_DCACHESIZE (16*1024) | ||
| 46 | #define BLKFIN_DSUPBANKS 1 | ||
| 47 | #else | ||
| 48 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) | ||
| 49 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | ||
| 50 | #define L1_DATA_B_LENGTH (0x8000 - 0x4000) | ||
| 51 | #define BLKFIN_DCACHESIZE (32*1024) | ||
| 52 | #define BLKFIN_DSUPBANKS 2 | ||
| 53 | #endif | ||
| 54 | |||
| 55 | #else | ||
| 56 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) | ||
| 57 | #define L1_DATA_A_LENGTH 0x8000 | ||
| 58 | #define L1_DATA_B_LENGTH 0x8000 | ||
| 59 | #define BLKFIN_DCACHESIZE (0*1024) | ||
| 60 | #define BLKFIN_DSUPBANKS 0 | ||
| 61 | #endif /*CONFIG_BLKFIN_DCACHE*/ | ||
| 62 | #endif | ||
| 63 | |||
| 64 | /* Level 2 Memory */ | ||
| 65 | #define L2_START 0xFEB00000 | ||
| 66 | #define L2_LENGTH 0x20000 | ||
| 67 | |||
| 68 | /* Scratch Pad Memory */ | ||
| 69 | |||
| 70 | #if defined(CONFIG_BF561) | ||
| 71 | #define L1_SCRATCH_START 0xFFB00000 | ||
| 72 | #define L1_SCRATCH_LENGTH 0x1000 | ||
| 73 | #endif | ||
| 74 | |||
| 75 | #endif /* _MEM_MAP_533_H_ */ | ||