diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf561/mem_map.h')
-rw-r--r-- | include/asm-blackfin/mach-bf561/mem_map.h | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h index ebac9a8d838d..f7ac09cf2c3d 100644 --- a/include/asm-blackfin/mach-bf561/mem_map.h +++ b/include/asm-blackfin/mach-bf561/mem_map.h | |||
@@ -21,10 +21,10 @@ | |||
21 | 21 | ||
22 | /* Level 1 Memory */ | 22 | /* Level 1 Memory */ |
23 | 23 | ||
24 | #ifdef CONFIG_BLKFIN_CACHE | 24 | #ifdef CONFIG_BFIN_ICACHE |
25 | #define BLKFIN_ICACHESIZE (16*1024) | 25 | #define BFIN_ICACHESIZE (16*1024) |
26 | #else | 26 | #else |
27 | #define BLKFIN_ICACHESIZE (0*1024) | 27 | #define BFIN_ICACHESIZE (0*1024) |
28 | #endif | 28 | #endif |
29 | 29 | ||
30 | /* Memory Map for ADSP-BF561 processors */ | 30 | /* Memory Map for ADSP-BF561 processors */ |
@@ -36,29 +36,29 @@ | |||
36 | 36 | ||
37 | #define L1_CODE_LENGTH 0x4000 | 37 | #define L1_CODE_LENGTH 0x4000 |
38 | 38 | ||
39 | #ifdef CONFIG_BLKFIN_DCACHE | 39 | #ifdef CONFIG_BFIN_DCACHE |
40 | 40 | ||
41 | #ifdef CONFIG_BLKFIN_DCACHE_BANKA | 41 | #ifdef CONFIG_BFIN_DCACHE_BANKA |
42 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) | 42 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) |
43 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | 43 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) |
44 | #define L1_DATA_B_LENGTH 0x8000 | 44 | #define L1_DATA_B_LENGTH 0x8000 |
45 | #define BLKFIN_DCACHESIZE (16*1024) | 45 | #define BFIN_DCACHESIZE (16*1024) |
46 | #define BLKFIN_DSUPBANKS 1 | 46 | #define BFIN_DSUPBANKS 1 |
47 | #else | 47 | #else |
48 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) | 48 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) |
49 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | 49 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) |
50 | #define L1_DATA_B_LENGTH (0x8000 - 0x4000) | 50 | #define L1_DATA_B_LENGTH (0x8000 - 0x4000) |
51 | #define BLKFIN_DCACHESIZE (32*1024) | 51 | #define BFIN_DCACHESIZE (32*1024) |
52 | #define BLKFIN_DSUPBANKS 2 | 52 | #define BFIN_DSUPBANKS 2 |
53 | #endif | 53 | #endif |
54 | 54 | ||
55 | #else | 55 | #else |
56 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) | 56 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) |
57 | #define L1_DATA_A_LENGTH 0x8000 | 57 | #define L1_DATA_A_LENGTH 0x8000 |
58 | #define L1_DATA_B_LENGTH 0x8000 | 58 | #define L1_DATA_B_LENGTH 0x8000 |
59 | #define BLKFIN_DCACHESIZE (0*1024) | 59 | #define BFIN_DCACHESIZE (0*1024) |
60 | #define BLKFIN_DSUPBANKS 0 | 60 | #define BFIN_DSUPBANKS 0 |
61 | #endif /*CONFIG_BLKFIN_DCACHE*/ | 61 | #endif /*CONFIG_BFIN_DCACHE*/ |
62 | #endif | 62 | #endif |
63 | 63 | ||
64 | /* Level 2 Memory */ | 64 | /* Level 2 Memory */ |