1 files changed, 19 insertions, 12 deletions
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index c3c0eb13c819..366c9b9a0cb7 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -110,18 +110,23 @@
 #define WDOGB_STAT                              0xFFC01208      /* Watchdog Status register */
 /* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART_THR                0xFFC00400      /* Transmit Holding register */
-#define UART_RBR                0xFFC00400      /* Receive Buffer register */
+/*
-#define UART_DLL                0xFFC00400      /* Divisor Latch (Low-Byte) */
+ * Because include/linux/serial_reg.h have defined UART_*,
-#define UART_IER                0xFFC00404      /* Interrupt Enable Register */
+ * So we define blackfin uart regs to BFIN_UART0_*.
-#define UART_DLH                0xFFC00404      /* Divisor Latch (High-Byte) */
+ */
-#define UART_IIR                0xFFC00408      /* Interrupt Identification Register */
+#define BFIN_UART_THR                   0xFFC00400  /* Transmit Holding register */
-#define UART_LCR                0xFFC0040C      /* Line Control Register */
+#define BFIN_UART_RBR                   0xFFC00400  /* Receive Buffer register */
-#define UART_MCR                                0xFFC00410      /* Modem Control Register */
+#define BFIN_UART_DLL                   0xFFC00400  /* Divisor Latch (Low-Byte) */
-#define UART_LSR                0xFFC00414      /* Line Status Register */
+#define BFIN_UART_IER                   0xFFC00404  /* Interrupt Enable Register */
-#define UART_MSR                0xFFC00418      /* Modem Status Register */
+#define BFIN_UART_DLH                   0xFFC00404  /* Divisor Latch (High-Byte) */
-#define UART_SCR                0xFFC0041C      /* SCR Scratch Register */
+#define BFIN_UART_IIR                   0xFFC00408  /* Interrupt Identification Register */
-#define UART_GCTL               0xFFC00424      /* Global Control Register */
+#define BFIN_UART_LCR                   0xFFC0040C  /* Line Control Register */
+#define BFIN_UART_MCR                   0xFFC00410  /* Modem Control Register */
+#define BFIN_UART_LSR                   0xFFC00414  /* Line Status Register */
+#define BFIN_UART_MSR                   0xFFC00418  /* Modem Status Register */
+#define BFIN_UART_SCR                   0xFFC0041C  /* SCR Scratch Register */
+#define BFIN_UART_GCTL                  0xFFC00424  /* Global Control Register */
 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
 #define SPI0_REGBASE                    0xFFC00500
@@ -866,6 +871,8 @@
 /* PLL_DIV Masks */
 #define SCLK_DIV(x)  (x)        /* SCLK = VCO / x */
+#define CSEL                    0x30            /* Core Select */
+#define SSEL                    0xf             /* System Select */
 #define CCLK_DIV1              0x00000000       /* CCLK = VCO / 1 */
 #define CCLK_DIV2              0x00000010       /* CCLK = VCO / 2 */
 #define CCLK_DIV4              0x00000020       /* CCLK = VCO / 4 */

diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h index c3c0eb13c819..366c9b9a0cb7 100644 --- a/include/asm-blackfin/mach-bf561/defBF561.h +++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -110,18 +110,23 @@
110	#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */	110	#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
111		111
112	/* UART Controller (0xFFC00400 - 0xFFC004FF) */	112	/* UART Controller (0xFFC00400 - 0xFFC004FF) */
113	#define UART_THR 0xFFC00400 /* Transmit Holding register */	113
114	#define UART_RBR 0xFFC00400 /* Receive Buffer register */	114	/*
115	#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */	115	* Because include/linux/serial_reg.h have defined UART_*,
116	#define UART_IER 0xFFC00404 /* Interrupt Enable Register */	116	* So we define blackfin uart regs to BFIN_UART0_*.
117	#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */	117	*/
118	#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */	118	#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
119	#define UART_LCR 0xFFC0040C /* Line Control Register */	119	#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
120	#define UART_MCR 0xFFC00410 /* Modem Control Register */	120	#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
121	#define UART_LSR 0xFFC00414 /* Line Status Register */	121	#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
122	#define UART_MSR 0xFFC00418 /* Modem Status Register */	122	#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
123	#define UART_SCR 0xFFC0041C /* SCR Scratch Register */	123	#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
124	#define UART_GCTL 0xFFC00424 /* Global Control Register */	124	#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
		125	#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
		126	#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
		127	#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */
		128	#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
		129	#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
125		130
126	/* SPI Controller (0xFFC00500 - 0xFFC005FF) */	131	/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
127	#define SPI0_REGBASE 0xFFC00500	132	#define SPI0_REGBASE 0xFFC00500
@@ -866,6 +871,8 @@
866	/* PLL_DIV Masks */	871	/* PLL_DIV Masks */
867	#define SCLK_DIV(x) (x) /* SCLK = VCO / x */	872	#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
868		873
		874	#define CSEL 0x30 /* Core Select */
		875	#define SSEL 0xf /* System Select */
869	#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */	876	#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
870	#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */	877	#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
871	#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */	878	#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */