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-rw-r--r--include/asm-blackfin/mach-bf561/cdefBF561.h1579
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diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
deleted file mode 100644
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--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
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@@ -1,1579 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/cdefBF561.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF561_H
32#define _CDEF_BF561_H
33
34#include <asm/blackfin.h>
35
36/* include all Core registers and bit definitions */
37#include "defBF561.h"
38
39/*include core specific register pointer definitions*/
40#include <asm/mach-common/cdef_LPBlackfin.h>
41
42#include <asm/system.h>
43
44/*********************************************************************************** */
45/* System MMR Register Map */
46/*********************************************************************************** */
47
48/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
49#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
50/* Writing to PLL_CTL initiates a PLL relock sequence. */
51static __inline__ void bfin_write_PLL_CTL(unsigned int val)
52{
53 unsigned long flags, iwr0, iwr1;
54
55 if (val == bfin_read_PLL_CTL())
56 return;
57
58 local_irq_save(flags);
59 /* Enable the PLL Wakeup bit in SIC IWR */
60 iwr0 = bfin_read32(SICA_IWR0);
61 iwr1 = bfin_read32(SICA_IWR1);
62 /* Only allow PPL Wakeup) */
63 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
64 bfin_write32(SICA_IWR1, 0);
65
66 bfin_write16(PLL_CTL, val);
67 SSYNC();
68 asm("IDLE;");
69
70 bfin_write32(SICA_IWR0, iwr0);
71 bfin_write32(SICA_IWR1, iwr1);
72 local_irq_restore(flags);
73}
74#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
75#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
76#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
77/* Writing to VR_CTL initiates a PLL relock sequence. */
78static __inline__ void bfin_write_VR_CTL(unsigned int val)
79{
80 unsigned long flags, iwr0, iwr1;
81
82 if (val == bfin_read_VR_CTL())
83 return;
84
85 local_irq_save(flags);
86 /* Enable the PLL Wakeup bit in SIC IWR */
87 iwr0 = bfin_read32(SICA_IWR0);
88 iwr1 = bfin_read32(SICA_IWR1);
89 /* Only allow PPL Wakeup) */
90 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
91 bfin_write32(SICA_IWR1, 0);
92
93 bfin_write16(VR_CTL, val);
94 SSYNC();
95 asm("IDLE;");
96
97 bfin_write32(SICA_IWR0, iwr0);
98 bfin_write32(SICA_IWR1, iwr1);
99 local_irq_restore(flags);
100}
101#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
102#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
103#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
104#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
105#define bfin_read_CHIPID() bfin_read32(CHIPID)
106
107/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
108#define bfin_read_SWRST() bfin_read_SICA_SWRST()
109#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
110#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()
111#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
112
113/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
114#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
115#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val)
116#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR)
117#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val)
118#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT)
119#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val)
120#define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK)
121#define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val)
122#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0)
123#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val)
124#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1)
125#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val)
126#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0)
127#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val)
128#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1)
129#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val)
130#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2)
131#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val)
132#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3)
133#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val)
134#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4)
135#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val)
136#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5)
137#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val)
138#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6)
139#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val)
140#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7)
141#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val)
142#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0)
143#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val)
144#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1)
145#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val)
146#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0)
147#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val)
148#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1)
149#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val)
150
151/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
152#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
153#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST,val)
154#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR)
155#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR,val)
156#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT)
157#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT,val)
158#define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0)
159#define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val)
160#define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1)
161#define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1,val)
162#define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0)
163#define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0,val)
164#define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1)
165#define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1,val)
166#define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2)
167#define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2,val)
168#define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3)
169#define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3,val)
170#define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4)
171#define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4,val)
172#define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5)
173#define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5,val)
174#define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6)
175#define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6,val)
176#define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7)
177#define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7,val)
178#define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0)
179#define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0,val)
180#define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1)
181#define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1,val)
182#define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0)
183#define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0,val)
184#define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1)
185#define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1,val)
186/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
187#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL)
188#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL,val)
189#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT)
190#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT,val)
191#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT)
192#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT,val)
193
194/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
195#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL)
196#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL,val)
197#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT)
198#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT,val)
199#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT)
200#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT,val)
201
202/* UART Controller (0xFFC00400 - 0xFFC004FF) */
203#define bfin_read_UART_THR() bfin_read16(UART_THR)
204#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
205#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
206#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
207#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
208#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
209#define bfin_read_UART_IER() bfin_read16(UART_IER)
210#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
211#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
212#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
213#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
214#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
215#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
216#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
217#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
218#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
219#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
220#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
221#define bfin_read_UART_MSR() bfin_read16(UART_MSR)
222#define bfin_write_UART_MSR(val) bfin_write16(UART_MSR,val)
223#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
224#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
225#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
226#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
227
228/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
229#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
230#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
231#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
232#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
233#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
234#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
235#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
236#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
237#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
238#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
239#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
240#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
241#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
242#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
243
244/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
245#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
246#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
247#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
248#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
249#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
250#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
251#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
252#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
253#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
254#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
255#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
256#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
257#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
258#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
259#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
260#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
261#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
262#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
263#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
264#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
265#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
266#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
267#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
268#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
269#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
270#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
271#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
272#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
273#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
274#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
275#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
276#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
277#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
278#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
279#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
280#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
281#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
282#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
283#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
284#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
285#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
286#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
287#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
288#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
289#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
290#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
291#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
292#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
293#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
294#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
295#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
296#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
297#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
298#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
299#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
300#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
301#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
302#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
303#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
304#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
305#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
306#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
307#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
308#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
309
310/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
311#define bfin_read_TMRS8_ENABLE() bfin_read16(TMRS8_ENABLE)
312#define bfin_write_TMRS8_ENABLE(val) bfin_write16(TMRS8_ENABLE,val)
313#define bfin_read_TMRS8_DISABLE() bfin_read16(TMRS8_DISABLE)
314#define bfin_write_TMRS8_DISABLE(val) bfin_write16(TMRS8_DISABLE,val)
315#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS)
316#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS,val)
317#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
318#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG,val)
319#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
320#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER,val)
321#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
322#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD,val)
323#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
324#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH,val)
325#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
326#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG,val)
327#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
328#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER,val)
329#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
330#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD,val)
331#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
332#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH,val)
333#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
334#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG,val)
335#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
336#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER,val)
337#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
338#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD,val)
339#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
340#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH,val)
341#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG)
342#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG,val)
343#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER)
344#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER,val)
345#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD)
346#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD,val)
347#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH)
348#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH,val)
349#define bfin_read_TMRS4_ENABLE() bfin_read16(TMRS4_ENABLE)
350#define bfin_write_TMRS4_ENABLE(val) bfin_write16(TMRS4_ENABLE,val)
351#define bfin_read_TMRS4_DISABLE() bfin_read16(TMRS4_DISABLE)
352#define bfin_write_TMRS4_DISABLE(val) bfin_write16(TMRS4_DISABLE,val)
353#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS)
354#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS,val)
355
356/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
357#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D)
358#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D,val)
359#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C)
360#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C,val)
361#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S)
362#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S,val)
363#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T)
364#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T,val)
365#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D)
366#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D,val)
367#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C)
368#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C,val)
369#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S)
370#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S,val)
371#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T)
372#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T,val)
373#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D)
374#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D,val)
375#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C)
376#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C,val)
377#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S)
378#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S,val)
379#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T)
380#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T,val)
381#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR)
382#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR,val)
383#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR)
384#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR,val)
385#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE)
386#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE,val)
387#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH)
388#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH,val)
389#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN)
390#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN,val)
391/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
392#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D)
393#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D,val)
394#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C)
395#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C,val)
396#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S)
397#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S,val)
398#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T)
399#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T,val)
400#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D)
401#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D,val)
402#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C)
403#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C,val)
404#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S)
405#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S,val)
406#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T)
407#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T,val)
408#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D)
409#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D,val)
410#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C)
411#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C,val)
412#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S)
413#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S,val)
414#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T)
415#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T,val)
416#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR)
417#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR,val)
418#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR)
419#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR,val)
420#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE)
421#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE,val)
422#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH)
423#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH,val)
424#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN)
425#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN,val)
426/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
427#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D)
428#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D,val)
429#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C)
430#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C,val)
431#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S)
432#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S,val)
433#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T)
434#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T,val)
435#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D)
436#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D,val)
437#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C)
438#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C,val)
439#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S)
440#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S,val)
441#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T)
442#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T,val)
443#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D)
444#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D,val)
445#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C)
446#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C,val)
447#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S)
448#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S,val)
449#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T)
450#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T,val)
451#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR)
452#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR,val)
453#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR)
454#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR,val)
455#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE)
456#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE,val)
457#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH)
458#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH,val)
459#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN)
460#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN,val)
461/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
462#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
463#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
464#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
465#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
466#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
467#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
468#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
469#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
470#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
471#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
472#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
473#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
474#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
475#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
476#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
477#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
478#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
479#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
480#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
481#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
482#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
483#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
484#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
485#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
486#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
487#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
488#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
489#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
490#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
491#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
492#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
493#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
494#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
495#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
496#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
497#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
498#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
499#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
500#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
501#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
502#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
503#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
504#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
505#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
506#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
507#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
508#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
509#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
510#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
511#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
512#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
513#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
514/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
515#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
516#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
517#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
518#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
519#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
520#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
521#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
522#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
523#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
524#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
525#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
526#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
527#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
528#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
529#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
530#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
531#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
532#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
533#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
534#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
535#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
536#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
537#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
538#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
539#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
540#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
541#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
542#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
543#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
544#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
545#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
546#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
547#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
548#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
549#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
550#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
551#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
552#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
553#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
554#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
555#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
556#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
557#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
558#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
559#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
560#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
561#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
562#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
563#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
564#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
565#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
566#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
567/* Asynchronous Memory Controller - External Bus Interface Unit */
568#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
569#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
570#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
571#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
572#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
573#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
574/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
575#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
576#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
577#define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL)
578#define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val)
579#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
580#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
581#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
582#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
583/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
584#define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL)
585#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val)
586#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS)
587#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val)
588#define bfin_clear_PPI0_STATUS() bfin_read_PPI0_STATUS()
589#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT)
590#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val)
591#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY)
592#define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY,val)
593#define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME)
594#define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME,val)
595/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
596#define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL)
597#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val)
598#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS)
599#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val)
600#define bfin_clear_PPI1_STATUS() bfin_read_PPI1_STATUS()
601#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT)
602#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val)
603#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY)
604#define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY,val)
605#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME)
606#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val)
607/*DMA traffic control registers */
608#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER)
609#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER,val)
610#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT)
611#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT,val)
612#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER)
613#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER,val)
614#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT)
615#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT,val)
616/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
617#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG)
618#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val)
619#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_read32(DMA1_0_NEXT_DESC_PTR)
620#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_write32(DMA1_0_NEXT_DESC_PTR,val)
621#define bfin_read_DMA1_0_START_ADDR() bfin_read32(DMA1_0_START_ADDR)
622#define bfin_write_DMA1_0_START_ADDR(val) bfin_write32(DMA1_0_START_ADDR,val)
623#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT)
624#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT,val)
625#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT)
626#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT,val)
627#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY)
628#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY,val)
629#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY)
630#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY,val)
631#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_read32(DMA1_0_CURR_DESC_PTR)
632#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_write32(DMA1_0_CURR_DESC_PTR,val)
633#define bfin_read_DMA1_0_CURR_ADDR() bfin_read32(DMA1_0_CURR_ADDR)
634#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_write32(DMA1_0_CURR_ADDR,val)
635#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)
636#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT,val)
637#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)
638#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT,val)
639#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS)
640#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS,val)
641#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)
642#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP,val)
643#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG)
644#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG,val)
645#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_read32(DMA1_1_NEXT_DESC_PTR)
646#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_write32(DMA1_1_NEXT_DESC_PTR,val)
647#define bfin_read_DMA1_1_START_ADDR() bfin_read32(DMA1_1_START_ADDR)
648#define bfin_write_DMA1_1_START_ADDR(val) bfin_write32(DMA1_1_START_ADDR,val)
649#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT)
650#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT,val)
651#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT)
652#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT,val)
653#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY)
654#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY,val)
655#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY)
656#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY,val)
657#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_read32(DMA1_1_CURR_DESC_PTR)
658#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_write32(DMA1_1_CURR_DESC_PTR,val)
659#define bfin_read_DMA1_1_CURR_ADDR() bfin_read32(DMA1_1_CURR_ADDR)
660#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_write32(DMA1_1_CURR_ADDR,val)
661#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)
662#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT,val)
663#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)
664#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT,val)
665#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS)
666#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS,val)
667#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)
668#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP,val)
669#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG)
670#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG,val)
671#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_read32(DMA1_2_NEXT_DESC_PTR)
672#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_write32(DMA1_2_NEXT_DESC_PTR,val)
673#define bfin_read_DMA1_2_START_ADDR() bfin_read32(DMA1_2_START_ADDR)
674#define bfin_write_DMA1_2_START_ADDR(val) bfin_write32(DMA1_2_START_ADDR,val)
675#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT)
676#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT,val)
677#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT)
678#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT,val)
679#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY)
680#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY,val)
681#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY)
682#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY,val)
683#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_read32(DMA1_2_CURR_DESC_PTR)
684#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_write32(DMA1_2_CURR_DESC_PTR,val)
685#define bfin_read_DMA1_2_CURR_ADDR() bfin_read32(DMA1_2_CURR_ADDR)
686#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_write32(DMA1_2_CURR_ADDR,val)
687#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)
688#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT,val)
689#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)
690#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT,val)
691#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS)
692#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS,val)
693#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)
694#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP,val)
695#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG)
696#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG,val)
697#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_read32(DMA1_3_NEXT_DESC_PTR)
698#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_write32(DMA1_3_NEXT_DESC_PTR,val)
699#define bfin_read_DMA1_3_START_ADDR() bfin_read32(DMA1_3_START_ADDR)
700#define bfin_write_DMA1_3_START_ADDR(val) bfin_write32(DMA1_3_START_ADDR,val)
701#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT)
702#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT,val)
703#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT)
704#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT,val)
705#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY)
706#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY,val)
707#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY)
708#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY,val)
709#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_read32(DMA1_3_CURR_DESC_PTR)
710#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_write32(DMA1_3_CURR_DESC_PTR,val)
711#define bfin_read_DMA1_3_CURR_ADDR() bfin_read32(DMA1_3_CURR_ADDR)
712#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_write32(DMA1_3_CURR_ADDR,val)
713#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)
714#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT,val)
715#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)
716#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT,val)
717#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS)
718#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS,val)
719#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)
720#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP,val)
721#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG)
722#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG,val)
723#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_read32(DMA1_4_NEXT_DESC_PTR)
724#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_write32(DMA1_4_NEXT_DESC_PTR,val)
725#define bfin_read_DMA1_4_START_ADDR() bfin_read32(DMA1_4_START_ADDR)
726#define bfin_write_DMA1_4_START_ADDR(val) bfin_write32(DMA1_4_START_ADDR,val)
727#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT)
728#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT,val)
729#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT)
730#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT,val)
731#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY)
732#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY,val)
733#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY)
734#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY,val)
735#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_read32(DMA1_4_CURR_DESC_PTR)
736#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_write32(DMA1_4_CURR_DESC_PTR,val)
737#define bfin_read_DMA1_4_CURR_ADDR() bfin_read32(DMA1_4_CURR_ADDR)
738#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_write32(DMA1_4_CURR_ADDR,val)
739#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)
740#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT,val)
741#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)
742#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT,val)
743#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS)
744#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS,val)
745#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)
746#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP,val)
747#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG)
748#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG,val)
749#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_read32(DMA1_5_NEXT_DESC_PTR)
750#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_write32(DMA1_5_NEXT_DESC_PTR,val)
751#define bfin_read_DMA1_5_START_ADDR() bfin_read32(DMA1_5_START_ADDR)
752#define bfin_write_DMA1_5_START_ADDR(val) bfin_write32(DMA1_5_START_ADDR,val)
753#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT)
754#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT,val)
755#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT)
756#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT,val)
757#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY)
758#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY,val)
759#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY)
760#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY,val)
761#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_read32(DMA1_5_CURR_DESC_PTR)
762#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_write32(DMA1_5_CURR_DESC_PTR,val)
763#define bfin_read_DMA1_5_CURR_ADDR() bfin_read32(DMA1_5_CURR_ADDR)
764#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_write32(DMA1_5_CURR_ADDR,val)
765#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)
766#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT,val)
767#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)
768#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT,val)
769#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS)
770#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS,val)
771#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)
772#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP,val)
773#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG)
774#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG,val)
775#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_read32(DMA1_6_NEXT_DESC_PTR)
776#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_write32(DMA1_6_NEXT_DESC_PTR,val)
777#define bfin_read_DMA1_6_START_ADDR() bfin_read32(DMA1_6_START_ADDR)
778#define bfin_write_DMA1_6_START_ADDR(val) bfin_write32(DMA1_6_START_ADDR,val)
779#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT)
780#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT,val)
781#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT)
782#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT,val)
783#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY)
784#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY,val)
785#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY)
786#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY,val)
787#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_read32(DMA1_6_CURR_DESC_PTR)
788#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_write32(DMA1_6_CURR_DESC_PTR,val)
789#define bfin_read_DMA1_6_CURR_ADDR() bfin_read32(DMA1_6_CURR_ADDR)
790#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_write32(DMA1_6_CURR_ADDR,val)
791#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)
792#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT,val)
793#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)
794#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT,val)
795#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS)
796#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS,val)
797#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)
798#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP,val)
799#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG)
800#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG,val)
801#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_read32(DMA1_7_NEXT_DESC_PTR)
802#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_write32(DMA1_7_NEXT_DESC_PTR,val)
803#define bfin_read_DMA1_7_START_ADDR() bfin_read32(DMA1_7_START_ADDR)
804#define bfin_write_DMA1_7_START_ADDR(val) bfin_write32(DMA1_7_START_ADDR,val)
805#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT)
806#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT,val)
807#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT)
808#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT,val)
809#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY)
810#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY,val)
811#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY)
812#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY,val)
813#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_read32(DMA1_7_CURR_DESC_PTR)
814#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_write32(DMA1_7_CURR_DESC_PTR,val)
815#define bfin_read_DMA1_7_CURR_ADDR() bfin_read32(DMA1_7_CURR_ADDR)
816#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_write32(DMA1_7_CURR_ADDR,val)
817#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT)
818#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT,val)
819#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT)
820#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT,val)
821#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS)
822#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS,val)
823#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP)
824#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP,val)
825#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG)
826#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG,val)
827#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_read32(DMA1_8_NEXT_DESC_PTR)
828#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_write32(DMA1_8_NEXT_DESC_PTR,val)
829#define bfin_read_DMA1_8_START_ADDR() bfin_read32(DMA1_8_START_ADDR)
830#define bfin_write_DMA1_8_START_ADDR(val) bfin_write32(DMA1_8_START_ADDR,val)
831#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT)
832#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT,val)
833#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT)
834#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT,val)
835#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY)
836#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY,val)
837#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY)
838#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY,val)
839#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_read32(DMA1_8_CURR_DESC_PTR)
840#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_write32(DMA1_8_CURR_DESC_PTR,val)
841#define bfin_read_DMA1_8_CURR_ADDR() bfin_read32(DMA1_8_CURR_ADDR)
842#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_write32(DMA1_8_CURR_ADDR,val)
843#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT)
844#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT,val)
845#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT)
846#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT,val)
847#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS)
848#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS,val)
849#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP)
850#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP,val)
851#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG)
852#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG,val)
853#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_read32(DMA1_9_NEXT_DESC_PTR)
854#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_write32(DMA1_9_NEXT_DESC_PTR,val)
855#define bfin_read_DMA1_9_START_ADDR() bfin_read32(DMA1_9_START_ADDR)
856#define bfin_write_DMA1_9_START_ADDR(val) bfin_write32(DMA1_9_START_ADDR,val)
857#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT)
858#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT,val)
859#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT)
860#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT,val)
861#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY)
862#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY,val)
863#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY)
864#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY,val)
865#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_read32(DMA1_9_CURR_DESC_PTR)
866#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_write32(DMA1_9_CURR_DESC_PTR,val)
867#define bfin_read_DMA1_9_CURR_ADDR() bfin_read32(DMA1_9_CURR_ADDR)
868#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_write32(DMA1_9_CURR_ADDR,val)
869#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT)
870#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT,val)
871#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT)
872#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT,val)
873#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS)
874#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS,val)
875#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP)
876#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP,val)
877#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG)
878#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG,val)
879#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_read32(DMA1_10_NEXT_DESC_PTR)
880#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_write32(DMA1_10_NEXT_DESC_PTR,val)
881#define bfin_read_DMA1_10_START_ADDR() bfin_read32(DMA1_10_START_ADDR)
882#define bfin_write_DMA1_10_START_ADDR(val) bfin_write32(DMA1_10_START_ADDR,val)
883#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT)
884#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT,val)
885#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT)
886#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT,val)
887#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY)
888#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY,val)
889#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY)
890#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY,val)
891#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_read32(DMA1_10_CURR_DESC_PTR)
892#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_write32(DMA1_10_CURR_DESC_PTR,val)
893#define bfin_read_DMA1_10_CURR_ADDR() bfin_read32(DMA1_10_CURR_ADDR)
894#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_write32(DMA1_10_CURR_ADDR,val)
895#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT)
896#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT,val)
897#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT)
898#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT,val)
899#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS)
900#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS,val)
901#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP)
902#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP,val)
903#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG)
904#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG,val)
905#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_read32(DMA1_11_NEXT_DESC_PTR)
906#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_write32(DMA1_11_NEXT_DESC_PTR,val)
907#define bfin_read_DMA1_11_START_ADDR() bfin_read32(DMA1_11_START_ADDR)
908#define bfin_write_DMA1_11_START_ADDR(val) bfin_write32(DMA1_11_START_ADDR,val)
909#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT)
910#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT,val)
911#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT)
912#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT,val)
913#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY)
914#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY,val)
915#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY)
916#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY,val)
917#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_read32(DMA1_11_CURR_DESC_PTR)
918#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_write32(DMA1_11_CURR_DESC_PTR,val)
919#define bfin_read_DMA1_11_CURR_ADDR() bfin_read32(DMA1_11_CURR_ADDR)
920#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_write32(DMA1_11_CURR_ADDR,val)
921#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT)
922#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT,val)
923#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT)
924#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT,val)
925#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS)
926#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS,val)
927#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
928#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
929/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
930#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG)
931#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG,val)
932#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_read32(MDMA1_D0_NEXT_DESC_PTR)
933#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D0_NEXT_DESC_PTR,val)
934#define bfin_read_MDMA1_D0_START_ADDR() bfin_read32(MDMA1_D0_START_ADDR)
935#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_write32(MDMA1_D0_START_ADDR,val)
936#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT)
937#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT,val)
938#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT)
939#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT,val)
940#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY)
941#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY,val)
942#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY)
943#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY,val)
944#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_read32(MDMA1_D0_CURR_DESC_PTR)
945#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_write32(MDMA1_D0_CURR_DESC_PTR,val)
946#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_read32(MDMA1_D0_CURR_ADDR)
947#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_write32(MDMA1_D0_CURR_ADDR,val)
948#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
949#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT,val)
950#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
951#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT,val)
952#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
953#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS,val)
954#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
955#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP,val)
956#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG)
957#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG,val)
958#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_read32(MDMA1_S0_NEXT_DESC_PTR)
959#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S0_NEXT_DESC_PTR,val)
960#define bfin_read_MDMA1_S0_START_ADDR() bfin_read32(MDMA1_S0_START_ADDR)
961#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_write32(MDMA1_S0_START_ADDR,val)
962#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT)
963#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT,val)
964#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT)
965#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT,val)
966#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY)
967#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY,val)
968#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY)
969#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY,val)
970#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_read32(MDMA1_S0_CURR_DESC_PTR)
971#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_write32(MDMA1_S0_CURR_DESC_PTR,val)
972#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_read32(MDMA1_S0_CURR_ADDR)
973#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_write32(MDMA1_S0_CURR_ADDR,val)
974#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
975#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT,val)
976#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
977#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT,val)
978#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
979#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS,val)
980#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
981#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP,val)
982#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG)
983#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG,val)
984#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_read32(MDMA1_D1_NEXT_DESC_PTR)
985#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D1_NEXT_DESC_PTR,val)
986#define bfin_read_MDMA1_D1_START_ADDR() bfin_read32(MDMA1_D1_START_ADDR)
987#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_write32(MDMA1_D1_START_ADDR,val)
988#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT)
989#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT,val)
990#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT)
991#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT,val)
992#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY)
993#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY,val)
994#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY)
995#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY,val)
996#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_read32(MDMA1_D1_CURR_DESC_PTR)
997#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_write32(MDMA1_D1_CURR_DESC_PTR,val)
998#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_read32(MDMA1_D1_CURR_ADDR)
999#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_write32(MDMA1_D1_CURR_ADDR,val)
1000#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
1001#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT,val)
1002#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
1003#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT,val)
1004#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
1005#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS,val)
1006#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
1007#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP,val)
1008#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG)
1009#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG,val)
1010#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_read32(MDMA1_S1_NEXT_DESC_PTR)
1011#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S1_NEXT_DESC_PTR,val)
1012#define bfin_read_MDMA1_S1_START_ADDR() bfin_read32(MDMA1_S1_START_ADDR)
1013#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_write32(MDMA1_S1_START_ADDR,val)
1014#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT)
1015#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT,val)
1016#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT)
1017#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT,val)
1018#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY)
1019#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY,val)
1020#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY)
1021#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY,val)
1022#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_read32(MDMA1_S1_CURR_DESC_PTR)
1023#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_write32(MDMA1_S1_CURR_DESC_PTR,val)
1024#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_read32(MDMA1_S1_CURR_ADDR)
1025#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_write32(MDMA1_S1_CURR_ADDR,val)
1026#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
1027#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT,val)
1028#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
1029#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT,val)
1030#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
1031#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS,val)
1032#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
1033#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP,val)
1034/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
1035#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG)
1036#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val)
1037#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_read32(DMA2_0_NEXT_DESC_PTR)
1038#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_write32(DMA2_0_NEXT_DESC_PTR,val)
1039#define bfin_read_DMA2_0_START_ADDR() bfin_read32(DMA2_0_START_ADDR)
1040#define bfin_write_DMA2_0_START_ADDR(val) bfin_write32(DMA2_0_START_ADDR,val)
1041#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT)
1042#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT,val)
1043#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT)
1044#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT,val)
1045#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY)
1046#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY,val)
1047#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY)
1048#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY,val)
1049#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_read32(DMA2_0_CURR_DESC_PTR)
1050#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_write32(DMA2_0_CURR_DESC_PTR,val)
1051#define bfin_read_DMA2_0_CURR_ADDR() bfin_read32(DMA2_0_CURR_ADDR)
1052#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_write32(DMA2_0_CURR_ADDR,val)
1053#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT)
1054#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT,val)
1055#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT)
1056#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT,val)
1057#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS)
1058#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS,val)
1059#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP)
1060#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP,val)
1061#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG)
1062#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG,val)
1063#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_read32(DMA2_1_NEXT_DESC_PTR)
1064#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_write32(DMA2_1_NEXT_DESC_PTR,val)
1065#define bfin_read_DMA2_1_START_ADDR() bfin_read32(DMA2_1_START_ADDR)
1066#define bfin_write_DMA2_1_START_ADDR(val) bfin_write32(DMA2_1_START_ADDR,val)
1067#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT)
1068#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT,val)
1069#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT)
1070#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT,val)
1071#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY)
1072#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY,val)
1073#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY)
1074#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY,val)
1075#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_read32(DMA2_1_CURR_DESC_PTR)
1076#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_write32(DMA2_1_CURR_DESC_PTR,val)
1077#define bfin_read_DMA2_1_CURR_ADDR() bfin_read32(DMA2_1_CURR_ADDR)
1078#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_write32(DMA2_1_CURR_ADDR,val)
1079#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT)
1080#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT,val)
1081#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT)
1082#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT,val)
1083#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS)
1084#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS,val)
1085#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP)
1086#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP,val)
1087#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG)
1088#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG,val)
1089#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_read32(DMA2_2_NEXT_DESC_PTR)
1090#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_write32(DMA2_2_NEXT_DESC_PTR,val)
1091#define bfin_read_DMA2_2_START_ADDR() bfin_read32(DMA2_2_START_ADDR)
1092#define bfin_write_DMA2_2_START_ADDR(val) bfin_write32(DMA2_2_START_ADDR,val)
1093#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT)
1094#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT,val)
1095#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT)
1096#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT,val)
1097#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY)
1098#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY,val)
1099#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY)
1100#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY,val)
1101#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_read32(DMA2_2_CURR_DESC_PTR)
1102#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_write32(DMA2_2_CURR_DESC_PTR,val)
1103#define bfin_read_DMA2_2_CURR_ADDR() bfin_read32(DMA2_2_CURR_ADDR)
1104#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_write32(DMA2_2_CURR_ADDR,val)
1105#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT)
1106#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT,val)
1107#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT)
1108#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT,val)
1109#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS)
1110#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS,val)
1111#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP)
1112#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP,val)
1113#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG)
1114#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG,val)
1115#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_read32(DMA2_3_NEXT_DESC_PTR)
1116#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_write32(DMA2_3_NEXT_DESC_PTR,val)
1117#define bfin_read_DMA2_3_START_ADDR() bfin_read32(DMA2_3_START_ADDR)
1118#define bfin_write_DMA2_3_START_ADDR(val) bfin_write32(DMA2_3_START_ADDR,val)
1119#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT)
1120#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT,val)
1121#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT)
1122#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT,val)
1123#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY)
1124#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY,val)
1125#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY)
1126#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY,val)
1127#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_read32(DMA2_3_CURR_DESC_PTR)
1128#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_write32(DMA2_3_CURR_DESC_PTR,val)
1129#define bfin_read_DMA2_3_CURR_ADDR() bfin_read32(DMA2_3_CURR_ADDR)
1130#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_write32(DMA2_3_CURR_ADDR,val)
1131#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT)
1132#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT,val)
1133#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT)
1134#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT,val)
1135#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS)
1136#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS,val)
1137#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP)
1138#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP,val)
1139#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG)
1140#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG,val)
1141#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_read32(DMA2_4_NEXT_DESC_PTR)
1142#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_write32(DMA2_4_NEXT_DESC_PTR,val)
1143#define bfin_read_DMA2_4_START_ADDR() bfin_read32(DMA2_4_START_ADDR)
1144#define bfin_write_DMA2_4_START_ADDR(val) bfin_write32(DMA2_4_START_ADDR,val)
1145#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT)
1146#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT,val)
1147#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT)
1148#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT,val)
1149#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY)
1150#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY,val)
1151#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY)
1152#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY,val)
1153#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_read32(DMA2_4_CURR_DESC_PTR)
1154#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_write32(DMA2_4_CURR_DESC_PTR,val)
1155#define bfin_read_DMA2_4_CURR_ADDR() bfin_read32(DMA2_4_CURR_ADDR)
1156#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_write32(DMA2_4_CURR_ADDR,val)
1157#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT)
1158#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT,val)
1159#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT)
1160#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT,val)
1161#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS)
1162#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS,val)
1163#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP)
1164#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP,val)
1165#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG)
1166#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG,val)
1167#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_read32(DMA2_5_NEXT_DESC_PTR)
1168#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_write32(DMA2_5_NEXT_DESC_PTR,val)
1169#define bfin_read_DMA2_5_START_ADDR() bfin_read32(DMA2_5_START_ADDR)
1170#define bfin_write_DMA2_5_START_ADDR(val) bfin_write32(DMA2_5_START_ADDR,val)
1171#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT)
1172#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT,val)
1173#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT)
1174#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT,val)
1175#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY)
1176#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY,val)
1177#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY)
1178#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY,val)
1179#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_read32(DMA2_5_CURR_DESC_PTR)
1180#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_write32(DMA2_5_CURR_DESC_PTR,val)
1181#define bfin_read_DMA2_5_CURR_ADDR() bfin_read32(DMA2_5_CURR_ADDR)
1182#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_write32(DMA2_5_CURR_ADDR,val)
1183#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT)
1184#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT,val)
1185#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT)
1186#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT,val)
1187#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS)
1188#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS,val)
1189#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP)
1190#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP,val)
1191#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG)
1192#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG,val)
1193#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_read32(DMA2_6_NEXT_DESC_PTR)
1194#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_write32(DMA2_6_NEXT_DESC_PTR,val)
1195#define bfin_read_DMA2_6_START_ADDR() bfin_read32(DMA2_6_START_ADDR)
1196#define bfin_write_DMA2_6_START_ADDR(val) bfin_write32(DMA2_6_START_ADDR,val)
1197#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT)
1198#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT,val)
1199#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT)
1200#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT,val)
1201#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY)
1202#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY,val)
1203#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY)
1204#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY,val)
1205#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_read32(DMA2_6_CURR_DESC_PTR)
1206#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_write32(DMA2_6_CURR_DESC_PTR,val)
1207#define bfin_read_DMA2_6_CURR_ADDR() bfin_read32(DMA2_6_CURR_ADDR)
1208#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_write32(DMA2_6_CURR_ADDR,val)
1209#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT)
1210#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT,val)
1211#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT)
1212#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT,val)
1213#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS)
1214#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS,val)
1215#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP)
1216#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP,val)
1217#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG)
1218#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG,val)
1219#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_read32(DMA2_7_NEXT_DESC_PTR)
1220#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_write32(DMA2_7_NEXT_DESC_PTR,val)
1221#define bfin_read_DMA2_7_START_ADDR() bfin_read32(DMA2_7_START_ADDR)
1222#define bfin_write_DMA2_7_START_ADDR(val) bfin_write32(DMA2_7_START_ADDR,val)
1223#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT)
1224#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT,val)
1225#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT)
1226#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT,val)
1227#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY)
1228#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY,val)
1229#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY)
1230#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY,val)
1231#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_read32(DMA2_7_CURR_DESC_PTR)
1232#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_write32(DMA2_7_CURR_DESC_PTR,val)
1233#define bfin_read_DMA2_7_CURR_ADDR() bfin_read32(DMA2_7_CURR_ADDR)
1234#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_write32(DMA2_7_CURR_ADDR,val)
1235#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT)
1236#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT,val)
1237#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT)
1238#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT,val)
1239#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS)
1240#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS,val)
1241#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP)
1242#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP,val)
1243#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG)
1244#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG,val)
1245#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_read32(DMA2_8_NEXT_DESC_PTR)
1246#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_write32(DMA2_8_NEXT_DESC_PTR,val)
1247#define bfin_read_DMA2_8_START_ADDR() bfin_read32(DMA2_8_START_ADDR)
1248#define bfin_write_DMA2_8_START_ADDR(val) bfin_write32(DMA2_8_START_ADDR,val)
1249#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT)
1250#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT,val)
1251#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT)
1252#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT,val)
1253#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY)
1254#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY,val)
1255#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY)
1256#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY,val)
1257#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_read32(DMA2_8_CURR_DESC_PTR)
1258#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_write32(DMA2_8_CURR_DESC_PTR,val)
1259#define bfin_read_DMA2_8_CURR_ADDR() bfin_read32(DMA2_8_CURR_ADDR)
1260#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_write32(DMA2_8_CURR_ADDR,val)
1261#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT)
1262#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT,val)
1263#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT)
1264#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT,val)
1265#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS)
1266#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS,val)
1267#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP)
1268#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP,val)
1269#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG)
1270#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG,val)
1271#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_read32(DMA2_9_NEXT_DESC_PTR)
1272#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_write32(DMA2_9_NEXT_DESC_PTR,val)
1273#define bfin_read_DMA2_9_START_ADDR() bfin_read32(DMA2_9_START_ADDR)
1274#define bfin_write_DMA2_9_START_ADDR(val) bfin_write32(DMA2_9_START_ADDR,val)
1275#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT)
1276#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT,val)
1277#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT)
1278#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT,val)
1279#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY)
1280#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY,val)
1281#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY)
1282#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY,val)
1283#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_read32(DMA2_9_CURR_DESC_PTR)
1284#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_write32(DMA2_9_CURR_DESC_PTR,val)
1285#define bfin_read_DMA2_9_CURR_ADDR() bfin_read32(DMA2_9_CURR_ADDR)
1286#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_write32(DMA2_9_CURR_ADDR,val)
1287#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT)
1288#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT,val)
1289#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT)
1290#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT,val)
1291#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS)
1292#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS,val)
1293#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP)
1294#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP,val)
1295#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG)
1296#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG,val)
1297#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_read32(DMA2_10_NEXT_DESC_PTR)
1298#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_write32(DMA2_10_NEXT_DESC_PTR,val)
1299#define bfin_read_DMA2_10_START_ADDR() bfin_read32(DMA2_10_START_ADDR)
1300#define bfin_write_DMA2_10_START_ADDR(val) bfin_write32(DMA2_10_START_ADDR,val)
1301#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT)
1302#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT,val)
1303#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT)
1304#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT,val)
1305#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY)
1306#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY,val)
1307#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY)
1308#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY,val)
1309#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_read32(DMA2_10_CURR_DESC_PTR)
1310#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_write32(DMA2_10_CURR_DESC_PTR,val)
1311#define bfin_read_DMA2_10_CURR_ADDR() bfin_read32(DMA2_10_CURR_ADDR)
1312#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_write32(DMA2_10_CURR_ADDR,val)
1313#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT)
1314#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT,val)
1315#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT)
1316#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT,val)
1317#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS)
1318#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS,val)
1319#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP)
1320#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP,val)
1321#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG)
1322#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG,val)
1323#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_read32(DMA2_11_NEXT_DESC_PTR)
1324#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_write32(DMA2_11_NEXT_DESC_PTR,val)
1325#define bfin_read_DMA2_11_START_ADDR() bfin_read32(DMA2_11_START_ADDR)
1326#define bfin_write_DMA2_11_START_ADDR(val) bfin_write32(DMA2_11_START_ADDR,val)
1327#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT)
1328#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT,val)
1329#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT)
1330#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT,val)
1331#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY)
1332#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY,val)
1333#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY)
1334#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY,val)
1335#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_read32(DMA2_11_CURR_DESC_PTR)
1336#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_write32(DMA2_11_CURR_DESC_PTR,val)
1337#define bfin_read_DMA2_11_CURR_ADDR() bfin_read32(DMA2_11_CURR_ADDR)
1338#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_write32(DMA2_11_CURR_ADDR,val)
1339#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT)
1340#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT,val)
1341#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT)
1342#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT,val)
1343#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS)
1344#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS,val)
1345#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
1346#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
1347/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
1348#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG)
1349#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG,val)
1350#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_read32(MDMA2_D0_NEXT_DESC_PTR)
1351#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D0_NEXT_DESC_PTR,val)
1352#define bfin_read_MDMA2_D0_START_ADDR() bfin_read32(MDMA2_D0_START_ADDR)
1353#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_write32(MDMA2_D0_START_ADDR,val)
1354#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT)
1355#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT,val)
1356#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT)
1357#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT,val)
1358#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY)
1359#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY,val)
1360#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY)
1361#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY,val)
1362#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_read32(MDMA2_D0_CURR_DESC_PTR)
1363#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_write32(MDMA2_D0_CURR_DESC_PTR,val)
1364#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_read32(MDMA2_D0_CURR_ADDR)
1365#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_write32(MDMA2_D0_CURR_ADDR,val)
1366#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT)
1367#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT,val)
1368#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT)
1369#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT,val)
1370#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS)
1371#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS,val)
1372#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
1373#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP,val)
1374#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG)
1375#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG,val)
1376#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_read32(MDMA2_S0_NEXT_DESC_PTR)
1377#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S0_NEXT_DESC_PTR,val)
1378#define bfin_read_MDMA2_S0_START_ADDR() bfin_read32(MDMA2_S0_START_ADDR)
1379#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_write32(MDMA2_S0_START_ADDR,val)
1380#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT)
1381#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT,val)
1382#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT)
1383#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT,val)
1384#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY)
1385#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY,val)
1386#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY)
1387#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY,val)
1388#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_read32(MDMA2_S0_CURR_DESC_PTR)
1389#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_write32(MDMA2_S0_CURR_DESC_PTR,val)
1390#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_read32(MDMA2_S0_CURR_ADDR)
1391#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_write32(MDMA2_S0_CURR_ADDR,val)
1392#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT)
1393#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT,val)
1394#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT)
1395#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT,val)
1396#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS)
1397#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS,val)
1398#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
1399#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP,val)
1400#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG)
1401#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG,val)
1402#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_read32(MDMA2_D1_NEXT_DESC_PTR)
1403#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D1_NEXT_DESC_PTR,val)
1404#define bfin_read_MDMA2_D1_START_ADDR() bfin_read32(MDMA2_D1_START_ADDR)
1405#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_write32(MDMA2_D1_START_ADDR,val)
1406#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT)
1407#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT,val)
1408#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT)
1409#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT,val)
1410#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY)
1411#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY,val)
1412#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY)
1413#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY,val)
1414#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_read32(MDMA2_D1_CURR_DESC_PTR)
1415#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_write32(MDMA2_D1_CURR_DESC_PTR,val)
1416#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_read32(MDMA2_D1_CURR_ADDR)
1417#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_write32(MDMA2_D1_CURR_ADDR,val)
1418#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT)
1419#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT,val)
1420#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT)
1421#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT,val)
1422#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS)
1423#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS,val)
1424#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
1425#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP,val)
1426#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG)
1427#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG,val)
1428#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_read32(MDMA2_S1_NEXT_DESC_PTR)
1429#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S1_NEXT_DESC_PTR,val)
1430#define bfin_read_MDMA2_S1_START_ADDR() bfin_read32(MDMA2_S1_START_ADDR)
1431#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_write32(MDMA2_S1_START_ADDR,val)
1432#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT)
1433#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT,val)
1434#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT)
1435#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT,val)
1436#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY)
1437#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY,val)
1438#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY)
1439#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY,val)
1440#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_read32(MDMA2_S1_CURR_DESC_PTR)
1441#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_write32(MDMA2_S1_CURR_DESC_PTR,val)
1442#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_read32(MDMA2_S1_CURR_ADDR)
1443#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_write32(MDMA2_S1_CURR_ADDR,val)
1444#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT)
1445#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT,val)
1446#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT)
1447#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT,val)
1448#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS)
1449#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS,val)
1450#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
1451#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP,val)
1452/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
1453#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG)
1454#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val)
1455#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_read32(IMDMA_D0_NEXT_DESC_PTR)
1456#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D0_NEXT_DESC_PTR,val)
1457#define bfin_read_IMDMA_D0_START_ADDR() bfin_read32(IMDMA_D0_START_ADDR)
1458#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_write32(IMDMA_D0_START_ADDR,val)
1459#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT)
1460#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT,val)
1461#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT)
1462#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT,val)
1463#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY)
1464#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY,val)
1465#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY)
1466#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY,val)
1467#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_read32(IMDMA_D0_CURR_DESC_PTR)
1468#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_write32(IMDMA_D0_CURR_DESC_PTR,val)
1469#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_read32(IMDMA_D0_CURR_ADDR)
1470#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_write32(IMDMA_D0_CURR_ADDR,val)
1471#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT)
1472#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT,val)
1473#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT)
1474#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT,val)
1475#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS)
1476#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS,val)
1477#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG)
1478#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG,val)
1479#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_read32(IMDMA_S0_NEXT_DESC_PTR)
1480#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S0_NEXT_DESC_PTR,val)
1481#define bfin_read_IMDMA_S0_START_ADDR() bfin_read32(IMDMA_S0_START_ADDR)
1482#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_write32(IMDMA_S0_START_ADDR,val)
1483#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT)
1484#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT,val)
1485#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT)
1486#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT,val)
1487#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY)
1488#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY,val)
1489#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY)
1490#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY,val)
1491#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_read32(IMDMA_S0_CURR_DESC_PTR)
1492#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_write32(IMDMA_S0_CURR_DESC_PTR,val)
1493#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_read32(IMDMA_S0_CURR_ADDR)
1494#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_write32(IMDMA_S0_CURR_ADDR,val)
1495#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT)
1496#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT,val)
1497#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT)
1498#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT,val)
1499#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS)
1500#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS,val)
1501#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG)
1502#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG,val)
1503#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_read32(IMDMA_D1_NEXT_DESC_PTR)
1504#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D1_NEXT_DESC_PTR,val)
1505#define bfin_read_IMDMA_D1_START_ADDR() bfin_read32(IMDMA_D1_START_ADDR)
1506#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_write32(IMDMA_D1_START_ADDR,val)
1507#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT)
1508#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT,val)
1509#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT)
1510#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT,val)
1511#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY)
1512#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY,val)
1513#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY)
1514#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY,val)
1515#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_read32(IMDMA_D1_CURR_DESC_PTR)
1516#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_write32(IMDMA_D1_CURR_DESC_PTR,val)
1517#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_read32(IMDMA_D1_CURR_ADDR)
1518#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_write32(IMDMA_D1_CURR_ADDR,val)
1519#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT)
1520#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT,val)
1521#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT)
1522#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT,val)
1523#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS)
1524#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS,val)
1525#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG)
1526#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG,val)
1527#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_read32(IMDMA_S1_NEXT_DESC_PTR)
1528#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S1_NEXT_DESC_PTR,val)
1529#define bfin_read_IMDMA_S1_START_ADDR() bfin_read32(IMDMA_S1_START_ADDR)
1530#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_write32(IMDMA_S1_START_ADDR,val)
1531#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT)
1532#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT,val)
1533#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT)
1534#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT,val)
1535#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY)
1536#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY,val)
1537#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY)
1538#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY,val)
1539#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_read32(IMDMA_S1_CURR_DESC_PTR)
1540#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_write32(IMDMA_S1_CURR_DESC_PTR,val)
1541#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_read32(IMDMA_S1_CURR_ADDR)
1542#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_write32(IMDMA_S1_CURR_ADDR,val)
1543#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT)
1544#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT,val)
1545#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT)
1546#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT,val)
1547#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
1548#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val)
1549
1550#define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA1_S0_CONFIG()
1551#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA1_S0_CONFIG(val)
1552#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA1_S0_IRQ_STATUS()
1553#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA1_S0_IRQ_STATUS(val)
1554#define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA1_S0_X_MODIFY()
1555#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA1_S0_X_MODIFY(val)
1556#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA1_S0_Y_MODIFY()
1557#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA1_S0_Y_MODIFY(val)
1558#define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA1_S0_X_COUNT()
1559#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA1_S0_X_COUNT(val)
1560#define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA1_S0_Y_COUNT()
1561#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA1_S0_Y_COUNT(val)
1562#define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA1_S0_START_ADDR()
1563#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA1_S0_START_ADDR(val)
1564#define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA1_D0_CONFIG()
1565#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA1_D0_CONFIG(val)
1566#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA1_D0_IRQ_STATUS()
1567#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA1_D0_IRQ_STATUS(val)
1568#define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA1_D0_X_MODIFY()
1569#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA1_D0_X_MODIFY(val)
1570#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA1_D0_Y_MODIFY()
1571#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA1_D0_Y_MODIFY(val)
1572#define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA1_D0_X_COUNT()
1573#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA1_D0_X_COUNT(val)
1574#define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA1_D0_Y_COUNT()
1575#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA1_D0_Y_COUNT(val)
1576#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR()
1577#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
1578
1579#endif /* _CDEF_BF561_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 00:23:29 -0500