diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf561/cdefBF561.h')
-rw-r--r-- | include/asm-blackfin/mach-bf561/cdefBF561.h | 34 |
1 files changed, 30 insertions, 4 deletions
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h index 1bc8d2f89ccc..b07ffccd66dd 100644 --- a/include/asm-blackfin/mach-bf561/cdefBF561.h +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h | |||
@@ -47,7 +47,30 @@ | |||
47 | 47 | ||
48 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | 48 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ |
49 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | 49 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) |
50 | #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) | 50 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ |
51 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
52 | { | ||
53 | unsigned long flags, iwr0, iwr1; | ||
54 | |||
55 | if (val == bfin_read_PLL_CTL()) | ||
56 | return; | ||
57 | |||
58 | local_irq_save(flags); | ||
59 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
60 | iwr0 = bfin_read32(SICA_IWR0); | ||
61 | iwr1 = bfin_read32(SICA_IWR1); | ||
62 | /* Only allow PPL Wakeup) */ | ||
63 | bfin_write32(SICA_IWR0, IWR_ENABLE(0)); | ||
64 | bfin_write32(SICA_IWR1, 0); | ||
65 | |||
66 | bfin_write16(PLL_CTL, val); | ||
67 | SSYNC(); | ||
68 | asm("IDLE;"); | ||
69 | |||
70 | bfin_write32(SICA_IWR0, iwr0); | ||
71 | bfin_write32(SICA_IWR1, iwr1); | ||
72 | local_irq_restore(flags); | ||
73 | } | ||
51 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) | 74 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) |
52 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) | 75 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) |
53 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | 76 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) |
@@ -56,6 +79,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
56 | { | 79 | { |
57 | unsigned long flags, iwr0, iwr1; | 80 | unsigned long flags, iwr0, iwr1; |
58 | 81 | ||
82 | if (val == bfin_read_VR_CTL()) | ||
83 | return; | ||
84 | |||
85 | local_irq_save(flags); | ||
59 | /* Enable the PLL Wakeup bit in SIC IWR */ | 86 | /* Enable the PLL Wakeup bit in SIC IWR */ |
60 | iwr0 = bfin_read32(SICA_IWR0); | 87 | iwr0 = bfin_read32(SICA_IWR0); |
61 | iwr1 = bfin_read32(SICA_IWR1); | 88 | iwr1 = bfin_read32(SICA_IWR1); |
@@ -65,12 +92,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
65 | 92 | ||
66 | bfin_write16(VR_CTL, val); | 93 | bfin_write16(VR_CTL, val); |
67 | SSYNC(); | 94 | SSYNC(); |
68 | |||
69 | local_irq_save(flags); | ||
70 | asm("IDLE;"); | 95 | asm("IDLE;"); |
71 | local_irq_restore(flags); | 96 | |
72 | bfin_write32(SICA_IWR0, iwr0); | 97 | bfin_write32(SICA_IWR0, iwr0); |
73 | bfin_write32(SICA_IWR1, iwr1); | 98 | bfin_write32(SICA_IWR1, iwr1); |
99 | local_irq_restore(flags); | ||
74 | } | 100 | } |
75 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) | 101 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) |
76 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) | 102 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) |