diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf561/cdefBF561.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf561/cdefBF561.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h index 1a8ec9e46922..6e87ab269ffe 100644 --- a/include/asm-blackfin/mach-bf561/cdefBF561.h +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h | |||
| @@ -81,6 +81,12 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 81 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) | 81 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) |
| 82 | #define bfin_read_CHIPID() bfin_read32(CHIPID) | 82 | #define bfin_read_CHIPID() bfin_read32(CHIPID) |
| 83 | 83 | ||
| 84 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ | ||
| 85 | #define bfin_read_SWRST() bfin_read_SICA_SWRST() | ||
| 86 | #define bfin_write_SWRST() bfin_write_SICA_SWRST() | ||
| 87 | #define bfin_read_SYSCR() bfin_read_SICA_SYSCR() | ||
| 88 | #define bfin_write_SYSCR() bfin_write_SICA_SYSCR() | ||
| 89 | |||
| 84 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ | 90 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ |
| 85 | #define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) | 91 | #define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) |
| 86 | #define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) | 92 | #define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) |