aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-blackfin/mach-bf561/blackfin.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-blackfin/mach-bf561/blackfin.h')
-rw-r--r--include/asm-blackfin/mach-bf561/blackfin.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h
index 3a16df2c86d8..0ea8666e6764 100644
--- a/include/asm-blackfin/mach-bf561/blackfin.h
+++ b/include/asm-blackfin/mach-bf561/blackfin.h
@@ -69,5 +69,19 @@
69#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) 69#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
70#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) 70#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
71 71
72#define BFIN_UART_NR_PORTS 1
73
74#define OFFSET_THR 0x00 /* Transmit Holding register */
75#define OFFSET_RBR 0x00 /* Receive Buffer register */
76#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
77#define OFFSET_IER 0x04 /* Interrupt Enable Register */
78#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
79#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
80#define OFFSET_LCR 0x0C /* Line Control Register */
81#define OFFSET_MCR 0x10 /* Modem Control Register */
82#define OFFSET_LSR 0x14 /* Line Status Register */
83#define OFFSET_MSR 0x18 /* Modem Status Register */
84#define OFFSET_SCR 0x1C /* SCR Scratch Register */
85#define OFFSET_GCTL 0x24 /* Global Control Register */
72 86
73#endif /* _MACH_BLACKFIN_H_ */ 87#endif /* _MACH_BLACKFIN_H_ */