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-rw-r--r--include/asm-blackfin/mach-bf561/bf561.h223
1 files changed, 0 insertions, 223 deletions
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
deleted file mode 100644
index 3ef9e5f36136..000000000000
--- a/include/asm-blackfin/mach-bf561/bf561.h
+++ /dev/null
@@ -1,223 +0,0 @@
1/*
2 * File: include/asm-blackfin/mach-bf561/bf561.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF561_H__
31#define __MACH_BF561_H__
32
33#define SUPPORTED_REVID 0x3
34
35#define OFFSET_(x) ((x) & 0x0000FFFF)
36
37/*some misc defines*/
38#define IMASK_IVG15 0x8000
39#define IMASK_IVG14 0x4000
40#define IMASK_IVG13 0x2000
41#define IMASK_IVG12 0x1000
42
43#define IMASK_IVG11 0x0800
44#define IMASK_IVG10 0x0400
45#define IMASK_IVG9 0x0200
46#define IMASK_IVG8 0x0100
47
48#define IMASK_IVG7 0x0080
49#define IMASK_IVGTMR 0x0040
50#define IMASK_IVGHW 0x0020
51
52/***************************
53 * Blackfin Cache setup
54 */
55
56
57#define BFIN_ISUBBANKS 4
58#define BFIN_IWAYS 4
59#define BFIN_ILINES 32
60
61#define BFIN_DSUBBANKS 4
62#define BFIN_DWAYS 2
63#define BFIN_DLINES 64
64
65#define WAY0_L 0x1
66#define WAY1_L 0x2
67#define WAY01_L 0x3
68#define WAY2_L 0x4
69#define WAY02_L 0x5
70#define WAY12_L 0x6
71#define WAY012_L 0x7
72
73#define WAY3_L 0x8
74#define WAY03_L 0x9
75#define WAY13_L 0xA
76#define WAY013_L 0xB
77
78#define WAY32_L 0xC
79#define WAY320_L 0xD
80#define WAY321_L 0xE
81#define WAYALL_L 0xF
82
83#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
84
85/* IAR0 BIT FIELDS */
86#define PLL_WAKEUP_BIT 0xFFFFFFFF
87#define DMA1_ERROR_BIT 0xFFFFFF0F
88#define DMA2_ERROR_BIT 0xFFFFF0FF
89#define IMDMA_ERROR_BIT 0xFFFF0FFF
90#define PPI1_ERROR_BIT 0xFFF0FFFF
91#define PPI2_ERROR_BIT 0xFF0FFFFF
92#define SPORT0_ERROR_BIT 0xF0FFFFFF
93#define SPORT1_ERROR_BIT 0x0FFFFFFF
94/* IAR1 BIT FIELDS */
95#define SPI_ERROR_BIT 0xFFFFFFFF
96#define UART_ERROR_BIT 0xFFFFFF0F
97#define RESERVED_ERROR_BIT 0xFFFFF0FF
98#define DMA1_0_BIT 0xFFFF0FFF
99#define DMA1_1_BIT 0xFFF0FFFF
100#define DMA1_2_BIT 0xFF0FFFFF
101#define DMA1_3_BIT 0xF0FFFFFF
102#define DMA1_4_BIT 0x0FFFFFFF
103/* IAR2 BIT FIELDS */
104#define DMA1_5_BIT 0xFFFFFFFF
105#define DMA1_6_BIT 0xFFFFFF0F
106#define DMA1_7_BIT 0xFFFFF0FF
107#define DMA1_8_BIT 0xFFFF0FFF
108#define DMA1_9_BIT 0xFFF0FFFF
109#define DMA1_10_BIT 0xFF0FFFFF
110#define DMA1_11_BIT 0xF0FFFFFF
111#define DMA2_0_BIT 0x0FFFFFFF
112/* IAR3 BIT FIELDS */
113#define DMA2_1_BIT 0xFFFFFFFF
114#define DMA2_2_BIT 0xFFFFFF0F
115#define DMA2_3_BIT 0xFFFFF0FF
116#define DMA2_4_BIT 0xFFFF0FFF
117#define DMA2_5_BIT 0xFFF0FFFF
118#define DMA2_6_BIT 0xFF0FFFFF
119#define DMA2_7_BIT 0xF0FFFFFF
120#define DMA2_8_BIT 0x0FFFFFFF
121/* IAR4 BIT FIELDS */
122#define DMA2_9_BIT 0xFFFFFFFF
123#define DMA2_10_BIT 0xFFFFFF0F
124#define DMA2_11_BIT 0xFFFFF0FF
125#define TIMER0_BIT 0xFFFF0FFF
126#define TIMER1_BIT 0xFFF0FFFF
127#define TIMER2_BIT 0xFF0FFFFF
128#define TIMER3_BIT 0xF0FFFFFF
129#define TIMER4_BIT 0x0FFFFFFF
130/* IAR5 BIT FIELDS */
131#define TIMER5_BIT 0xFFFFFFFF
132#define TIMER6_BIT 0xFFFFFF0F
133#define TIMER7_BIT 0xFFFFF0FF
134#define TIMER8_BIT 0xFFFF0FFF
135#define TIMER9_BIT 0xFFF0FFFF
136#define TIMER10_BIT 0xFF0FFFFF
137#define TIMER11_BIT 0xF0FFFFFF
138#define PROG0_INTA_BIT 0x0FFFFFFF
139/* IAR6 BIT FIELDS */
140#define PROG0_INTB_BIT 0xFFFFFFFF
141#define PROG1_INTA_BIT 0xFFFFFF0F
142#define PROG1_INTB_BIT 0xFFFFF0FF
143#define PROG2_INTA_BIT 0xFFFF0FFF
144#define PROG2_INTB_BIT 0xFFF0FFFF
145#define DMA1_WRRD0_BIT 0xFF0FFFFF
146#define DMA1_WRRD1_BIT 0xF0FFFFFF
147#define DMA2_WRRD0_BIT 0x0FFFFFFF
148/* IAR7 BIT FIELDS */
149#define DMA2_WRRD1_BIT 0xFFFFFFFF
150#define IMDMA_WRRD0_BIT 0xFFFFFF0F
151#define IMDMA_WRRD1_BIT 0xFFFFF0FF
152#define WATCH_BIT 0xFFFF0FFF
153#define RESERVED_1_BIT 0xFFF0FFFF
154#define RESERVED_2_BIT 0xFF0FFFFF
155#define SUPPLE_0_BIT 0xF0FFFFFF
156#define SUPPLE_1_BIT 0x0FFFFFFF
157
158/* Miscellaneous Values */
159
160/****************************** EBIU Settings ********************************/
161#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
162#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
163
164#if defined(CONFIG_C_AMBEN_ALL)
165#define V_AMBEN AMBEN_ALL
166#elif defined(CONFIG_C_AMBEN)
167#define V_AMBEN 0x0
168#elif defined(CONFIG_C_AMBEN_B0)
169#define V_AMBEN AMBEN_B0
170#elif defined(CONFIG_C_AMBEN_B0_B1)
171#define V_AMBEN AMBEN_B0_B1
172#elif defined(CONFIG_C_AMBEN_B0_B1_B2)
173#define V_AMBEN AMBEN_B0_B1_B2
174#endif
175
176#ifdef CONFIG_C_AMCKEN
177#define V_AMCKEN AMCKEN
178#else
179#define V_AMCKEN 0x0
180#endif
181
182#ifdef CONFIG_C_B0PEN
183#define V_B0PEN 0x10
184#else
185#define V_B0PEN 0x00
186#endif
187
188#ifdef CONFIG_C_B1PEN
189#define V_B1PEN 0x20
190#else
191#define V_B1PEN 0x00
192#endif
193
194#ifdef CONFIG_C_B2PEN
195#define V_B2PEN 0x40
196#else
197#define V_B2PEN 0x00
198#endif
199
200#ifdef CONFIG_C_B3PEN
201#define V_B3PEN 0x80
202#else
203#define V_B3PEN 0x00
204#endif
205
206#ifdef CONFIG_C_CDPRIO
207#define V_CDPRIO 0x100
208#else
209#define V_CDPRIO 0x0
210#endif
211
212#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
213
214#ifdef CONFIG_BF561
215#define CPU "BF561"
216#define CPUID 0x027bb000
217#endif
218#ifndef CPU
219#define CPU "UNKNOWN"
220#define CPUID 0x0
221#endif
222
223#endif /* __MACH_BF561_H__ */
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