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Diffstat (limited to 'include/asm-blackfin/mach-bf561/bf561.h')
-rw-r--r--include/asm-blackfin/mach-bf561/bf561.h178
1 files changed, 6 insertions, 172 deletions
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
index 96a5d3a47e45..17e1d5dcef02 100644
--- a/include/asm-blackfin/mach-bf561/bf561.h
+++ b/include/asm-blackfin/mach-bf561/bf561.h
@@ -73,13 +73,13 @@
73 */ 73 */
74 74
75 75
76#define BLKFIN_ISUBBANKS 4 76#define BFIN_ISUBBANKS 4
77#define BLKFIN_IWAYS 4 77#define BFIN_IWAYS 4
78#define BLKFIN_ILINES 32 78#define BFIN_ILINES 32
79 79
80#define BLKFIN_DSUBBANKS 4 80#define BFIN_DSUBBANKS 4
81#define BLKFIN_DWAYS 2 81#define BFIN_DWAYS 2
82#define BLKFIN_DLINES 64 82#define BFIN_DLINES 64
83 83
84#define WAY0_L 0x1 84#define WAY0_L 0x1
85#define WAY1_L 0x2 85#define WAY1_L 0x2
@@ -230,93 +230,6 @@
230 230
231#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002) 231#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
232 232
233#define MAX_VC 600000000
234#define MIN_VC 50000000
235
236/******************************* PLL Settings ********************************/
237#ifdef CONFIG_BFIN_KERNEL_CLOCK
238#if (CONFIG_VCO_MULT < 0)
239#error "VCO Multiplier is less than 0. Please select a different value"
240#endif
241
242#if (CONFIG_VCO_MULT == 0)
243#error "VCO Multiplier should be greater than 0. Please select a different value"
244#endif
245
246#ifndef CONFIG_CLKIN_HALF
247#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
248#else
249#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
250#endif
251
252#ifndef CONFIG_PLL_BYPASS
253#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
254#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
255#else
256#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
257#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
258#endif
259
260#if (CONFIG_SCLK_DIV < 1)
261#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
262#endif
263
264#if (CONFIG_SCLK_DIV > 15)
265#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
266#endif
267
268#if (CONFIG_CCLK_DIV != 1)
269#if (CONFIG_CCLK_DIV != 2)
270#if (CONFIG_CCLK_DIV != 4)
271#if (CONFIG_CCLK_DIV != 8)
272#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
273#endif
274#endif
275#endif
276#endif
277
278#if (CONFIG_VCO_HZ > MAX_VC)
279#error "VCO selected is more than maximum value. Please change the VCO multipler"
280#endif
281
282#if (CONFIG_SCLK_HZ > 133000000)
283#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
284#endif
285
286#if (CONFIG_SCLK_HZ < 27000000)
287#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
288#endif
289
290#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
291#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
292#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
293#error "Please select sclk less than cclk"
294#endif
295#endif
296#endif
297
298#if (CONFIG_CCLK_DIV == 1)
299#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
300#endif
301#if (CONFIG_CCLK_DIV == 2)
302#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
303#endif
304#if (CONFIG_CCLK_DIV == 4)
305#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
306#endif
307#if (CONFIG_CCLK_DIV == 8)
308#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
309#endif
310#ifndef CONFIG_CCLK_ACT_DIV
311#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
312#endif
313
314#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1)
315#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
316#endif
317
318#endif /* CONFIG_BFIN_KERNEL_CLOCK */
319
320#ifdef CONFIG_BF561 233#ifdef CONFIG_BF561
321#define CPU "BF561" 234#define CPU "BF561"
322#define CPUID 0x027bb000 235#define CPUID 0x027bb000
@@ -326,83 +239,4 @@
326#define CPUID 0x0 239#define CPUID 0x0
327#endif 240#endif
328 241
329#if (CONFIG_MEM_SIZE % 4)
330#error "SDRAM memory size must be a multiple of 4MB!"
331#endif
332#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
333#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
334#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
335#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
336
337/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
338
339#define ANOMALY_05000158_WORKAROUND 0x200
340#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
341#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
342 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
343#else /*Write Through */
344#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \
345 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
346#endif
347
348
349#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
350#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
351#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
352#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
353
354#define L2_MEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
355
356#define SIZE_1K 0x00000400 /* 1K */
357#define SIZE_4K 0x00001000 /* 4K */
358#define SIZE_1M 0x00100000 /* 1M */
359#define SIZE_4M 0x00400000 /* 4M */
360
361#define MAX_CPLBS (16 * 2)
362
363/*
364* Number of required data CPLB switchtable entries
365* MEMSIZE / 4 (we mostly install 4M page size CPLBs
366* approx 16 for smaller 1MB page size CPLBs for allignment purposes
367* 1 for L1 Data Memory
368* 1 for L2 Data Memory
369* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
370* 64 for ASYNC Memory
371*/
372
373
374#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 + 64) * 2)
375
376/*
377* Number of required instruction CPLB switchtable entries
378* MEMSIZE / 4 (we mostly install 4M page size CPLBs
379* approx 12 for smaller 1MB page size CPLBs for allignment purposes
380* 1 for L1 Instruction Memory
381* 1 for L2 Instruction Memory
382* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
383*/
384
385#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
386
387#if 0 /* comment by mhfan */
388/* Event Vector Table Address */
389#define EVT_EMULATION_ADDR 0xffe02000
390#define EVT_RESET_ADDR 0xffe02004
391#define EVT_NMI_ADDR 0xffe02008
392#define EVT_EXCEPTION_ADDR 0xffe0200c
393#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
394#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
395#define EVT_TIMER_ADDR 0xffe02018
396#define EVT_IVG7_ADDR 0xffe0201c
397#define EVT_IVG8_ADDR 0xffe02020
398#define EVT_IVG9_ADDR 0xffe02024
399#define EVT_IVG10_ADDR 0xffe02028
400#define EVT_IVG11_ADDR 0xffe0202c
401#define EVT_IVG12_ADDR 0xffe02030
402#define EVT_IVG13_ADDR 0xffe02034
403#define EVT_IVG14_ADDR 0xffe02038
404#define EVT_IVG15_ADDR 0xffe0203c
405#define EVT_OVERRIDE_ADDR 0xffe02100
406#endif /* comment by mhfan */
407
408#endif /* __MACH_BF561_H__ */ 242#endif /* __MACH_BF561_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-05 22:04:42 -0500