aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-blackfin/mach-bf548/mem_map.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-blackfin/mach-bf548/mem_map.h')
-rw-r--r--include/asm-blackfin/mach-bf548/mem_map.h24
1 files changed, 12 insertions, 12 deletions
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h
index 72d80e8a6e81..ec1597e31831 100644
--- a/include/asm-blackfin/mach-bf548/mem_map.h
+++ b/include/asm-blackfin/mach-bf548/mem_map.h
@@ -51,10 +51,10 @@
51/* Level 1 Memory */ 51/* Level 1 Memory */
52 52
53/* Memory Map for ADSP-BF548 processors */ 53/* Memory Map for ADSP-BF548 processors */
54#ifdef CONFIG_BLKFIN_ICACHE 54#ifdef CONFIG_BFIN_ICACHE
55#define BLKFIN_ICACHESIZE (16*1024) 55#define BFIN_ICACHESIZE (16*1024)
56#else 56#else
57#define BLKFIN_ICACHESIZE (0*1024) 57#define BFIN_ICACHESIZE (0*1024)
58#endif 58#endif
59 59
60#define L1_CODE_START 0xFFA00000 60#define L1_CODE_START 0xFFA00000
@@ -63,29 +63,29 @@
63 63
64#define L1_CODE_LENGTH 0xC000 64#define L1_CODE_LENGTH 0xC000
65 65
66#ifdef CONFIG_BLKFIN_DCACHE 66#ifdef CONFIG_BFIN_DCACHE
67 67
68#ifdef CONFIG_BLKFIN_DCACHE_BANKA 68#ifdef CONFIG_BFIN_DCACHE_BANKA
69#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 69#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
70#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 70#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
71#define L1_DATA_B_LENGTH 0x8000 71#define L1_DATA_B_LENGTH 0x8000
72#define BLKFIN_DCACHESIZE (16*1024) 72#define BFIN_DCACHESIZE (16*1024)
73#define BLKFIN_DSUPBANKS 1 73#define BFIN_DSUPBANKS 1
74#else 74#else
75#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 75#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
76#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 76#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
77#define L1_DATA_B_LENGTH (0x8000 - 0x4000) 77#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
78#define BLKFIN_DCACHESIZE (32*1024) 78#define BFIN_DCACHESIZE (32*1024)
79#define BLKFIN_DSUPBANKS 2 79#define BFIN_DSUPBANKS 2
80#endif 80#endif
81 81
82#else 82#else
83#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 83#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
84#define L1_DATA_A_LENGTH 0x8000 84#define L1_DATA_A_LENGTH 0x8000
85#define L1_DATA_B_LENGTH 0x8000 85#define L1_DATA_B_LENGTH 0x8000
86#define BLKFIN_DCACHESIZE (0*1024) 86#define BFIN_DCACHESIZE (0*1024)
87#define BLKFIN_DSUPBANKS 0 87#define BFIN_DSUPBANKS 0
88#endif /*CONFIG_BLKFIN_DCACHE*/ 88#endif /*CONFIG_BFIN_DCACHE*/
89 89
90/* Scratch Pad Memory */ 90/* Scratch Pad Memory */
91 91