diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf548/irq.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf548/irq.h | 174 |
1 files changed, 123 insertions, 51 deletions
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index a7f6703ea1dd..93f5db0f4657 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h | |||
| @@ -51,7 +51,7 @@ Events (highest priority) EMU 0 | |||
| 51 | (lowest priority) IVG15 32 * | 51 | (lowest priority) IVG15 32 * |
| 52 | */ | 52 | */ |
| 53 | 53 | ||
| 54 | #define NR_PERI_INTS 32 | 54 | #define NR_PERI_INTS (32 * 3) |
| 55 | 55 | ||
| 56 | /* The ABSTRACT IRQ definitions */ | 56 | /* The ABSTRACT IRQ definitions */ |
| 57 | /** the first seven of the following are fixed, the rest you change if you need to **/ | 57 | /** the first seven of the following are fixed, the rest you change if you need to **/ |
| @@ -92,7 +92,7 @@ Events (highest priority) EMU 0 | |||
| 92 | #define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ | 92 | #define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ |
| 93 | #define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ | 93 | #define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ |
| 94 | #define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ | 94 | #define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ |
| 95 | #define IRQ_MXVR BFIN_IRQ(27) /* SPORT3 Error Interrupt */ | 95 | #define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */ |
| 96 | #define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ | 96 | #define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ |
| 97 | #define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ | 97 | #define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ |
| 98 | #define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ | 98 | #define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ |
| @@ -102,8 +102,8 @@ Events (highest priority) EMU 0 | |||
| 102 | #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ | 102 | #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ |
| 103 | #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ | 103 | #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ |
| 104 | #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ | 104 | #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ |
| 105 | #define IRQ_EPP1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ | 105 | #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ |
| 106 | #define IRQ_EPP2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ | 106 | #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ |
| 107 | #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ | 107 | #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ |
| 108 | #define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ | 108 | #define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ |
| 109 | #define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ | 109 | #define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ |
| @@ -143,14 +143,14 @@ Events (highest priority) EMU 0 | |||
| 143 | #define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ | 143 | #define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ |
| 144 | #define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ | 144 | #define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ |
| 145 | #define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ | 145 | #define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ |
| 146 | #define IRQ_TMR0 BFIN_IRQ(86) /* Timer 0 Interrupt */ | 146 | #define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */ |
| 147 | #define IRQ_TMR1 BFIN_IRQ(87) /* Timer 1 Interrupt */ | 147 | #define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */ |
| 148 | #define IRQ_TMR2 BFIN_IRQ(88) /* Timer 2 Interrupt */ | 148 | #define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */ |
| 149 | #define IRQ_TMR3 BFIN_IRQ(89) /* Timer 3 Interrupt */ | 149 | #define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */ |
| 150 | #define IRQ_TMR4 BFIN_IRQ(90) /* Timer 4 Interrupt */ | 150 | #define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */ |
| 151 | #define IRQ_TMR5 BFIN_IRQ(91) /* Timer 5 Interrupt */ | 151 | #define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */ |
| 152 | #define IRQ_TMR6 BFIN_IRQ(92) /* Timer 6 Interrupt */ | 152 | #define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */ |
| 153 | #define IRQ_TMR7 BFIN_IRQ(93) /* Timer 7 Interrupt */ | 153 | #define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */ |
| 154 | #define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ | 154 | #define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ |
| 155 | #define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ | 155 | #define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ |
| 156 | 156 | ||
| @@ -248,9 +248,9 @@ Events (highest priority) EMU 0 | |||
| 248 | 248 | ||
| 249 | 249 | ||
| 250 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO | 250 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO |
| 251 | #define NR_IRQS (IRQ_PH15+1) | 251 | #define NR_IRQS (IRQ_PE15+1) |
| 252 | #else | 252 | #else |
| 253 | #define NR_IRQS (IRQ_UART1_ERROR+1) | 253 | #define NR_IRQS (SYS_IRQS+1) |
| 254 | #endif | 254 | #endif |
| 255 | 255 | ||
| 256 | #define IVG7 7 | 256 | #define IVG7 7 |
| @@ -263,44 +263,116 @@ Events (highest priority) EMU 0 | |||
| 263 | #define IVG14 14 | 263 | #define IVG14 14 |
| 264 | #define IVG15 15 | 264 | #define IVG15 15 |
| 265 | 265 | ||
| 266 | /* IAR0 BIT FIELDS*/ | 266 | /* IAR0 BIT FIELDS */ |
| 267 | #define IRQ_PLL_WAKEUP_POS 0 | 267 | #define IRQ_PLL_WAKEUP_POS 0 |
| 268 | #define IRQ_DMA_ERROR_POS 4 | 268 | #define IRQ_DMAC0_ERR_POS 4 |
| 269 | #define IRQ_ERROR_POS 8 | 269 | #define IRQ_EPPI0_ERR_POS 8 |
| 270 | #define IRQ_RTC_POS 12 | 270 | #define IRQ_SPORT0_ERR_POS 12 |
| 271 | #define IRQ_PPI_POS 16 | 271 | #define IRQ_SPORT1_ERR_POS 16 |
| 272 | #define IRQ_SPORT0_RX_POS 20 | 272 | #define IRQ_SPI0_ERR_POS 20 |
| 273 | #define IRQ_SPORT0_TX_POS 24 | 273 | #define IRQ_UART0_ERR_POS 24 |
| 274 | #define IRQ_SPORT1_RX_POS 28 | 274 | #define IRQ_RTC_POS 28 |
| 275 | 275 | ||
| 276 | /* IAR1 BIT FIELDS*/ | 276 | /* IAR1 BIT FIELDS */ |
| 277 | #define IRQ_SPORT1_TX_POS 0 | 277 | #define IRQ_EPPI0_POS 0 |
| 278 | #define IRQ_TWI_POS 4 | 278 | #define IRQ_SPORT0_RX_POS 4 |
| 279 | #define IRQ_SPI_POS 8 | 279 | #define IRQ_SPORT0_TX_POS 8 |
| 280 | #define IRQ_UART0_RX_POS 12 | 280 | #define IRQ_SPORT1_RX_POS 12 |
| 281 | #define IRQ_UART0_TX_POS 16 | 281 | #define IRQ_SPORT1_TX_POS 16 |
| 282 | #define IRQ_UART1_RX_POS 20 | 282 | #define IRQ_SPI0_POS 20 |
| 283 | #define IRQ_UART1_TX_POS 24 | 283 | #define IRQ_UART0_RX_POS 24 |
| 284 | #define IRQ_CAN_RX_POS 28 | 284 | #define IRQ_UART0_TX_POS 28 |
| 285 | 285 | ||
| 286 | /* IAR2 BIT FIELDS*/ | 286 | /* IAR2 BIT FIELDS */ |
| 287 | #define IRQ_CAN_TX_POS 0 | 287 | #define IRQ_TIMER8_POS 0 |
| 288 | #define IRQ_MAC_RX_POS 4 | 288 | #define IRQ_TIMER9_POS 4 |
| 289 | #define IRQ_MAC_TX_POS 8 | 289 | #define IRQ_TIMER10_POS 8 |
| 290 | #define IRQ_TMR0_POS 12 | 290 | #define IRQ_PINT0_POS 12 |
| 291 | #define IRQ_TMR1_POS 16 | 291 | #define IRQ_PINT1_POS 16 |
| 292 | #define IRQ_TMR2_POS 20 | 292 | #define IRQ_MDMAS0_POS 20 |
| 293 | #define IRQ_TMR3_POS 24 | 293 | #define IRQ_MDMAS1_POS 24 |
| 294 | #define IRQ_TMR4_POS 28 | 294 | #define IRQ_WATCHDOG_POS 28 |
| 295 | 295 | ||
| 296 | /* IAR3 BIT FIELDS*/ | 296 | /* IAR3 BIT FIELDS */ |
| 297 | #define IRQ_TMR5_POS 0 | 297 | #define IRQ_DMAC1_ERR_POS 0 |
| 298 | #define IRQ_TMR6_POS 4 | 298 | #define IRQ_SPORT2_ERR_POS 4 |
| 299 | #define IRQ_TMR7_POS 8 | 299 | #define IRQ_SPORT3_ERR_POS 8 |
| 300 | #define IRQ_PROG_INTA_POS 12 | 300 | #define IRQ_MXVR_DATA_POS 12 |
| 301 | #define IRQ_PORTG_INTB_POS 16 | 301 | #define IRQ_SPI1_ERR_POS 16 |
| 302 | #define IRQ_MEM_DMA0_POS 20 | 302 | #define IRQ_SPI2_ERR_POS 20 |
| 303 | #define IRQ_MEM_DMA1_POS 24 | 303 | #define IRQ_UART1_ERR_POS 24 |
| 304 | #define IRQ_WATCH_POS 28 | 304 | #define IRQ_UART2_ERR_POS 28 |
| 305 | 305 | ||
| 306 | #endif /* _BF537_IRQ_H_ */ | 306 | /* IAR4 BIT FILEDS */ |
| 307 | #define IRQ_CAN0_ERR_POS 0 | ||
| 308 | #define IRQ_SPORT2_RX_POS 4 | ||
| 309 | #define IRQ_SPORT2_TX_POS 8 | ||
| 310 | #define IRQ_SPORT3_RX_POS 12 | ||
| 311 | #define IRQ_SPORT3_TX_POS 16 | ||
| 312 | #define IRQ_EPPI1_POS 20 | ||
| 313 | #define IRQ_EPPI2_POS 24 | ||
| 314 | #define IRQ_SPI1_POS 28 | ||
| 315 | |||
| 316 | /* IAR5 BIT FIELDS */ | ||
| 317 | #define IRQ_SPI2_POS 0 | ||
| 318 | #define IRQ_UART1_RX_POS 4 | ||
| 319 | #define IRQ_UART1_TX_POS 8 | ||
| 320 | #define IRQ_ATAPI_RX_POS 12 | ||
| 321 | #define IRQ_ATAPI_TX_POS 16 | ||
| 322 | #define IRQ_TWI0_POS 20 | ||
| 323 | #define IRQ_TWI1_POS 24 | ||
| 324 | #define IRQ_CAN0_RX_POS 28 | ||
| 325 | |||
| 326 | /* IAR6 BIT FIELDS */ | ||
| 327 | #define IRQ_CAN0_TX_POS 0 | ||
| 328 | #define IRQ_MDMAS2_POS 4 | ||
| 329 | #define IRQ_MDMAS3_POS 8 | ||
| 330 | #define IRQ_MXVR_ERR_POS 12 | ||
| 331 | #define IRQ_MXVR_MSG_POS 16 | ||
| 332 | #define IRQ_MXVR_PKT_POS 20 | ||
| 333 | #define IRQ_EPPI1_ERR_POS 24 | ||
| 334 | #define IRQ_EPPI2_ERR_POS 28 | ||
| 335 | |||
| 336 | /* IAR7 BIT FIELDS */ | ||
| 337 | #define IRQ_UART3_ERR_POS 0 | ||
| 338 | #define IRQ_HOST_ERR_POS 4 | ||
| 339 | #define IRQ_PIXC_ERR_POS 12 | ||
| 340 | #define IRQ_NFC_ERR_POS 16 | ||
| 341 | #define IRQ_ATAPI_ERR_POS 20 | ||
| 342 | #define IRQ_CAN1_ERR_POS 24 | ||
| 343 | #define IRQ_HS_DMA_ERR_POS 28 | ||
| 344 | |||
| 345 | /* IAR8 BIT FIELDS */ | ||
| 346 | #define IRQ_PIXC_IN0_POS 0 | ||
| 347 | #define IRQ_PIXC_IN1_POS 4 | ||
| 348 | #define IRQ_PIXC_OUT_POS 8 | ||
| 349 | #define IRQ_SDH_POS 12 | ||
| 350 | #define IRQ_CNT_POS 16 | ||
| 351 | #define IRQ_KEY_POS 20 | ||
| 352 | #define IRQ_CAN1_RX_POS 24 | ||
| 353 | #define IRQ_CAN1_TX_POS 28 | ||
| 354 | |||
| 355 | /* IAR9 BIT FIELDS */ | ||
| 356 | #define IRQ_SDH_MASK0_POS 0 | ||
| 357 | #define IRQ_SDH_MASK1_POS 4 | ||
| 358 | #define IRQ_USB_INT0_POS 12 | ||
| 359 | #define IRQ_USB_INT1_POS 16 | ||
| 360 | #define IRQ_USB_INT2_POS 20 | ||
| 361 | #define IRQ_USB_DMA_POS 24 | ||
| 362 | #define IRQ_OTPSEC_POS 28 | ||
| 363 | |||
| 364 | /* IAR10 BIT FIELDS */ | ||
| 365 | #define IRQ_TIMER0_POS 24 | ||
| 366 | #define IRQ_TIMER1_POS 28 | ||
| 367 | |||
| 368 | /* IAR11 BIT FIELDS */ | ||
| 369 | #define IRQ_TIMER2_POS 0 | ||
| 370 | #define IRQ_TIMER3_POS 4 | ||
| 371 | #define IRQ_TIMER4_POS 8 | ||
| 372 | #define IRQ_TIMER5_POS 12 | ||
| 373 | #define IRQ_TIMER6_POS 16 | ||
| 374 | #define IRQ_TIMER7_POS 20 | ||
| 375 | #define IRQ_PINT2_POS 24 | ||
| 376 | #define IRQ_PINT3_POS 28 | ||
| 377 | |||
| 378 | #endif /* _BF548_IRQ_H_ */ | ||