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-rw-r--r--include/asm-blackfin/mach-bf548/irq.h501
1 files changed, 0 insertions, 501 deletions
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
deleted file mode 100644
index ad380d1f5872..000000000000
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ /dev/null
@@ -1,501 +0,0 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/irq.h
3 * based on: include/asm-blackfin/mach-bf537/irq.h
4 * author: Roy Huang (roy.huang@analog.com)
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _BF548_IRQ_H_
33#define _BF548_IRQ_H_
34
35/*
36 * Interrupt source definitions
37 Event Source Core Event Name
38Core Emulation **
39Events (highest priority) EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47.....
48
49 Software Interrupt 1 IVG14 31
50 Software Interrupt 2 --
51 (lowest priority) IVG15 32 *
52 */
53
54#define NR_PERI_INTS (32 * 3)
55
56/* The ABSTRACT IRQ definitions */
57/** the first seven of the following are fixed, the rest you change if you need to **/
58#define IRQ_EMU 0 /* Emulation */
59#define IRQ_RST 1 /* reset */
60#define IRQ_NMI 2 /* Non Maskable */
61#define IRQ_EVX 3 /* Exception */
62#define IRQ_UNUSED 4 /* - unused interrupt*/
63#define IRQ_HWERR 5 /* Hardware Error */
64#define IRQ_CORETMR 6 /* Core timer */
65
66#define BFIN_IRQ(x) ((x) + 7)
67
68#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
69#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
70#define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */
71#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
72#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
73#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */
74#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */
75#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
76#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */
77#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */
78#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */
79#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */
80#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */
81#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */
82#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */
83#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */
84#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */
85#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */
86#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */
87#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */
88#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
89#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
90#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
91#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
92#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
93#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
94#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
95#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */
96#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */
97#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */
98#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */
99#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
100#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
101#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
102#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
103#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
104#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
105#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
106#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
107#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
108#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
109#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
110#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
111#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
112#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
113#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */
114#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */
115#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */
116#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */
117#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */
118#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
119#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */
120#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */
121#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */
122#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */
123#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */
124#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */
125#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */
126#define IRQ_EPP1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */
127#define IRQ_EPP2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */
128#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */
129#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */
130#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */
131#define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */
132#define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */
133#define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */
134#define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */
135#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */
136#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */
137#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */
138#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */
139#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */
140#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */
141#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */
142#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */
143#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */
144#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */
145#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */
146#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */
147#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */
148#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */
149#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */
150#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */
151#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */
152#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */
153#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */
154#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */
155#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */
156#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */
157#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */
158#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
159#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
160
161#define SYS_IRQS IRQ_PINT3
162
163#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
164#define IRQ_PA0 BFIN_PA_IRQ(0)
165#define IRQ_PA1 BFIN_PA_IRQ(1)
166#define IRQ_PA2 BFIN_PA_IRQ(2)
167#define IRQ_PA3 BFIN_PA_IRQ(3)
168#define IRQ_PA4 BFIN_PA_IRQ(4)
169#define IRQ_PA5 BFIN_PA_IRQ(5)
170#define IRQ_PA6 BFIN_PA_IRQ(6)
171#define IRQ_PA7 BFIN_PA_IRQ(7)
172#define IRQ_PA8 BFIN_PA_IRQ(8)
173#define IRQ_PA9 BFIN_PA_IRQ(9)
174#define IRQ_PA10 BFIN_PA_IRQ(10)
175#define IRQ_PA11 BFIN_PA_IRQ(11)
176#define IRQ_PA12 BFIN_PA_IRQ(12)
177#define IRQ_PA13 BFIN_PA_IRQ(13)
178#define IRQ_PA14 BFIN_PA_IRQ(14)
179#define IRQ_PA15 BFIN_PA_IRQ(15)
180
181#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
182#define IRQ_PB0 BFIN_PB_IRQ(0)
183#define IRQ_PB1 BFIN_PB_IRQ(1)
184#define IRQ_PB2 BFIN_PB_IRQ(2)
185#define IRQ_PB3 BFIN_PB_IRQ(3)
186#define IRQ_PB4 BFIN_PB_IRQ(4)
187#define IRQ_PB5 BFIN_PB_IRQ(5)
188#define IRQ_PB6 BFIN_PB_IRQ(6)
189#define IRQ_PB7 BFIN_PB_IRQ(7)
190#define IRQ_PB8 BFIN_PB_IRQ(8)
191#define IRQ_PB9 BFIN_PB_IRQ(9)
192#define IRQ_PB10 BFIN_PB_IRQ(10)
193#define IRQ_PB11 BFIN_PB_IRQ(11)
194#define IRQ_PB12 BFIN_PB_IRQ(12)
195#define IRQ_PB13 BFIN_PB_IRQ(13)
196#define IRQ_PB14 BFIN_PB_IRQ(14)
197#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
198
199#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
200#define IRQ_PC0 BFIN_PC_IRQ(0)
201#define IRQ_PC1 BFIN_PC_IRQ(1)
202#define IRQ_PC2 BFIN_PC_IRQ(2)
203#define IRQ_PC3 BFIN_PC_IRQ(3)
204#define IRQ_PC4 BFIN_PC_IRQ(4)
205#define IRQ_PC5 BFIN_PC_IRQ(5)
206#define IRQ_PC6 BFIN_PC_IRQ(6)
207#define IRQ_PC7 BFIN_PC_IRQ(7)
208#define IRQ_PC8 BFIN_PC_IRQ(8)
209#define IRQ_PC9 BFIN_PC_IRQ(9)
210#define IRQ_PC10 BFIN_PC_IRQ(10)
211#define IRQ_PC11 BFIN_PC_IRQ(11)
212#define IRQ_PC12 BFIN_PC_IRQ(12)
213#define IRQ_PC13 BFIN_PC_IRQ(13)
214#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
215#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
216
217#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
218#define IRQ_PD0 BFIN_PD_IRQ(0)
219#define IRQ_PD1 BFIN_PD_IRQ(1)
220#define IRQ_PD2 BFIN_PD_IRQ(2)
221#define IRQ_PD3 BFIN_PD_IRQ(3)
222#define IRQ_PD4 BFIN_PD_IRQ(4)
223#define IRQ_PD5 BFIN_PD_IRQ(5)
224#define IRQ_PD6 BFIN_PD_IRQ(6)
225#define IRQ_PD7 BFIN_PD_IRQ(7)
226#define IRQ_PD8 BFIN_PD_IRQ(8)
227#define IRQ_PD9 BFIN_PD_IRQ(9)
228#define IRQ_PD10 BFIN_PD_IRQ(10)
229#define IRQ_PD11 BFIN_PD_IRQ(11)
230#define IRQ_PD12 BFIN_PD_IRQ(12)
231#define IRQ_PD13 BFIN_PD_IRQ(13)
232#define IRQ_PD14 BFIN_PD_IRQ(14)
233#define IRQ_PD15 BFIN_PD_IRQ(15)
234
235#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
236#define IRQ_PE0 BFIN_PE_IRQ(0)
237#define IRQ_PE1 BFIN_PE_IRQ(1)
238#define IRQ_PE2 BFIN_PE_IRQ(2)
239#define IRQ_PE3 BFIN_PE_IRQ(3)
240#define IRQ_PE4 BFIN_PE_IRQ(4)
241#define IRQ_PE5 BFIN_PE_IRQ(5)
242#define IRQ_PE6 BFIN_PE_IRQ(6)
243#define IRQ_PE7 BFIN_PE_IRQ(7)
244#define IRQ_PE8 BFIN_PE_IRQ(8)
245#define IRQ_PE9 BFIN_PE_IRQ(9)
246#define IRQ_PE10 BFIN_PE_IRQ(10)
247#define IRQ_PE11 BFIN_PE_IRQ(11)
248#define IRQ_PE12 BFIN_PE_IRQ(12)
249#define IRQ_PE13 BFIN_PE_IRQ(13)
250#define IRQ_PE14 BFIN_PE_IRQ(14)
251#define IRQ_PE15 BFIN_PE_IRQ(15)
252
253#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
254#define IRQ_PF0 BFIN_PF_IRQ(0)
255#define IRQ_PF1 BFIN_PF_IRQ(1)
256#define IRQ_PF2 BFIN_PF_IRQ(2)
257#define IRQ_PF3 BFIN_PF_IRQ(3)
258#define IRQ_PF4 BFIN_PF_IRQ(4)
259#define IRQ_PF5 BFIN_PF_IRQ(5)
260#define IRQ_PF6 BFIN_PF_IRQ(6)
261#define IRQ_PF7 BFIN_PF_IRQ(7)
262#define IRQ_PF8 BFIN_PF_IRQ(8)
263#define IRQ_PF9 BFIN_PF_IRQ(9)
264#define IRQ_PF10 BFIN_PF_IRQ(10)
265#define IRQ_PF11 BFIN_PF_IRQ(11)
266#define IRQ_PF12 BFIN_PF_IRQ(12)
267#define IRQ_PF13 BFIN_PF_IRQ(13)
268#define IRQ_PF14 BFIN_PF_IRQ(14)
269#define IRQ_PF15 BFIN_PF_IRQ(15)
270
271#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
272#define IRQ_PG0 BFIN_PG_IRQ(0)
273#define IRQ_PG1 BFIN_PG_IRQ(1)
274#define IRQ_PG2 BFIN_PG_IRQ(2)
275#define IRQ_PG3 BFIN_PG_IRQ(3)
276#define IRQ_PG4 BFIN_PG_IRQ(4)
277#define IRQ_PG5 BFIN_PG_IRQ(5)
278#define IRQ_PG6 BFIN_PG_IRQ(6)
279#define IRQ_PG7 BFIN_PG_IRQ(7)
280#define IRQ_PG8 BFIN_PG_IRQ(8)
281#define IRQ_PG9 BFIN_PG_IRQ(9)
282#define IRQ_PG10 BFIN_PG_IRQ(10)
283#define IRQ_PG11 BFIN_PG_IRQ(11)
284#define IRQ_PG12 BFIN_PG_IRQ(12)
285#define IRQ_PG13 BFIN_PG_IRQ(13)
286#define IRQ_PG14 BFIN_PG_IRQ(14)
287#define IRQ_PG15 BFIN_PG_IRQ(15)
288
289#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1)
290#define IRQ_PH0 BFIN_PH_IRQ(0)
291#define IRQ_PH1 BFIN_PH_IRQ(1)
292#define IRQ_PH2 BFIN_PH_IRQ(2)
293#define IRQ_PH3 BFIN_PH_IRQ(3)
294#define IRQ_PH4 BFIN_PH_IRQ(4)
295#define IRQ_PH5 BFIN_PH_IRQ(5)
296#define IRQ_PH6 BFIN_PH_IRQ(6)
297#define IRQ_PH7 BFIN_PH_IRQ(7)
298#define IRQ_PH8 BFIN_PH_IRQ(8)
299#define IRQ_PH9 BFIN_PH_IRQ(9)
300#define IRQ_PH10 BFIN_PH_IRQ(10)
301#define IRQ_PH11 BFIN_PH_IRQ(11)
302#define IRQ_PH12 BFIN_PH_IRQ(12)
303#define IRQ_PH13 BFIN_PH_IRQ(13)
304#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */
305#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */
306
307#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1)
308#define IRQ_PI0 BFIN_PI_IRQ(0)
309#define IRQ_PI1 BFIN_PI_IRQ(1)
310#define IRQ_PI2 BFIN_PI_IRQ(2)
311#define IRQ_PI3 BFIN_PI_IRQ(3)
312#define IRQ_PI4 BFIN_PI_IRQ(4)
313#define IRQ_PI5 BFIN_PI_IRQ(5)
314#define IRQ_PI6 BFIN_PI_IRQ(6)
315#define IRQ_PI7 BFIN_PI_IRQ(7)
316#define IRQ_PI8 BFIN_PI_IRQ(8)
317#define IRQ_PI9 BFIN_PI_IRQ(9)
318#define IRQ_PI10 BFIN_PI_IRQ(10)
319#define IRQ_PI11 BFIN_PI_IRQ(11)
320#define IRQ_PI12 BFIN_PI_IRQ(12)
321#define IRQ_PI13 BFIN_PI_IRQ(13)
322#define IRQ_PI14 BFIN_PI_IRQ(14)
323#define IRQ_PI15 BFIN_PI_IRQ(15)
324
325#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1)
326#define IRQ_PJ0 BFIN_PJ_IRQ(0)
327#define IRQ_PJ1 BFIN_PJ_IRQ(1)
328#define IRQ_PJ2 BFIN_PJ_IRQ(2)
329#define IRQ_PJ3 BFIN_PJ_IRQ(3)
330#define IRQ_PJ4 BFIN_PJ_IRQ(4)
331#define IRQ_PJ5 BFIN_PJ_IRQ(5)
332#define IRQ_PJ6 BFIN_PJ_IRQ(6)
333#define IRQ_PJ7 BFIN_PJ_IRQ(7)
334#define IRQ_PJ8 BFIN_PJ_IRQ(8)
335#define IRQ_PJ9 BFIN_PJ_IRQ(9)
336#define IRQ_PJ10 BFIN_PJ_IRQ(10)
337#define IRQ_PJ11 BFIN_PJ_IRQ(11)
338#define IRQ_PJ12 BFIN_PJ_IRQ(12)
339#define IRQ_PJ13 BFIN_PJ_IRQ(13)
340#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */
341#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */
342
343#define GPIO_IRQ_BASE IRQ_PA0
344
345#define NR_IRQS (IRQ_PJ15+1)
346
347/* For compatibility reasons with existing code */
348
349#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
350#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
351#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR
352#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR
353#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
354#define IRQ_UART0_ERR IRQ_UART0_ERROR
355#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
356#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR
357#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR
358#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
359#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
360#define IRQ_UART1_ERR IRQ_UART1_ERROR
361#define IRQ_UART2_ERR IRQ_UART2_ERROR
362#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
363#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
364#define IRQ_EPP1_ERR IRQ_EPP1_ERROR
365#define IRQ_EPP2_ERR IRQ_EPP2_ERROR
366#define IRQ_UART3_ERR IRQ_UART3_ERROR
367#define IRQ_HOST_ERR IRQ_HOST_ERROR
368#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
369#define IRQ_NFC_ERR IRQ_NFC_ERROR
370#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
371#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
372#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR
373
374
375#define IVG7 7
376#define IVG8 8
377#define IVG9 9
378#define IVG10 10
379#define IVG11 11
380#define IVG12 12
381#define IVG13 13
382#define IVG14 14
383#define IVG15 15
384
385/* IAR0 BIT FIELDS */
386#define IRQ_PLL_WAKEUP_POS 0
387#define IRQ_DMAC0_ERR_POS 4
388#define IRQ_EPPI0_ERR_POS 8
389#define IRQ_SPORT0_ERR_POS 12
390#define IRQ_SPORT1_ERR_POS 16
391#define IRQ_SPI0_ERR_POS 20
392#define IRQ_UART0_ERR_POS 24
393#define IRQ_RTC_POS 28
394
395/* IAR1 BIT FIELDS */
396#define IRQ_EPPI0_POS 0
397#define IRQ_SPORT0_RX_POS 4
398#define IRQ_SPORT0_TX_POS 8
399#define IRQ_SPORT1_RX_POS 12
400#define IRQ_SPORT1_TX_POS 16
401#define IRQ_SPI0_POS 20
402#define IRQ_UART0_RX_POS 24
403#define IRQ_UART0_TX_POS 28
404
405/* IAR2 BIT FIELDS */
406#define IRQ_TIMER8_POS 0
407#define IRQ_TIMER9_POS 4
408#define IRQ_TIMER10_POS 8
409#define IRQ_PINT0_POS 12
410#define IRQ_PINT1_POS 16
411#define IRQ_MDMAS0_POS 20
412#define IRQ_MDMAS1_POS 24
413#define IRQ_WATCH_POS 28
414
415/* IAR3 BIT FIELDS */
416#define IRQ_DMAC1_ERR_POS 0
417#define IRQ_SPORT2_ERR_POS 4
418#define IRQ_SPORT3_ERR_POS 8
419#define IRQ_MXVR_DATA_POS 12
420#define IRQ_SPI1_ERR_POS 16
421#define IRQ_SPI2_ERR_POS 20
422#define IRQ_UART1_ERR_POS 24
423#define IRQ_UART2_ERR_POS 28
424
425/* IAR4 BIT FILEDS */
426#define IRQ_CAN0_ERR_POS 0
427#define IRQ_SPORT2_RX_POS 4
428#define IRQ_UART2_RX_POS 4
429#define IRQ_SPORT2_TX_POS 8
430#define IRQ_UART2_TX_POS 8
431#define IRQ_SPORT3_RX_POS 12
432#define IRQ_UART3_RX_POS 12
433#define IRQ_SPORT3_TX_POS 16
434#define IRQ_UART3_TX_POS 16
435#define IRQ_EPPI1_POS 20
436#define IRQ_EPPI2_POS 24
437#define IRQ_SPI1_POS 28
438
439/* IAR5 BIT FIELDS */
440#define IRQ_SPI2_POS 0
441#define IRQ_UART1_RX_POS 4
442#define IRQ_UART1_TX_POS 8
443#define IRQ_ATAPI_RX_POS 12
444#define IRQ_ATAPI_TX_POS 16
445#define IRQ_TWI0_POS 20
446#define IRQ_TWI1_POS 24
447#define IRQ_CAN0_RX_POS 28
448
449/* IAR6 BIT FIELDS */
450#define IRQ_CAN0_TX_POS 0
451#define IRQ_MDMAS2_POS 4
452#define IRQ_MDMAS3_POS 8
453#define IRQ_MXVR_ERR_POS 12
454#define IRQ_MXVR_MSG_POS 16
455#define IRQ_MXVR_PKT_POS 20
456#define IRQ_EPPI1_ERR_POS 24
457#define IRQ_EPPI2_ERR_POS 28
458
459/* IAR7 BIT FIELDS */
460#define IRQ_UART3_ERR_POS 0
461#define IRQ_HOST_ERR_POS 4
462#define IRQ_PIXC_ERR_POS 12
463#define IRQ_NFC_ERR_POS 16
464#define IRQ_ATAPI_ERR_POS 20
465#define IRQ_CAN1_ERR_POS 24
466#define IRQ_HS_DMA_ERR_POS 28
467
468/* IAR8 BIT FIELDS */
469#define IRQ_PIXC_IN0_POS 0
470#define IRQ_PIXC_IN1_POS 4
471#define IRQ_PIXC_OUT_POS 8
472#define IRQ_SDH_POS 12
473#define IRQ_CNT_POS 16
474#define IRQ_KEY_POS 20
475#define IRQ_CAN1_RX_POS 24
476#define IRQ_CAN1_TX_POS 28
477
478/* IAR9 BIT FIELDS */
479#define IRQ_SDH_MASK0_POS 0
480#define IRQ_SDH_MASK1_POS 4
481#define IRQ_USB_INT0_POS 12
482#define IRQ_USB_INT1_POS 16
483#define IRQ_USB_INT2_POS 20
484#define IRQ_USB_DMA_POS 24
485#define IRQ_OTPSEC_POS 28
486
487/* IAR10 BIT FIELDS */
488#define IRQ_TIMER0_POS 24
489#define IRQ_TIMER1_POS 28
490
491/* IAR11 BIT FIELDS */
492#define IRQ_TIMER2_POS 0
493#define IRQ_TIMER3_POS 4
494#define IRQ_TIMER4_POS 8
495#define IRQ_TIMER5_POS 12
496#define IRQ_TIMER6_POS 16
497#define IRQ_TIMER7_POS 20
498#define IRQ_PINT2_POS 24
499#define IRQ_PINT3_POS 28
500
501#endif /* _BF548_IRQ_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 03:36:11 -0400