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-rw-r--r--include/asm-blackfin/mach-bf548/dma.h76
1 files changed, 0 insertions, 76 deletions
diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h
deleted file mode 100644
index 36a2ef7e7849..000000000000
--- a/include/asm-blackfin/mach-bf548/dma.h
+++ /dev/null
@@ -1,76 +0,0 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/dma.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _MACH_DMA_H_
33#define _MACH_DMA_H_
34
35#define CH_SPORT0_RX 0
36#define CH_SPORT0_TX 1
37#define CH_SPORT1_RX 2
38#define CH_SPORT1_TX 3
39#define CH_SPI0 4
40#define CH_SPI1 5
41#define CH_UART0_RX 6
42#define CH_UART0_TX 7
43#define CH_UART1_RX 8
44#define CH_UART1_TX 9
45#define CH_ATAPI_RX 10
46#define CH_ATAPI_TX 11
47#define CH_EPPI0 12
48#define CH_EPPI1 13
49#define CH_EPPI2 14
50#define CH_PIXC_IMAGE 15
51#define CH_PIXC_OVERLAY 16
52#define CH_PIXC_OUTPUT 17
53#define CH_SPORT2_RX 18
54#define CH_UART2_RX 18
55#define CH_SPORT2_TX 19
56#define CH_UART2_TX 19
57#define CH_SPORT3_RX 20
58#define CH_UART3_RX 20
59#define CH_SPORT3_TX 21
60#define CH_UART3_TX 21
61#define CH_SDH 22
62#define CH_NFC 22
63#define CH_SPI2 23
64
65#define CH_MEM_STREAM0_DEST 24
66#define CH_MEM_STREAM0_SRC 25
67#define CH_MEM_STREAM1_DEST 26
68#define CH_MEM_STREAM1_SRC 27
69#define CH_MEM_STREAM2_DEST 28
70#define CH_MEM_STREAM2_SRC 29
71#define CH_MEM_STREAM3_DEST 30
72#define CH_MEM_STREAM3_SRC 31
73
74#define MAX_BLACKFIN_DMA_CHANNEL 32
75
76#endif