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Diffstat (limited to 'include/asm-blackfin/mach-bf548/defBF54x_base.h')
-rw-r--r--include/asm-blackfin/mach-bf548/defBF54x_base.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index e2632db74baa..1d365c844ffe 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -47,6 +47,10 @@
47/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ 47/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
48 48
49#define CHIPID 0xffc00014 49#define CHIPID 0xffc00014
50/* CHIPID Masks */
51#define CHIPID_VERSION 0xF0000000
52#define CHIPID_FAMILY 0x0FFFF000
53#define CHIPID_MANUFACTURE 0x00000FFE
50 54
51/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */ 55/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
52 56
@@ -3299,7 +3303,7 @@
3299 3303
3300#define MFD 0xf000 /* Multi channel Frame Delay */ 3304#define MFD 0xf000 /* Multi channel Frame Delay */
3301#define FSDR 0x80 /* Frame Sync to Data Relationship */ 3305#define FSDR 0x80 /* Frame Sync to Data Relationship */
3302#define MCMEM 0x10 /* Multi channel Frame Mode Enable */ 3306#define MCMEN 0x10 /* Multi channel Frame Mode Enable */
3303#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */ 3307#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */
3304#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */ 3308#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */
3305#define MCCRM 0x3 /* 2X Clock Recovery Mode */ 3309#define MCCRM 0x3 /* 2X Clock Recovery Mode */