diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf548/defBF54x_base.h')
-rw-r--r-- | include/asm-blackfin/mach-bf548/defBF54x_base.h | 4902 |
1 files changed, 4902 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h new file mode 100644 index 000000000000..a1b200fe6a1f --- /dev/null +++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h | |||
@@ -0,0 +1,4902 @@ | |||
1 | /* | ||
2 | * File: include/asm-blackfin/mach-bf548/defBF54x_base.h | ||
3 | * Based on: | ||
4 | * Author: | ||
5 | * | ||
6 | * Created: | ||
7 | * Description: | ||
8 | * | ||
9 | * Rev: | ||
10 | * | ||
11 | * Modified: | ||
12 | * | ||
13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or modify | ||
16 | * it under the terms of the GNU General Public License as published by | ||
17 | * the Free Software Foundation; either version 2, or (at your option) | ||
18 | * any later version. | ||
19 | * | ||
20 | * This program is distributed in the hope that it will be useful, | ||
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
23 | * GNU General Public License for more details. | ||
24 | * | ||
25 | * You should have received a copy of the GNU General Public License | ||
26 | * along with this program; see the file COPYING. | ||
27 | * If not, write to the Free Software Foundation, | ||
28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
29 | */ | ||
30 | |||
31 | #ifndef _DEF_BF54X_H | ||
32 | #define _DEF_BF54X_H | ||
33 | |||
34 | |||
35 | /* ************************************************************** */ | ||
36 | /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ | ||
37 | /* ************************************************************** */ | ||
38 | |||
39 | /* PLL Registers */ | ||
40 | |||
41 | #define PLL_CTL 0xffc00000 /* PLL Control Register */ | ||
42 | #define PLL_DIV 0xffc00004 /* PLL Divisor Register */ | ||
43 | #define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */ | ||
44 | #define PLL_STAT 0xffc0000c /* PLL Status Register */ | ||
45 | #define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */ | ||
46 | |||
47 | /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ | ||
48 | |||
49 | #define CHIPID 0xffc00014 | ||
50 | |||
51 | /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */ | ||
52 | |||
53 | #define SWRST 0xffc00100 /* Software Reset Register */ | ||
54 | #define SYSCR 0xffc00104 /* System Configuration register */ | ||
55 | |||
56 | /* SIC Registers */ | ||
57 | |||
58 | #define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */ | ||
59 | #define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */ | ||
60 | #define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */ | ||
61 | #define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */ | ||
62 | #define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */ | ||
63 | #define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */ | ||
64 | #define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */ | ||
65 | #define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */ | ||
66 | #define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */ | ||
67 | #define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */ | ||
68 | #define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */ | ||
69 | #define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */ | ||
70 | #define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */ | ||
71 | #define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */ | ||
72 | #define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */ | ||
73 | #define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */ | ||
74 | #define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */ | ||
75 | #define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */ | ||
76 | #define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */ | ||
77 | #define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */ | ||
78 | #define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */ | ||
79 | |||
80 | /* Watchdog Timer Registers */ | ||
81 | |||
82 | #define WDOG_CTL 0xffc00200 /* Watchdog Control Register */ | ||
83 | #define WDOG_CNT 0xffc00204 /* Watchdog Count Register */ | ||
84 | #define WDOG_STAT 0xffc00208 /* Watchdog Status Register */ | ||
85 | |||
86 | /* RTC Registers */ | ||
87 | |||
88 | #define RTC_STAT 0xffc00300 /* RTC Status Register */ | ||
89 | #define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */ | ||
90 | #define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */ | ||
91 | #define RTC_SWCNT 0xffc0030c /* RTC Stopwatch Count Register */ | ||
92 | #define RTC_ALARM 0xffc00310 /* RTC Alarm Register */ | ||
93 | #define RTC_PREN 0xffc00314 /* RTC Prescaler Enable Register */ | ||
94 | |||
95 | /* UART0 Registers */ | ||
96 | |||
97 | #define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */ | ||
98 | #define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */ | ||
99 | #define UART0_GCTL 0xffc00408 /* Global Control Register */ | ||
100 | #define UART0_LCR 0xffc0040c /* Line Control Register */ | ||
101 | #define UART0_MCR 0xffc00410 /* Modem Control Register */ | ||
102 | #define UART0_LSR 0xffc00414 /* Line Status Register */ | ||
103 | #define UART0_MSR 0xffc00418 /* Modem Status Register */ | ||
104 | #define UART0_SCR 0xffc0041c /* Scratch Register */ | ||
105 | #define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */ | ||
106 | #define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */ | ||
107 | #define UART0_THR 0xffc00428 /* Transmit Hold Register */ | ||
108 | #define UART0_RBR 0xffc0042c /* Receive Buffer Register */ | ||
109 | |||
110 | /* SPI0 Registers */ | ||
111 | |||
112 | #define SPI0_CTL 0xffc00500 /* SPI0 Control Register */ | ||
113 | #define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */ | ||
114 | #define SPI0_STAT 0xffc00508 /* SPI0 Status Register */ | ||
115 | #define SPI0_TDBR 0xffc0050c /* SPI0 Transmit Data Buffer Register */ | ||
116 | #define SPI0_RDBR 0xffc00510 /* SPI0 Receive Data Buffer Register */ | ||
117 | #define SPI0_BAUD 0xffc00514 /* SPI0 Baud Rate Register */ | ||
118 | #define SPI0_SHADOW 0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */ | ||
119 | |||
120 | /* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */ | ||
121 | |||
122 | /* Two Wire Interface Registers (TWI0) */ | ||
123 | |||
124 | #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ | ||
125 | #define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ | ||
126 | #define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */ | ||
127 | #define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */ | ||
128 | #define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */ | ||
129 | #define TWI0_MASTER_CTRL 0xffc00714 /* TWI Master Mode Control Register */ | ||
130 | #define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */ | ||
131 | #define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */ | ||
132 | #define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */ | ||
133 | #define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */ | ||
134 | #define TWI0_FIFO_CTRL 0xffc00728 /* TWI FIFO Control Register */ | ||
135 | #define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */ | ||
136 | #define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */ | ||
137 | #define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */ | ||
138 | #define TWI0_RCV_DATA8 0xffc00788 /* TWI FIFO Receive Data Single Byte Register */ | ||
139 | #define TWI0_RCV_DATA16 0xffc0078c /* TWI FIFO Receive Data Double Byte Register */ | ||
140 | |||
141 | /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */ | ||
142 | |||
143 | /* SPORT1 Registers */ | ||
144 | |||
145 | #define SPORT1_TCR1 0xffc00900 /* SPORT1 Transmit Configuration 1 Register */ | ||
146 | #define SPORT1_TCR2 0xffc00904 /* SPORT1 Transmit Configuration 2 Register */ | ||
147 | #define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */ | ||
148 | #define SPORT1_TFSDIV 0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */ | ||
149 | #define SPORT1_TX 0xffc00910 /* SPORT1 Transmit Data Register */ | ||
150 | #define SPORT1_RX 0xffc00918 /* SPORT1 Receive Data Register */ | ||
151 | #define SPORT1_RCR1 0xffc00920 /* SPORT1 Receive Configuration 1 Register */ | ||
152 | #define SPORT1_RCR2 0xffc00924 /* SPORT1 Receive Configuration 2 Register */ | ||
153 | #define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */ | ||
154 | #define SPORT1_RFSDIV 0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */ | ||
155 | #define SPORT1_STAT 0xffc00930 /* SPORT1 Status Register */ | ||
156 | #define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */ | ||
157 | #define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */ | ||
158 | #define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */ | ||
159 | #define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */ | ||
160 | #define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */ | ||
161 | #define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */ | ||
162 | #define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */ | ||
163 | #define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */ | ||
164 | #define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */ | ||
165 | #define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */ | ||
166 | #define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */ | ||
167 | |||
168 | /* Asynchronous Memory Control Registers */ | ||
169 | |||
170 | #define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */ | ||
171 | #define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */ | ||
172 | #define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */ | ||
173 | #define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */ | ||
174 | #define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */ | ||
175 | #define EBIU_MODE 0xffc00a14 /* Asynchronous Mode Control Register */ | ||
176 | #define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */ | ||
177 | |||
178 | /* DDR Memory Control Registers */ | ||
179 | |||
180 | #define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */ | ||
181 | #define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */ | ||
182 | #define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */ | ||
183 | #define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */ | ||
184 | #define EBIU_DDRQUE 0xffc00a30 /* DDR Queue Configuration Register */ | ||
185 | #define EBIU_ERRADD 0xffc00a34 /* DDR Error Address Register */ | ||
186 | #define EBIU_ERRMST 0xffc00a38 /* DDR Error Master Register */ | ||
187 | #define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */ | ||
188 | |||
189 | /* DDR BankRead and Write Count Registers */ | ||
190 | |||
191 | #define EBIU_DDRBRC0 0xffc00a60 /* DDR Bank0 Read Count Register */ | ||
192 | #define EBIU_DDRBRC1 0xffc00a64 /* DDR Bank1 Read Count Register */ | ||
193 | #define EBIU_DDRBRC2 0xffc00a68 /* DDR Bank2 Read Count Register */ | ||
194 | #define EBIU_DDRBRC3 0xffc00a6c /* DDR Bank3 Read Count Register */ | ||
195 | #define EBIU_DDRBRC4 0xffc00a70 /* DDR Bank4 Read Count Register */ | ||
196 | #define EBIU_DDRBRC5 0xffc00a74 /* DDR Bank5 Read Count Register */ | ||
197 | #define EBIU_DDRBRC6 0xffc00a78 /* DDR Bank6 Read Count Register */ | ||
198 | #define EBIU_DDRBRC7 0xffc00a7c /* DDR Bank7 Read Count Register */ | ||
199 | #define EBIU_DDRBWC0 0xffc00a80 /* DDR Bank0 Write Count Register */ | ||
200 | #define EBIU_DDRBWC1 0xffc00a84 /* DDR Bank1 Write Count Register */ | ||
201 | #define EBIU_DDRBWC2 0xffc00a88 /* DDR Bank2 Write Count Register */ | ||
202 | #define EBIU_DDRBWC3 0xffc00a8c /* DDR Bank3 Write Count Register */ | ||
203 | #define EBIU_DDRBWC4 0xffc00a90 /* DDR Bank4 Write Count Register */ | ||
204 | #define EBIU_DDRBWC5 0xffc00a94 /* DDR Bank5 Write Count Register */ | ||
205 | #define EBIU_DDRBWC6 0xffc00a98 /* DDR Bank6 Write Count Register */ | ||
206 | #define EBIU_DDRBWC7 0xffc00a9c /* DDR Bank7 Write Count Register */ | ||
207 | #define EBIU_DDRACCT 0xffc00aa0 /* DDR Activation Count Register */ | ||
208 | #define EBIU_DDRTACT 0xffc00aa8 /* DDR Turn Around Count Register */ | ||
209 | #define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */ | ||
210 | #define EBIU_DDRGC0 0xffc00ab0 /* DDR Grant Count 0 Register */ | ||
211 | #define EBIU_DDRGC1 0xffc00ab4 /* DDR Grant Count 1 Register */ | ||
212 | #define EBIU_DDRGC2 0xffc00ab8 /* DDR Grant Count 2 Register */ | ||
213 | #define EBIU_DDRGC3 0xffc00abc /* DDR Grant Count 3 Register */ | ||
214 | #define EBIU_DDRMCEN 0xffc00ac0 /* DDR Metrics Counter Enable Register */ | ||
215 | #define EBIU_DDRMCCL 0xffc00ac4 /* DDR Metrics Counter Clear Register */ | ||
216 | |||
217 | /* DMAC0 Registers */ | ||
218 | |||
219 | #define DMAC0_TCPER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */ | ||
220 | #define DMAC0_TCCNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */ | ||
221 | |||
222 | /* DMA Channel 0 Registers */ | ||
223 | |||
224 | #define DMA0_NEXT_DESC_PTR 0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */ | ||
225 | #define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */ | ||
226 | #define DMA0_CONFIG 0xffc00c08 /* DMA Channel 0 Configuration Register */ | ||
227 | #define DMA0_X_COUNT 0xffc00c10 /* DMA Channel 0 X Count Register */ | ||
228 | #define DMA0_X_MODIFY 0xffc00c14 /* DMA Channel 0 X Modify Register */ | ||
229 | #define DMA0_Y_COUNT 0xffc00c18 /* DMA Channel 0 Y Count Register */ | ||
230 | #define DMA0_Y_MODIFY 0xffc00c1c /* DMA Channel 0 Y Modify Register */ | ||
231 | #define DMA0_CURR_DESC_PTR 0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */ | ||
232 | #define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */ | ||
233 | #define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */ | ||
234 | #define DMA0_PERIPHERAL_MAP 0xffc00c2c /* DMA Channel 0 Peripheral Map Register */ | ||
235 | #define DMA0_CURR_X_COUNT 0xffc00c30 /* DMA Channel 0 Current X Count Register */ | ||
236 | #define DMA0_CURR_Y_COUNT 0xffc00c38 /* DMA Channel 0 Current Y Count Register */ | ||
237 | |||
238 | /* DMA Channel 1 Registers */ | ||
239 | |||
240 | #define DMA1_NEXT_DESC_PTR 0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */ | ||
241 | #define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */ | ||
242 | #define DMA1_CONFIG 0xffc00c48 /* DMA Channel 1 Configuration Register */ | ||
243 | #define DMA1_X_COUNT 0xffc00c50 /* DMA Channel 1 X Count Register */ | ||
244 | #define DMA1_X_MODIFY 0xffc00c54 /* DMA Channel 1 X Modify Register */ | ||
245 | #define DMA1_Y_COUNT 0xffc00c58 /* DMA Channel 1 Y Count Register */ | ||
246 | #define DMA1_Y_MODIFY 0xffc00c5c /* DMA Channel 1 Y Modify Register */ | ||
247 | #define DMA1_CURR_DESC_PTR 0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */ | ||
248 | #define DMA1_CURR_ADDR 0xffc00c64 /* DMA Channel 1 Current Address Register */ | ||
249 | #define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */ | ||
250 | #define DMA1_PERIPHERAL_MAP 0xffc00c6c /* DMA Channel 1 Peripheral Map Register */ | ||
251 | #define DMA1_CURR_X_COUNT 0xffc00c70 /* DMA Channel 1 Current X Count Register */ | ||
252 | #define DMA1_CURR_Y_COUNT 0xffc00c78 /* DMA Channel 1 Current Y Count Register */ | ||
253 | |||
254 | /* DMA Channel 2 Registers */ | ||
255 | |||
256 | #define DMA2_NEXT_DESC_PTR 0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */ | ||
257 | #define DMA2_START_ADDR 0xffc00c84 /* DMA Channel 2 Start Address Register */ | ||
258 | #define DMA2_CONFIG 0xffc00c88 /* DMA Channel 2 Configuration Register */ | ||
259 | #define DMA2_X_COUNT 0xffc00c90 /* DMA Channel 2 X Count Register */ | ||
260 | #define DMA2_X_MODIFY 0xffc00c94 /* DMA Channel 2 X Modify Register */ | ||
261 | #define DMA2_Y_COUNT 0xffc00c98 /* DMA Channel 2 Y Count Register */ | ||
262 | #define DMA2_Y_MODIFY 0xffc00c9c /* DMA Channel 2 Y Modify Register */ | ||
263 | #define DMA2_CURR_DESC_PTR 0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */ | ||
264 | #define DMA2_CURR_ADDR 0xffc00ca4 /* DMA Channel 2 Current Address Register */ | ||
265 | #define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */ | ||
266 | #define DMA2_PERIPHERAL_MAP 0xffc00cac /* DMA Channel 2 Peripheral Map Register */ | ||
267 | #define DMA2_CURR_X_COUNT 0xffc00cb0 /* DMA Channel 2 Current X Count Register */ | ||
268 | #define DMA2_CURR_Y_COUNT 0xffc00cb8 /* DMA Channel 2 Current Y Count Register */ | ||
269 | |||
270 | /* DMA Channel 3 Registers */ | ||
271 | |||
272 | #define DMA3_NEXT_DESC_PTR 0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */ | ||
273 | #define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */ | ||
274 | #define DMA3_CONFIG 0xffc00cc8 /* DMA Channel 3 Configuration Register */ | ||
275 | #define DMA3_X_COUNT 0xffc00cd0 /* DMA Channel 3 X Count Register */ | ||
276 | #define DMA3_X_MODIFY 0xffc00cd4 /* DMA Channel 3 X Modify Register */ | ||
277 | #define DMA3_Y_COUNT 0xffc00cd8 /* DMA Channel 3 Y Count Register */ | ||
278 | #define DMA3_Y_MODIFY 0xffc00cdc /* DMA Channel 3 Y Modify Register */ | ||
279 | #define DMA3_CURR_DESC_PTR 0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */ | ||
280 | #define DMA3_CURR_ADDR 0xffc00ce4 /* DMA Channel 3 Current Address Register */ | ||
281 | #define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */ | ||
282 | #define DMA3_PERIPHERAL_MAP 0xffc00cec /* DMA Channel 3 Peripheral Map Register */ | ||
283 | #define DMA3_CURR_X_COUNT 0xffc00cf0 /* DMA Channel 3 Current X Count Register */ | ||
284 | #define DMA3_CURR_Y_COUNT 0xffc00cf8 /* DMA Channel 3 Current Y Count Register */ | ||
285 | |||
286 | /* DMA Channel 4 Registers */ | ||
287 | |||
288 | #define DMA4_NEXT_DESC_PTR 0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */ | ||
289 | #define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */ | ||
290 | #define DMA4_CONFIG 0xffc00d08 /* DMA Channel 4 Configuration Register */ | ||
291 | #define DMA4_X_COUNT 0xffc00d10 /* DMA Channel 4 X Count Register */ | ||
292 | #define DMA4_X_MODIFY 0xffc00d14 /* DMA Channel 4 X Modify Register */ | ||
293 | #define DMA4_Y_COUNT 0xffc00d18 /* DMA Channel 4 Y Count Register */ | ||
294 | #define DMA4_Y_MODIFY 0xffc00d1c /* DMA Channel 4 Y Modify Register */ | ||
295 | #define DMA4_CURR_DESC_PTR 0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */ | ||
296 | #define DMA4_CURR_ADDR 0xffc00d24 /* DMA Channel 4 Current Address Register */ | ||
297 | #define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */ | ||
298 | #define DMA4_PERIPHERAL_MAP 0xffc00d2c /* DMA Channel 4 Peripheral Map Register */ | ||
299 | #define DMA4_CURR_X_COUNT 0xffc00d30 /* DMA Channel 4 Current X Count Register */ | ||
300 | #define DMA4_CURR_Y_COUNT 0xffc00d38 /* DMA Channel 4 Current Y Count Register */ | ||
301 | |||
302 | /* DMA Channel 5 Registers */ | ||
303 | |||
304 | #define DMA5_NEXT_DESC_PTR 0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */ | ||
305 | #define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */ | ||
306 | #define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */ | ||
307 | #define DMA5_X_COUNT 0xffc00d50 /* DMA Channel 5 X Count Register */ | ||
308 | #define DMA5_X_MODIFY 0xffc00d54 /* DMA Channel 5 X Modify Register */ | ||
309 | #define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */ | ||
310 | #define DMA5_Y_MODIFY 0xffc00d5c /* DMA Channel 5 Y Modify Register */ | ||
311 | #define DMA5_CURR_DESC_PTR 0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */ | ||
312 | #define DMA5_CURR_ADDR 0xffc00d64 /* DMA Channel 5 Current Address Register */ | ||
313 | #define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */ | ||
314 | #define DMA5_PERIPHERAL_MAP 0xffc00d6c /* DMA Channel 5 Peripheral Map Register */ | ||
315 | #define DMA5_CURR_X_COUNT 0xffc00d70 /* DMA Channel 5 Current X Count Register */ | ||
316 | #define DMA5_CURR_Y_COUNT 0xffc00d78 /* DMA Channel 5 Current Y Count Register */ | ||
317 | |||
318 | /* DMA Channel 6 Registers */ | ||
319 | |||
320 | #define DMA6_NEXT_DESC_PTR 0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */ | ||
321 | #define DMA6_START_ADDR 0xffc00d84 /* DMA Channel 6 Start Address Register */ | ||
322 | #define DMA6_CONFIG 0xffc00d88 /* DMA Channel 6 Configuration Register */ | ||
323 | #define DMA6_X_COUNT 0xffc00d90 /* DMA Channel 6 X Count Register */ | ||
324 | #define DMA6_X_MODIFY 0xffc00d94 /* DMA Channel 6 X Modify Register */ | ||
325 | #define DMA6_Y_COUNT 0xffc00d98 /* DMA Channel 6 Y Count Register */ | ||
326 | #define DMA6_Y_MODIFY 0xffc00d9c /* DMA Channel 6 Y Modify Register */ | ||
327 | #define DMA6_CURR_DESC_PTR 0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */ | ||
328 | #define DMA6_CURR_ADDR 0xffc00da4 /* DMA Channel 6 Current Address Register */ | ||
329 | #define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */ | ||
330 | #define DMA6_PERIPHERAL_MAP 0xffc00dac /* DMA Channel 6 Peripheral Map Register */ | ||
331 | #define DMA6_CURR_X_COUNT 0xffc00db0 /* DMA Channel 6 Current X Count Register */ | ||
332 | #define DMA6_CURR_Y_COUNT 0xffc00db8 /* DMA Channel 6 Current Y Count Register */ | ||
333 | |||
334 | /* DMA Channel 7 Registers */ | ||
335 | |||
336 | #define DMA7_NEXT_DESC_PTR 0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */ | ||
337 | #define DMA7_START_ADDR 0xffc00dc4 /* DMA Channel 7 Start Address Register */ | ||
338 | #define DMA7_CONFIG 0xffc00dc8 /* DMA Channel 7 Configuration Register */ | ||
339 | #define DMA7_X_COUNT 0xffc00dd0 /* DMA Channel 7 X Count Register */ | ||
340 | #define DMA7_X_MODIFY 0xffc00dd4 /* DMA Channel 7 X Modify Register */ | ||
341 | #define DMA7_Y_COUNT 0xffc00dd8 /* DMA Channel 7 Y Count Register */ | ||
342 | #define DMA7_Y_MODIFY 0xffc00ddc /* DMA Channel 7 Y Modify Register */ | ||
343 | #define DMA7_CURR_DESC_PTR 0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */ | ||
344 | #define DMA7_CURR_ADDR 0xffc00de4 /* DMA Channel 7 Current Address Register */ | ||
345 | #define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */ | ||
346 | #define DMA7_PERIPHERAL_MAP 0xffc00dec /* DMA Channel 7 Peripheral Map Register */ | ||
347 | #define DMA7_CURR_X_COUNT 0xffc00df0 /* DMA Channel 7 Current X Count Register */ | ||
348 | #define DMA7_CURR_Y_COUNT 0xffc00df8 /* DMA Channel 7 Current Y Count Register */ | ||
349 | |||
350 | /* DMA Channel 8 Registers */ | ||
351 | |||
352 | #define DMA8_NEXT_DESC_PTR 0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */ | ||
353 | #define DMA8_START_ADDR 0xffc00e04 /* DMA Channel 8 Start Address Register */ | ||
354 | #define DMA8_CONFIG 0xffc00e08 /* DMA Channel 8 Configuration Register */ | ||
355 | #define DMA8_X_COUNT 0xffc00e10 /* DMA Channel 8 X Count Register */ | ||
356 | #define DMA8_X_MODIFY 0xffc00e14 /* DMA Channel 8 X Modify Register */ | ||
357 | #define DMA8_Y_COUNT 0xffc00e18 /* DMA Channel 8 Y Count Register */ | ||
358 | #define DMA8_Y_MODIFY 0xffc00e1c /* DMA Channel 8 Y Modify Register */ | ||
359 | #define DMA8_CURR_DESC_PTR 0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */ | ||
360 | #define DMA8_CURR_ADDR 0xffc00e24 /* DMA Channel 8 Current Address Register */ | ||
361 | #define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */ | ||
362 | #define DMA8_PERIPHERAL_MAP 0xffc00e2c /* DMA Channel 8 Peripheral Map Register */ | ||
363 | #define DMA8_CURR_X_COUNT 0xffc00e30 /* DMA Channel 8 Current X Count Register */ | ||
364 | #define DMA8_CURR_Y_COUNT 0xffc00e38 /* DMA Channel 8 Current Y Count Register */ | ||
365 | |||
366 | /* DMA Channel 9 Registers */ | ||
367 | |||
368 | #define DMA9_NEXT_DESC_PTR 0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */ | ||
369 | #define DMA9_START_ADDR 0xffc00e44 /* DMA Channel 9 Start Address Register */ | ||
370 | #define DMA9_CONFIG 0xffc00e48 /* DMA Channel 9 Configuration Register */ | ||
371 | #define DMA9_X_COUNT 0xffc00e50 /* DMA Channel 9 X Count Register */ | ||
372 | #define DMA9_X_MODIFY 0xffc00e54 /* DMA Channel 9 X Modify Register */ | ||
373 | #define DMA9_Y_COUNT 0xffc00e58 /* DMA Channel 9 Y Count Register */ | ||
374 | #define DMA9_Y_MODIFY 0xffc00e5c /* DMA Channel 9 Y Modify Register */ | ||
375 | #define DMA9_CURR_DESC_PTR 0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */ | ||
376 | #define DMA9_CURR_ADDR 0xffc00e64 /* DMA Channel 9 Current Address Register */ | ||
377 | #define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */ | ||
378 | #define DMA9_PERIPHERAL_MAP 0xffc00e6c /* DMA Channel 9 Peripheral Map Register */ | ||
379 | #define DMA9_CURR_X_COUNT 0xffc00e70 /* DMA Channel 9 Current X Count Register */ | ||
380 | #define DMA9_CURR_Y_COUNT 0xffc00e78 /* DMA Channel 9 Current Y Count Register */ | ||
381 | |||
382 | /* DMA Channel 10 Registers */ | ||
383 | |||
384 | #define DMA10_NEXT_DESC_PTR 0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */ | ||
385 | #define DMA10_START_ADDR 0xffc00e84 /* DMA Channel 10 Start Address Register */ | ||
386 | #define DMA10_CONFIG 0xffc00e88 /* DMA Channel 10 Configuration Register */ | ||
387 | #define DMA10_X_COUNT 0xffc00e90 /* DMA Channel 10 X Count Register */ | ||
388 | #define DMA10_X_MODIFY 0xffc00e94 /* DMA Channel 10 X Modify Register */ | ||
389 | #define DMA10_Y_COUNT 0xffc00e98 /* DMA Channel 10 Y Count Register */ | ||
390 | #define DMA10_Y_MODIFY 0xffc00e9c /* DMA Channel 10 Y Modify Register */ | ||
391 | #define DMA10_CURR_DESC_PTR 0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */ | ||
392 | #define DMA10_CURR_ADDR 0xffc00ea4 /* DMA Channel 10 Current Address Register */ | ||
393 | #define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */ | ||
394 | #define DMA10_PERIPHERAL_MAP 0xffc00eac /* DMA Channel 10 Peripheral Map Register */ | ||
395 | #define DMA10_CURR_X_COUNT 0xffc00eb0 /* DMA Channel 10 Current X Count Register */ | ||
396 | #define DMA10_CURR_Y_COUNT 0xffc00eb8 /* DMA Channel 10 Current Y Count Register */ | ||
397 | |||
398 | /* DMA Channel 11 Registers */ | ||
399 | |||
400 | #define DMA11_NEXT_DESC_PTR 0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */ | ||
401 | #define DMA11_START_ADDR 0xffc00ec4 /* DMA Channel 11 Start Address Register */ | ||
402 | #define DMA11_CONFIG 0xffc00ec8 /* DMA Channel 11 Configuration Register */ | ||
403 | #define DMA11_X_COUNT 0xffc00ed0 /* DMA Channel 11 X Count Register */ | ||
404 | #define DMA11_X_MODIFY 0xffc00ed4 /* DMA Channel 11 X Modify Register */ | ||
405 | #define DMA11_Y_COUNT 0xffc00ed8 /* DMA Channel 11 Y Count Register */ | ||
406 | #define DMA11_Y_MODIFY 0xffc00edc /* DMA Channel 11 Y Modify Register */ | ||
407 | #define DMA11_CURR_DESC_PTR 0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */ | ||
408 | #define DMA11_CURR_ADDR 0xffc00ee4 /* DMA Channel 11 Current Address Register */ | ||
409 | #define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */ | ||
410 | #define DMA11_PERIPHERAL_MAP 0xffc00eec /* DMA Channel 11 Peripheral Map Register */ | ||
411 | #define DMA11_CURR_X_COUNT 0xffc00ef0 /* DMA Channel 11 Current X Count Register */ | ||
412 | #define DMA11_CURR_Y_COUNT 0xffc00ef8 /* DMA Channel 11 Current Y Count Register */ | ||
413 | |||
414 | /* MDMA Stream 0 Registers */ | ||
415 | |||
416 | #define MDMA_D0_NEXT_DESC_PTR 0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ | ||
417 | #define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */ | ||
418 | #define MDMA_D0_CONFIG 0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */ | ||
419 | #define MDMA_D0_X_COUNT 0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */ | ||
420 | #define MDMA_D0_X_MODIFY 0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */ | ||
421 | #define MDMA_D0_Y_COUNT 0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */ | ||
422 | #define MDMA_D0_Y_MODIFY 0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */ | ||
423 | #define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ | ||
424 | #define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */ | ||
425 | #define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */ | ||
426 | #define MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */ | ||
427 | #define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */ | ||
428 | #define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */ | ||
429 | #define MDMA_S0_NEXT_DESC_PTR 0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ | ||
430 | #define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */ | ||
431 | #define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */ | ||
432 | #define MDMA_S0_X_COUNT 0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */ | ||
433 | #define MDMA_S0_X_MODIFY 0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */ | ||
434 | #define MDMA_S0_Y_COUNT 0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */ | ||
435 | #define MDMA_S0_Y_MODIFY 0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */ | ||
436 | #define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ | ||
437 | #define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */ | ||
438 | #define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */ | ||
439 | #define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */ | ||
440 | #define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */ | ||
441 | #define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */ | ||
442 | |||
443 | /* MDMA Stream 1 Registers */ | ||
444 | |||
445 | #define MDMA_D1_NEXT_DESC_PTR 0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ | ||
446 | #define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */ | ||
447 | #define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */ | ||
448 | #define MDMA_D1_X_COUNT 0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */ | ||
449 | #define MDMA_D1_X_MODIFY 0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */ | ||
450 | #define MDMA_D1_Y_COUNT 0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */ | ||
451 | #define MDMA_D1_Y_MODIFY 0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */ | ||
452 | #define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ | ||
453 | #define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */ | ||
454 | #define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */ | ||
455 | #define MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */ | ||
456 | #define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */ | ||
457 | #define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */ | ||
458 | #define MDMA_S1_NEXT_DESC_PTR 0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ | ||
459 | #define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */ | ||
460 | #define MDMA_S1_CONFIG 0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */ | ||
461 | #define MDMA_S1_X_COUNT 0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */ | ||
462 | #define MDMA_S1_X_MODIFY 0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */ | ||
463 | #define MDMA_S1_Y_COUNT 0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */ | ||
464 | #define MDMA_S1_Y_MODIFY 0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */ | ||
465 | #define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ | ||
466 | #define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */ | ||
467 | #define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */ | ||
468 | #define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */ | ||
469 | #define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */ | ||
470 | #define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */ | ||
471 | |||
472 | /* UART3 Registers */ | ||
473 | |||
474 | #define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */ | ||
475 | #define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */ | ||
476 | #define UART3_GCTL 0xffc03108 /* Global Control Register */ | ||
477 | #define UART3_LCR 0xffc0310c /* Line Control Register */ | ||
478 | #define UART3_MCR 0xffc03110 /* Modem Control Register */ | ||
479 | #define UART3_LSR 0xffc03114 /* Line Status Register */ | ||
480 | #define UART3_MSR 0xffc03118 /* Modem Status Register */ | ||
481 | #define UART3_SCR 0xffc0311c /* Scratch Register */ | ||
482 | #define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */ | ||
483 | #define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */ | ||
484 | #define UART3_THR 0xffc03128 /* Transmit Hold Register */ | ||
485 | #define UART3_RBR 0xffc0312c /* Receive Buffer Register */ | ||
486 | |||
487 | /* EPPI1 Registers */ | ||
488 | |||
489 | #define EPPI1_STATUS 0xffc01300 /* EPPI1 Status Register */ | ||
490 | #define EPPI1_HCOUNT 0xffc01304 /* EPPI1 Horizontal Transfer Count Register */ | ||
491 | #define EPPI1_HDELAY 0xffc01308 /* EPPI1 Horizontal Delay Count Register */ | ||
492 | #define EPPI1_VCOUNT 0xffc0130c /* EPPI1 Vertical Transfer Count Register */ | ||
493 | #define EPPI1_VDELAY 0xffc01310 /* EPPI1 Vertical Delay Count Register */ | ||
494 | #define EPPI1_FRAME 0xffc01314 /* EPPI1 Lines per Frame Register */ | ||
495 | #define EPPI1_LINE 0xffc01318 /* EPPI1 Samples per Line Register */ | ||
496 | #define EPPI1_CLKDIV 0xffc0131c /* EPPI1 Clock Divide Register */ | ||
497 | #define EPPI1_CONTROL 0xffc01320 /* EPPI1 Control Register */ | ||
498 | #define EPPI1_FS1W_HBL 0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ | ||
499 | #define EPPI1_FS1P_AVPL 0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ | ||
500 | #define EPPI1_FS2W_LVB 0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ | ||
501 | #define EPPI1_FS2P_LAVF 0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ | ||
502 | #define EPPI1_CLIP 0xffc01334 /* EPPI1 Clipping Register */ | ||
503 | |||
504 | /* Port Interrupt 0 Registers (32-bit) */ | ||
505 | |||
506 | #define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */ | ||
507 | #define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */ | ||
508 | #define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */ | ||
509 | #define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */ | ||
510 | #define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */ | ||
511 | #define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */ | ||
512 | #define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */ | ||
513 | #define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */ | ||
514 | #define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */ | ||
515 | #define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */ | ||
516 | |||
517 | /* Port Interrupt 1 Registers (32-bit) */ | ||
518 | |||
519 | #define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */ | ||
520 | #define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */ | ||
521 | #define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */ | ||
522 | #define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */ | ||
523 | #define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */ | ||
524 | #define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */ | ||
525 | #define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */ | ||
526 | #define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */ | ||
527 | #define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */ | ||
528 | #define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */ | ||
529 | |||
530 | /* Port Interrupt 2 Registers (32-bit) */ | ||
531 | |||
532 | #define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */ | ||
533 | #define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */ | ||
534 | #define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */ | ||
535 | #define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */ | ||
536 | #define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */ | ||
537 | #define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */ | ||
538 | #define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */ | ||
539 | #define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */ | ||
540 | #define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */ | ||
541 | #define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */ | ||
542 | |||
543 | /* Port Interrupt 3 Registers (32-bit) */ | ||
544 | |||
545 | #define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */ | ||
546 | #define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */ | ||
547 | #define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */ | ||
548 | #define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */ | ||
549 | #define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */ | ||
550 | #define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */ | ||
551 | #define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */ | ||
552 | #define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */ | ||
553 | #define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */ | ||
554 | #define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */ | ||
555 | |||
556 | /* Port A Registers */ | ||
557 | |||
558 | #define PORTA_FER 0xffc014c0 /* Function Enable Register */ | ||
559 | #define PORTA 0xffc014c4 /* GPIO Data Register */ | ||
560 | #define PORTA_SET 0xffc014c8 /* GPIO Data Set Register */ | ||
561 | #define PORTA_CLEAR 0xffc014cc /* GPIO Data Clear Register */ | ||
562 | #define PORTA_DIR_SET 0xffc014d0 /* GPIO Direction Set Register */ | ||
563 | #define PORTA_DIR_CLEAR 0xffc014d4 /* GPIO Direction Clear Register */ | ||
564 | #define PORTA_INEN 0xffc014d8 /* GPIO Input Enable Register */ | ||
565 | #define PORTA_MUX 0xffc014dc /* Multiplexer Control Register */ | ||
566 | |||
567 | /* Port B Registers */ | ||
568 | |||
569 | #define PORTB_FER 0xffc014e0 /* Function Enable Register */ | ||
570 | #define PORTB 0xffc014e4 /* GPIO Data Register */ | ||
571 | #define PORTB_SET 0xffc014e8 /* GPIO Data Set Register */ | ||
572 | #define PORTB_CLEAR 0xffc014ec /* GPIO Data Clear Register */ | ||
573 | #define PORTB_DIR_SET 0xffc014f0 /* GPIO Direction Set Register */ | ||
574 | #define PORTB_DIR_CLEAR 0xffc014f4 /* GPIO Direction Clear Register */ | ||
575 | #define PORTB_INEN 0xffc014f8 /* GPIO Input Enable Register */ | ||
576 | #define PORTB_MUX 0xffc014fc /* Multiplexer Control Register */ | ||
577 | |||
578 | /* Port C Registers */ | ||
579 | |||
580 | #define PORTC_FER 0xffc01500 /* Function Enable Register */ | ||
581 | #define PORTC 0xffc01504 /* GPIO Data Register */ | ||
582 | #define PORTC_SET 0xffc01508 /* GPIO Data Set Register */ | ||
583 | #define PORTC_CLEAR 0xffc0150c /* GPIO Data Clear Register */ | ||
584 | #define PORTC_DIR_SET 0xffc01510 /* GPIO Direction Set Register */ | ||
585 | #define PORTC_DIR_CLEAR 0xffc01514 /* GPIO Direction Clear Register */ | ||
586 | #define PORTC_INEN 0xffc01518 /* GPIO Input Enable Register */ | ||
587 | #define PORTC_MUX 0xffc0151c /* Multiplexer Control Register */ | ||
588 | |||
589 | /* Port D Registers */ | ||
590 | |||
591 | #define PORTD_FER 0xffc01520 /* Function Enable Register */ | ||
592 | #define PORTD 0xffc01524 /* GPIO Data Register */ | ||
593 | #define PORTD_SET 0xffc01528 /* GPIO Data Set Register */ | ||
594 | #define PORTD_CLEAR 0xffc0152c /* GPIO Data Clear Register */ | ||
595 | #define PORTD_DIR_SET 0xffc01530 /* GPIO Direction Set Register */ | ||
596 | #define PORTD_DIR_CLEAR 0xffc01534 /* GPIO Direction Clear Register */ | ||
597 | #define PORTD_INEN 0xffc01538 /* GPIO Input Enable Register */ | ||
598 | #define PORTD_MUX 0xffc0153c /* Multiplexer Control Register */ | ||
599 | |||
600 | /* Port E Registers */ | ||
601 | |||
602 | #define PORTE_FER 0xffc01540 /* Function Enable Register */ | ||
603 | #define PORTE 0xffc01544 /* GPIO Data Register */ | ||
604 | #define PORTE_SET 0xffc01548 /* GPIO Data Set Register */ | ||
605 | #define PORTE_CLEAR 0xffc0154c /* GPIO Data Clear Register */ | ||
606 | #define PORTE_DIR_SET 0xffc01550 /* GPIO Direction Set Register */ | ||
607 | #define PORTE_DIR_CLEAR 0xffc01554 /* GPIO Direction Clear Register */ | ||
608 | #define PORTE_INEN 0xffc01558 /* GPIO Input Enable Register */ | ||
609 | #define PORTE_MUX 0xffc0155c /* Multiplexer Control Register */ | ||
610 | |||
611 | /* Port F Registers */ | ||
612 | |||
613 | #define PORTF_FER 0xffc01560 /* Function Enable Register */ | ||
614 | #define PORTF 0xffc01564 /* GPIO Data Register */ | ||
615 | #define PORTF_SET 0xffc01568 /* GPIO Data Set Register */ | ||
616 | #define PORTF_CLEAR 0xffc0156c /* GPIO Data Clear Register */ | ||
617 | #define PORTF_DIR_SET 0xffc01570 /* GPIO Direction Set Register */ | ||
618 | #define PORTF_DIR_CLEAR 0xffc01574 /* GPIO Direction Clear Register */ | ||
619 | #define PORTF_INEN 0xffc01578 /* GPIO Input Enable Register */ | ||
620 | #define PORTF_MUX 0xffc0157c /* Multiplexer Control Register */ | ||
621 | |||
622 | /* Port G Registers */ | ||
623 | |||
624 | #define PORTG_FER 0xffc01580 /* Function Enable Register */ | ||
625 | #define PORTG 0xffc01584 /* GPIO Data Register */ | ||
626 | #define PORTG_SET 0xffc01588 /* GPIO Data Set Register */ | ||
627 | #define PORTG_CLEAR 0xffc0158c /* GPIO Data Clear Register */ | ||
628 | #define PORTG_DIR_SET 0xffc01590 /* GPIO Direction Set Register */ | ||
629 | #define PORTG_DIR_CLEAR 0xffc01594 /* GPIO Direction Clear Register */ | ||
630 | #define PORTG_INEN 0xffc01598 /* GPIO Input Enable Register */ | ||
631 | #define PORTG_MUX 0xffc0159c /* Multiplexer Control Register */ | ||
632 | |||
633 | /* Port H Registers */ | ||
634 | |||
635 | #define PORTH_FER 0xffc015a0 /* Function Enable Register */ | ||
636 | #define PORTH 0xffc015a4 /* GPIO Data Register */ | ||
637 | #define PORTH_SET 0xffc015a8 /* GPIO Data Set Register */ | ||
638 | #define PORTH_CLEAR 0xffc015ac /* GPIO Data Clear Register */ | ||
639 | #define PORTH_DIR_SET 0xffc015b0 /* GPIO Direction Set Register */ | ||
640 | #define PORTH_DIR_CLEAR 0xffc015b4 /* GPIO Direction Clear Register */ | ||
641 | #define PORTH_INEN 0xffc015b8 /* GPIO Input Enable Register */ | ||
642 | #define PORTH_MUX 0xffc015bc /* Multiplexer Control Register */ | ||
643 | |||
644 | /* Port I Registers */ | ||
645 | |||
646 | #define PORTI_FER 0xffc015c0 /* Function Enable Register */ | ||
647 | #define PORTI 0xffc015c4 /* GPIO Data Register */ | ||
648 | #define PORTI_SET 0xffc015c8 /* GPIO Data Set Register */ | ||
649 | #define PORTI_CLEAR 0xffc015cc /* GPIO Data Clear Register */ | ||
650 | #define PORTI_DIR_SET 0xffc015d0 /* GPIO Direction Set Register */ | ||
651 | #define PORTI_DIR_CLEAR 0xffc015d4 /* GPIO Direction Clear Register */ | ||
652 | #define PORTI_INEN 0xffc015d8 /* GPIO Input Enable Register */ | ||
653 | #define PORTI_MUX 0xffc015dc /* Multiplexer Control Register */ | ||
654 | |||
655 | /* Port J Registers */ | ||
656 | |||
657 | #define PORTJ_FER 0xffc015e0 /* Function Enable Register */ | ||
658 | #define PORTJ 0xffc015e4 /* GPIO Data Register */ | ||
659 | #define PORTJ_SET 0xffc015e8 /* GPIO Data Set Register */ | ||
660 | #define PORTJ_CLEAR 0xffc015ec /* GPIO Data Clear Register */ | ||
661 | #define PORTJ_DIR_SET 0xffc015f0 /* GPIO Direction Set Register */ | ||
662 | #define PORTJ_DIR_CLEAR 0xffc015f4 /* GPIO Direction Clear Register */ | ||
663 | #define PORTJ_INEN 0xffc015f8 /* GPIO Input Enable Register */ | ||
664 | #define PORTJ_MUX 0xffc015fc /* Multiplexer Control Register */ | ||
665 | |||
666 | /* PWM Timer Registers */ | ||
667 | |||
668 | #define TIMER0_CONFIG 0xffc01600 /* Timer 0 Configuration Register */ | ||
669 | #define TIMER0_COUNTER 0xffc01604 /* Timer 0 Counter Register */ | ||
670 | #define TIMER0_PERIOD 0xffc01608 /* Timer 0 Period Register */ | ||
671 | #define TIMER0_WIDTH 0xffc0160c /* Timer 0 Width Register */ | ||
672 | #define TIMER1_CONFIG 0xffc01610 /* Timer 1 Configuration Register */ | ||
673 | #define TIMER1_COUNTER 0xffc01614 /* Timer 1 Counter Register */ | ||
674 | #define TIMER1_PERIOD 0xffc01618 /* Timer 1 Period Register */ | ||
675 | #define TIMER1_WIDTH 0xffc0161c /* Timer 1 Width Register */ | ||
676 | #define TIMER2_CONFIG 0xffc01620 /* Timer 2 Configuration Register */ | ||
677 | #define TIMER2_COUNTER 0xffc01624 /* Timer 2 Counter Register */ | ||
678 | #define TIMER2_PERIOD 0xffc01628 /* Timer 2 Period Register */ | ||
679 | #define TIMER2_WIDTH 0xffc0162c /* Timer 2 Width Register */ | ||
680 | #define TIMER3_CONFIG 0xffc01630 /* Timer 3 Configuration Register */ | ||
681 | #define TIMER3_COUNTER 0xffc01634 /* Timer 3 Counter Register */ | ||
682 | #define TIMER3_PERIOD 0xffc01638 /* Timer 3 Period Register */ | ||
683 | #define TIMER3_WIDTH 0xffc0163c /* Timer 3 Width Register */ | ||
684 | #define TIMER4_CONFIG 0xffc01640 /* Timer 4 Configuration Register */ | ||
685 | #define TIMER4_COUNTER 0xffc01644 /* Timer 4 Counter Register */ | ||
686 | #define TIMER4_PERIOD 0xffc01648 /* Timer 4 Period Register */ | ||
687 | #define TIMER4_WIDTH 0xffc0164c /* Timer 4 Width Register */ | ||
688 | #define TIMER5_CONFIG 0xffc01650 /* Timer 5 Configuration Register */ | ||
689 | #define TIMER5_COUNTER 0xffc01654 /* Timer 5 Counter Register */ | ||
690 | #define TIMER5_PERIOD 0xffc01658 /* Timer 5 Period Register */ | ||
691 | #define TIMER5_WIDTH 0xffc0165c /* Timer 5 Width Register */ | ||
692 | #define TIMER6_CONFIG 0xffc01660 /* Timer 6 Configuration Register */ | ||
693 | #define TIMER6_COUNTER 0xffc01664 /* Timer 6 Counter Register */ | ||
694 | #define TIMER6_PERIOD 0xffc01668 /* Timer 6 Period Register */ | ||
695 | #define TIMER6_WIDTH 0xffc0166c /* Timer 6 Width Register */ | ||
696 | #define TIMER7_CONFIG 0xffc01670 /* Timer 7 Configuration Register */ | ||
697 | #define TIMER7_COUNTER 0xffc01674 /* Timer 7 Counter Register */ | ||
698 | #define TIMER7_PERIOD 0xffc01678 /* Timer 7 Period Register */ | ||
699 | #define TIMER7_WIDTH 0xffc0167c /* Timer 7 Width Register */ | ||
700 | |||
701 | /* Timer Group of 8 */ | ||
702 | |||
703 | #define TIMER_ENABLE0 0xffc01680 /* Timer Group of 8 Enable Register */ | ||
704 | #define TIMER_DISABLE0 0xffc01684 /* Timer Group of 8 Disable Register */ | ||
705 | #define TIMER_STATUS0 0xffc01688 /* Timer Group of 8 Status Register */ | ||
706 | |||
707 | /* DMAC1 Registers */ | ||
708 | |||
709 | #define DMAC1_TCPER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */ | ||
710 | #define DMAC1_TCCNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */ | ||
711 | |||
712 | /* DMA Channel 12 Registers */ | ||
713 | |||
714 | #define DMA12_NEXT_DESC_PTR 0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */ | ||
715 | #define DMA12_START_ADDR 0xffc01c04 /* DMA Channel 12 Start Address Register */ | ||
716 | #define DMA12_CONFIG 0xffc01c08 /* DMA Channel 12 Configuration Register */ | ||
717 | #define DMA12_X_COUNT 0xffc01c10 /* DMA Channel 12 X Count Register */ | ||
718 | #define DMA12_X_MODIFY 0xffc01c14 /* DMA Channel 12 X Modify Register */ | ||
719 | #define DMA12_Y_COUNT 0xffc01c18 /* DMA Channel 12 Y Count Register */ | ||
720 | #define DMA12_Y_MODIFY 0xffc01c1c /* DMA Channel 12 Y Modify Register */ | ||
721 | #define DMA12_CURR_DESC_PTR 0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */ | ||
722 | #define DMA12_CURR_ADDR 0xffc01c24 /* DMA Channel 12 Current Address Register */ | ||
723 | #define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */ | ||
724 | #define DMA12_PERIPHERAL_MAP 0xffc01c2c /* DMA Channel 12 Peripheral Map Register */ | ||
725 | #define DMA12_CURR_X_COUNT 0xffc01c30 /* DMA Channel 12 Current X Count Register */ | ||
726 | #define DMA12_CURR_Y_COUNT 0xffc01c38 /* DMA Channel 12 Current Y Count Register */ | ||
727 | |||
728 | /* DMA Channel 13 Registers */ | ||
729 | |||
730 | #define DMA13_NEXT_DESC_PTR 0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */ | ||
731 | #define DMA13_START_ADDR 0xffc01c44 /* DMA Channel 13 Start Address Register */ | ||
732 | #define DMA13_CONFIG 0xffc01c48 /* DMA Channel 13 Configuration Register */ | ||
733 | #define DMA13_X_COUNT 0xffc01c50 /* DMA Channel 13 X Count Register */ | ||
734 | #define DMA13_X_MODIFY 0xffc01c54 /* DMA Channel 13 X Modify Register */ | ||
735 | #define DMA13_Y_COUNT 0xffc01c58 /* DMA Channel 13 Y Count Register */ | ||
736 | #define DMA13_Y_MODIFY 0xffc01c5c /* DMA Channel 13 Y Modify Register */ | ||
737 | #define DMA13_CURR_DESC_PTR 0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */ | ||
738 | #define DMA13_CURR_ADDR 0xffc01c64 /* DMA Channel 13 Current Address Register */ | ||
739 | #define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */ | ||
740 | #define DMA13_PERIPHERAL_MAP 0xffc01c6c /* DMA Channel 13 Peripheral Map Register */ | ||
741 | #define DMA13_CURR_X_COUNT 0xffc01c70 /* DMA Channel 13 Current X Count Register */ | ||
742 | #define DMA13_CURR_Y_COUNT 0xffc01c78 /* DMA Channel 13 Current Y Count Register */ | ||
743 | |||
744 | /* DMA Channel 14 Registers */ | ||
745 | |||
746 | #define DMA14_NEXT_DESC_PTR 0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */ | ||
747 | #define DMA14_START_ADDR 0xffc01c84 /* DMA Channel 14 Start Address Register */ | ||
748 | #define DMA14_CONFIG 0xffc01c88 /* DMA Channel 14 Configuration Register */ | ||
749 | #define DMA14_X_COUNT 0xffc01c90 /* DMA Channel 14 X Count Register */ | ||
750 | #define DMA14_X_MODIFY 0xffc01c94 /* DMA Channel 14 X Modify Register */ | ||
751 | #define DMA14_Y_COUNT 0xffc01c98 /* DMA Channel 14 Y Count Register */ | ||
752 | #define DMA14_Y_MODIFY 0xffc01c9c /* DMA Channel 14 Y Modify Register */ | ||
753 | #define DMA14_CURR_DESC_PTR 0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */ | ||
754 | #define DMA14_CURR_ADDR 0xffc01ca4 /* DMA Channel 14 Current Address Register */ | ||
755 | #define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */ | ||
756 | #define DMA14_PERIPHERAL_MAP 0xffc01cac /* DMA Channel 14 Peripheral Map Register */ | ||
757 | #define DMA14_CURR_X_COUNT 0xffc01cb0 /* DMA Channel 14 Current X Count Register */ | ||
758 | #define DMA14_CURR_Y_COUNT 0xffc01cb8 /* DMA Channel 14 Current Y Count Register */ | ||
759 | |||
760 | /* DMA Channel 15 Registers */ | ||
761 | |||
762 | #define DMA15_NEXT_DESC_PTR 0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */ | ||
763 | #define DMA15_START_ADDR 0xffc01cc4 /* DMA Channel 15 Start Address Register */ | ||
764 | #define DMA15_CONFIG 0xffc01cc8 /* DMA Channel 15 Configuration Register */ | ||
765 | #define DMA15_X_COUNT 0xffc01cd0 /* DMA Channel 15 X Count Register */ | ||
766 | #define DMA15_X_MODIFY 0xffc01cd4 /* DMA Channel 15 X Modify Register */ | ||
767 | #define DMA15_Y_COUNT 0xffc01cd8 /* DMA Channel 15 Y Count Register */ | ||
768 | #define DMA15_Y_MODIFY 0xffc01cdc /* DMA Channel 15 Y Modify Register */ | ||
769 | #define DMA15_CURR_DESC_PTR 0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */ | ||
770 | #define DMA15_CURR_ADDR 0xffc01ce4 /* DMA Channel 15 Current Address Register */ | ||
771 | #define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */ | ||
772 | #define DMA15_PERIPHERAL_MAP 0xffc01cec /* DMA Channel 15 Peripheral Map Register */ | ||
773 | #define DMA15_CURR_X_COUNT 0xffc01cf0 /* DMA Channel 15 Current X Count Register */ | ||
774 | #define DMA15_CURR_Y_COUNT 0xffc01cf8 /* DMA Channel 15 Current Y Count Register */ | ||
775 | |||
776 | /* DMA Channel 16 Registers */ | ||
777 | |||
778 | #define DMA16_NEXT_DESC_PTR 0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */ | ||
779 | #define DMA16_START_ADDR 0xffc01d04 /* DMA Channel 16 Start Address Register */ | ||
780 | #define DMA16_CONFIG 0xffc01d08 /* DMA Channel 16 Configuration Register */ | ||
781 | #define DMA16_X_COUNT 0xffc01d10 /* DMA Channel 16 X Count Register */ | ||
782 | #define DMA16_X_MODIFY 0xffc01d14 /* DMA Channel 16 X Modify Register */ | ||
783 | #define DMA16_Y_COUNT 0xffc01d18 /* DMA Channel 16 Y Count Register */ | ||
784 | #define DMA16_Y_MODIFY 0xffc01d1c /* DMA Channel 16 Y Modify Register */ | ||
785 | #define DMA16_CURR_DESC_PTR 0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */ | ||
786 | #define DMA16_CURR_ADDR 0xffc01d24 /* DMA Channel 16 Current Address Register */ | ||
787 | #define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */ | ||
788 | #define DMA16_PERIPHERAL_MAP 0xffc01d2c /* DMA Channel 16 Peripheral Map Register */ | ||
789 | #define DMA16_CURR_X_COUNT 0xffc01d30 /* DMA Channel 16 Current X Count Register */ | ||
790 | #define DMA16_CURR_Y_COUNT 0xffc01d38 /* DMA Channel 16 Current Y Count Register */ | ||
791 | |||
792 | /* DMA Channel 17 Registers */ | ||
793 | |||
794 | #define DMA17_NEXT_DESC_PTR 0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */ | ||
795 | #define DMA17_START_ADDR 0xffc01d44 /* DMA Channel 17 Start Address Register */ | ||
796 | #define DMA17_CONFIG 0xffc01d48 /* DMA Channel 17 Configuration Register */ | ||
797 | #define DMA17_X_COUNT 0xffc01d50 /* DMA Channel 17 X Count Register */ | ||
798 | #define DMA17_X_MODIFY 0xffc01d54 /* DMA Channel 17 X Modify Register */ | ||
799 | #define DMA17_Y_COUNT 0xffc01d58 /* DMA Channel 17 Y Count Register */ | ||
800 | #define DMA17_Y_MODIFY 0xffc01d5c /* DMA Channel 17 Y Modify Register */ | ||
801 | #define DMA17_CURR_DESC_PTR 0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */ | ||
802 | #define DMA17_CURR_ADDR 0xffc01d64 /* DMA Channel 17 Current Address Register */ | ||
803 | #define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */ | ||
804 | #define DMA17_PERIPHERAL_MAP 0xffc01d6c /* DMA Channel 17 Peripheral Map Register */ | ||
805 | #define DMA17_CURR_X_COUNT 0xffc01d70 /* DMA Channel 17 Current X Count Register */ | ||
806 | #define DMA17_CURR_Y_COUNT 0xffc01d78 /* DMA Channel 17 Current Y Count Register */ | ||
807 | |||
808 | /* DMA Channel 18 Registers */ | ||
809 | |||
810 | #define DMA18_NEXT_DESC_PTR 0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */ | ||
811 | #define DMA18_START_ADDR 0xffc01d84 /* DMA Channel 18 Start Address Register */ | ||
812 | #define DMA18_CONFIG 0xffc01d88 /* DMA Channel 18 Configuration Register */ | ||
813 | #define DMA18_X_COUNT 0xffc01d90 /* DMA Channel 18 X Count Register */ | ||
814 | #define DMA18_X_MODIFY 0xffc01d94 /* DMA Channel 18 X Modify Register */ | ||
815 | #define DMA18_Y_COUNT 0xffc01d98 /* DMA Channel 18 Y Count Register */ | ||
816 | #define DMA18_Y_MODIFY 0xffc01d9c /* DMA Channel 18 Y Modify Register */ | ||
817 | #define DMA18_CURR_DESC_PTR 0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */ | ||
818 | #define DMA18_CURR_ADDR 0xffc01da4 /* DMA Channel 18 Current Address Register */ | ||
819 | #define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */ | ||
820 | #define DMA18_PERIPHERAL_MAP 0xffc01dac /* DMA Channel 18 Peripheral Map Register */ | ||
821 | #define DMA18_CURR_X_COUNT 0xffc01db0 /* DMA Channel 18 Current X Count Register */ | ||
822 | #define DMA18_CURR_Y_COUNT 0xffc01db8 /* DMA Channel 18 Current Y Count Register */ | ||
823 | |||
824 | /* DMA Channel 19 Registers */ | ||
825 | |||
826 | #define DMA19_NEXT_DESC_PTR 0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */ | ||
827 | #define DMA19_START_ADDR 0xffc01dc4 /* DMA Channel 19 Start Address Register */ | ||
828 | #define DMA19_CONFIG 0xffc01dc8 /* DMA Channel 19 Configuration Register */ | ||
829 | #define DMA19_X_COUNT 0xffc01dd0 /* DMA Channel 19 X Count Register */ | ||
830 | #define DMA19_X_MODIFY 0xffc01dd4 /* DMA Channel 19 X Modify Register */ | ||
831 | #define DMA19_Y_COUNT 0xffc01dd8 /* DMA Channel 19 Y Count Register */ | ||
832 | #define DMA19_Y_MODIFY 0xffc01ddc /* DMA Channel 19 Y Modify Register */ | ||
833 | #define DMA19_CURR_DESC_PTR 0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */ | ||
834 | #define DMA19_CURR_ADDR 0xffc01de4 /* DMA Channel 19 Current Address Register */ | ||
835 | #define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */ | ||
836 | #define DMA19_PERIPHERAL_MAP 0xffc01dec /* DMA Channel 19 Peripheral Map Register */ | ||
837 | #define DMA19_CURR_X_COUNT 0xffc01df0 /* DMA Channel 19 Current X Count Register */ | ||
838 | #define DMA19_CURR_Y_COUNT 0xffc01df8 /* DMA Channel 19 Current Y Count Register */ | ||
839 | |||
840 | /* DMA Channel 20 Registers */ | ||
841 | |||
842 | #define DMA20_NEXT_DESC_PTR 0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */ | ||
843 | #define DMA20_START_ADDR 0xffc01e04 /* DMA Channel 20 Start Address Register */ | ||
844 | #define DMA20_CONFIG 0xffc01e08 /* DMA Channel 20 Configuration Register */ | ||
845 | #define DMA20_X_COUNT 0xffc01e10 /* DMA Channel 20 X Count Register */ | ||
846 | #define DMA20_X_MODIFY 0xffc01e14 /* DMA Channel 20 X Modify Register */ | ||
847 | #define DMA20_Y_COUNT 0xffc01e18 /* DMA Channel 20 Y Count Register */ | ||
848 | #define DMA20_Y_MODIFY 0xffc01e1c /* DMA Channel 20 Y Modify Register */ | ||
849 | #define DMA20_CURR_DESC_PTR 0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */ | ||
850 | #define DMA20_CURR_ADDR 0xffc01e24 /* DMA Channel 20 Current Address Register */ | ||
851 | #define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */ | ||
852 | #define DMA20_PERIPHERAL_MAP 0xffc01e2c /* DMA Channel 20 Peripheral Map Register */ | ||
853 | #define DMA20_CURR_X_COUNT 0xffc01e30 /* DMA Channel 20 Current X Count Register */ | ||
854 | #define DMA20_CURR_Y_COUNT 0xffc01e38 /* DMA Channel 20 Current Y Count Register */ | ||
855 | |||
856 | /* DMA Channel 21 Registers */ | ||
857 | |||
858 | #define DMA21_NEXT_DESC_PTR 0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */ | ||
859 | #define DMA21_START_ADDR 0xffc01e44 /* DMA Channel 21 Start Address Register */ | ||
860 | #define DMA21_CONFIG 0xffc01e48 /* DMA Channel 21 Configuration Register */ | ||
861 | #define DMA21_X_COUNT 0xffc01e50 /* DMA Channel 21 X Count Register */ | ||
862 | #define DMA21_X_MODIFY 0xffc01e54 /* DMA Channel 21 X Modify Register */ | ||
863 | #define DMA21_Y_COUNT 0xffc01e58 /* DMA Channel 21 Y Count Register */ | ||
864 | #define DMA21_Y_MODIFY 0xffc01e5c /* DMA Channel 21 Y Modify Register */ | ||
865 | #define DMA21_CURR_DESC_PTR 0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */ | ||
866 | #define DMA21_CURR_ADDR 0xffc01e64 /* DMA Channel 21 Current Address Register */ | ||
867 | #define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */ | ||
868 | #define DMA21_PERIPHERAL_MAP 0xffc01e6c /* DMA Channel 21 Peripheral Map Register */ | ||
869 | #define DMA21_CURR_X_COUNT 0xffc01e70 /* DMA Channel 21 Current X Count Register */ | ||
870 | #define DMA21_CURR_Y_COUNT 0xffc01e78 /* DMA Channel 21 Current Y Count Register */ | ||
871 | |||
872 | /* DMA Channel 22 Registers */ | ||
873 | |||
874 | #define DMA22_NEXT_DESC_PTR 0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */ | ||
875 | #define DMA22_START_ADDR 0xffc01e84 /* DMA Channel 22 Start Address Register */ | ||
876 | #define DMA22_CONFIG 0xffc01e88 /* DMA Channel 22 Configuration Register */ | ||
877 | #define DMA22_X_COUNT 0xffc01e90 /* DMA Channel 22 X Count Register */ | ||
878 | #define DMA22_X_MODIFY 0xffc01e94 /* DMA Channel 22 X Modify Register */ | ||
879 | #define DMA22_Y_COUNT 0xffc01e98 /* DMA Channel 22 Y Count Register */ | ||
880 | #define DMA22_Y_MODIFY 0xffc01e9c /* DMA Channel 22 Y Modify Register */ | ||
881 | #define DMA22_CURR_DESC_PTR 0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */ | ||
882 | #define DMA22_CURR_ADDR 0xffc01ea4 /* DMA Channel 22 Current Address Register */ | ||
883 | #define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */ | ||
884 | #define DMA22_PERIPHERAL_MAP 0xffc01eac /* DMA Channel 22 Peripheral Map Register */ | ||
885 | #define DMA22_CURR_X_COUNT 0xffc01eb0 /* DMA Channel 22 Current X Count Register */ | ||
886 | #define DMA22_CURR_Y_COUNT 0xffc01eb8 /* DMA Channel 22 Current Y Count Register */ | ||
887 | |||
888 | /* DMA Channel 23 Registers */ | ||
889 | |||
890 | #define DMA23_NEXT_DESC_PTR 0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */ | ||
891 | #define DMA23_START_ADDR 0xffc01ec4 /* DMA Channel 23 Start Address Register */ | ||
892 | #define DMA23_CONFIG 0xffc01ec8 /* DMA Channel 23 Configuration Register */ | ||
893 | #define DMA23_X_COUNT 0xffc01ed0 /* DMA Channel 23 X Count Register */ | ||
894 | #define DMA23_X_MODIFY 0xffc01ed4 /* DMA Channel 23 X Modify Register */ | ||
895 | #define DMA23_Y_COUNT 0xffc01ed8 /* DMA Channel 23 Y Count Register */ | ||
896 | #define DMA23_Y_MODIFY 0xffc01edc /* DMA Channel 23 Y Modify Register */ | ||
897 | #define DMA23_CURR_DESC_PTR 0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */ | ||
898 | #define DMA23_CURR_ADDR 0xffc01ee4 /* DMA Channel 23 Current Address Register */ | ||
899 | #define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */ | ||
900 | #define DMA23_PERIPHERAL_MAP 0xffc01eec /* DMA Channel 23 Peripheral Map Register */ | ||
901 | #define DMA23_CURR_X_COUNT 0xffc01ef0 /* DMA Channel 23 Current X Count Register */ | ||
902 | #define DMA23_CURR_Y_COUNT 0xffc01ef8 /* DMA Channel 23 Current Y Count Register */ | ||
903 | |||
904 | /* MDMA Stream 2 Registers */ | ||
905 | |||
906 | #define MDMA_D2_NEXT_DESC_PTR 0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ | ||
907 | #define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */ | ||
908 | #define MDMA_D2_CONFIG 0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */ | ||
909 | #define MDMA_D2_X_COUNT 0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */ | ||
910 | #define MDMA_D2_X_MODIFY 0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */ | ||
911 | #define MDMA_D2_Y_COUNT 0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */ | ||
912 | #define MDMA_D2_Y_MODIFY 0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */ | ||
913 | #define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ | ||
914 | #define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */ | ||
915 | #define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */ | ||
916 | #define MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */ | ||
917 | #define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */ | ||
918 | #define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */ | ||
919 | #define MDMA_S2_NEXT_DESC_PTR 0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ | ||
920 | #define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */ | ||
921 | #define MDMA_S2_CONFIG 0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */ | ||
922 | #define MDMA_S2_X_COUNT 0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */ | ||
923 | #define MDMA_S2_X_MODIFY 0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */ | ||
924 | #define MDMA_S2_Y_COUNT 0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */ | ||
925 | #define MDMA_S2_Y_MODIFY 0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */ | ||
926 | #define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ | ||
927 | #define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */ | ||
928 | #define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */ | ||
929 | #define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */ | ||
930 | #define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */ | ||
931 | #define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */ | ||
932 | |||
933 | /* MDMA Stream 3 Registers */ | ||
934 | |||
935 | #define MDMA_D3_NEXT_DESC_PTR 0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ | ||
936 | #define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */ | ||
937 | #define MDMA_D3_CONFIG 0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */ | ||
938 | #define MDMA_D3_X_COUNT 0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */ | ||
939 | #define MDMA_D3_X_MODIFY 0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */ | ||
940 | #define MDMA_D3_Y_COUNT 0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */ | ||
941 | #define MDMA_D3_Y_MODIFY 0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */ | ||
942 | #define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ | ||
943 | #define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */ | ||
944 | #define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */ | ||
945 | #define MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */ | ||
946 | #define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */ | ||
947 | #define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */ | ||
948 | #define MDMA_S3_NEXT_DESC_PTR 0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ | ||
949 | #define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */ | ||
950 | #define MDMA_S3_CONFIG 0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */ | ||
951 | #define MDMA_S3_X_COUNT 0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */ | ||
952 | #define MDMA_S3_X_MODIFY 0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */ | ||
953 | #define MDMA_S3_Y_COUNT 0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */ | ||
954 | #define MDMA_S3_Y_MODIFY 0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */ | ||
955 | #define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ | ||
956 | #define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */ | ||
957 | #define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */ | ||
958 | #define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */ | ||
959 | #define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */ | ||
960 | #define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */ | ||
961 | |||
962 | /* UART1 Registers */ | ||
963 | |||
964 | #define UART1_DLL 0xffc02000 /* Divisor Latch Low Byte */ | ||
965 | #define UART1_DLH 0xffc02004 /* Divisor Latch High Byte */ | ||
966 | #define UART1_GCTL 0xffc02008 /* Global Control Register */ | ||
967 | #define UART1_LCR 0xffc0200c /* Line Control Register */ | ||
968 | #define UART1_MCR 0xffc02010 /* Modem Control Register */ | ||
969 | #define UART1_LSR 0xffc02014 /* Line Status Register */ | ||
970 | #define UART1_MSR 0xffc02018 /* Modem Status Register */ | ||
971 | #define UART1_SCR 0xffc0201c /* Scratch Register */ | ||
972 | #define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */ | ||
973 | #define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */ | ||
974 | #define UART1_THR 0xffc02028 /* Transmit Hold Register */ | ||
975 | #define UART1_RBR 0xffc0202c /* Receive Buffer Register */ | ||
976 | |||
977 | /* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */ | ||
978 | |||
979 | /* SPI1 Registers */ | ||
980 | |||
981 | #define SPI1_CTL 0xffc02300 /* SPI1 Control Register */ | ||
982 | #define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */ | ||
983 | #define SPI1_STAT 0xffc02308 /* SPI1 Status Register */ | ||
984 | #define SPI1_TDBR 0xffc0230c /* SPI1 Transmit Data Buffer Register */ | ||
985 | #define SPI1_RDBR 0xffc02310 /* SPI1 Receive Data Buffer Register */ | ||
986 | #define SPI1_BAUD 0xffc02314 /* SPI1 Baud Rate Register */ | ||
987 | #define SPI1_SHADOW 0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */ | ||
988 | |||
989 | /* SPORT2 Registers */ | ||
990 | |||
991 | #define SPORT2_TCR1 0xffc02500 /* SPORT2 Transmit Configuration 1 Register */ | ||
992 | #define SPORT2_TCR2 0xffc02504 /* SPORT2 Transmit Configuration 2 Register */ | ||
993 | #define SPORT2_TCLKDIV 0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */ | ||
994 | #define SPORT2_TFSDIV 0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */ | ||
995 | #define SPORT2_TX 0xffc02510 /* SPORT2 Transmit Data Register */ | ||
996 | #define SPORT2_RX 0xffc02518 /* SPORT2 Receive Data Register */ | ||
997 | #define SPORT2_RCR1 0xffc02520 /* SPORT2 Receive Configuration 1 Register */ | ||
998 | #define SPORT2_RCR2 0xffc02524 /* SPORT2 Receive Configuration 2 Register */ | ||
999 | #define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */ | ||
1000 | #define SPORT2_RFSDIV 0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */ | ||
1001 | #define SPORT2_STAT 0xffc02530 /* SPORT2 Status Register */ | ||
1002 | #define SPORT2_CHNL 0xffc02534 /* SPORT2 Current Channel Register */ | ||
1003 | #define SPORT2_MCMC1 0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */ | ||
1004 | #define SPORT2_MCMC2 0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */ | ||
1005 | #define SPORT2_MTCS0 0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */ | ||
1006 | #define SPORT2_MTCS1 0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */ | ||
1007 | #define SPORT2_MTCS2 0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */ | ||
1008 | #define SPORT2_MTCS3 0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */ | ||
1009 | #define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */ | ||
1010 | #define SPORT2_MRCS1 0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */ | ||
1011 | #define SPORT2_MRCS2 0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */ | ||
1012 | #define SPORT2_MRCS3 0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */ | ||
1013 | |||
1014 | /* SPORT3 Registers */ | ||
1015 | |||
1016 | #define SPORT3_TCR1 0xffc02600 /* SPORT3 Transmit Configuration 1 Register */ | ||
1017 | #define SPORT3_TCR2 0xffc02604 /* SPORT3 Transmit Configuration 2 Register */ | ||
1018 | #define SPORT3_TCLKDIV 0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */ | ||
1019 | #define SPORT3_TFSDIV 0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */ | ||
1020 | #define SPORT3_TX 0xffc02610 /* SPORT3 Transmit Data Register */ | ||
1021 | #define SPORT3_RX 0xffc02618 /* SPORT3 Receive Data Register */ | ||
1022 | #define SPORT3_RCR1 0xffc02620 /* SPORT3 Receive Configuration 1 Register */ | ||
1023 | #define SPORT3_RCR2 0xffc02624 /* SPORT3 Receive Configuration 2 Register */ | ||
1024 | #define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */ | ||
1025 | #define SPORT3_RFSDIV 0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */ | ||
1026 | #define SPORT3_STAT 0xffc02630 /* SPORT3 Status Register */ | ||
1027 | #define SPORT3_CHNL 0xffc02634 /* SPORT3 Current Channel Register */ | ||
1028 | #define SPORT3_MCMC1 0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */ | ||
1029 | #define SPORT3_MCMC2 0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */ | ||
1030 | #define SPORT3_MTCS0 0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */ | ||
1031 | #define SPORT3_MTCS1 0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */ | ||
1032 | #define SPORT3_MTCS2 0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */ | ||
1033 | #define SPORT3_MTCS3 0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */ | ||
1034 | #define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */ | ||
1035 | #define SPORT3_MRCS1 0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */ | ||
1036 | #define SPORT3_MRCS2 0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */ | ||
1037 | #define SPORT3_MRCS3 0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */ | ||
1038 | |||
1039 | /* EPPI2 Registers */ | ||
1040 | |||
1041 | #define EPPI2_STATUS 0xffc02900 /* EPPI2 Status Register */ | ||
1042 | #define EPPI2_HCOUNT 0xffc02904 /* EPPI2 Horizontal Transfer Count Register */ | ||
1043 | #define EPPI2_HDELAY 0xffc02908 /* EPPI2 Horizontal Delay Count Register */ | ||
1044 | #define EPPI2_VCOUNT 0xffc0290c /* EPPI2 Vertical Transfer Count Register */ | ||
1045 | #define EPPI2_VDELAY 0xffc02910 /* EPPI2 Vertical Delay Count Register */ | ||
1046 | #define EPPI2_FRAME 0xffc02914 /* EPPI2 Lines per Frame Register */ | ||
1047 | #define EPPI2_LINE 0xffc02918 /* EPPI2 Samples per Line Register */ | ||
1048 | #define EPPI2_CLKDIV 0xffc0291c /* EPPI2 Clock Divide Register */ | ||
1049 | #define EPPI2_CONTROL 0xffc02920 /* EPPI2 Control Register */ | ||
1050 | #define EPPI2_FS1W_HBL 0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ | ||
1051 | #define EPPI2_FS1P_AVPL 0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ | ||
1052 | #define EPPI2_FS2W_LVB 0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ | ||
1053 | #define EPPI2_FS2P_LAVF 0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ | ||
1054 | #define EPPI2_CLIP 0xffc02934 /* EPPI2 Clipping Register */ | ||
1055 | |||
1056 | /* CAN Controller 0 Config 1 Registers */ | ||
1057 | |||
1058 | #define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */ | ||
1059 | #define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */ | ||
1060 | #define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */ | ||
1061 | #define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */ | ||
1062 | #define CAN0_TA1 0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */ | ||
1063 | #define CAN0_AA1 0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */ | ||
1064 | #define CAN0_RMP1 0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */ | ||
1065 | #define CAN0_RML1 0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */ | ||
1066 | #define CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ | ||
1067 | #define CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ | ||
1068 | #define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ | ||
1069 | #define CAN0_RFH1 0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ | ||
1070 | #define CAN0_OPSS1 0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ | ||
1071 | |||
1072 | /* CAN Controller 0 Config 2 Registers */ | ||
1073 | |||
1074 | #define CAN0_MC2 0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */ | ||
1075 | #define CAN0_MD2 0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */ | ||
1076 | #define CAN0_TRS2 0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */ | ||
1077 | #define CAN0_TRR2 0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */ | ||
1078 | #define CAN0_TA2 0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */ | ||
1079 | #define CAN0_AA2 0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */ | ||
1080 | #define CAN0_RMP2 0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */ | ||
1081 | #define CAN0_RML2 0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */ | ||
1082 | #define CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ | ||
1083 | #define CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ | ||
1084 | #define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ | ||
1085 | #define CAN0_RFH2 0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ | ||
1086 | #define CAN0_OPSS2 0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ | ||
1087 | |||
1088 | /* CAN Controller 0 Clock/Interrupt/Counter Registers */ | ||
1089 | |||
1090 | #define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */ | ||
1091 | #define CAN0_TIMING 0xffc02a84 /* CAN Controller 0 Timing Register */ | ||
1092 | #define CAN0_DEBUG 0xffc02a88 /* CAN Controller 0 Debug Register */ | ||
1093 | #define CAN0_STATUS 0xffc02a8c /* CAN Controller 0 Global Status Register */ | ||
1094 | #define CAN0_CEC 0xffc02a90 /* CAN Controller 0 Error Counter Register */ | ||
1095 | #define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */ | ||
1096 | #define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */ | ||
1097 | #define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */ | ||
1098 | #define CAN0_CONTROL 0xffc02aa0 /* CAN Controller 0 Master Control Register */ | ||
1099 | #define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */ | ||
1100 | #define CAN0_MBTD 0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */ | ||
1101 | #define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */ | ||
1102 | #define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */ | ||
1103 | #define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Register */ | ||
1104 | #define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */ | ||
1105 | #define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */ | ||
1106 | |||
1107 | /* CAN Controller 0 Acceptance Registers */ | ||
1108 | |||
1109 | #define CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ | ||
1110 | #define CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ | ||
1111 | #define CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ | ||
1112 | #define CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ | ||
1113 | #define CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ | ||
1114 | #define CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ | ||
1115 | #define CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ | ||
1116 | #define CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ | ||
1117 | #define CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ | ||
1118 | #define CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ | ||
1119 | #define CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ | ||
1120 | #define CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ | ||
1121 | #define CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ | ||
1122 | #define CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ | ||
1123 | #define CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ | ||
1124 | #define CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ | ||
1125 | #define CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ | ||
1126 | #define CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ | ||
1127 | #define CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ | ||
1128 | #define CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ | ||
1129 | #define CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ | ||
1130 | #define CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ | ||
1131 | #define CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ | ||
1132 | #define CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ | ||
1133 | #define CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ | ||
1134 | #define CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ | ||
1135 | #define CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ | ||
1136 | #define CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ | ||
1137 | #define CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ | ||
1138 | #define CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ | ||
1139 | #define CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ | ||
1140 | #define CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ | ||
1141 | |||
1142 | /* CAN Controller 0 Acceptance Registers */ | ||
1143 | |||
1144 | #define CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ | ||
1145 | #define CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ | ||
1146 | #define CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ | ||
1147 | #define CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ | ||
1148 | #define CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ | ||
1149 | #define CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ | ||
1150 | #define CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ | ||
1151 | #define CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ | ||
1152 | #define CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ | ||
1153 | #define CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ | ||
1154 | #define CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ | ||
1155 | #define CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ | ||
1156 | #define CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ | ||
1157 | #define CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ | ||
1158 | #define CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ | ||
1159 | #define CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ | ||
1160 | #define CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ | ||
1161 | #define CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ | ||
1162 | #define CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ | ||
1163 | #define CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ | ||
1164 | #define CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ | ||
1165 | #define CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ | ||
1166 | #define CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ | ||
1167 | #define CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ | ||
1168 | #define CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ | ||
1169 | #define CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ | ||
1170 | #define CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ | ||
1171 | #define CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ | ||
1172 | #define CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ | ||
1173 | #define CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ | ||
1174 | #define CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ | ||
1175 | #define CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ | ||
1176 | |||
1177 | /* CAN Controller 0 Mailbox Data Registers */ | ||
1178 | |||
1179 | #define CAN0_MB00_DATA0 0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */ | ||
1180 | #define CAN0_MB00_DATA1 0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */ | ||
1181 | #define CAN0_MB00_DATA2 0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */ | ||
1182 | #define CAN0_MB00_DATA3 0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */ | ||
1183 | #define CAN0_MB00_LENGTH 0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */ | ||
1184 | #define CAN0_MB00_TIMESTAMP 0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */ | ||
1185 | #define CAN0_MB00_ID0 0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */ | ||
1186 | #define CAN0_MB00_ID1 0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */ | ||
1187 | #define CAN0_MB01_DATA0 0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */ | ||
1188 | #define CAN0_MB01_DATA1 0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */ | ||
1189 | #define CAN0_MB01_DATA2 0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */ | ||
1190 | #define CAN0_MB01_DATA3 0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */ | ||
1191 | #define CAN0_MB01_LENGTH 0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */ | ||
1192 | #define CAN0_MB01_TIMESTAMP 0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */ | ||
1193 | #define CAN0_MB01_ID0 0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */ | ||
1194 | #define CAN0_MB01_ID1 0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */ | ||
1195 | #define CAN0_MB02_DATA0 0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */ | ||
1196 | #define CAN0_MB02_DATA1 0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */ | ||
1197 | #define CAN0_MB02_DATA2 0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */ | ||
1198 | #define CAN0_MB02_DATA3 0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */ | ||
1199 | #define CAN0_MB02_LENGTH 0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */ | ||
1200 | #define CAN0_MB02_TIMESTAMP 0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */ | ||
1201 | #define CAN0_MB02_ID0 0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */ | ||
1202 | #define CAN0_MB02_ID1 0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */ | ||
1203 | #define CAN0_MB03_DATA0 0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */ | ||
1204 | #define CAN0_MB03_DATA1 0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */ | ||
1205 | #define CAN0_MB03_DATA2 0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */ | ||
1206 | #define CAN0_MB03_DATA3 0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */ | ||
1207 | #define CAN0_MB03_LENGTH 0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */ | ||
1208 | #define CAN0_MB03_TIMESTAMP 0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */ | ||
1209 | #define CAN0_MB03_ID0 0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */ | ||
1210 | #define CAN0_MB03_ID1 0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */ | ||
1211 | #define CAN0_MB04_DATA0 0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */ | ||
1212 | #define CAN0_MB04_DATA1 0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */ | ||
1213 | #define CAN0_MB04_DATA2 0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */ | ||
1214 | #define CAN0_MB04_DATA3 0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */ | ||
1215 | #define CAN0_MB04_LENGTH 0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */ | ||
1216 | #define CAN0_MB04_TIMESTAMP 0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */ | ||
1217 | #define CAN0_MB04_ID0 0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */ | ||
1218 | #define CAN0_MB04_ID1 0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */ | ||
1219 | #define CAN0_MB05_DATA0 0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */ | ||
1220 | #define CAN0_MB05_DATA1 0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */ | ||
1221 | #define CAN0_MB05_DATA2 0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */ | ||
1222 | #define CAN0_MB05_DATA3 0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */ | ||
1223 | #define CAN0_MB05_LENGTH 0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */ | ||
1224 | #define CAN0_MB05_TIMESTAMP 0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */ | ||
1225 | #define CAN0_MB05_ID0 0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */ | ||
1226 | #define CAN0_MB05_ID1 0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */ | ||
1227 | #define CAN0_MB06_DATA0 0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */ | ||
1228 | #define CAN0_MB06_DATA1 0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */ | ||
1229 | #define CAN0_MB06_DATA2 0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */ | ||
1230 | #define CAN0_MB06_DATA3 0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */ | ||
1231 | #define CAN0_MB06_LENGTH 0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */ | ||
1232 | #define CAN0_MB06_TIMESTAMP 0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */ | ||
1233 | #define CAN0_MB06_ID0 0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */ | ||
1234 | #define CAN0_MB06_ID1 0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */ | ||
1235 | #define CAN0_MB07_DATA0 0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */ | ||
1236 | #define CAN0_MB07_DATA1 0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */ | ||
1237 | #define CAN0_MB07_DATA2 0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */ | ||
1238 | #define CAN0_MB07_DATA3 0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */ | ||
1239 | #define CAN0_MB07_LENGTH 0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */ | ||
1240 | #define CAN0_MB07_TIMESTAMP 0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */ | ||
1241 | #define CAN0_MB07_ID0 0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */ | ||
1242 | #define CAN0_MB07_ID1 0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */ | ||
1243 | #define CAN0_MB08_DATA0 0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */ | ||
1244 | #define CAN0_MB08_DATA1 0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */ | ||
1245 | #define CAN0_MB08_DATA2 0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */ | ||
1246 | #define CAN0_MB08_DATA3 0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */ | ||
1247 | #define CAN0_MB08_LENGTH 0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */ | ||
1248 | #define CAN0_MB08_TIMESTAMP 0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */ | ||
1249 | #define CAN0_MB08_ID0 0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */ | ||
1250 | #define CAN0_MB08_ID1 0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */ | ||
1251 | #define CAN0_MB09_DATA0 0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */ | ||
1252 | #define CAN0_MB09_DATA1 0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */ | ||
1253 | #define CAN0_MB09_DATA2 0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */ | ||
1254 | #define CAN0_MB09_DATA3 0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */ | ||
1255 | #define CAN0_MB09_LENGTH 0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */ | ||
1256 | #define CAN0_MB09_TIMESTAMP 0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */ | ||
1257 | #define CAN0_MB09_ID0 0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */ | ||
1258 | #define CAN0_MB09_ID1 0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */ | ||
1259 | #define CAN0_MB10_DATA0 0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */ | ||
1260 | #define CAN0_MB10_DATA1 0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */ | ||
1261 | #define CAN0_MB10_DATA2 0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */ | ||
1262 | #define CAN0_MB10_DATA3 0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */ | ||
1263 | #define CAN0_MB10_LENGTH 0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */ | ||
1264 | #define CAN0_MB10_TIMESTAMP 0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */ | ||
1265 | #define CAN0_MB10_ID0 0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */ | ||
1266 | #define CAN0_MB10_ID1 0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */ | ||
1267 | #define CAN0_MB11_DATA0 0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */ | ||
1268 | #define CAN0_MB11_DATA1 0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */ | ||
1269 | #define CAN0_MB11_DATA2 0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */ | ||
1270 | #define CAN0_MB11_DATA3 0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */ | ||
1271 | #define CAN0_MB11_LENGTH 0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */ | ||
1272 | #define CAN0_MB11_TIMESTAMP 0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */ | ||
1273 | #define CAN0_MB11_ID0 0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */ | ||
1274 | #define CAN0_MB11_ID1 0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */ | ||
1275 | #define CAN0_MB12_DATA0 0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */ | ||
1276 | #define CAN0_MB12_DATA1 0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */ | ||
1277 | #define CAN0_MB12_DATA2 0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */ | ||
1278 | #define CAN0_MB12_DATA3 0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */ | ||
1279 | #define CAN0_MB12_LENGTH 0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */ | ||
1280 | #define CAN0_MB12_TIMESTAMP 0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */ | ||
1281 | #define CAN0_MB12_ID0 0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */ | ||
1282 | #define CAN0_MB12_ID1 0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */ | ||
1283 | #define CAN0_MB13_DATA0 0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */ | ||
1284 | #define CAN0_MB13_DATA1 0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */ | ||
1285 | #define CAN0_MB13_DATA2 0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */ | ||
1286 | #define CAN0_MB13_DATA3 0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */ | ||
1287 | #define CAN0_MB13_LENGTH 0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */ | ||
1288 | #define CAN0_MB13_TIMESTAMP 0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */ | ||
1289 | #define CAN0_MB13_ID0 0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */ | ||
1290 | #define CAN0_MB13_ID1 0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */ | ||
1291 | #define CAN0_MB14_DATA0 0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */ | ||
1292 | #define CAN0_MB14_DATA1 0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */ | ||
1293 | #define CAN0_MB14_DATA2 0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */ | ||
1294 | #define CAN0_MB14_DATA3 0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */ | ||
1295 | #define CAN0_MB14_LENGTH 0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */ | ||
1296 | #define CAN0_MB14_TIMESTAMP 0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */ | ||
1297 | #define CAN0_MB14_ID0 0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */ | ||
1298 | #define CAN0_MB14_ID1 0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */ | ||
1299 | #define CAN0_MB15_DATA0 0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */ | ||
1300 | #define CAN0_MB15_DATA1 0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */ | ||
1301 | #define CAN0_MB15_DATA2 0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */ | ||
1302 | #define CAN0_MB15_DATA3 0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */ | ||
1303 | #define CAN0_MB15_LENGTH 0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */ | ||
1304 | #define CAN0_MB15_TIMESTAMP 0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */ | ||
1305 | #define CAN0_MB15_ID0 0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */ | ||
1306 | #define CAN0_MB15_ID1 0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */ | ||
1307 | |||
1308 | /* CAN Controller 0 Mailbox Data Registers */ | ||
1309 | |||
1310 | #define CAN0_MB16_DATA0 0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */ | ||
1311 | #define CAN0_MB16_DATA1 0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */ | ||
1312 | #define CAN0_MB16_DATA2 0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */ | ||
1313 | #define CAN0_MB16_DATA3 0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */ | ||
1314 | #define CAN0_MB16_LENGTH 0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */ | ||
1315 | #define CAN0_MB16_TIMESTAMP 0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */ | ||
1316 | #define CAN0_MB16_ID0 0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */ | ||
1317 | #define CAN0_MB16_ID1 0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */ | ||
1318 | #define CAN0_MB17_DATA0 0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */ | ||
1319 | #define CAN0_MB17_DATA1 0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */ | ||
1320 | #define CAN0_MB17_DATA2 0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */ | ||
1321 | #define CAN0_MB17_DATA3 0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */ | ||
1322 | #define CAN0_MB17_LENGTH 0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */ | ||
1323 | #define CAN0_MB17_TIMESTAMP 0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */ | ||
1324 | #define CAN0_MB17_ID0 0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */ | ||
1325 | #define CAN0_MB17_ID1 0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */ | ||
1326 | #define CAN0_MB18_DATA0 0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */ | ||
1327 | #define CAN0_MB18_DATA1 0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */ | ||
1328 | #define CAN0_MB18_DATA2 0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */ | ||
1329 | #define CAN0_MB18_DATA3 0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */ | ||
1330 | #define CAN0_MB18_LENGTH 0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */ | ||
1331 | #define CAN0_MB18_TIMESTAMP 0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */ | ||
1332 | #define CAN0_MB18_ID0 0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */ | ||
1333 | #define CAN0_MB18_ID1 0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */ | ||
1334 | #define CAN0_MB19_DATA0 0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */ | ||
1335 | #define CAN0_MB19_DATA1 0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */ | ||
1336 | #define CAN0_MB19_DATA2 0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */ | ||
1337 | #define CAN0_MB19_DATA3 0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */ | ||
1338 | #define CAN0_MB19_LENGTH 0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */ | ||
1339 | #define CAN0_MB19_TIMESTAMP 0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */ | ||
1340 | #define CAN0_MB19_ID0 0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */ | ||
1341 | #define CAN0_MB19_ID1 0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */ | ||
1342 | #define CAN0_MB20_DATA0 0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */ | ||
1343 | #define CAN0_MB20_DATA1 0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */ | ||
1344 | #define CAN0_MB20_DATA2 0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */ | ||
1345 | #define CAN0_MB20_DATA3 0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */ | ||
1346 | #define CAN0_MB20_LENGTH 0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */ | ||
1347 | #define CAN0_MB20_TIMESTAMP 0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */ | ||
1348 | #define CAN0_MB20_ID0 0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */ | ||
1349 | #define CAN0_MB20_ID1 0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */ | ||
1350 | #define CAN0_MB21_DATA0 0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */ | ||
1351 | #define CAN0_MB21_DATA1 0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */ | ||
1352 | #define CAN0_MB21_DATA2 0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */ | ||
1353 | #define CAN0_MB21_DATA3 0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */ | ||
1354 | #define CAN0_MB21_LENGTH 0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */ | ||
1355 | #define CAN0_MB21_TIMESTAMP 0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */ | ||
1356 | #define CAN0_MB21_ID0 0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */ | ||
1357 | #define CAN0_MB21_ID1 0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */ | ||
1358 | #define CAN0_MB22_DATA0 0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */ | ||
1359 | #define CAN0_MB22_DATA1 0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */ | ||
1360 | #define CAN0_MB22_DATA2 0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */ | ||
1361 | #define CAN0_MB22_DATA3 0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */ | ||
1362 | #define CAN0_MB22_LENGTH 0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */ | ||
1363 | #define CAN0_MB22_TIMESTAMP 0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */ | ||
1364 | #define CAN0_MB22_ID0 0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */ | ||
1365 | #define CAN0_MB22_ID1 0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */ | ||
1366 | #define CAN0_MB23_DATA0 0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */ | ||
1367 | #define CAN0_MB23_DATA1 0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */ | ||
1368 | #define CAN0_MB23_DATA2 0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */ | ||
1369 | #define CAN0_MB23_DATA3 0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */ | ||
1370 | #define CAN0_MB23_LENGTH 0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */ | ||
1371 | #define CAN0_MB23_TIMESTAMP 0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */ | ||
1372 | #define CAN0_MB23_ID0 0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */ | ||
1373 | #define CAN0_MB23_ID1 0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */ | ||
1374 | #define CAN0_MB24_DATA0 0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */ | ||
1375 | #define CAN0_MB24_DATA1 0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */ | ||
1376 | #define CAN0_MB24_DATA2 0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */ | ||
1377 | #define CAN0_MB24_DATA3 0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */ | ||
1378 | #define CAN0_MB24_LENGTH 0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */ | ||
1379 | #define CAN0_MB24_TIMESTAMP 0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */ | ||
1380 | #define CAN0_MB24_ID0 0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */ | ||
1381 | #define CAN0_MB24_ID1 0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */ | ||
1382 | #define CAN0_MB25_DATA0 0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */ | ||
1383 | #define CAN0_MB25_DATA1 0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */ | ||
1384 | #define CAN0_MB25_DATA2 0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */ | ||
1385 | #define CAN0_MB25_DATA3 0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */ | ||
1386 | #define CAN0_MB25_LENGTH 0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */ | ||
1387 | #define CAN0_MB25_TIMESTAMP 0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */ | ||
1388 | #define CAN0_MB25_ID0 0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */ | ||
1389 | #define CAN0_MB25_ID1 0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */ | ||
1390 | #define CAN0_MB26_DATA0 0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */ | ||
1391 | #define CAN0_MB26_DATA1 0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */ | ||
1392 | #define CAN0_MB26_DATA2 0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */ | ||
1393 | #define CAN0_MB26_DATA3 0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */ | ||
1394 | #define CAN0_MB26_LENGTH 0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */ | ||
1395 | #define CAN0_MB26_TIMESTAMP 0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */ | ||
1396 | #define CAN0_MB26_ID0 0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */ | ||
1397 | #define CAN0_MB26_ID1 0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */ | ||
1398 | #define CAN0_MB27_DATA0 0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */ | ||
1399 | #define CAN0_MB27_DATA1 0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */ | ||
1400 | #define CAN0_MB27_DATA2 0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */ | ||
1401 | #define CAN0_MB27_DATA3 0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */ | ||
1402 | #define CAN0_MB27_LENGTH 0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */ | ||
1403 | #define CAN0_MB27_TIMESTAMP 0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */ | ||
1404 | #define CAN0_MB27_ID0 0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */ | ||
1405 | #define CAN0_MB27_ID1 0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */ | ||
1406 | #define CAN0_MB28_DATA0 0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */ | ||
1407 | #define CAN0_MB28_DATA1 0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */ | ||
1408 | #define CAN0_MB28_DATA2 0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */ | ||
1409 | #define CAN0_MB28_DATA3 0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */ | ||
1410 | #define CAN0_MB28_LENGTH 0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */ | ||
1411 | #define CAN0_MB28_TIMESTAMP 0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */ | ||
1412 | #define CAN0_MB28_ID0 0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */ | ||
1413 | #define CAN0_MB28_ID1 0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */ | ||
1414 | #define CAN0_MB29_DATA0 0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */ | ||
1415 | #define CAN0_MB29_DATA1 0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */ | ||
1416 | #define CAN0_MB29_DATA2 0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */ | ||
1417 | #define CAN0_MB29_DATA3 0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */ | ||
1418 | #define CAN0_MB29_LENGTH 0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */ | ||
1419 | #define CAN0_MB29_TIMESTAMP 0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */ | ||
1420 | #define CAN0_MB29_ID0 0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */ | ||
1421 | #define CAN0_MB29_ID1 0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */ | ||
1422 | #define CAN0_MB30_DATA0 0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */ | ||
1423 | #define CAN0_MB30_DATA1 0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */ | ||
1424 | #define CAN0_MB30_DATA2 0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */ | ||
1425 | #define CAN0_MB30_DATA3 0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */ | ||
1426 | #define CAN0_MB30_LENGTH 0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */ | ||
1427 | #define CAN0_MB30_TIMESTAMP 0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */ | ||
1428 | #define CAN0_MB30_ID0 0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */ | ||
1429 | #define CAN0_MB30_ID1 0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */ | ||
1430 | #define CAN0_MB31_DATA0 0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */ | ||
1431 | #define CAN0_MB31_DATA1 0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */ | ||
1432 | #define CAN0_MB31_DATA2 0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */ | ||
1433 | #define CAN0_MB31_DATA3 0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */ | ||
1434 | #define CAN0_MB31_LENGTH 0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */ | ||
1435 | #define CAN0_MB31_TIMESTAMP 0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */ | ||
1436 | #define CAN0_MB31_ID0 0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */ | ||
1437 | #define CAN0_MB31_ID1 0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */ | ||
1438 | |||
1439 | /* UART3 Registers */ | ||
1440 | |||
1441 | #define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */ | ||
1442 | #define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */ | ||
1443 | #define UART3_GCTL 0xffc03108 /* Global Control Register */ | ||
1444 | #define UART3_LCR 0xffc0310c /* Line Control Register */ | ||
1445 | #define UART3_MCR 0xffc03110 /* Modem Control Register */ | ||
1446 | #define UART3_LSR 0xffc03114 /* Line Status Register */ | ||
1447 | #define UART3_MSR 0xffc03118 /* Modem Status Register */ | ||
1448 | #define UART3_SCR 0xffc0311c /* Scratch Register */ | ||
1449 | #define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */ | ||
1450 | #define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */ | ||
1451 | #define UART3_THR 0xffc03128 /* Transmit Hold Register */ | ||
1452 | #define UART3_RBR 0xffc0312c /* Receive Buffer Register */ | ||
1453 | |||
1454 | /* NFC Registers */ | ||
1455 | |||
1456 | #define NFC_CTL 0xffc03b00 /* NAND Control Register */ | ||
1457 | #define NFC_STAT 0xffc03b04 /* NAND Status Register */ | ||
1458 | #define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */ | ||
1459 | #define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */ | ||
1460 | #define NFC_ECC0 0xffc03b10 /* NAND ECC Register 0 */ | ||
1461 | #define NFC_ECC1 0xffc03b14 /* NAND ECC Register 1 */ | ||
1462 | #define NFC_ECC2 0xffc03b18 /* NAND ECC Register 2 */ | ||
1463 | #define NFC_ECC3 0xffc03b1c /* NAND ECC Register 3 */ | ||
1464 | #define NFC_COUNT 0xffc03b20 /* NAND ECC Count Register */ | ||
1465 | #define NFC_RST 0xffc03b24 /* NAND ECC Reset Register */ | ||
1466 | #define NFC_PGCTL 0xffc03b28 /* NAND Page Control Register */ | ||
1467 | #define NFC_READ 0xffc03b2c /* NAND Read Data Register */ | ||
1468 | #define NFC_ADDR 0xffc03b40 /* NAND Address Register */ | ||
1469 | #define NFC_CMD 0xffc03b44 /* NAND Command Register */ | ||
1470 | #define NFC_DATA_WR 0xffc03b48 /* NAND Data Write Register */ | ||
1471 | #define NFC_DATA_RD 0xffc03b4c /* NAND Data Read Register */ | ||
1472 | |||
1473 | /* Counter Registers */ | ||
1474 | |||
1475 | #define CNT_CONFIG 0xffc04200 /* Configuration Register */ | ||
1476 | #define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */ | ||
1477 | #define CNT_STATUS 0xffc04208 /* Status Register */ | ||
1478 | #define CNT_COMMAND 0xffc0420c /* Command Register */ | ||
1479 | #define CNT_DEBOUNCE 0xffc04210 /* Debounce Register */ | ||
1480 | #define CNT_COUNTER 0xffc04214 /* Counter Register */ | ||
1481 | #define CNT_MAX 0xffc04218 /* Maximal Count Register */ | ||
1482 | #define CNT_MIN 0xffc0421c /* Minimal Count Register */ | ||
1483 | |||
1484 | /* OTP/FUSE Registers */ | ||
1485 | |||
1486 | #define OTP_CONTROL 0xffc04300 /* OTP/Fuse Control Register */ | ||
1487 | #define OTP_BEN 0xffc04304 /* OTP/Fuse Byte Enable */ | ||
1488 | #define OTP_STATUS 0xffc04308 /* OTP/Fuse Status */ | ||
1489 | #define OTP_TIMING 0xffc0430c /* OTP/Fuse Access Timing */ | ||
1490 | |||
1491 | /* Security Registers */ | ||
1492 | |||
1493 | #define SECURE_SYSSWT 0xffc04320 /* Secure System Switches */ | ||
1494 | #define SECURE_CONTROL 0xffc04324 /* Secure Control */ | ||
1495 | #define SECURE_STATUS 0xffc04328 /* Secure Status */ | ||
1496 | |||
1497 | /* DMA Peripheral Mux Register */ | ||
1498 | |||
1499 | #define DMAC1_PERIMUX 0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */ | ||
1500 | |||
1501 | /* OTP Read/Write Data Buffer Registers */ | ||
1502 | |||
1503 | #define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
1504 | #define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
1505 | #define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
1506 | #define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
1507 | |||
1508 | /* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */ | ||
1509 | |||
1510 | /* ********************************************************** */ | ||
1511 | /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ | ||
1512 | /* and MULTI BIT READ MACROS */ | ||
1513 | /* ********************************************************** */ | ||
1514 | |||
1515 | /* Bit masks for SIC_IAR0 */ | ||
1516 | |||
1517 | #define IRQ_PLL_WAKEUP 0x1 /* PLL Wakeup */ | ||
1518 | #define nIRQ_PLL_WAKEUP 0x0 | ||
1519 | |||
1520 | /* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */ | ||
1521 | |||
1522 | #define IRQ_DMA0_ERR 0x2 /* DMA Controller 0 Error */ | ||
1523 | #define nIRQ_DMA0_ERR 0x0 | ||
1524 | #define IRQ_EPPI0_ERR 0x4 /* EPPI0 Error */ | ||
1525 | #define nIRQ_EPPI0_ERR 0x0 | ||
1526 | #define IRQ_SPORT0_ERR 0x8 /* SPORT0 Error */ | ||
1527 | #define nIRQ_SPORT0_ERR 0x0 | ||
1528 | #define IRQ_SPORT1_ERR 0x10 /* SPORT1 Error */ | ||
1529 | #define nIRQ_SPORT1_ERR 0x0 | ||
1530 | #define IRQ_SPI0_ERR 0x20 /* SPI0 Error */ | ||
1531 | #define nIRQ_SPI0_ERR 0x0 | ||
1532 | #define IRQ_UART0_ERR 0x40 /* UART0 Error */ | ||
1533 | #define nIRQ_UART0_ERR 0x0 | ||
1534 | #define IRQ_RTC 0x80 /* Real-Time Clock */ | ||
1535 | #define nIRQ_RTC 0x0 | ||
1536 | #define IRQ_DMA12 0x100 /* DMA Channel 12 */ | ||
1537 | #define nIRQ_DMA12 0x0 | ||
1538 | #define IRQ_DMA0 0x200 /* DMA Channel 0 */ | ||
1539 | #define nIRQ_DMA0 0x0 | ||
1540 | #define IRQ_DMA1 0x400 /* DMA Channel 1 */ | ||
1541 | #define nIRQ_DMA1 0x0 | ||
1542 | #define IRQ_DMA2 0x800 /* DMA Channel 2 */ | ||
1543 | #define nIRQ_DMA2 0x0 | ||
1544 | #define IRQ_DMA3 0x1000 /* DMA Channel 3 */ | ||
1545 | #define nIRQ_DMA3 0x0 | ||
1546 | #define IRQ_DMA4 0x2000 /* DMA Channel 4 */ | ||
1547 | #define nIRQ_DMA4 0x0 | ||
1548 | #define IRQ_DMA6 0x4000 /* DMA Channel 6 */ | ||
1549 | #define nIRQ_DMA6 0x0 | ||
1550 | #define IRQ_DMA7 0x8000 /* DMA Channel 7 */ | ||
1551 | #define nIRQ_DMA7 0x0 | ||
1552 | #define IRQ_PINT0 0x80000 /* Pin Interrupt 0 */ | ||
1553 | #define nIRQ_PINT0 0x0 | ||
1554 | #define IRQ_PINT1 0x100000 /* Pin Interrupt 1 */ | ||
1555 | #define nIRQ_PINT1 0x0 | ||
1556 | #define IRQ_MDMA0 0x200000 /* Memory DMA Stream 0 */ | ||
1557 | #define nIRQ_MDMA0 0x0 | ||
1558 | #define IRQ_MDMA1 0x400000 /* Memory DMA Stream 1 */ | ||
1559 | #define nIRQ_MDMA1 0x0 | ||
1560 | #define IRQ_WDOG 0x800000 /* Watchdog Timer */ | ||
1561 | #define nIRQ_WDOG 0x0 | ||
1562 | #define IRQ_DMA1_ERR 0x1000000 /* DMA Controller 1 Error */ | ||
1563 | #define nIRQ_DMA1_ERR 0x0 | ||
1564 | #define IRQ_SPORT2_ERR 0x2000000 /* SPORT2 Error */ | ||
1565 | #define nIRQ_SPORT2_ERR 0x0 | ||
1566 | #define IRQ_SPORT3_ERR 0x4000000 /* SPORT3 Error */ | ||
1567 | #define nIRQ_SPORT3_ERR 0x0 | ||
1568 | #define IRQ_MXVR_SD 0x8000000 /* MXVR Synchronous Data */ | ||
1569 | #define nIRQ_MXVR_SD 0x0 | ||
1570 | #define IRQ_SPI1_ERR 0x10000000 /* SPI1 Error */ | ||
1571 | #define nIRQ_SPI1_ERR 0x0 | ||
1572 | #define IRQ_SPI2_ERR 0x20000000 /* SPI2 Error */ | ||
1573 | #define nIRQ_SPI2_ERR 0x0 | ||
1574 | #define IRQ_UART1_ERR 0x40000000 /* UART1 Error */ | ||
1575 | #define nIRQ_UART1_ERR 0x0 | ||
1576 | #define IRQ_UART2_ERR 0x80000000 /* UART2 Error */ | ||
1577 | #define nIRQ_UART2_ERR 0x0 | ||
1578 | |||
1579 | /* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */ | ||
1580 | |||
1581 | #define IRQ_CAN0_ERR 0x1 /* CAN0 Error */ | ||
1582 | #define nIRQ_CAN0_ERR 0x0 | ||
1583 | #define IRQ_DMA18 0x2 /* DMA Channel 18 */ | ||
1584 | #define nIRQ_DMA18 0x0 | ||
1585 | #define IRQ_DMA19 0x4 /* DMA Channel 19 */ | ||
1586 | #define nIRQ_DMA19 0x0 | ||
1587 | #define IRQ_DMA20 0x8 /* DMA Channel 20 */ | ||
1588 | #define nIRQ_DMA20 0x0 | ||
1589 | #define IRQ_DMA21 0x10 /* DMA Channel 21 */ | ||
1590 | #define nIRQ_DMA21 0x0 | ||
1591 | #define IRQ_DMA13 0x20 /* DMA Channel 13 */ | ||
1592 | #define nIRQ_DMA13 0x0 | ||
1593 | #define IRQ_DMA14 0x40 /* DMA Channel 14 */ | ||
1594 | #define nIRQ_DMA14 0x0 | ||
1595 | #define IRQ_DMA5 0x80 /* DMA Channel 5 */ | ||
1596 | #define nIRQ_DMA5 0x0 | ||
1597 | #define IRQ_DMA23 0x100 /* DMA Channel 23 */ | ||
1598 | #define nIRQ_DMA23 0x0 | ||
1599 | #define IRQ_DMA8 0x200 /* DMA Channel 8 */ | ||
1600 | #define nIRQ_DMA8 0x0 | ||
1601 | #define IRQ_DMA9 0x400 /* DMA Channel 9 */ | ||
1602 | #define nIRQ_DMA9 0x0 | ||
1603 | #define IRQ_DMA10 0x800 /* DMA Channel 10 */ | ||
1604 | #define nIRQ_DMA10 0x0 | ||
1605 | #define IRQ_DMA11 0x1000 /* DMA Channel 11 */ | ||
1606 | #define nIRQ_DMA11 0x0 | ||
1607 | #define IRQ_TWI0 0x2000 /* TWI0 */ | ||
1608 | #define nIRQ_TWI0 0x0 | ||
1609 | #define IRQ_TWI1 0x4000 /* TWI1 */ | ||
1610 | #define nIRQ_TWI1 0x0 | ||
1611 | #define IRQ_CAN0_RX 0x8000 /* CAN0 Receive */ | ||
1612 | #define nIRQ_CAN0_RX 0x0 | ||
1613 | #define IRQ_CAN0_TX 0x10000 /* CAN0 Transmit */ | ||
1614 | #define nIRQ_CAN0_TX 0x0 | ||
1615 | #define IRQ_MDMA2 0x20000 /* Memory DMA Stream 0 */ | ||
1616 | #define nIRQ_MDMA2 0x0 | ||
1617 | #define IRQ_MDMA3 0x40000 /* Memory DMA Stream 1 */ | ||
1618 | #define nIRQ_MDMA3 0x0 | ||
1619 | #define IRQ_MXVR_STAT 0x80000 /* MXVR Status */ | ||
1620 | #define nIRQ_MXVR_STAT 0x0 | ||
1621 | #define IRQ_MXVR_CM 0x100000 /* MXVR Control Message */ | ||
1622 | #define nIRQ_MXVR_CM 0x0 | ||
1623 | #define IRQ_MXVR_AP 0x200000 /* MXVR Asynchronous Packet */ | ||
1624 | #define nIRQ_MXVR_AP 0x0 | ||
1625 | #define IRQ_EPPI1_ERR 0x400000 /* EPPI1 Error */ | ||
1626 | #define nIRQ_EPPI1_ERR 0x0 | ||
1627 | #define IRQ_EPPI2_ERR 0x800000 /* EPPI2 Error */ | ||
1628 | #define nIRQ_EPPI2_ERR 0x0 | ||
1629 | #define IRQ_UART3_ERR 0x1000000 /* UART3 Error */ | ||
1630 | #define nIRQ_UART3_ERR 0x0 | ||
1631 | #define IRQ_HOST_ERR 0x2000000 /* Host DMA Port Error */ | ||
1632 | #define nIRQ_HOST_ERR 0x0 | ||
1633 | #define IRQ_USB_ERR 0x4000000 /* USB Error */ | ||
1634 | #define nIRQ_USB_ERR 0x0 | ||
1635 | #define IRQ_PIXC_ERR 0x8000000 /* Pixel Compositor Error */ | ||
1636 | #define nIRQ_PIXC_ERR 0x0 | ||
1637 | #define IRQ_NFC_ERR 0x10000000 /* Nand Flash Controller Error */ | ||
1638 | #define nIRQ_NFC_ERR 0x0 | ||
1639 | #define IRQ_ATAPI_ERR 0x20000000 /* ATAPI Error */ | ||
1640 | #define nIRQ_ATAPI_ERR 0x0 | ||
1641 | #define IRQ_CAN1_ERR 0x40000000 /* CAN1 Error */ | ||
1642 | #define nIRQ_CAN1_ERR 0x0 | ||
1643 | #define IRQ_DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */ | ||
1644 | #define nIRQ_DMAR0_ERR 0x0 | ||
1645 | #define IRQ_DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */ | ||
1646 | #define nIRQ_DMAR1_ERR 0x0 | ||
1647 | #define IRQ_DMAR0 0x80000000 /* DMAR0 Block */ | ||
1648 | #define nIRQ_DMAR0 0x0 | ||
1649 | #define IRQ_DMAR1 0x80000000 /* DMAR1 Block */ | ||
1650 | #define nIRQ_DMAR1 0x0 | ||
1651 | |||
1652 | /* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */ | ||
1653 | |||
1654 | #define IRQ_DMA15 0x1 /* DMA Channel 15 */ | ||
1655 | #define nIRQ_DMA15 0x0 | ||
1656 | #define IRQ_DMA16 0x2 /* DMA Channel 16 */ | ||
1657 | #define nIRQ_DMA16 0x0 | ||
1658 | #define IRQ_DMA17 0x4 /* DMA Channel 17 */ | ||
1659 | #define nIRQ_DMA17 0x0 | ||
1660 | #define IRQ_DMA22 0x8 /* DMA Channel 22 */ | ||
1661 | #define nIRQ_DMA22 0x0 | ||
1662 | #define IRQ_CNT 0x10 /* Counter */ | ||
1663 | #define nIRQ_CNT 0x0 | ||
1664 | #define IRQ_KEY 0x20 /* Keypad */ | ||
1665 | #define nIRQ_KEY 0x0 | ||
1666 | #define IRQ_CAN1_RX 0x40 /* CAN1 Receive */ | ||
1667 | #define nIRQ_CAN1_RX 0x0 | ||
1668 | #define IRQ_CAN1_TX 0x80 /* CAN1 Transmit */ | ||
1669 | #define nIRQ_CAN1_TX 0x0 | ||
1670 | #define IRQ_SDH_MASK0 0x100 /* SDH Mask 0 */ | ||
1671 | #define nIRQ_SDH_MASK0 0x0 | ||
1672 | #define IRQ_SDH_MASK1 0x200 /* SDH Mask 1 */ | ||
1673 | #define nIRQ_SDH_MASK1 0x0 | ||
1674 | #define IRQ_USB_EINT 0x400 /* USB Exception */ | ||
1675 | #define nIRQ_USB_EINT 0x0 | ||
1676 | #define IRQ_USB_INT0 0x800 /* USB Interrupt 0 */ | ||
1677 | #define nIRQ_USB_INT0 0x0 | ||
1678 | #define IRQ_USB_INT1 0x1000 /* USB Interrupt 1 */ | ||
1679 | #define nIRQ_USB_INT1 0x0 | ||
1680 | #define IRQ_USB_INT2 0x2000 /* USB Interrupt 2 */ | ||
1681 | #define nIRQ_USB_INT2 0x0 | ||
1682 | #define IRQ_USB_DMAINT 0x4000 /* USB DMA */ | ||
1683 | #define nIRQ_USB_DMAINT 0x0 | ||
1684 | #define IRQ_OTPSEC 0x8000 /* OTP Access Complete */ | ||
1685 | #define nIRQ_OTPSEC 0x0 | ||
1686 | #define IRQ_TIMER0 0x400000 /* Timer 0 */ | ||
1687 | #define nIRQ_TIMER0 0x0 | ||
1688 | #define IRQ_TIMER1 0x800000 /* Timer 1 */ | ||
1689 | #define nIRQ_TIMER1 0x0 | ||
1690 | #define IRQ_TIMER2 0x1000000 /* Timer 2 */ | ||
1691 | #define nIRQ_TIMER2 0x0 | ||
1692 | #define IRQ_TIMER3 0x2000000 /* Timer 3 */ | ||
1693 | #define nIRQ_TIMER3 0x0 | ||
1694 | #define IRQ_TIMER4 0x4000000 /* Timer 4 */ | ||
1695 | #define nIRQ_TIMER4 0x0 | ||
1696 | #define IRQ_TIMER5 0x8000000 /* Timer 5 */ | ||
1697 | #define nIRQ_TIMER5 0x0 | ||
1698 | #define IRQ_TIMER6 0x10000000 /* Timer 6 */ | ||
1699 | #define nIRQ_TIMER6 0x0 | ||
1700 | #define IRQ_TIMER7 0x20000000 /* Timer 7 */ | ||
1701 | #define nIRQ_TIMER7 0x0 | ||
1702 | #define IRQ_PINT2 0x40000000 /* Pin Interrupt 2 */ | ||
1703 | #define nIRQ_PINT2 0x0 | ||
1704 | #define IRQ_PINT3 0x80000000 /* Pin Interrupt 3 */ | ||
1705 | #define nIRQ_PINT3 0x0 | ||
1706 | |||
1707 | /* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */ | ||
1708 | |||
1709 | #define DMAEN 0x1 /* DMA Channel Enable */ | ||
1710 | #define nDMAEN 0x0 | ||
1711 | #define WNR 0x2 /* DMA Direction */ | ||
1712 | #define nWNR 0x0 | ||
1713 | #define WDSIZE 0xc /* Transfer Word Size */ | ||
1714 | #define DMA2D 0x10 /* DMA Mode */ | ||
1715 | #define nDMA2D 0x0 | ||
1716 | #define RESTART 0x20 /* Work Unit Transitions */ | ||
1717 | #define nRESTART 0x0 | ||
1718 | #define DI_SEL 0x40 /* Data Interrupt Timing Select */ | ||
1719 | #define nDI_SEL 0x0 | ||
1720 | #define DI_EN 0x80 /* Data Interrupt Enable */ | ||
1721 | #define nDI_EN 0x0 | ||
1722 | #define NDSIZE 0xf00 /* Flex Descriptor Size */ | ||
1723 | #define DMAFLOW 0xf000 /* Next Operation */ | ||
1724 | |||
1725 | /* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ | ||
1726 | |||
1727 | #define DMA_DONE 0x1 /* DMA Completion Interrupt Status */ | ||
1728 | #define nDMA_DONE 0x0 | ||
1729 | #define DMA_ERR 0x2 /* DMA Error Interrupt Status */ | ||
1730 | #define nDMA_ERR 0x0 | ||
1731 | #define DFETCH 0x4 /* DMA Descriptor Fetch */ | ||
1732 | #define nDFETCH 0x0 | ||
1733 | #define DMA_RUN 0x8 /* DMA Channel Running */ | ||
1734 | #define nDMA_RUN 0x0 | ||
1735 | |||
1736 | /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ | ||
1737 | |||
1738 | #define CTYPE 0x40 /* DMA Channel Type */ | ||
1739 | #define nCTYPE 0x0 | ||
1740 | #define PMAP 0xf000 /* Peripheral Mapped To This Channel */ | ||
1741 | |||
1742 | /* Bit masks for DMACx_TCPER */ | ||
1743 | |||
1744 | #define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */ | ||
1745 | #define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */ | ||
1746 | #define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */ | ||
1747 | #define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */ | ||
1748 | |||
1749 | /* Bit masks for DMACx_TCCNT */ | ||
1750 | |||
1751 | #define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */ | ||
1752 | #define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */ | ||
1753 | #define DAB_TRAFFIC_COUNT 0x700 /* DAB Traffic Control Count */ | ||
1754 | #define MDMA_ROUND_ROBIN_COUNT 0xf800 /* MDMA Round Robin Count */ | ||
1755 | |||
1756 | /* Bit masks for DMAC1_PERIMUX */ | ||
1757 | |||
1758 | #define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */ | ||
1759 | #define nPMUXSDH 0x0 | ||
1760 | |||
1761 | /* Bit masks for EBIU_AMGCTL */ | ||
1762 | |||
1763 | #define AMCKEN 0x1 /* Async Memory Enable */ | ||
1764 | #define nAMCKEN 0x0 | ||
1765 | #define AMBEN 0xe /* Async bank enable */ | ||
1766 | |||
1767 | /* Bit masks for EBIU_AMBCTL0 */ | ||
1768 | |||
1769 | #define B0RDYEN 0x1 /* Bank 0 ARDY Enable */ | ||
1770 | #define nB0RDYEN 0x0 | ||
1771 | #define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */ | ||
1772 | #define nB0RDYPOL 0x0 | ||
1773 | #define B0TT 0xc /* Bank 0 transition time */ | ||
1774 | #define B0ST 0x30 /* Bank 0 Setup time */ | ||
1775 | #define B0HT 0xc0 /* Bank 0 Hold time */ | ||
1776 | #define B0RAT 0xf00 /* Bank 0 Read access time */ | ||
1777 | #define B0WAT 0xf000 /* Bank 0 write access time */ | ||
1778 | #define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */ | ||
1779 | #define nB1RDYEN 0x0 | ||
1780 | #define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */ | ||
1781 | #define nB1RDYPOL 0x0 | ||
1782 | #define B1TT 0xc0000 /* Bank 1 transition time */ | ||
1783 | #define B1ST 0x300000 /* Bank 1 Setup time */ | ||
1784 | #define B1HT 0xc00000 /* Bank 1 Hold time */ | ||
1785 | #define B1RAT 0xf000000 /* Bank 1 Read access time */ | ||
1786 | #define B1WAT 0xf0000000 /* Bank 1 write access time */ | ||
1787 | |||
1788 | /* Bit masks for EBIU_AMBCTL1 */ | ||
1789 | |||
1790 | #define B2RDYEN 0x1 /* Bank 2 ARDY Enable */ | ||
1791 | #define nB2RDYEN 0x0 | ||
1792 | #define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */ | ||
1793 | #define nB2RDYPOL 0x0 | ||
1794 | #define B2TT 0xc /* Bank 2 transition time */ | ||
1795 | #define B2ST 0x30 /* Bank 2 Setup time */ | ||
1796 | #define B2HT 0xc0 /* Bank 2 Hold time */ | ||
1797 | #define B2RAT 0xf00 /* Bank 2 Read access time */ | ||
1798 | #define B2WAT 0xf000 /* Bank 2 write access time */ | ||
1799 | #define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */ | ||
1800 | #define nB3RDYEN 0x0 | ||
1801 | #define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */ | ||
1802 | #define nB3RDYPOL 0x0 | ||
1803 | #define B3TT 0xc0000 /* Bank 3 transition time */ | ||
1804 | #define B3ST 0x300000 /* Bank 3 Setup time */ | ||
1805 | #define B3HT 0xc00000 /* Bank 3 Hold time */ | ||
1806 | #define B3RAT 0xf000000 /* Bank 3 Read access time */ | ||
1807 | #define B3WAT 0xf0000000 /* Bank 3 write access time */ | ||
1808 | |||
1809 | /* Bit masks for EBIU_MBSCTL */ | ||
1810 | |||
1811 | #define AMSB0CTL 0x3 /* Async Memory Bank 0 select */ | ||
1812 | #define AMSB1CTL 0xc /* Async Memory Bank 1 select */ | ||
1813 | #define AMSB2CTL 0x30 /* Async Memory Bank 2 select */ | ||
1814 | #define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */ | ||
1815 | |||
1816 | /* Bit masks for EBIU_MODE */ | ||
1817 | |||
1818 | #define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */ | ||
1819 | #define B1MODE 0xc /* Async Memory Bank 1 Access Mode */ | ||
1820 | #define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */ | ||
1821 | #define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */ | ||
1822 | |||
1823 | /* Bit masks for EBIU_FCTL */ | ||
1824 | |||
1825 | #define TESTSETLOCK 0x1 /* Test set lock */ | ||
1826 | #define nTESTSETLOCK 0x0 | ||
1827 | #define BCLK 0x6 /* Burst clock frequency */ | ||
1828 | #define PGWS 0x38 /* Page wait states */ | ||
1829 | #define PGSZ 0x40 /* Page size */ | ||
1830 | #define nPGSZ 0x0 | ||
1831 | #define RDDL 0x380 /* Read data delay */ | ||
1832 | |||
1833 | /* Bit masks for EBIU_ARBSTAT */ | ||
1834 | |||
1835 | #define ARBSTAT 0x1 /* Arbitration status */ | ||
1836 | #define nARBSTAT 0x0 | ||
1837 | #define BGSTAT 0x2 /* Bus grant status */ | ||
1838 | #define nBGSTAT 0x0 | ||
1839 | |||
1840 | /* Bit masks for EBIU_DDRCTL0 */ | ||
1841 | |||
1842 | #define TREFI 0x3fff /* Refresh Interval */ | ||
1843 | #define TRFC 0x3c000 /* Auto-refresh command period */ | ||
1844 | #define TRP 0x3c0000 /* Pre charge-to-active command period */ | ||
1845 | #define TRAS 0x3c00000 /* Min Active-to-pre charge time */ | ||
1846 | #define TRC 0x3c000000 /* Active-to-active time */ | ||
1847 | |||
1848 | /* Bit masks for EBIU_DDRCTL1 */ | ||
1849 | |||
1850 | #define TRCD 0xf /* Active-to-Read/write delay */ | ||
1851 | #define MRD 0xf0 /* Mode register set to active */ | ||
1852 | #define TWR 0x300 /* Write Recovery time */ | ||
1853 | #define DDRDATWIDTH 0x3000 /* DDR data width */ | ||
1854 | #define EXTBANKS 0xc000 /* External banks */ | ||
1855 | #define DDRDEVWIDTH 0x30000 /* DDR device width */ | ||
1856 | #define DDRDEVSIZE 0xc0000 /* DDR device size */ | ||
1857 | #define TWWTR 0xf0000000 /* Write-to-read delay */ | ||
1858 | |||
1859 | /* Bit masks for EBIU_DDRCTL2 */ | ||
1860 | |||
1861 | #define BURSTLENGTH 0x7 /* Burst length */ | ||
1862 | #define CASLATENCY 0x70 /* CAS latency */ | ||
1863 | #define DLLRESET 0x100 /* DLL Reset */ | ||
1864 | #define nDLLRESET 0x0 | ||
1865 | #define REGE 0x1000 /* Register mode enable */ | ||
1866 | #define nREGE 0x0 | ||
1867 | |||
1868 | /* Bit masks for EBIU_DDRCTL3 */ | ||
1869 | |||
1870 | #define PASR 0x7 /* Partial array self-refresh */ | ||
1871 | |||
1872 | /* Bit masks for EBIU_DDRQUE */ | ||
1873 | |||
1874 | #define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */ | ||
1875 | #define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */ | ||
1876 | #define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */ | ||
1877 | #define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */ | ||
1878 | #define DEB1_URGENT 0x1000 /* DEB1 Urgent */ | ||
1879 | #define nDEB1_URGENT 0x0 | ||
1880 | #define DEB2_URGENT 0x2000 /* DEB2 Urgent */ | ||
1881 | #define nDEB2_URGENT 0x0 | ||
1882 | #define DEB3_URGENT 0x4000 /* DEB3 Urgent */ | ||
1883 | #define nDEB3_URGENT 0x0 | ||
1884 | |||
1885 | /* Bit masks for EBIU_ERRMST */ | ||
1886 | |||
1887 | #define DEB1_ERROR 0x1 /* DEB1 Error */ | ||
1888 | #define nDEB1_ERROR 0x0 | ||
1889 | #define DEB2_ERROR 0x2 /* DEB2 Error */ | ||
1890 | #define nDEB2_ERROR 0x0 | ||
1891 | #define DEB3_ERROR 0x4 /* DEB3 Error */ | ||
1892 | #define nDEB3_ERROR 0x0 | ||
1893 | #define CORE_ERROR 0x8 /* Core error */ | ||
1894 | #define nCORE_ERROR 0x0 | ||
1895 | #define DEB_MERROR 0x10 /* DEB1 Error (2nd) */ | ||
1896 | #define nDEB_MERROR 0x0 | ||
1897 | #define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */ | ||
1898 | #define nDEB2_MERROR 0x0 | ||
1899 | #define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */ | ||
1900 | #define nDEB3_MERROR 0x0 | ||
1901 | #define CORE_MERROR 0x80 /* Core Error (2nd) */ | ||
1902 | #define nCORE_MERROR 0x0 | ||
1903 | |||
1904 | /* Bit masks for EBIU_ERRADD */ | ||
1905 | |||
1906 | #define ERROR_ADDRESS 0xffffffff /* Error Address */ | ||
1907 | |||
1908 | /* Bit masks for EBIU_RSTCTL */ | ||
1909 | |||
1910 | #define DDRSRESET 0x1 /* DDR soft reset */ | ||
1911 | #define nDDRSRESET 0x0 | ||
1912 | #define PFTCHSRESET 0x4 /* DDR prefetch reset */ | ||
1913 | #define nPFTCHSRESET 0x0 | ||
1914 | #define SRREQ 0x8 /* Self-refresh request */ | ||
1915 | #define nSRREQ 0x0 | ||
1916 | #define SRACK 0x10 /* Self-refresh acknowledge */ | ||
1917 | #define nSRACK 0x0 | ||
1918 | #define MDDRENABLE 0x20 /* Mobile DDR enable */ | ||
1919 | #define nMDDRENABLE 0x0 | ||
1920 | |||
1921 | /* Bit masks for EBIU_DDRBRC0 */ | ||
1922 | |||
1923 | #define BRC0 0xffffffff /* Count */ | ||
1924 | |||
1925 | /* Bit masks for EBIU_DDRBRC1 */ | ||
1926 | |||
1927 | #define BRC1 0xffffffff /* Count */ | ||
1928 | |||
1929 | /* Bit masks for EBIU_DDRBRC2 */ | ||
1930 | |||
1931 | #define BRC2 0xffffffff /* Count */ | ||
1932 | |||
1933 | /* Bit masks for EBIU_DDRBRC3 */ | ||
1934 | |||
1935 | #define BRC3 0xffffffff /* Count */ | ||
1936 | |||
1937 | /* Bit masks for EBIU_DDRBRC4 */ | ||
1938 | |||
1939 | #define BRC4 0xffffffff /* Count */ | ||
1940 | |||
1941 | /* Bit masks for EBIU_DDRBRC5 */ | ||
1942 | |||
1943 | #define BRC5 0xffffffff /* Count */ | ||
1944 | |||
1945 | /* Bit masks for EBIU_DDRBRC6 */ | ||
1946 | |||
1947 | #define BRC6 0xffffffff /* Count */ | ||
1948 | |||
1949 | /* Bit masks for EBIU_DDRBRC7 */ | ||
1950 | |||
1951 | #define BRC7 0xffffffff /* Count */ | ||
1952 | |||
1953 | /* Bit masks for EBIU_DDRBWC0 */ | ||
1954 | |||
1955 | #define BWC0 0xffffffff /* Count */ | ||
1956 | |||
1957 | /* Bit masks for EBIU_DDRBWC1 */ | ||
1958 | |||
1959 | #define BWC1 0xffffffff /* Count */ | ||
1960 | |||
1961 | /* Bit masks for EBIU_DDRBWC2 */ | ||
1962 | |||
1963 | #define BWC2 0xffffffff /* Count */ | ||
1964 | |||
1965 | /* Bit masks for EBIU_DDRBWC3 */ | ||
1966 | |||
1967 | #define BWC3 0xffffffff /* Count */ | ||
1968 | |||
1969 | /* Bit masks for EBIU_DDRBWC4 */ | ||
1970 | |||
1971 | #define BWC4 0xffffffff /* Count */ | ||
1972 | |||
1973 | /* Bit masks for EBIU_DDRBWC5 */ | ||
1974 | |||
1975 | #define BWC5 0xffffffff /* Count */ | ||
1976 | |||
1977 | /* Bit masks for EBIU_DDRBWC6 */ | ||
1978 | |||
1979 | #define BWC6 0xffffffff /* Count */ | ||
1980 | |||
1981 | /* Bit masks for EBIU_DDRBWC7 */ | ||
1982 | |||
1983 | #define BWC7 0xffffffff /* Count */ | ||
1984 | |||
1985 | /* Bit masks for EBIU_DDRACCT */ | ||
1986 | |||
1987 | #define ACCT 0xffffffff /* Count */ | ||
1988 | |||
1989 | /* Bit masks for EBIU_DDRTACT */ | ||
1990 | |||
1991 | #define TECT 0xffffffff /* Count */ | ||
1992 | |||
1993 | /* Bit masks for EBIU_DDRARCT */ | ||
1994 | |||
1995 | #define ARCT 0xffffffff /* Count */ | ||
1996 | |||
1997 | /* Bit masks for EBIU_DDRGC0 */ | ||
1998 | |||
1999 | #define GC0 0xffffffff /* Count */ | ||
2000 | |||
2001 | /* Bit masks for EBIU_DDRGC1 */ | ||
2002 | |||
2003 | #define GC1 0xffffffff /* Count */ | ||
2004 | |||
2005 | /* Bit masks for EBIU_DDRGC2 */ | ||
2006 | |||
2007 | #define GC2 0xffffffff /* Count */ | ||
2008 | |||
2009 | /* Bit masks for EBIU_DDRGC3 */ | ||
2010 | |||
2011 | #define GC3 0xffffffff /* Count */ | ||
2012 | |||
2013 | /* Bit masks for EBIU_DDRMCEN */ | ||
2014 | |||
2015 | #define B0WCENABLE 0x1 /* Bank 0 write count enable */ | ||
2016 | #define nB0WCENABLE 0x0 | ||
2017 | #define B1WCENABLE 0x2 /* Bank 1 write count enable */ | ||
2018 | #define nB1WCENABLE 0x0 | ||
2019 | #define B2WCENABLE 0x4 /* Bank 2 write count enable */ | ||
2020 | #define nB2WCENABLE 0x0 | ||
2021 | #define B3WCENABLE 0x8 /* Bank 3 write count enable */ | ||
2022 | #define nB3WCENABLE 0x0 | ||
2023 | #define B4WCENABLE 0x10 /* Bank 4 write count enable */ | ||
2024 | #define nB4WCENABLE 0x0 | ||
2025 | #define B5WCENABLE 0x20 /* Bank 5 write count enable */ | ||
2026 | #define nB5WCENABLE 0x0 | ||
2027 | #define B6WCENABLE 0x40 /* Bank 6 write count enable */ | ||
2028 | #define nB6WCENABLE 0x0 | ||
2029 | #define B7WCENABLE 0x80 /* Bank 7 write count enable */ | ||
2030 | #define nB7WCENABLE 0x0 | ||
2031 | #define B0RCENABLE 0x100 /* Bank 0 read count enable */ | ||
2032 | #define nB0RCENABLE 0x0 | ||
2033 | #define B1RCENABLE 0x200 /* Bank 1 read count enable */ | ||
2034 | #define nB1RCENABLE 0x0 | ||
2035 | #define B2RCENABLE 0x400 /* Bank 2 read count enable */ | ||
2036 | #define nB2RCENABLE 0x0 | ||
2037 | #define B3RCENABLE 0x800 /* Bank 3 read count enable */ | ||
2038 | #define nB3RCENABLE 0x0 | ||
2039 | #define B4RCENABLE 0x1000 /* Bank 4 read count enable */ | ||
2040 | #define nB4RCENABLE 0x0 | ||
2041 | #define B5RCENABLE 0x2000 /* Bank 5 read count enable */ | ||
2042 | #define nB5RCENABLE 0x0 | ||
2043 | #define B6RCENABLE 0x4000 /* Bank 6 read count enable */ | ||
2044 | #define nB6RCENABLE 0x0 | ||
2045 | #define B7RCENABLE 0x8000 /* Bank 7 read count enable */ | ||
2046 | #define nB7RCENABLE 0x0 | ||
2047 | #define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */ | ||
2048 | #define nROWACTCENABLE 0x0 | ||
2049 | #define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */ | ||
2050 | #define nRWTCENABLE 0x0 | ||
2051 | #define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */ | ||
2052 | #define nARCENABLE 0x0 | ||
2053 | #define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */ | ||
2054 | #define nGC0ENABLE 0x0 | ||
2055 | #define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */ | ||
2056 | #define nGC1ENABLE 0x0 | ||
2057 | #define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */ | ||
2058 | #define nGC2ENABLE 0x0 | ||
2059 | #define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */ | ||
2060 | #define nGC3ENABLE 0x0 | ||
2061 | #define GCCONTROL 0x3000000 /* DDR Grant Count Control */ | ||
2062 | |||
2063 | /* Bit masks for EBIU_DDRMCCL */ | ||
2064 | |||
2065 | #define CB0WCOUNT 0x1 /* Clear write count 0 */ | ||
2066 | #define nCB0WCOUNT 0x0 | ||
2067 | #define CB1WCOUNT 0x2 /* Clear write count 1 */ | ||
2068 | #define nCB1WCOUNT 0x0 | ||
2069 | #define CB2WCOUNT 0x4 /* Clear write count 2 */ | ||
2070 | #define nCB2WCOUNT 0x0 | ||
2071 | #define CB3WCOUNT 0x8 /* Clear write count 3 */ | ||
2072 | #define nCB3WCOUNT 0x0 | ||
2073 | #define CB4WCOUNT 0x10 /* Clear write count 4 */ | ||
2074 | #define nCB4WCOUNT 0x0 | ||
2075 | #define CB5WCOUNT 0x20 /* Clear write count 5 */ | ||
2076 | #define nCB5WCOUNT 0x0 | ||
2077 | #define CB6WCOUNT 0x40 /* Clear write count 6 */ | ||
2078 | #define nCB6WCOUNT 0x0 | ||
2079 | #define CB7WCOUNT 0x80 /* Clear write count 7 */ | ||
2080 | #define nCB7WCOUNT 0x0 | ||
2081 | #define CBRCOUNT 0x100 /* Clear read count 0 */ | ||
2082 | #define nCBRCOUNT 0x0 | ||
2083 | #define CB1RCOUNT 0x200 /* Clear read count 1 */ | ||
2084 | #define nCB1RCOUNT 0x0 | ||
2085 | #define CB2RCOUNT 0x400 /* Clear read count 2 */ | ||
2086 | #define nCB2RCOUNT 0x0 | ||
2087 | #define CB3RCOUNT 0x800 /* Clear read count 3 */ | ||
2088 | #define nCB3RCOUNT 0x0 | ||
2089 | #define CB4RCOUNT 0x1000 /* Clear read count 4 */ | ||
2090 | #define nCB4RCOUNT 0x0 | ||
2091 | #define CB5RCOUNT 0x2000 /* Clear read count 5 */ | ||
2092 | #define nCB5RCOUNT 0x0 | ||
2093 | #define CB6RCOUNT 0x4000 /* Clear read count 6 */ | ||
2094 | #define nCB6RCOUNT 0x0 | ||
2095 | #define CB7RCOUNT 0x8000 /* Clear read count 7 */ | ||
2096 | #define nCB7RCOUNT 0x0 | ||
2097 | #define CRACOUNT 0x10000 /* Clear row activation count */ | ||
2098 | #define nCRACOUNT 0x0 | ||
2099 | #define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */ | ||
2100 | #define nCRWTACOUNT 0x0 | ||
2101 | #define CARCOUNT 0x40000 /* Clear auto-refresh count */ | ||
2102 | #define nCARCOUNT 0x0 | ||
2103 | #define CG0COUNT 0x100000 /* Clear grant count 0 */ | ||
2104 | #define nCG0COUNT 0x0 | ||
2105 | #define CG1COUNT 0x200000 /* Clear grant count 1 */ | ||
2106 | #define nCG1COUNT 0x0 | ||
2107 | #define CG2COUNT 0x400000 /* Clear grant count 2 */ | ||
2108 | #define nCG2COUNT 0x0 | ||
2109 | #define CG3COUNT 0x800000 /* Clear grant count 3 */ | ||
2110 | #define nCG3COUNT 0x0 | ||
2111 | |||
2112 | /* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */ | ||
2113 | |||
2114 | #define Px0 0x1 /* GPIO 0 */ | ||
2115 | #define nPx0 0x0 | ||
2116 | #define Px1 0x2 /* GPIO 1 */ | ||
2117 | #define nPx1 0x0 | ||
2118 | #define Px2 0x4 /* GPIO 2 */ | ||
2119 | #define nPx2 0x0 | ||
2120 | #define Px3 0x8 /* GPIO 3 */ | ||
2121 | #define nPx3 0x0 | ||
2122 | #define Px4 0x10 /* GPIO 4 */ | ||
2123 | #define nPx4 0x0 | ||
2124 | #define Px5 0x20 /* GPIO 5 */ | ||
2125 | #define nPx5 0x0 | ||
2126 | #define Px6 0x40 /* GPIO 6 */ | ||
2127 | #define nPx6 0x0 | ||
2128 | #define Px7 0x80 /* GPIO 7 */ | ||
2129 | #define nPx7 0x0 | ||
2130 | #define Px8 0x100 /* GPIO 8 */ | ||
2131 | #define nPx8 0x0 | ||
2132 | #define Px9 0x200 /* GPIO 9 */ | ||
2133 | #define nPx9 0x0 | ||
2134 | #define Px10 0x400 /* GPIO 10 */ | ||
2135 | #define nPx10 0x0 | ||
2136 | #define Px11 0x800 /* GPIO 11 */ | ||
2137 | #define nPx11 0x0 | ||
2138 | #define Px12 0x1000 /* GPIO 12 */ | ||
2139 | #define nPx12 0x0 | ||
2140 | #define Px13 0x2000 /* GPIO 13 */ | ||
2141 | #define nPx13 0x0 | ||
2142 | #define Px14 0x4000 /* GPIO 14 */ | ||
2143 | #define nPx14 0x0 | ||
2144 | #define Px15 0x8000 /* GPIO 15 */ | ||
2145 | #define nPx15 0x0 | ||
2146 | |||
2147 | /* Bit masks for PORTA_MUX - PORTJ_MUX */ | ||
2148 | |||
2149 | #define PxM0 0x3 /* GPIO Mux 0 */ | ||
2150 | #define PxM1 0xc /* GPIO Mux 1 */ | ||
2151 | #define PxM2 0x30 /* GPIO Mux 2 */ | ||
2152 | #define PxM3 0xc0 /* GPIO Mux 3 */ | ||
2153 | #define PxM4 0x300 /* GPIO Mux 4 */ | ||
2154 | #define PxM5 0xc00 /* GPIO Mux 5 */ | ||
2155 | #define PxM6 0x3000 /* GPIO Mux 6 */ | ||
2156 | #define PxM7 0xc000 /* GPIO Mux 7 */ | ||
2157 | #define PxM8 0x30000 /* GPIO Mux 8 */ | ||
2158 | #define PxM9 0xc0000 /* GPIO Mux 9 */ | ||
2159 | #define PxM10 0x300000 /* GPIO Mux 10 */ | ||
2160 | #define PxM11 0xc00000 /* GPIO Mux 11 */ | ||
2161 | #define PxM12 0x3000000 /* GPIO Mux 12 */ | ||
2162 | #define PxM13 0xc000000 /* GPIO Mux 13 */ | ||
2163 | #define PxM14 0x30000000 /* GPIO Mux 14 */ | ||
2164 | #define PxM15 0xc0000000 /* GPIO Mux 15 */ | ||
2165 | |||
2166 | |||
2167 | /* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */ | ||
2168 | |||
2169 | #define IB0 0x1 /* Interrupt Bit 0 */ | ||
2170 | #define nIB0 0x0 | ||
2171 | #define IB1 0x2 /* Interrupt Bit 1 */ | ||
2172 | #define nIB1 0x0 | ||
2173 | #define IB2 0x4 /* Interrupt Bit 2 */ | ||
2174 | #define nIB2 0x0 | ||
2175 | #define IB3 0x8 /* Interrupt Bit 3 */ | ||
2176 | #define nIB3 0x0 | ||
2177 | #define IB4 0x10 /* Interrupt Bit 4 */ | ||
2178 | #define nIB4 0x0 | ||
2179 | #define IB5 0x20 /* Interrupt Bit 5 */ | ||
2180 | #define nIB5 0x0 | ||
2181 | #define IB6 0x40 /* Interrupt Bit 6 */ | ||
2182 | #define nIB6 0x0 | ||
2183 | #define IB7 0x80 /* Interrupt Bit 7 */ | ||
2184 | #define nIB7 0x0 | ||
2185 | #define IB8 0x100 /* Interrupt Bit 8 */ | ||
2186 | #define nIB8 0x0 | ||
2187 | #define IB9 0x200 /* Interrupt Bit 9 */ | ||
2188 | #define nIB9 0x0 | ||
2189 | #define IB10 0x400 /* Interrupt Bit 10 */ | ||
2190 | #define nIB10 0x0 | ||
2191 | #define IB11 0x800 /* Interrupt Bit 11 */ | ||
2192 | #define nIB11 0x0 | ||
2193 | #define IB12 0x1000 /* Interrupt Bit 12 */ | ||
2194 | #define nIB12 0x0 | ||
2195 | #define IB13 0x2000 /* Interrupt Bit 13 */ | ||
2196 | #define nIB13 0x0 | ||
2197 | #define IB14 0x4000 /* Interrupt Bit 14 */ | ||
2198 | #define nIB14 0x0 | ||
2199 | #define IB15 0x8000 /* Interrupt Bit 15 */ | ||
2200 | #define nIB15 0x0 | ||
2201 | |||
2202 | /* Bit masks for TIMERx_CONFIG */ | ||
2203 | |||
2204 | #define TMODE 0x3 /* Timer Mode */ | ||
2205 | #define PULSE_HI 0x4 /* Pulse Polarity */ | ||
2206 | #define nPULSE_HI 0x0 | ||
2207 | #define PERIOD_CNT 0x8 /* Period Count */ | ||
2208 | #define nPERIOD_CNT 0x0 | ||
2209 | #define IRQ_ENA 0x10 /* Interrupt Request Enable */ | ||
2210 | #define nIRQ_ENA 0x0 | ||
2211 | #define TIN_SEL 0x20 /* Timer Input Select */ | ||
2212 | #define nTIN_SEL 0x0 | ||
2213 | #define OUT_DIS 0x40 /* Output Pad Disable */ | ||
2214 | #define nOUT_DIS 0x0 | ||
2215 | #define CLK_SEL 0x80 /* Timer Clock Select */ | ||
2216 | #define nCLK_SEL 0x0 | ||
2217 | #define TOGGLE_HI 0x100 /* Toggle Mode */ | ||
2218 | #define nTOGGLE_HI 0x0 | ||
2219 | #define EMU_RUN 0x200 /* Emulation Behavior Select */ | ||
2220 | #define nEMU_RUN 0x0 | ||
2221 | #define ERR_TYP 0xc000 /* Error Type */ | ||
2222 | |||
2223 | /* Bit masks for TIMER_ENABLE0 */ | ||
2224 | |||
2225 | #define TIMEN0 0x1 /* Timer 0 Enable */ | ||
2226 | #define nTIMEN0 0x0 | ||
2227 | #define TIMEN1 0x2 /* Timer 1 Enable */ | ||
2228 | #define nTIMEN1 0x0 | ||
2229 | #define TIMEN2 0x4 /* Timer 2 Enable */ | ||
2230 | #define nTIMEN2 0x0 | ||
2231 | #define TIMEN3 0x8 /* Timer 3 Enable */ | ||
2232 | #define nTIMEN3 0x0 | ||
2233 | #define TIMEN4 0x10 /* Timer 4 Enable */ | ||
2234 | #define nTIMEN4 0x0 | ||
2235 | #define TIMEN5 0x20 /* Timer 5 Enable */ | ||
2236 | #define nTIMEN5 0x0 | ||
2237 | #define TIMEN6 0x40 /* Timer 6 Enable */ | ||
2238 | #define nTIMEN6 0x0 | ||
2239 | #define TIMEN7 0x80 /* Timer 7 Enable */ | ||
2240 | #define nTIMEN7 0x0 | ||
2241 | |||
2242 | /* Bit masks for TIMER_DISABLE0 */ | ||
2243 | |||
2244 | #define TIMDIS0 0x1 /* Timer 0 Disable */ | ||
2245 | #define nTIMDIS0 0x0 | ||
2246 | #define TIMDIS1 0x2 /* Timer 1 Disable */ | ||
2247 | #define nTIMDIS1 0x0 | ||
2248 | #define TIMDIS2 0x4 /* Timer 2 Disable */ | ||
2249 | #define nTIMDIS2 0x0 | ||
2250 | #define TIMDIS3 0x8 /* Timer 3 Disable */ | ||
2251 | #define nTIMDIS3 0x0 | ||
2252 | #define TIMDIS4 0x10 /* Timer 4 Disable */ | ||
2253 | #define nTIMDIS4 0x0 | ||
2254 | #define TIMDIS5 0x20 /* Timer 5 Disable */ | ||
2255 | #define nTIMDIS5 0x0 | ||
2256 | #define TIMDIS6 0x40 /* Timer 6 Disable */ | ||
2257 | #define nTIMDIS6 0x0 | ||
2258 | #define TIMDIS7 0x80 /* Timer 7 Disable */ | ||
2259 | #define nTIMDIS7 0x0 | ||
2260 | |||
2261 | /* Bit masks for TIMER_STATUS0 */ | ||
2262 | |||
2263 | #define TIMIL0 0x1 /* Timer 0 Interrupt */ | ||
2264 | #define nTIMIL0 0x0 | ||
2265 | #define TIMIL1 0x2 /* Timer 1 Interrupt */ | ||
2266 | #define nTIMIL1 0x0 | ||
2267 | #define TIMIL2 0x4 /* Timer 2 Interrupt */ | ||
2268 | #define nTIMIL2 0x0 | ||
2269 | #define TIMIL3 0x8 /* Timer 3 Interrupt */ | ||
2270 | #define nTIMIL3 0x0 | ||
2271 | #define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */ | ||
2272 | #define nTOVF_ERR0 0x0 | ||
2273 | #define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */ | ||
2274 | #define nTOVF_ERR1 0x0 | ||
2275 | #define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */ | ||
2276 | #define nTOVF_ERR2 0x0 | ||
2277 | #define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */ | ||
2278 | #define nTOVF_ERR3 0x0 | ||
2279 | #define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ | ||
2280 | #define nTRUN0 0x0 | ||
2281 | #define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ | ||
2282 | #define nTRUN1 0x0 | ||
2283 | #define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ | ||
2284 | #define nTRUN2 0x0 | ||
2285 | #define TRUN3 0x8000 /* Timer 3 Slave Enable Status */ | ||
2286 | #define nTRUN3 0x0 | ||
2287 | #define TIMIL4 0x10000 /* Timer 4 Interrupt */ | ||
2288 | #define nTIMIL4 0x0 | ||
2289 | #define TIMIL5 0x20000 /* Timer 5 Interrupt */ | ||
2290 | #define nTIMIL5 0x0 | ||
2291 | #define TIMIL6 0x40000 /* Timer 6 Interrupt */ | ||
2292 | #define nTIMIL6 0x0 | ||
2293 | #define TIMIL7 0x80000 /* Timer 7 Interrupt */ | ||
2294 | #define nTIMIL7 0x0 | ||
2295 | #define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */ | ||
2296 | #define nTOVF_ERR4 0x0 | ||
2297 | #define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */ | ||
2298 | #define nTOVF_ERR5 0x0 | ||
2299 | #define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */ | ||
2300 | #define nTOVF_ERR6 0x0 | ||
2301 | #define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */ | ||
2302 | #define nTOVF_ERR7 0x0 | ||
2303 | #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ | ||
2304 | #define nTRUN4 0x0 | ||
2305 | #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ | ||
2306 | #define nTRUN5 0x0 | ||
2307 | #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ | ||
2308 | #define nTRUN6 0x0 | ||
2309 | #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ | ||
2310 | #define nTRUN7 0x0 | ||
2311 | |||
2312 | /* Bit masks for WDOG_CTL */ | ||
2313 | |||
2314 | #define WDEV 0x6 /* Watchdog Event */ | ||
2315 | #define WDEN 0xff0 /* Watchdog Enable */ | ||
2316 | #define WDRO 0x8000 /* Watchdog Rolled Over */ | ||
2317 | #define nWDRO 0x0 | ||
2318 | |||
2319 | /* Bit masks for CNT_CONFIG */ | ||
2320 | |||
2321 | #define CNTE 0x1 /* Counter Enable */ | ||
2322 | #define nCNTE 0x0 | ||
2323 | #define DEBE 0x2 /* Debounce Enable */ | ||
2324 | #define nDEBE 0x0 | ||
2325 | #define CDGINV 0x10 /* CDG Pin Polarity Invert */ | ||
2326 | #define nCDGINV 0x0 | ||
2327 | #define CUDINV 0x20 /* CUD Pin Polarity Invert */ | ||
2328 | #define nCUDINV 0x0 | ||
2329 | #define CZMINV 0x40 /* CZM Pin Polarity Invert */ | ||
2330 | #define nCZMINV 0x0 | ||
2331 | #define CNTMODE 0x700 /* Counter Operating Mode */ | ||
2332 | #define ZMZC 0x800 /* CZM Zeroes Counter Enable */ | ||
2333 | #define nZMZC 0x0 | ||
2334 | #define BNDMODE 0x3000 /* Boundary register Mode */ | ||
2335 | #define INPDIS 0x8000 /* CUG and CDG Input Disable */ | ||
2336 | #define nINPDIS 0x0 | ||
2337 | |||
2338 | /* Bit masks for CNT_IMASK */ | ||
2339 | |||
2340 | #define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ | ||
2341 | #define nICIE 0x0 | ||
2342 | #define UCIE 0x2 /* Up count Interrupt Enable */ | ||
2343 | #define nUCIE 0x0 | ||
2344 | #define DCIE 0x4 /* Down count Interrupt Enable */ | ||
2345 | #define nDCIE 0x0 | ||
2346 | #define MINCIE 0x8 /* Min Count Interrupt Enable */ | ||
2347 | #define nMINCIE 0x0 | ||
2348 | #define MAXCIE 0x10 /* Max Count Interrupt Enable */ | ||
2349 | #define nMAXCIE 0x0 | ||
2350 | #define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ | ||
2351 | #define nCOV31IE 0x0 | ||
2352 | #define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ | ||
2353 | #define nCOV15IE 0x0 | ||
2354 | #define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ | ||
2355 | #define nCZEROIE 0x0 | ||
2356 | #define CZMIE 0x100 /* CZM Pin Interrupt Enable */ | ||
2357 | #define nCZMIE 0x0 | ||
2358 | #define CZMEIE 0x200 /* CZM Error Interrupt Enable */ | ||
2359 | #define nCZMEIE 0x0 | ||
2360 | #define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ | ||
2361 | #define nCZMZIE 0x0 | ||
2362 | |||
2363 | /* Bit masks for CNT_STATUS */ | ||
2364 | |||
2365 | #define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ | ||
2366 | #define nICII 0x0 | ||
2367 | #define UCII 0x2 /* Up count Interrupt Identifier */ | ||
2368 | #define nUCII 0x0 | ||
2369 | #define DCII 0x4 /* Down count Interrupt Identifier */ | ||
2370 | #define nDCII 0x0 | ||
2371 | #define MINCII 0x8 /* Min Count Interrupt Identifier */ | ||
2372 | #define nMINCII 0x0 | ||
2373 | #define MAXCII 0x10 /* Max Count Interrupt Identifier */ | ||
2374 | #define nMAXCII 0x0 | ||
2375 | #define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ | ||
2376 | #define nCOV31II 0x0 | ||
2377 | #define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ | ||
2378 | #define nCOV15II 0x0 | ||
2379 | #define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ | ||
2380 | #define nCZEROII 0x0 | ||
2381 | #define CZMII 0x100 /* CZM Pin Interrupt Identifier */ | ||
2382 | #define nCZMII 0x0 | ||
2383 | #define CZMEII 0x200 /* CZM Error Interrupt Identifier */ | ||
2384 | #define nCZMEII 0x0 | ||
2385 | #define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ | ||
2386 | #define nCZMZII 0x0 | ||
2387 | |||
2388 | /* Bit masks for CNT_COMMAND */ | ||
2389 | |||
2390 | #define W1LCNT 0xf /* Load Counter Register */ | ||
2391 | #define W1LMIN 0xf0 /* Load Min Register */ | ||
2392 | #define W1LMAX 0xf00 /* Load Max Register */ | ||
2393 | #define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ | ||
2394 | #define nW1ZMONCE 0x0 | ||
2395 | |||
2396 | /* Bit masks for CNT_DEBOUNCE */ | ||
2397 | |||
2398 | #define DPRESCALE 0xf /* Load Counter Register */ | ||
2399 | |||
2400 | /* Bit masks for RTC_STAT */ | ||
2401 | |||
2402 | #define SECONDS 0x3f /* Seconds */ | ||
2403 | #define MINUTES 0xfc0 /* Minutes */ | ||
2404 | #define HOURS 0x1f000 /* Hours */ | ||
2405 | #define DAY_COUNTER 0xfffe0000 /* Day Counter */ | ||
2406 | |||
2407 | /* Bit masks for RTC_ICTL */ | ||
2408 | |||
2409 | #define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */ | ||
2410 | #define nSTOPWATCH_INTERRUPT_ENABLE 0x0 | ||
2411 | #define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */ | ||
2412 | #define nALARM_INTERRUPT_ENABLE 0x0 | ||
2413 | #define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */ | ||
2414 | #define nSECONDS_INTERRUPT_ENABLE 0x0 | ||
2415 | #define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */ | ||
2416 | #define nMINUTES_INTERRUPT_ENABLE 0x0 | ||
2417 | #define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */ | ||
2418 | #define nHOURS_INTERRUPT_ENABLE 0x0 | ||
2419 | #define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */ | ||
2420 | #define nTWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x0 | ||
2421 | #define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */ | ||
2422 | #define nDAY_ALARM_INTERRUPT_ENABLE 0x0 | ||
2423 | #define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */ | ||
2424 | #define nWRITE_COMPLETE_INTERRUPT_ENABLE 0x0 | ||
2425 | |||
2426 | /* Bit masks for RTC_ISTAT */ | ||
2427 | |||
2428 | #define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */ | ||
2429 | #define nSTOPWATCH_EVENT_FLAG 0x0 | ||
2430 | #define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */ | ||
2431 | #define nALARM_EVENT_FLAG 0x0 | ||
2432 | #define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */ | ||
2433 | #define nSECONDS_EVENT_FLAG 0x0 | ||
2434 | #define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */ | ||
2435 | #define nMINUTES_EVENT_FLAG 0x0 | ||
2436 | #define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */ | ||
2437 | #define nHOURS_EVENT_FLAG 0x0 | ||
2438 | #define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */ | ||
2439 | #define nTWENTY_FOUR_HOURS_EVENT_FLAG 0x0 | ||
2440 | #define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */ | ||
2441 | #define nDAY_ALARM_EVENT_FLAG 0x0 | ||
2442 | #define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */ | ||
2443 | #define nWRITE_PENDING__STATUS 0x0 | ||
2444 | #define WRITE_COMPLETE 0x8000 /* Write Complete */ | ||
2445 | #define nWRITE_COMPLETE 0x0 | ||
2446 | |||
2447 | /* Bit masks for RTC_SWCNT */ | ||
2448 | |||
2449 | #define STOPWATCH_COUNT 0xffff /* Stopwatch Count */ | ||
2450 | |||
2451 | /* Bit masks for RTC_ALARM */ | ||
2452 | |||
2453 | #define SECONDS 0x3f /* Seconds */ | ||
2454 | #define MINUTES 0xfc0 /* Minutes */ | ||
2455 | #define HOURS 0x1f000 /* Hours */ | ||
2456 | #define DAY 0xfffe0000 /* Day */ | ||
2457 | |||
2458 | /* Bit masks for RTC_PREN */ | ||
2459 | |||
2460 | #define PREN 0x1 /* Prescaler Enable */ | ||
2461 | #define nPREN 0x0 | ||
2462 | |||
2463 | /* Bit masks for OTP_CONTROL */ | ||
2464 | |||
2465 | #define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ | ||
2466 | #define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ | ||
2467 | #define nFIEN 0x0 | ||
2468 | #define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ | ||
2469 | #define nFTESTDEC 0x0 | ||
2470 | #define FWRTEST 0x2000 /* OTP/Fuse Write Test */ | ||
2471 | #define nFWRTEST 0x0 | ||
2472 | #define FRDEN 0x4000 /* OTP/Fuse Read Enable */ | ||
2473 | #define nFRDEN 0x0 | ||
2474 | #define FWREN 0x8000 /* OTP/Fuse Write Enable */ | ||
2475 | #define nFWREN 0x0 | ||
2476 | |||
2477 | /* Bit masks for OTP_BEN */ | ||
2478 | |||
2479 | #define FBEN 0xffff /* OTP/Fuse Byte Enable */ | ||
2480 | |||
2481 | /* Bit masks for OTP_STATUS */ | ||
2482 | |||
2483 | #define FCOMP 0x1 /* OTP/Fuse Access Complete */ | ||
2484 | #define nFCOMP 0x0 | ||
2485 | #define FERROR 0x2 /* OTP/Fuse Access Error */ | ||
2486 | #define nFERROR 0x0 | ||
2487 | #define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ | ||
2488 | #define nMMRGLOAD 0x0 | ||
2489 | #define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ | ||
2490 | #define nMMRGLOCK 0x0 | ||
2491 | #define FPGMEN 0x40 /* OTP/Fuse Program Enable */ | ||
2492 | #define nFPGMEN 0x0 | ||
2493 | |||
2494 | /* Bit masks for OTP_TIMING */ | ||
2495 | |||
2496 | #define USECDIV 0xff /* Micro Second Divider */ | ||
2497 | #define READACC 0x7f00 /* Read Access Time */ | ||
2498 | #define CPUMPRL 0x38000 /* Charge Pump Release Time */ | ||
2499 | #define CPUMPSU 0xc0000 /* Charge Pump Setup Time */ | ||
2500 | #define CPUMPHD 0xf00000 /* Charge Pump Hold Time */ | ||
2501 | #define PGMTIME 0xff000000 /* Program Time */ | ||
2502 | |||
2503 | /* Bit masks for SECURE_SYSSWT */ | ||
2504 | |||
2505 | #define EMUDABL 0x1 /* Emulation Disable. */ | ||
2506 | #define nEMUDABL 0x0 | ||
2507 | #define RSTDABL 0x2 /* Reset Disable */ | ||
2508 | #define nRSTDABL 0x0 | ||
2509 | #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ | ||
2510 | #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ | ||
2511 | #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ | ||
2512 | #define DMA0OVR 0x800 /* DMA0 Memory Access Override */ | ||
2513 | #define nDMA0OVR 0x0 | ||
2514 | #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ | ||
2515 | #define nDMA1OVR 0x0 | ||
2516 | #define EMUOVR 0x4000 /* Emulation Override */ | ||
2517 | #define nEMUOVR 0x0 | ||
2518 | #define OTPSEN 0x8000 /* OTP Secrets Enable. */ | ||
2519 | #define nOTPSEN 0x0 | ||
2520 | #define L2DABL 0x70000 /* L2 Memory Disable. */ | ||
2521 | |||
2522 | /* Bit masks for SECURE_CONTROL */ | ||
2523 | |||
2524 | #define SECURE0 0x1 /* SECURE 0 */ | ||
2525 | #define nSECURE0 0x0 | ||
2526 | #define SECURE1 0x2 /* SECURE 1 */ | ||
2527 | #define nSECURE1 0x0 | ||
2528 | #define SECURE2 0x4 /* SECURE 2 */ | ||
2529 | #define nSECURE2 0x0 | ||
2530 | #define SECURE3 0x8 /* SECURE 3 */ | ||
2531 | #define nSECURE3 0x0 | ||
2532 | |||
2533 | /* Bit masks for SECURE_STATUS */ | ||
2534 | |||
2535 | #define SECMODE 0x3 /* Secured Mode Control State */ | ||
2536 | #define NMI 0x4 /* Non Maskable Interrupt */ | ||
2537 | #define nNMI 0x0 | ||
2538 | #define AFVALID 0x8 /* Authentication Firmware Valid */ | ||
2539 | #define nAFVALID 0x0 | ||
2540 | #define AFEXIT 0x10 /* Authentication Firmware Exit */ | ||
2541 | #define nAFEXIT 0x0 | ||
2542 | #define SECSTAT 0xe0 /* Secure Status */ | ||
2543 | |||
2544 | /* Bit masks for PLL_DIV */ | ||
2545 | |||
2546 | #define CSEL 0x30 /* Core Select */ | ||
2547 | #define SSEL 0xf /* System Select */ | ||
2548 | |||
2549 | /* Bit masks for PLL_CTL */ | ||
2550 | |||
2551 | #define MSEL 0x7e00 /* Multiplier Select */ | ||
2552 | #define BYPASS 0x100 /* PLL Bypass Enable */ | ||
2553 | #define nBYPASS 0x0 | ||
2554 | #define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */ | ||
2555 | #define nOUTPUT_DELAY 0x0 | ||
2556 | #define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */ | ||
2557 | #define nINPUT_DELAY 0x0 | ||
2558 | #define PDWN 0x20 /* Power Down */ | ||
2559 | #define nPDWN 0x0 | ||
2560 | #define STOPCK 0x8 /* Stop Clock */ | ||
2561 | #define nSTOPCK 0x0 | ||
2562 | #define PLL_OFF 0x2 /* Disable PLL */ | ||
2563 | #define nPLL_OFF 0x0 | ||
2564 | #define DF 0x1 /* Divide Frequency */ | ||
2565 | #define nDF 0x0 | ||
2566 | |||
2567 | /* Bit masks for PLL_STAT */ | ||
2568 | |||
2569 | #define PLL_LOCKED 0x20 /* PLL Locked Status */ | ||
2570 | #define nPLL_LOCKED 0x0 | ||
2571 | #define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */ | ||
2572 | #define nACTIVE_PLLDISABLED 0x0 | ||
2573 | #define FULL_ON 0x2 /* Full-On Mode */ | ||
2574 | #define nFULL_ON 0x0 | ||
2575 | #define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */ | ||
2576 | #define nACTIVE_PLLENABLED 0x0 | ||
2577 | #define RTCWS 0x400 /* RTC/Reset Wake-Up Status */ | ||
2578 | #define nRTCWS 0x0 | ||
2579 | #define CANWS 0x800 /* CAN Wake-Up Status */ | ||
2580 | #define nCANWS 0x0 | ||
2581 | #define USBWS 0x2000 /* USB Wake-Up Status */ | ||
2582 | #define nUSBWS 0x0 | ||
2583 | #define KPADWS 0x4000 /* Keypad Wake-Up Status */ | ||
2584 | #define nKPADWS 0x0 | ||
2585 | #define ROTWS 0x8000 /* Rotary Wake-Up Status */ | ||
2586 | #define nROTWS 0x0 | ||
2587 | #define GPWS 0x1000 /* General-Purpose Wake-Up Status */ | ||
2588 | #define nGPWS 0x0 | ||
2589 | |||
2590 | /* Bit masks for VR_CTL */ | ||
2591 | |||
2592 | #define FREQ 0x3 /* Regulator Switching Frequency */ | ||
2593 | #define GAIN 0xc /* Voltage Output Level Gain */ | ||
2594 | #define VLEV 0xf0 /* Internal Voltage Level */ | ||
2595 | #define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */ | ||
2596 | #define nSCKELOW 0x0 | ||
2597 | #define WAKE 0x100 /* RTC/Reset Wake-Up Enable */ | ||
2598 | #define nWAKE 0x0 | ||
2599 | #define CANWE 0x200 /* CAN0/1 Wake-Up Enable */ | ||
2600 | #define nCANWE 0x0 | ||
2601 | #define GPWE 0x400 /* General-Purpose Wake-Up Enable */ | ||
2602 | #define nGPWE 0x0 | ||
2603 | #define USBWE 0x800 /* USB Wake-Up Enable */ | ||
2604 | #define nUSBWE 0x0 | ||
2605 | #define KPADWE 0x1000 /* Keypad Wake-Up Enable */ | ||
2606 | #define nKPADWE 0x0 | ||
2607 | #define ROTWE 0x2000 /* Rotary Wake-Up Enable */ | ||
2608 | #define nROTWE 0x0 | ||
2609 | |||
2610 | /* Bit masks for NFC_CTL */ | ||
2611 | |||
2612 | #define WR_DLY 0xf /* Write Strobe Delay */ | ||
2613 | #define RD_DLY 0xf0 /* Read Strobe Delay */ | ||
2614 | #define NWIDTH 0x100 /* NAND Data Width */ | ||
2615 | #define nNWIDTH 0x0 | ||
2616 | #define PG_SIZE 0x200 /* Page Size */ | ||
2617 | #define nPG_SIZE 0x0 | ||
2618 | |||
2619 | /* Bit masks for NFC_STAT */ | ||
2620 | |||
2621 | #define NBUSY 0x1 /* Not Busy */ | ||
2622 | #define nNBUSY 0x0 | ||
2623 | #define WB_FULL 0x2 /* Write Buffer Full */ | ||
2624 | #define nWB_FULL 0x0 | ||
2625 | #define PG_WR_STAT 0x4 /* Page Write Pending */ | ||
2626 | #define nPG_WR_STAT 0x0 | ||
2627 | #define PG_RD_STAT 0x8 /* Page Read Pending */ | ||
2628 | #define nPG_RD_STAT 0x0 | ||
2629 | #define WB_EMPTY 0x10 /* Write Buffer Empty */ | ||
2630 | #define nWB_EMPTY 0x0 | ||
2631 | |||
2632 | /* Bit masks for NFC_IRQSTAT */ | ||
2633 | |||
2634 | #define NBUSYIRQ 0x1 /* Not Busy IRQ */ | ||
2635 | #define nNBUSYIRQ 0x0 | ||
2636 | #define WB_OVF 0x2 /* Write Buffer Overflow */ | ||
2637 | #define nWB_OVF 0x0 | ||
2638 | #define WB_EDGE 0x4 /* Write Buffer Edge Detect */ | ||
2639 | #define nWB_EDGE 0x0 | ||
2640 | #define RD_RDY 0x8 /* Read Data Ready */ | ||
2641 | #define nRD_RDY 0x0 | ||
2642 | #define WR_DONE 0x10 /* Page Write Done */ | ||
2643 | #define nWR_DONE 0x0 | ||
2644 | |||
2645 | /* Bit masks for NFC_IRQMASK */ | ||
2646 | |||
2647 | #define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ | ||
2648 | #define nMASK_BUSYIRQ 0x0 | ||
2649 | #define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ | ||
2650 | #define nMASK_WBOVF 0x0 | ||
2651 | #define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ | ||
2652 | #define nMASK_WBEMPTY 0x0 | ||
2653 | #define MASK_RDRDY 0x8 /* Mask Read Data Ready */ | ||
2654 | #define nMASK_RDRDY 0x0 | ||
2655 | #define MASK_WRDONE 0x10 /* Mask Write Done */ | ||
2656 | #define nMASK_WRDONE 0x0 | ||
2657 | |||
2658 | /* Bit masks for NFC_RST */ | ||
2659 | |||
2660 | #define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ | ||
2661 | #define nECC_RST 0x0 | ||
2662 | |||
2663 | /* Bit masks for NFC_PGCTL */ | ||
2664 | |||
2665 | #define PG_RD_START 0x1 /* Page Read Start */ | ||
2666 | #define nPG_RD_START 0x0 | ||
2667 | #define PG_WR_START 0x2 /* Page Write Start */ | ||
2668 | #define nPG_WR_START 0x0 | ||
2669 | |||
2670 | /* Bit masks for NFC_ECC0 */ | ||
2671 | |||
2672 | #define ECC0 0x7ff /* Parity Calculation Result0 */ | ||
2673 | |||
2674 | /* Bit masks for NFC_ECC1 */ | ||
2675 | |||
2676 | #define ECC1 0x7ff /* Parity Calculation Result1 */ | ||
2677 | |||
2678 | /* Bit masks for NFC_ECC2 */ | ||
2679 | |||
2680 | #define ECC2 0x7ff /* Parity Calculation Result2 */ | ||
2681 | |||
2682 | /* Bit masks for NFC_ECC3 */ | ||
2683 | |||
2684 | #define ECC3 0x7ff /* Parity Calculation Result3 */ | ||
2685 | |||
2686 | /* Bit masks for NFC_COUNT */ | ||
2687 | |||
2688 | #define ECCCNT 0x3ff /* Transfer Count */ | ||
2689 | |||
2690 | /* Bit masks for CAN0_CONTROL */ | ||
2691 | |||
2692 | #define SRS 0x1 /* Software Reset */ | ||
2693 | #define nSRS 0x0 | ||
2694 | #define DNM 0x2 /* DeviceNet Mode */ | ||
2695 | #define nDNM 0x0 | ||
2696 | #define ABO 0x4 /* Auto Bus On */ | ||
2697 | #define nABO 0x0 | ||
2698 | #define WBA 0x10 /* Wakeup On CAN Bus Activity */ | ||
2699 | #define nWBA 0x0 | ||
2700 | #define SMR 0x20 /* Sleep Mode Request */ | ||
2701 | #define nSMR 0x0 | ||
2702 | #define CSR 0x40 /* CAN Suspend Mode Request */ | ||
2703 | #define nCSR 0x0 | ||
2704 | #define CCR 0x80 /* CAN Configuration Mode Request */ | ||
2705 | #define nCCR 0x0 | ||
2706 | |||
2707 | /* Bit masks for CAN0_STATUS */ | ||
2708 | |||
2709 | #define WT 0x1 /* CAN Transmit Warning Flag */ | ||
2710 | #define nWT 0x0 | ||
2711 | #define WR 0x2 /* CAN Receive Warning Flag */ | ||
2712 | #define nWR 0x0 | ||
2713 | #define EP 0x4 /* CAN Error Passive Mode */ | ||
2714 | #define nEP 0x0 | ||
2715 | #define EBO 0x8 /* CAN Error Bus Off Mode */ | ||
2716 | #define nEBO 0x0 | ||
2717 | #define CSA 0x40 /* CAN Suspend Mode Acknowledge */ | ||
2718 | #define nCSA 0x0 | ||
2719 | #define CCA 0x80 /* CAN Configuration Mode Acknowledge */ | ||
2720 | #define nCCA 0x0 | ||
2721 | #define MBPTR 0x1f00 /* Mailbox Pointer */ | ||
2722 | #define TRM 0x4000 /* Transmit Mode Status */ | ||
2723 | #define nTRM 0x0 | ||
2724 | #define REC 0x8000 /* Receive Mode Status */ | ||
2725 | #define nREC 0x0 | ||
2726 | |||
2727 | /* Bit masks for CAN0_DEBUG */ | ||
2728 | |||
2729 | #define DEC 0x1 /* Disable Transmit/Receive Error Counters */ | ||
2730 | #define nDEC 0x0 | ||
2731 | #define DRI 0x2 /* Disable CANRX Input Pin */ | ||
2732 | #define nDRI 0x0 | ||
2733 | #define DTO 0x4 /* Disable CANTX Output Pin */ | ||
2734 | #define nDTO 0x0 | ||
2735 | #define DIL 0x8 /* Disable Internal Loop */ | ||
2736 | #define nDIL 0x0 | ||
2737 | #define MAA 0x10 /* Mode Auto-Acknowledge */ | ||
2738 | #define nMAA 0x0 | ||
2739 | #define MRB 0x20 /* Mode Read Back */ | ||
2740 | #define nMRB 0x0 | ||
2741 | #define CDE 0x8000 /* CAN Debug Mode Enable */ | ||
2742 | #define nCDE 0x0 | ||
2743 | |||
2744 | /* Bit masks for CAN0_CLOCK */ | ||
2745 | |||
2746 | #define BRP 0x3ff /* CAN Bit Rate Prescaler */ | ||
2747 | |||
2748 | /* Bit masks for CAN0_TIMING */ | ||
2749 | |||
2750 | #define SJW 0x300 /* Synchronization Jump Width */ | ||
2751 | #define SAM 0x80 /* Sampling */ | ||
2752 | #define nSAM 0x0 | ||
2753 | #define TSEG2 0x70 /* Time Segment 2 */ | ||
2754 | #define TSEG1 0xf /* Time Segment 1 */ | ||
2755 | |||
2756 | /* Bit masks for CAN0_INTR */ | ||
2757 | |||
2758 | #define CANRX 0x80 /* Serial Input From Transceiver */ | ||
2759 | #define nCANRX 0x0 | ||
2760 | #define CANTX 0x40 /* Serial Output To Transceiver */ | ||
2761 | #define nCANTX 0x0 | ||
2762 | #define SMACK 0x8 /* Sleep Mode Acknowledge */ | ||
2763 | #define nSMACK 0x0 | ||
2764 | #define GIRQ 0x4 /* Global Interrupt Request Status */ | ||
2765 | #define nGIRQ 0x0 | ||
2766 | #define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */ | ||
2767 | #define nMBTIRQ 0x0 | ||
2768 | #define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */ | ||
2769 | #define nMBRIRQ 0x0 | ||
2770 | |||
2771 | /* Bit masks for CAN0_GIM */ | ||
2772 | |||
2773 | #define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */ | ||
2774 | #define nEWTIM 0x0 | ||
2775 | #define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */ | ||
2776 | #define nEWRIM 0x0 | ||
2777 | #define EPIM 0x4 /* Error Passive Interrupt Mask */ | ||
2778 | #define nEPIM 0x0 | ||
2779 | #define BOIM 0x8 /* Bus Off Interrupt Mask */ | ||
2780 | #define nBOIM 0x0 | ||
2781 | #define WUIM 0x10 /* Wakeup Interrupt Mask */ | ||
2782 | #define nWUIM 0x0 | ||
2783 | #define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */ | ||
2784 | #define nUIAIM 0x0 | ||
2785 | #define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */ | ||
2786 | #define nAAIM 0x0 | ||
2787 | #define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */ | ||
2788 | #define nRMLIM 0x0 | ||
2789 | #define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */ | ||
2790 | #define nUCEIM 0x0 | ||
2791 | #define ADIM 0x400 /* Access Denied Interrupt Mask */ | ||
2792 | #define nADIM 0x0 | ||
2793 | |||
2794 | /* Bit masks for CAN0_GIS */ | ||
2795 | |||
2796 | #define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */ | ||
2797 | #define nEWTIS 0x0 | ||
2798 | #define EWRIS 0x2 /* Error Warning Receive Interrupt Status */ | ||
2799 | #define nEWRIS 0x0 | ||
2800 | #define EPIS 0x4 /* Error Passive Interrupt Status */ | ||
2801 | #define nEPIS 0x0 | ||
2802 | #define BOIS 0x8 /* Bus Off Interrupt Status */ | ||
2803 | #define nBOIS 0x0 | ||
2804 | #define WUIS 0x10 /* Wakeup Interrupt Status */ | ||
2805 | #define nWUIS 0x0 | ||
2806 | #define UIAIS 0x20 /* Unimplemented Address Interrupt Status */ | ||
2807 | #define nUIAIS 0x0 | ||
2808 | #define AAIS 0x40 /* Abort Acknowledge Interrupt Status */ | ||
2809 | #define nAAIS 0x0 | ||
2810 | #define RMLIS 0x80 /* Receive Message Lost Interrupt Status */ | ||
2811 | #define nRMLIS 0x0 | ||
2812 | #define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */ | ||
2813 | #define nUCEIS 0x0 | ||
2814 | #define ADIS 0x400 /* Access Denied Interrupt Status */ | ||
2815 | #define nADIS 0x0 | ||
2816 | |||
2817 | /* Bit masks for CAN0_GIF */ | ||
2818 | |||
2819 | #define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */ | ||
2820 | #define nEWTIF 0x0 | ||
2821 | #define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */ | ||
2822 | #define nEWRIF 0x0 | ||
2823 | #define EPIF 0x4 /* Error Passive Interrupt Flag */ | ||
2824 | #define nEPIF 0x0 | ||
2825 | #define BOIF 0x8 /* Bus Off Interrupt Flag */ | ||
2826 | #define nBOIF 0x0 | ||
2827 | #define WUIF 0x10 /* Wakeup Interrupt Flag */ | ||
2828 | #define nWUIF 0x0 | ||
2829 | #define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */ | ||
2830 | #define nUIAIF 0x0 | ||
2831 | #define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */ | ||
2832 | #define nAAIF 0x0 | ||
2833 | #define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */ | ||
2834 | #define nRMLIF 0x0 | ||
2835 | #define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */ | ||
2836 | #define nUCEIF 0x0 | ||
2837 | #define ADIF 0x400 /* Access Denied Interrupt Flag */ | ||
2838 | #define nADIF 0x0 | ||
2839 | |||
2840 | /* Bit masks for CAN0_MBTD */ | ||
2841 | |||
2842 | #define TDR 0x80 /* Temporary Disable Request */ | ||
2843 | #define nTDR 0x0 | ||
2844 | #define TDA 0x40 /* Temporary Disable Acknowledge */ | ||
2845 | #define nTDA 0x0 | ||
2846 | #define TDPTR 0x1f /* Temporary Disable Pointer */ | ||
2847 | |||
2848 | /* Bit masks for CAN0_UCCNF */ | ||
2849 | |||
2850 | #define UCCNF 0xf /* Universal Counter Configuration */ | ||
2851 | #define UCRC 0x20 /* Universal Counter Reload/Clear */ | ||
2852 | #define nUCRC 0x0 | ||
2853 | #define UCCT 0x40 /* Universal Counter CAN Trigger */ | ||
2854 | #define nUCCT 0x0 | ||
2855 | #define UCE 0x80 /* Universal Counter Enable */ | ||
2856 | #define nUCE 0x0 | ||
2857 | |||
2858 | /* Bit masks for CAN0_UCCNT */ | ||
2859 | |||
2860 | #define UCCNT 0xffff /* Universal Counter Count Value */ | ||
2861 | |||
2862 | /* Bit masks for CAN0_UCRC */ | ||
2863 | |||
2864 | #define UCVAL 0xffff /* Universal Counter Reload/Capture Value */ | ||
2865 | |||
2866 | /* Bit masks for CAN0_CEC */ | ||
2867 | |||
2868 | #define RXECNT 0xff /* Receive Error Counter */ | ||
2869 | #define TXECNT 0xff00 /* Transmit Error Counter */ | ||
2870 | |||
2871 | /* Bit masks for CAN0_ESR */ | ||
2872 | |||
2873 | #define FER 0x80 /* Form Error */ | ||
2874 | #define nFER 0x0 | ||
2875 | #define BEF 0x40 /* Bit Error Flag */ | ||
2876 | #define nBEF 0x0 | ||
2877 | #define SA0 0x20 /* Stuck At Dominant */ | ||
2878 | #define nSA0 0x0 | ||
2879 | #define CRCE 0x10 /* CRC Error */ | ||
2880 | #define nCRCE 0x0 | ||
2881 | #define SER 0x8 /* Stuff Bit Error */ | ||
2882 | #define nSER 0x0 | ||
2883 | #define ACKE 0x4 /* Acknowledge Error */ | ||
2884 | #define nACKE 0x0 | ||
2885 | |||
2886 | /* Bit masks for CAN0_EWR */ | ||
2887 | |||
2888 | #define EWLTEC 0xff00 /* Transmit Error Warning Limit */ | ||
2889 | #define EWLREC 0xff /* Receive Error Warning Limit */ | ||
2890 | |||
2891 | /* Bit masks for CAN0_AMxx_H */ | ||
2892 | |||
2893 | #define FDF 0x8000 /* Filter On Data Field */ | ||
2894 | #define nFDF 0x0 | ||
2895 | #define FMD 0x4000 /* Full Mask Data */ | ||
2896 | #define nFMD 0x0 | ||
2897 | #define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */ | ||
2898 | #define nAMIDE 0x0 | ||
2899 | #define BASEID 0x1ffc /* Base Identifier */ | ||
2900 | #define EXTID_HI 0x3 /* Extended Identifier High Bits */ | ||
2901 | |||
2902 | /* Bit masks for CAN0_AMxx_L */ | ||
2903 | |||
2904 | #define EXTID_LO 0xffff /* Extended Identifier Low Bits */ | ||
2905 | #define DFM 0xffff /* Data Field Mask */ | ||
2906 | |||
2907 | /* Bit masks for CAN0_MBxx_ID1 */ | ||
2908 | |||
2909 | #define AME 0x8000 /* Acceptance Mask Enable */ | ||
2910 | #define nAME 0x0 | ||
2911 | #define RTR 0x4000 /* Remote Transmission Request */ | ||
2912 | #define nRTR 0x0 | ||
2913 | #define IDE 0x2000 /* Identifier Extension */ | ||
2914 | #define nIDE 0x0 | ||
2915 | #define BASEID 0x1ffc /* Base Identifier */ | ||
2916 | #define EXTID_HI 0x3 /* Extended Identifier High Bits */ | ||
2917 | |||
2918 | /* Bit masks for CAN0_MBxx_ID0 */ | ||
2919 | |||
2920 | #define EXTID_LO 0xffff /* Extended Identifier Low Bits */ | ||
2921 | #define DFM 0xffff /* Data Field Mask */ | ||
2922 | |||
2923 | /* Bit masks for CAN0_MBxx_TIMESTAMP */ | ||
2924 | |||
2925 | #define TSV 0xffff /* Time Stamp Value */ | ||
2926 | |||
2927 | /* Bit masks for CAN0_MBxx_LENGTH */ | ||
2928 | |||
2929 | #define DLC 0xf /* Data Length Code */ | ||
2930 | |||
2931 | /* Bit masks for CAN0_MBxx_DATA3 */ | ||
2932 | |||
2933 | #define CAN_BYTE0 0xff00 /* Data Field Byte 0 */ | ||
2934 | #define CAN_BYTE1 0xff /* Data Field Byte 1 */ | ||
2935 | |||
2936 | /* Bit masks for CAN0_MBxx_DATA2 */ | ||
2937 | |||
2938 | #define CAN_BYTE2 0xff00 /* Data Field Byte 2 */ | ||
2939 | #define CAN_BYTE3 0xff /* Data Field Byte 3 */ | ||
2940 | |||
2941 | /* Bit masks for CAN0_MBxx_DATA1 */ | ||
2942 | |||
2943 | #define CAN_BYTE4 0xff00 /* Data Field Byte 4 */ | ||
2944 | #define CAN_BYTE5 0xff /* Data Field Byte 5 */ | ||
2945 | |||
2946 | /* Bit masks for CAN0_MBxx_DATA0 */ | ||
2947 | |||
2948 | #define CAN_BYTE6 0xff00 /* Data Field Byte 6 */ | ||
2949 | #define CAN_BYTE7 0xff /* Data Field Byte 7 */ | ||
2950 | |||
2951 | /* Bit masks for CAN0_MC1 */ | ||
2952 | |||
2953 | #define MC0 0x1 /* Mailbox 0 Enable */ | ||
2954 | #define nMC0 0x0 | ||
2955 | #define MC1 0x2 /* Mailbox 1 Enable */ | ||
2956 | #define nMC1 0x0 | ||
2957 | #define MC2 0x4 /* Mailbox 2 Enable */ | ||
2958 | #define nMC2 0x0 | ||
2959 | #define MC3 0x8 /* Mailbox 3 Enable */ | ||
2960 | #define nMC3 0x0 | ||
2961 | #define MC4 0x10 /* Mailbox 4 Enable */ | ||
2962 | #define nMC4 0x0 | ||
2963 | #define MC5 0x20 /* Mailbox 5 Enable */ | ||
2964 | #define nMC5 0x0 | ||
2965 | #define MC6 0x40 /* Mailbox 6 Enable */ | ||
2966 | #define nMC6 0x0 | ||
2967 | #define MC7 0x80 /* Mailbox 7 Enable */ | ||
2968 | #define nMC7 0x0 | ||
2969 | #define MC8 0x100 /* Mailbox 8 Enable */ | ||
2970 | #define nMC8 0x0 | ||
2971 | #define MC9 0x200 /* Mailbox 9 Enable */ | ||
2972 | #define nMC9 0x0 | ||
2973 | #define MC10 0x400 /* Mailbox 10 Enable */ | ||
2974 | #define nMC10 0x0 | ||
2975 | #define MC11 0x800 /* Mailbox 11 Enable */ | ||
2976 | #define nMC11 0x0 | ||
2977 | #define MC12 0x1000 /* Mailbox 12 Enable */ | ||
2978 | #define nMC12 0x0 | ||
2979 | #define MC13 0x2000 /* Mailbox 13 Enable */ | ||
2980 | #define nMC13 0x0 | ||
2981 | #define MC14 0x4000 /* Mailbox 14 Enable */ | ||
2982 | #define nMC14 0x0 | ||
2983 | #define MC15 0x8000 /* Mailbox 15 Enable */ | ||
2984 | #define nMC15 0x0 | ||
2985 | |||
2986 | /* Bit masks for CAN0_MC2 */ | ||
2987 | |||
2988 | #define MC16 0x1 /* Mailbox 16 Enable */ | ||
2989 | #define nMC16 0x0 | ||
2990 | #define MC17 0x2 /* Mailbox 17 Enable */ | ||
2991 | #define nMC17 0x0 | ||
2992 | #define MC18 0x4 /* Mailbox 18 Enable */ | ||
2993 | #define nMC18 0x0 | ||
2994 | #define MC19 0x8 /* Mailbox 19 Enable */ | ||
2995 | #define nMC19 0x0 | ||
2996 | #define MC20 0x10 /* Mailbox 20 Enable */ | ||
2997 | #define nMC20 0x0 | ||
2998 | #define MC21 0x20 /* Mailbox 21 Enable */ | ||
2999 | #define nMC21 0x0 | ||
3000 | #define MC22 0x40 /* Mailbox 22 Enable */ | ||
3001 | #define nMC22 0x0 | ||
3002 | #define MC23 0x80 /* Mailbox 23 Enable */ | ||
3003 | #define nMC23 0x0 | ||
3004 | #define MC24 0x100 /* Mailbox 24 Enable */ | ||
3005 | #define nMC24 0x0 | ||
3006 | #define MC25 0x200 /* Mailbox 25 Enable */ | ||
3007 | #define nMC25 0x0 | ||
3008 | #define MC26 0x400 /* Mailbox 26 Enable */ | ||
3009 | #define nMC26 0x0 | ||
3010 | #define MC27 0x800 /* Mailbox 27 Enable */ | ||
3011 | #define nMC27 0x0 | ||
3012 | #define MC28 0x1000 /* Mailbox 28 Enable */ | ||
3013 | #define nMC28 0x0 | ||
3014 | #define MC29 0x2000 /* Mailbox 29 Enable */ | ||
3015 | #define nMC29 0x0 | ||
3016 | #define MC30 0x4000 /* Mailbox 30 Enable */ | ||
3017 | #define nMC30 0x0 | ||
3018 | #define MC31 0x8000 /* Mailbox 31 Enable */ | ||
3019 | #define nMC31 0x0 | ||
3020 | |||
3021 | /* Bit masks for CAN0_MD1 */ | ||
3022 | |||
3023 | #define MD0 0x1 /* Mailbox 0 Receive Enable */ | ||
3024 | #define nMD0 0x0 | ||
3025 | #define MD1 0x2 /* Mailbox 1 Receive Enable */ | ||
3026 | #define nMD1 0x0 | ||
3027 | #define MD2 0x4 /* Mailbox 2 Receive Enable */ | ||
3028 | #define nMD2 0x0 | ||
3029 | #define MD3 0x8 /* Mailbox 3 Receive Enable */ | ||
3030 | #define nMD3 0x0 | ||
3031 | #define MD4 0x10 /* Mailbox 4 Receive Enable */ | ||
3032 | #define nMD4 0x0 | ||
3033 | #define MD5 0x20 /* Mailbox 5 Receive Enable */ | ||
3034 | #define nMD5 0x0 | ||
3035 | #define MD6 0x40 /* Mailbox 6 Receive Enable */ | ||
3036 | #define nMD6 0x0 | ||
3037 | #define MD7 0x80 /* Mailbox 7 Receive Enable */ | ||
3038 | #define nMD7 0x0 | ||
3039 | #define MD8 0x100 /* Mailbox 8 Receive Enable */ | ||
3040 | #define nMD8 0x0 | ||
3041 | #define MD9 0x200 /* Mailbox 9 Receive Enable */ | ||
3042 | #define nMD9 0x0 | ||
3043 | #define MD10 0x400 /* Mailbox 10 Receive Enable */ | ||
3044 | #define nMD10 0x0 | ||
3045 | #define MD11 0x800 /* Mailbox 11 Receive Enable */ | ||
3046 | #define nMD11 0x0 | ||
3047 | #define MD12 0x1000 /* Mailbox 12 Receive Enable */ | ||
3048 | #define nMD12 0x0 | ||
3049 | #define MD13 0x2000 /* Mailbox 13 Receive Enable */ | ||
3050 | #define nMD13 0x0 | ||
3051 | #define MD14 0x4000 /* Mailbox 14 Receive Enable */ | ||
3052 | #define nMD14 0x0 | ||
3053 | #define MD15 0x8000 /* Mailbox 15 Receive Enable */ | ||
3054 | #define nMD15 0x0 | ||
3055 | |||
3056 | /* Bit masks for CAN0_MD2 */ | ||
3057 | |||
3058 | #define MD16 0x1 /* Mailbox 16 Receive Enable */ | ||
3059 | #define nMD16 0x0 | ||
3060 | #define MD17 0x2 /* Mailbox 17 Receive Enable */ | ||
3061 | #define nMD17 0x0 | ||
3062 | #define MD18 0x4 /* Mailbox 18 Receive Enable */ | ||
3063 | #define nMD18 0x0 | ||
3064 | #define MD19 0x8 /* Mailbox 19 Receive Enable */ | ||
3065 | #define nMD19 0x0 | ||
3066 | #define MD20 0x10 /* Mailbox 20 Receive Enable */ | ||
3067 | #define nMD20 0x0 | ||
3068 | #define MD21 0x20 /* Mailbox 21 Receive Enable */ | ||
3069 | #define nMD21 0x0 | ||
3070 | #define MD22 0x40 /* Mailbox 22 Receive Enable */ | ||
3071 | #define nMD22 0x0 | ||
3072 | #define MD23 0x80 /* Mailbox 23 Receive Enable */ | ||
3073 | #define nMD23 0x0 | ||
3074 | #define MD24 0x100 /* Mailbox 24 Receive Enable */ | ||
3075 | #define nMD24 0x0 | ||
3076 | #define MD25 0x200 /* Mailbox 25 Receive Enable */ | ||
3077 | #define nMD25 0x0 | ||
3078 | #define MD26 0x400 /* Mailbox 26 Receive Enable */ | ||
3079 | #define nMD26 0x0 | ||
3080 | #define MD27 0x800 /* Mailbox 27 Receive Enable */ | ||
3081 | #define nMD27 0x0 | ||
3082 | #define MD28 0x1000 /* Mailbox 28 Receive Enable */ | ||
3083 | #define nMD28 0x0 | ||
3084 | #define MD29 0x2000 /* Mailbox 29 Receive Enable */ | ||
3085 | #define nMD29 0x0 | ||
3086 | #define MD30 0x4000 /* Mailbox 30 Receive Enable */ | ||
3087 | #define nMD30 0x0 | ||
3088 | #define MD31 0x8000 /* Mailbox 31 Receive Enable */ | ||
3089 | #define nMD31 0x0 | ||
3090 | |||
3091 | /* Bit masks for CAN0_RMP1 */ | ||
3092 | |||
3093 | #define RMP0 0x1 /* Mailbox 0 Receive Message Pending */ | ||
3094 | #define nRMP0 0x0 | ||
3095 | #define RMP1 0x2 /* Mailbox 1 Receive Message Pending */ | ||
3096 | #define nRMP1 0x0 | ||
3097 | #define RMP2 0x4 /* Mailbox 2 Receive Message Pending */ | ||
3098 | #define nRMP2 0x0 | ||
3099 | #define RMP3 0x8 /* Mailbox 3 Receive Message Pending */ | ||
3100 | #define nRMP3 0x0 | ||
3101 | #define RMP4 0x10 /* Mailbox 4 Receive Message Pending */ | ||
3102 | #define nRMP4 0x0 | ||
3103 | #define RMP5 0x20 /* Mailbox 5 Receive Message Pending */ | ||
3104 | #define nRMP5 0x0 | ||
3105 | #define RMP6 0x40 /* Mailbox 6 Receive Message Pending */ | ||
3106 | #define nRMP6 0x0 | ||
3107 | #define RMP7 0x80 /* Mailbox 7 Receive Message Pending */ | ||
3108 | #define nRMP7 0x0 | ||
3109 | #define RMP8 0x100 /* Mailbox 8 Receive Message Pending */ | ||
3110 | #define nRMP8 0x0 | ||
3111 | #define RMP9 0x200 /* Mailbox 9 Receive Message Pending */ | ||
3112 | #define nRMP9 0x0 | ||
3113 | #define RMP10 0x400 /* Mailbox 10 Receive Message Pending */ | ||
3114 | #define nRMP10 0x0 | ||
3115 | #define RMP11 0x800 /* Mailbox 11 Receive Message Pending */ | ||
3116 | #define nRMP11 0x0 | ||
3117 | #define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */ | ||
3118 | #define nRMP12 0x0 | ||
3119 | #define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */ | ||
3120 | #define nRMP13 0x0 | ||
3121 | #define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */ | ||
3122 | #define nRMP14 0x0 | ||
3123 | #define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */ | ||
3124 | #define nRMP15 0x0 | ||
3125 | |||
3126 | /* Bit masks for CAN0_RMP2 */ | ||
3127 | |||
3128 | #define RMP16 0x1 /* Mailbox 16 Receive Message Pending */ | ||
3129 | #define nRMP16 0x0 | ||
3130 | #define RMP17 0x2 /* Mailbox 17 Receive Message Pending */ | ||
3131 | #define nRMP17 0x0 | ||
3132 | #define RMP18 0x4 /* Mailbox 18 Receive Message Pending */ | ||
3133 | #define nRMP18 0x0 | ||
3134 | #define RMP19 0x8 /* Mailbox 19 Receive Message Pending */ | ||
3135 | #define nRMP19 0x0 | ||
3136 | #define RMP20 0x10 /* Mailbox 20 Receive Message Pending */ | ||
3137 | #define nRMP20 0x0 | ||
3138 | #define RMP21 0x20 /* Mailbox 21 Receive Message Pending */ | ||
3139 | #define nRMP21 0x0 | ||
3140 | #define RMP22 0x40 /* Mailbox 22 Receive Message Pending */ | ||
3141 | #define nRMP22 0x0 | ||
3142 | #define RMP23 0x80 /* Mailbox 23 Receive Message Pending */ | ||
3143 | #define nRMP23 0x0 | ||
3144 | #define RMP24 0x100 /* Mailbox 24 Receive Message Pending */ | ||
3145 | #define nRMP24 0x0 | ||
3146 | #define RMP25 0x200 /* Mailbox 25 Receive Message Pending */ | ||
3147 | #define nRMP25 0x0 | ||
3148 | #define RMP26 0x400 /* Mailbox 26 Receive Message Pending */ | ||
3149 | #define nRMP26 0x0 | ||
3150 | #define RMP27 0x800 /* Mailbox 27 Receive Message Pending */ | ||
3151 | #define nRMP27 0x0 | ||
3152 | #define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */ | ||
3153 | #define nRMP28 0x0 | ||
3154 | #define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */ | ||
3155 | #define nRMP29 0x0 | ||
3156 | #define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */ | ||
3157 | #define nRMP30 0x0 | ||
3158 | #define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */ | ||
3159 | #define nRMP31 0x0 | ||
3160 | |||
3161 | /* Bit masks for CAN0_RML1 */ | ||
3162 | |||
3163 | #define RML0 0x1 /* Mailbox 0 Receive Message Lost */ | ||
3164 | #define nRML0 0x0 | ||
3165 | #define RML1 0x2 /* Mailbox 1 Receive Message Lost */ | ||
3166 | #define nRML1 0x0 | ||
3167 | #define RML2 0x4 /* Mailbox 2 Receive Message Lost */ | ||
3168 | #define nRML2 0x0 | ||
3169 | #define RML3 0x8 /* Mailbox 3 Receive Message Lost */ | ||
3170 | #define nRML3 0x0 | ||
3171 | #define RML4 0x10 /* Mailbox 4 Receive Message Lost */ | ||
3172 | #define nRML4 0x0 | ||
3173 | #define RML5 0x20 /* Mailbox 5 Receive Message Lost */ | ||
3174 | #define nRML5 0x0 | ||
3175 | #define RML6 0x40 /* Mailbox 6 Receive Message Lost */ | ||
3176 | #define nRML6 0x0 | ||
3177 | #define RML7 0x80 /* Mailbox 7 Receive Message Lost */ | ||
3178 | #define nRML7 0x0 | ||
3179 | #define RML8 0x100 /* Mailbox 8 Receive Message Lost */ | ||
3180 | #define nRML8 0x0 | ||
3181 | #define RML9 0x200 /* Mailbox 9 Receive Message Lost */ | ||
3182 | #define nRML9 0x0 | ||
3183 | #define RML10 0x400 /* Mailbox 10 Receive Message Lost */ | ||
3184 | #define nRML10 0x0 | ||
3185 | #define RML11 0x800 /* Mailbox 11 Receive Message Lost */ | ||
3186 | #define nRML11 0x0 | ||
3187 | #define RML12 0x1000 /* Mailbox 12 Receive Message Lost */ | ||
3188 | #define nRML12 0x0 | ||
3189 | #define RML13 0x2000 /* Mailbox 13 Receive Message Lost */ | ||
3190 | #define nRML13 0x0 | ||
3191 | #define RML14 0x4000 /* Mailbox 14 Receive Message Lost */ | ||
3192 | #define nRML14 0x0 | ||
3193 | #define RML15 0x8000 /* Mailbox 15 Receive Message Lost */ | ||
3194 | #define nRML15 0x0 | ||
3195 | |||
3196 | /* Bit masks for CAN0_RML2 */ | ||
3197 | |||
3198 | #define RML16 0x1 /* Mailbox 16 Receive Message Lost */ | ||
3199 | #define nRML16 0x0 | ||
3200 | #define RML17 0x2 /* Mailbox 17 Receive Message Lost */ | ||
3201 | #define nRML17 0x0 | ||
3202 | #define RML18 0x4 /* Mailbox 18 Receive Message Lost */ | ||
3203 | #define nRML18 0x0 | ||
3204 | #define RML19 0x8 /* Mailbox 19 Receive Message Lost */ | ||
3205 | #define nRML19 0x0 | ||
3206 | #define RML20 0x10 /* Mailbox 20 Receive Message Lost */ | ||
3207 | #define nRML20 0x0 | ||
3208 | #define RML21 0x20 /* Mailbox 21 Receive Message Lost */ | ||
3209 | #define nRML21 0x0 | ||
3210 | #define RML22 0x40 /* Mailbox 22 Receive Message Lost */ | ||
3211 | #define nRML22 0x0 | ||
3212 | #define RML23 0x80 /* Mailbox 23 Receive Message Lost */ | ||
3213 | #define nRML23 0x0 | ||
3214 | #define RML24 0x100 /* Mailbox 24 Receive Message Lost */ | ||
3215 | #define nRML24 0x0 | ||
3216 | #define RML25 0x200 /* Mailbox 25 Receive Message Lost */ | ||
3217 | #define nRML25 0x0 | ||
3218 | #define RML26 0x400 /* Mailbox 26 Receive Message Lost */ | ||
3219 | #define nRML26 0x0 | ||
3220 | #define RML27 0x800 /* Mailbox 27 Receive Message Lost */ | ||
3221 | #define nRML27 0x0 | ||
3222 | #define RML28 0x1000 /* Mailbox 28 Receive Message Lost */ | ||
3223 | #define nRML28 0x0 | ||
3224 | #define RML29 0x2000 /* Mailbox 29 Receive Message Lost */ | ||
3225 | #define nRML29 0x0 | ||
3226 | #define RML30 0x4000 /* Mailbox 30 Receive Message Lost */ | ||
3227 | #define nRML30 0x0 | ||
3228 | #define RML31 0x8000 /* Mailbox 31 Receive Message Lost */ | ||
3229 | #define nRML31 0x0 | ||
3230 | |||
3231 | /* Bit masks for CAN0_OPSS1 */ | ||
3232 | |||
3233 | #define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3234 | #define nOPSS0 0x0 | ||
3235 | #define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3236 | #define nOPSS1 0x0 | ||
3237 | #define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3238 | #define nOPSS2 0x0 | ||
3239 | #define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3240 | #define nOPSS3 0x0 | ||
3241 | #define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3242 | #define nOPSS4 0x0 | ||
3243 | #define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3244 | #define nOPSS5 0x0 | ||
3245 | #define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3246 | #define nOPSS6 0x0 | ||
3247 | #define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3248 | #define nOPSS7 0x0 | ||
3249 | #define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3250 | #define nOPSS8 0x0 | ||
3251 | #define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3252 | #define nOPSS9 0x0 | ||
3253 | #define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3254 | #define nOPSS10 0x0 | ||
3255 | #define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3256 | #define nOPSS11 0x0 | ||
3257 | #define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3258 | #define nOPSS12 0x0 | ||
3259 | #define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3260 | #define nOPSS13 0x0 | ||
3261 | #define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3262 | #define nOPSS14 0x0 | ||
3263 | #define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3264 | #define nOPSS15 0x0 | ||
3265 | |||
3266 | /* Bit masks for CAN0_OPSS2 */ | ||
3267 | |||
3268 | #define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3269 | #define nOPSS16 0x0 | ||
3270 | #define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3271 | #define nOPSS17 0x0 | ||
3272 | #define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3273 | #define nOPSS18 0x0 | ||
3274 | #define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3275 | #define nOPSS19 0x0 | ||
3276 | #define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3277 | #define nOPSS20 0x0 | ||
3278 | #define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3279 | #define nOPSS21 0x0 | ||
3280 | #define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3281 | #define nOPSS22 0x0 | ||
3282 | #define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3283 | #define nOPSS23 0x0 | ||
3284 | #define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3285 | #define nOPSS24 0x0 | ||
3286 | #define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3287 | #define nOPSS25 0x0 | ||
3288 | #define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3289 | #define nOPSS26 0x0 | ||
3290 | #define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3291 | #define nOPSS27 0x0 | ||
3292 | #define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3293 | #define nOPSS28 0x0 | ||
3294 | #define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3295 | #define nOPSS29 0x0 | ||
3296 | #define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3297 | #define nOPSS30 0x0 | ||
3298 | #define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */ | ||
3299 | #define nOPSS31 0x0 | ||
3300 | |||
3301 | /* Bit masks for CAN0_TRS1 */ | ||
3302 | |||
3303 | #define TRS0 0x1 /* Mailbox 0 Transmit Request Set */ | ||
3304 | #define nTRS0 0x0 | ||
3305 | #define TRS1 0x2 /* Mailbox 1 Transmit Request Set */ | ||
3306 | #define nTRS1 0x0 | ||
3307 | #define TRS2 0x4 /* Mailbox 2 Transmit Request Set */ | ||
3308 | #define nTRS2 0x0 | ||
3309 | #define TRS3 0x8 /* Mailbox 3 Transmit Request Set */ | ||
3310 | #define nTRS3 0x0 | ||
3311 | #define TRS4 0x10 /* Mailbox 4 Transmit Request Set */ | ||
3312 | #define nTRS4 0x0 | ||
3313 | #define TRS5 0x20 /* Mailbox 5 Transmit Request Set */ | ||
3314 | #define nTRS5 0x0 | ||
3315 | #define TRS6 0x40 /* Mailbox 6 Transmit Request Set */ | ||
3316 | #define nTRS6 0x0 | ||
3317 | #define TRS7 0x80 /* Mailbox 7 Transmit Request Set */ | ||
3318 | #define nTRS7 0x0 | ||
3319 | #define TRS8 0x100 /* Mailbox 8 Transmit Request Set */ | ||
3320 | #define nTRS8 0x0 | ||
3321 | #define TRS9 0x200 /* Mailbox 9 Transmit Request Set */ | ||
3322 | #define nTRS9 0x0 | ||
3323 | #define TRS10 0x400 /* Mailbox 10 Transmit Request Set */ | ||
3324 | #define nTRS10 0x0 | ||
3325 | #define TRS11 0x800 /* Mailbox 11 Transmit Request Set */ | ||
3326 | #define nTRS11 0x0 | ||
3327 | #define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */ | ||
3328 | #define nTRS12 0x0 | ||
3329 | #define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */ | ||
3330 | #define nTRS13 0x0 | ||
3331 | #define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */ | ||
3332 | #define nTRS14 0x0 | ||
3333 | #define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */ | ||
3334 | #define nTRS15 0x0 | ||
3335 | |||
3336 | /* Bit masks for CAN0_TRS2 */ | ||
3337 | |||
3338 | #define TRS16 0x1 /* Mailbox 16 Transmit Request Set */ | ||
3339 | #define nTRS16 0x0 | ||
3340 | #define TRS17 0x2 /* Mailbox 17 Transmit Request Set */ | ||
3341 | #define nTRS17 0x0 | ||
3342 | #define TRS18 0x4 /* Mailbox 18 Transmit Request Set */ | ||
3343 | #define nTRS18 0x0 | ||
3344 | #define TRS19 0x8 /* Mailbox 19 Transmit Request Set */ | ||
3345 | #define nTRS19 0x0 | ||
3346 | #define TRS20 0x10 /* Mailbox 20 Transmit Request Set */ | ||
3347 | #define nTRS20 0x0 | ||
3348 | #define TRS21 0x20 /* Mailbox 21 Transmit Request Set */ | ||
3349 | #define nTRS21 0x0 | ||
3350 | #define TRS22 0x40 /* Mailbox 22 Transmit Request Set */ | ||
3351 | #define nTRS22 0x0 | ||
3352 | #define TRS23 0x80 /* Mailbox 23 Transmit Request Set */ | ||
3353 | #define nTRS23 0x0 | ||
3354 | #define TRS24 0x100 /* Mailbox 24 Transmit Request Set */ | ||
3355 | #define nTRS24 0x0 | ||
3356 | #define TRS25 0x200 /* Mailbox 25 Transmit Request Set */ | ||
3357 | #define nTRS25 0x0 | ||
3358 | #define TRS26 0x400 /* Mailbox 26 Transmit Request Set */ | ||
3359 | #define nTRS26 0x0 | ||
3360 | #define TRS27 0x800 /* Mailbox 27 Transmit Request Set */ | ||
3361 | #define nTRS27 0x0 | ||
3362 | #define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */ | ||
3363 | #define nTRS28 0x0 | ||
3364 | #define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */ | ||
3365 | #define nTRS29 0x0 | ||
3366 | #define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */ | ||
3367 | #define nTRS30 0x0 | ||
3368 | #define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */ | ||
3369 | #define nTRS31 0x0 | ||
3370 | |||
3371 | /* Bit masks for CAN0_TRR1 */ | ||
3372 | |||
3373 | #define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */ | ||
3374 | #define nTRR0 0x0 | ||
3375 | #define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */ | ||
3376 | #define nTRR1 0x0 | ||
3377 | #define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */ | ||
3378 | #define nTRR2 0x0 | ||
3379 | #define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */ | ||
3380 | #define nTRR3 0x0 | ||
3381 | #define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */ | ||
3382 | #define nTRR4 0x0 | ||
3383 | #define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */ | ||
3384 | #define nTRR5 0x0 | ||
3385 | #define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */ | ||
3386 | #define nTRR6 0x0 | ||
3387 | #define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */ | ||
3388 | #define nTRR7 0x0 | ||
3389 | #define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */ | ||
3390 | #define nTRR8 0x0 | ||
3391 | #define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */ | ||
3392 | #define nTRR9 0x0 | ||
3393 | #define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */ | ||
3394 | #define nTRR10 0x0 | ||
3395 | #define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */ | ||
3396 | #define nTRR11 0x0 | ||
3397 | #define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */ | ||
3398 | #define nTRR12 0x0 | ||
3399 | #define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */ | ||
3400 | #define nTRR13 0x0 | ||
3401 | #define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */ | ||
3402 | #define nTRR14 0x0 | ||
3403 | #define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */ | ||
3404 | #define nTRR15 0x0 | ||
3405 | |||
3406 | /* Bit masks for CAN0_TRR2 */ | ||
3407 | |||
3408 | #define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */ | ||
3409 | #define nTRR16 0x0 | ||
3410 | #define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */ | ||
3411 | #define nTRR17 0x0 | ||
3412 | #define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */ | ||
3413 | #define nTRR18 0x0 | ||
3414 | #define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */ | ||
3415 | #define nTRR19 0x0 | ||
3416 | #define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */ | ||
3417 | #define nTRR20 0x0 | ||
3418 | #define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */ | ||
3419 | #define nTRR21 0x0 | ||
3420 | #define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */ | ||
3421 | #define nTRR22 0x0 | ||
3422 | #define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */ | ||
3423 | #define nTRR23 0x0 | ||
3424 | #define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */ | ||
3425 | #define nTRR24 0x0 | ||
3426 | #define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */ | ||
3427 | #define nTRR25 0x0 | ||
3428 | #define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */ | ||
3429 | #define nTRR26 0x0 | ||
3430 | #define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */ | ||
3431 | #define nTRR27 0x0 | ||
3432 | #define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */ | ||
3433 | #define nTRR28 0x0 | ||
3434 | #define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */ | ||
3435 | #define nTRR29 0x0 | ||
3436 | #define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */ | ||
3437 | #define nTRR30 0x0 | ||
3438 | #define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */ | ||
3439 | #define nTRR31 0x0 | ||
3440 | |||
3441 | /* Bit masks for CAN0_AA1 */ | ||
3442 | |||
3443 | #define AA0 0x1 /* Mailbox 0 Abort Acknowledge */ | ||
3444 | #define nAA0 0x0 | ||
3445 | #define AA1 0x2 /* Mailbox 1 Abort Acknowledge */ | ||
3446 | #define nAA1 0x0 | ||
3447 | #define AA2 0x4 /* Mailbox 2 Abort Acknowledge */ | ||
3448 | #define nAA2 0x0 | ||
3449 | #define AA3 0x8 /* Mailbox 3 Abort Acknowledge */ | ||
3450 | #define nAA3 0x0 | ||
3451 | #define AA4 0x10 /* Mailbox 4 Abort Acknowledge */ | ||
3452 | #define nAA4 0x0 | ||
3453 | #define AA5 0x20 /* Mailbox 5 Abort Acknowledge */ | ||
3454 | #define nAA5 0x0 | ||
3455 | #define AA6 0x40 /* Mailbox 6 Abort Acknowledge */ | ||
3456 | #define nAA6 0x0 | ||
3457 | #define AA7 0x80 /* Mailbox 7 Abort Acknowledge */ | ||
3458 | #define nAA7 0x0 | ||
3459 | #define AA8 0x100 /* Mailbox 8 Abort Acknowledge */ | ||
3460 | #define nAA8 0x0 | ||
3461 | #define AA9 0x200 /* Mailbox 9 Abort Acknowledge */ | ||
3462 | #define nAA9 0x0 | ||
3463 | #define AA10 0x400 /* Mailbox 10 Abort Acknowledge */ | ||
3464 | #define nAA10 0x0 | ||
3465 | #define AA11 0x800 /* Mailbox 11 Abort Acknowledge */ | ||
3466 | #define nAA11 0x0 | ||
3467 | #define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */ | ||
3468 | #define nAA12 0x0 | ||
3469 | #define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */ | ||
3470 | #define nAA13 0x0 | ||
3471 | #define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */ | ||
3472 | #define nAA14 0x0 | ||
3473 | #define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */ | ||
3474 | #define nAA15 0x0 | ||
3475 | |||
3476 | /* Bit masks for CAN0_AA2 */ | ||
3477 | |||
3478 | #define AA16 0x1 /* Mailbox 16 Abort Acknowledge */ | ||
3479 | #define nAA16 0x0 | ||
3480 | #define AA17 0x2 /* Mailbox 17 Abort Acknowledge */ | ||
3481 | #define nAA17 0x0 | ||
3482 | #define AA18 0x4 /* Mailbox 18 Abort Acknowledge */ | ||
3483 | #define nAA18 0x0 | ||
3484 | #define AA19 0x8 /* Mailbox 19 Abort Acknowledge */ | ||
3485 | #define nAA19 0x0 | ||
3486 | #define AA20 0x10 /* Mailbox 20 Abort Acknowledge */ | ||
3487 | #define nAA20 0x0 | ||
3488 | #define AA21 0x20 /* Mailbox 21 Abort Acknowledge */ | ||
3489 | #define nAA21 0x0 | ||
3490 | #define AA22 0x40 /* Mailbox 22 Abort Acknowledge */ | ||
3491 | #define nAA22 0x0 | ||
3492 | #define AA23 0x80 /* Mailbox 23 Abort Acknowledge */ | ||
3493 | #define nAA23 0x0 | ||
3494 | #define AA24 0x100 /* Mailbox 24 Abort Acknowledge */ | ||
3495 | #define nAA24 0x0 | ||
3496 | #define AA25 0x200 /* Mailbox 25 Abort Acknowledge */ | ||
3497 | #define nAA25 0x0 | ||
3498 | #define AA26 0x400 /* Mailbox 26 Abort Acknowledge */ | ||
3499 | #define nAA26 0x0 | ||
3500 | #define AA27 0x800 /* Mailbox 27 Abort Acknowledge */ | ||
3501 | #define nAA27 0x0 | ||
3502 | #define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */ | ||
3503 | #define nAA28 0x0 | ||
3504 | #define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */ | ||
3505 | #define nAA29 0x0 | ||
3506 | #define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */ | ||
3507 | #define nAA30 0x0 | ||
3508 | #define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */ | ||
3509 | #define nAA31 0x0 | ||
3510 | |||
3511 | /* Bit masks for CAN0_TA1 */ | ||
3512 | |||
3513 | #define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */ | ||
3514 | #define nTA0 0x0 | ||
3515 | #define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */ | ||
3516 | #define nTA1 0x0 | ||
3517 | #define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */ | ||
3518 | #define nTA2 0x0 | ||
3519 | #define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */ | ||
3520 | #define nTA3 0x0 | ||
3521 | #define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */ | ||
3522 | #define nTA4 0x0 | ||
3523 | #define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */ | ||
3524 | #define nTA5 0x0 | ||
3525 | #define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */ | ||
3526 | #define nTA6 0x0 | ||
3527 | #define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */ | ||
3528 | #define nTA7 0x0 | ||
3529 | #define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */ | ||
3530 | #define nTA8 0x0 | ||
3531 | #define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */ | ||
3532 | #define nTA9 0x0 | ||
3533 | #define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */ | ||
3534 | #define nTA10 0x0 | ||
3535 | #define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */ | ||
3536 | #define nTA11 0x0 | ||
3537 | #define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */ | ||
3538 | #define nTA12 0x0 | ||
3539 | #define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */ | ||
3540 | #define nTA13 0x0 | ||
3541 | #define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */ | ||
3542 | #define nTA14 0x0 | ||
3543 | #define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */ | ||
3544 | #define nTA15 0x0 | ||
3545 | |||
3546 | /* Bit masks for CAN0_TA2 */ | ||
3547 | |||
3548 | #define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */ | ||
3549 | #define nTA16 0x0 | ||
3550 | #define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */ | ||
3551 | #define nTA17 0x0 | ||
3552 | #define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */ | ||
3553 | #define nTA18 0x0 | ||
3554 | #define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */ | ||
3555 | #define nTA19 0x0 | ||
3556 | #define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */ | ||
3557 | #define nTA20 0x0 | ||
3558 | #define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */ | ||
3559 | #define nTA21 0x0 | ||
3560 | #define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */ | ||
3561 | #define nTA22 0x0 | ||
3562 | #define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */ | ||
3563 | #define nTA23 0x0 | ||
3564 | #define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */ | ||
3565 | #define nTA24 0x0 | ||
3566 | #define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */ | ||
3567 | #define nTA25 0x0 | ||
3568 | #define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */ | ||
3569 | #define nTA26 0x0 | ||
3570 | #define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */ | ||
3571 | #define nTA27 0x0 | ||
3572 | #define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */ | ||
3573 | #define nTA28 0x0 | ||
3574 | #define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */ | ||
3575 | #define nTA29 0x0 | ||
3576 | #define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */ | ||
3577 | #define nTA30 0x0 | ||
3578 | #define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */ | ||
3579 | #define nTA31 0x0 | ||
3580 | |||
3581 | /* Bit masks for CAN0_RFH1 */ | ||
3582 | |||
3583 | #define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */ | ||
3584 | #define nRFH0 0x0 | ||
3585 | #define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */ | ||
3586 | #define nRFH1 0x0 | ||
3587 | #define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */ | ||
3588 | #define nRFH2 0x0 | ||
3589 | #define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */ | ||
3590 | #define nRFH3 0x0 | ||
3591 | #define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */ | ||
3592 | #define nRFH4 0x0 | ||
3593 | #define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */ | ||
3594 | #define nRFH5 0x0 | ||
3595 | #define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */ | ||
3596 | #define nRFH6 0x0 | ||
3597 | #define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */ | ||
3598 | #define nRFH7 0x0 | ||
3599 | #define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */ | ||
3600 | #define nRFH8 0x0 | ||
3601 | #define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */ | ||
3602 | #define nRFH9 0x0 | ||
3603 | #define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */ | ||
3604 | #define nRFH10 0x0 | ||
3605 | #define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */ | ||
3606 | #define nRFH11 0x0 | ||
3607 | #define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */ | ||
3608 | #define nRFH12 0x0 | ||
3609 | #define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */ | ||
3610 | #define nRFH13 0x0 | ||
3611 | #define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */ | ||
3612 | #define nRFH14 0x0 | ||
3613 | #define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */ | ||
3614 | #define nRFH15 0x0 | ||
3615 | |||
3616 | /* Bit masks for CAN0_RFH2 */ | ||
3617 | |||
3618 | #define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */ | ||
3619 | #define nRFH16 0x0 | ||
3620 | #define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */ | ||
3621 | #define nRFH17 0x0 | ||
3622 | #define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */ | ||
3623 | #define nRFH18 0x0 | ||
3624 | #define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */ | ||
3625 | #define nRFH19 0x0 | ||
3626 | #define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */ | ||
3627 | #define nRFH20 0x0 | ||
3628 | #define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */ | ||
3629 | #define nRFH21 0x0 | ||
3630 | #define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */ | ||
3631 | #define nRFH22 0x0 | ||
3632 | #define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */ | ||
3633 | #define nRFH23 0x0 | ||
3634 | #define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */ | ||
3635 | #define nRFH24 0x0 | ||
3636 | #define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */ | ||
3637 | #define nRFH25 0x0 | ||
3638 | #define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */ | ||
3639 | #define nRFH26 0x0 | ||
3640 | #define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */ | ||
3641 | #define nRFH27 0x0 | ||
3642 | #define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */ | ||
3643 | #define nRFH28 0x0 | ||
3644 | #define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */ | ||
3645 | #define nRFH29 0x0 | ||
3646 | #define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */ | ||
3647 | #define nRFH30 0x0 | ||
3648 | #define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */ | ||
3649 | #define nRFH31 0x0 | ||
3650 | |||
3651 | /* Bit masks for CAN0_MBIM1 */ | ||
3652 | |||
3653 | #define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */ | ||
3654 | #define nMBIM0 0x0 | ||
3655 | #define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */ | ||
3656 | #define nMBIM1 0x0 | ||
3657 | #define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */ | ||
3658 | #define nMBIM2 0x0 | ||
3659 | #define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */ | ||
3660 | #define nMBIM3 0x0 | ||
3661 | #define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */ | ||
3662 | #define nMBIM4 0x0 | ||
3663 | #define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */ | ||
3664 | #define nMBIM5 0x0 | ||
3665 | #define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */ | ||
3666 | #define nMBIM6 0x0 | ||
3667 | #define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */ | ||
3668 | #define nMBIM7 0x0 | ||
3669 | #define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */ | ||
3670 | #define nMBIM8 0x0 | ||
3671 | #define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */ | ||
3672 | #define nMBIM9 0x0 | ||
3673 | #define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */ | ||
3674 | #define nMBIM10 0x0 | ||
3675 | #define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */ | ||
3676 | #define nMBIM11 0x0 | ||
3677 | #define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */ | ||
3678 | #define nMBIM12 0x0 | ||
3679 | #define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */ | ||
3680 | #define nMBIM13 0x0 | ||
3681 | #define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */ | ||
3682 | #define nMBIM14 0x0 | ||
3683 | #define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */ | ||
3684 | #define nMBIM15 0x0 | ||
3685 | |||
3686 | /* Bit masks for CAN0_MBIM2 */ | ||
3687 | |||
3688 | #define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */ | ||
3689 | #define nMBIM16 0x0 | ||
3690 | #define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */ | ||
3691 | #define nMBIM17 0x0 | ||
3692 | #define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */ | ||
3693 | #define nMBIM18 0x0 | ||
3694 | #define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */ | ||
3695 | #define nMBIM19 0x0 | ||
3696 | #define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */ | ||
3697 | #define nMBIM20 0x0 | ||
3698 | #define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */ | ||
3699 | #define nMBIM21 0x0 | ||
3700 | #define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */ | ||
3701 | #define nMBIM22 0x0 | ||
3702 | #define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */ | ||
3703 | #define nMBIM23 0x0 | ||
3704 | #define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */ | ||
3705 | #define nMBIM24 0x0 | ||
3706 | #define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */ | ||
3707 | #define nMBIM25 0x0 | ||
3708 | #define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */ | ||
3709 | #define nMBIM26 0x0 | ||
3710 | #define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */ | ||
3711 | #define nMBIM27 0x0 | ||
3712 | #define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */ | ||
3713 | #define nMBIM28 0x0 | ||
3714 | #define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */ | ||
3715 | #define nMBIM29 0x0 | ||
3716 | #define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */ | ||
3717 | #define nMBIM30 0x0 | ||
3718 | #define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */ | ||
3719 | #define nMBIM31 0x0 | ||
3720 | |||
3721 | /* Bit masks for CAN0_MBTIF1 */ | ||
3722 | |||
3723 | #define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */ | ||
3724 | #define nMBTIF0 0x0 | ||
3725 | #define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */ | ||
3726 | #define nMBTIF1 0x0 | ||
3727 | #define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */ | ||
3728 | #define nMBTIF2 0x0 | ||
3729 | #define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */ | ||
3730 | #define nMBTIF3 0x0 | ||
3731 | #define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */ | ||
3732 | #define nMBTIF4 0x0 | ||
3733 | #define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */ | ||
3734 | #define nMBTIF5 0x0 | ||
3735 | #define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */ | ||
3736 | #define nMBTIF6 0x0 | ||
3737 | #define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */ | ||
3738 | #define nMBTIF7 0x0 | ||
3739 | #define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */ | ||
3740 | #define nMBTIF8 0x0 | ||
3741 | #define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */ | ||
3742 | #define nMBTIF9 0x0 | ||
3743 | #define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */ | ||
3744 | #define nMBTIF10 0x0 | ||
3745 | #define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */ | ||
3746 | #define nMBTIF11 0x0 | ||
3747 | #define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */ | ||
3748 | #define nMBTIF12 0x0 | ||
3749 | #define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */ | ||
3750 | #define nMBTIF13 0x0 | ||
3751 | #define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */ | ||
3752 | #define nMBTIF14 0x0 | ||
3753 | #define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */ | ||
3754 | #define nMBTIF15 0x0 | ||
3755 | |||
3756 | /* Bit masks for CAN0_MBTIF2 */ | ||
3757 | |||
3758 | #define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */ | ||
3759 | #define nMBTIF16 0x0 | ||
3760 | #define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */ | ||
3761 | #define nMBTIF17 0x0 | ||
3762 | #define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */ | ||
3763 | #define nMBTIF18 0x0 | ||
3764 | #define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */ | ||
3765 | #define nMBTIF19 0x0 | ||
3766 | #define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */ | ||
3767 | #define nMBTIF20 0x0 | ||
3768 | #define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */ | ||
3769 | #define nMBTIF21 0x0 | ||
3770 | #define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */ | ||
3771 | #define nMBTIF22 0x0 | ||
3772 | #define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */ | ||
3773 | #define nMBTIF23 0x0 | ||
3774 | #define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */ | ||
3775 | #define nMBTIF24 0x0 | ||
3776 | #define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */ | ||
3777 | #define nMBTIF25 0x0 | ||
3778 | #define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */ | ||
3779 | #define nMBTIF26 0x0 | ||
3780 | #define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */ | ||
3781 | #define nMBTIF27 0x0 | ||
3782 | #define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */ | ||
3783 | #define nMBTIF28 0x0 | ||
3784 | #define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */ | ||
3785 | #define nMBTIF29 0x0 | ||
3786 | #define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */ | ||
3787 | #define nMBTIF30 0x0 | ||
3788 | #define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */ | ||
3789 | #define nMBTIF31 0x0 | ||
3790 | |||
3791 | /* Bit masks for CAN0_MBRIF1 */ | ||
3792 | |||
3793 | #define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */ | ||
3794 | #define nMBRIF0 0x0 | ||
3795 | #define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */ | ||
3796 | #define nMBRIF1 0x0 | ||
3797 | #define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */ | ||
3798 | #define nMBRIF2 0x0 | ||
3799 | #define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */ | ||
3800 | #define nMBRIF3 0x0 | ||
3801 | #define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */ | ||
3802 | #define nMBRIF4 0x0 | ||
3803 | #define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */ | ||
3804 | #define nMBRIF5 0x0 | ||
3805 | #define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */ | ||
3806 | #define nMBRIF6 0x0 | ||
3807 | #define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */ | ||
3808 | #define nMBRIF7 0x0 | ||
3809 | #define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */ | ||
3810 | #define nMBRIF8 0x0 | ||
3811 | #define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */ | ||
3812 | #define nMBRIF9 0x0 | ||
3813 | #define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */ | ||
3814 | #define nMBRIF10 0x0 | ||
3815 | #define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */ | ||
3816 | #define nMBRIF11 0x0 | ||
3817 | #define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */ | ||
3818 | #define nMBRIF12 0x0 | ||
3819 | #define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */ | ||
3820 | #define nMBRIF13 0x0 | ||
3821 | #define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */ | ||
3822 | #define nMBRIF14 0x0 | ||
3823 | #define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */ | ||
3824 | #define nMBRIF15 0x0 | ||
3825 | |||
3826 | /* Bit masks for CAN0_MBRIF2 */ | ||
3827 | |||
3828 | #define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */ | ||
3829 | #define nMBRIF16 0x0 | ||
3830 | #define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */ | ||
3831 | #define nMBRIF17 0x0 | ||
3832 | #define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */ | ||
3833 | #define nMBRIF18 0x0 | ||
3834 | #define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */ | ||
3835 | #define nMBRIF19 0x0 | ||
3836 | #define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */ | ||
3837 | #define nMBRIF20 0x0 | ||
3838 | #define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */ | ||
3839 | #define nMBRIF21 0x0 | ||
3840 | #define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */ | ||
3841 | #define nMBRIF22 0x0 | ||
3842 | #define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */ | ||
3843 | #define nMBRIF23 0x0 | ||
3844 | #define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */ | ||
3845 | #define nMBRIF24 0x0 | ||
3846 | #define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */ | ||
3847 | #define nMBRIF25 0x0 | ||
3848 | #define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */ | ||
3849 | #define nMBRIF26 0x0 | ||
3850 | #define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */ | ||
3851 | #define nMBRIF27 0x0 | ||
3852 | #define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */ | ||
3853 | #define nMBRIF28 0x0 | ||
3854 | #define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */ | ||
3855 | #define nMBRIF29 0x0 | ||
3856 | #define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */ | ||
3857 | #define nMBRIF30 0x0 | ||
3858 | #define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */ | ||
3859 | #define nMBRIF31 0x0 | ||
3860 | |||
3861 | /* Bit masks for EPPIx_STATUS */ | ||
3862 | |||
3863 | #define CFIFO_ERR 0x1 /* Chroma FIFO Error */ | ||
3864 | #define nCFIFO_ERR 0x0 | ||
3865 | #define YFIFO_ERR 0x2 /* Luma FIFO Error */ | ||
3866 | #define nYFIFO_ERR 0x0 | ||
3867 | #define LTERR_OVR 0x4 /* Line Track Overflow */ | ||
3868 | #define nLTERR_OVR 0x0 | ||
3869 | #define LTERR_UNDR 0x8 /* Line Track Underflow */ | ||
3870 | #define nLTERR_UNDR 0x0 | ||
3871 | #define FTERR_OVR 0x10 /* Frame Track Overflow */ | ||
3872 | #define nFTERR_OVR 0x0 | ||
3873 | #define FTERR_UNDR 0x20 /* Frame Track Underflow */ | ||
3874 | #define nFTERR_UNDR 0x0 | ||
3875 | #define ERR_NCOR 0x40 /* Preamble Error Not Corrected */ | ||
3876 | #define nERR_NCOR 0x0 | ||
3877 | #define DMA1URQ 0x80 /* DMA1 Urgent Request */ | ||
3878 | #define nDMA1URQ 0x0 | ||
3879 | #define DMA0URQ 0x100 /* DMA0 Urgent Request */ | ||
3880 | #define nDMA0URQ 0x0 | ||
3881 | #define ERR_DET 0x4000 /* Preamble Error Detected */ | ||
3882 | #define nERR_DET 0x0 | ||
3883 | #define FLD 0x8000 /* Field */ | ||
3884 | #define nFLD 0x0 | ||
3885 | |||
3886 | /* Bit masks for EPPIx_CONTROL */ | ||
3887 | |||
3888 | #define EPPI_EN 0x1 /* Enable */ | ||
3889 | #define nEPPI_EN 0x0 | ||
3890 | #define EPPI_DIR 0x2 /* Direction */ | ||
3891 | #define nEPPI_DIR 0x0 | ||
3892 | #define XFR_TYPE 0xc /* Operating Mode */ | ||
3893 | #define FS_CFG 0x30 /* Frame Sync Configuration */ | ||
3894 | #define FLD_SEL 0x40 /* Field Select/Trigger */ | ||
3895 | #define nFLD_SEL 0x0 | ||
3896 | #define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */ | ||
3897 | #define nITU_TYPE 0x0 | ||
3898 | #define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */ | ||
3899 | #define nBLANKGEN 0x0 | ||
3900 | #define ICLKGEN 0x200 /* Internal Clock Generation */ | ||
3901 | #define nICLKGEN 0x0 | ||
3902 | #define IFSGEN 0x400 /* Internal Frame Sync Generation */ | ||
3903 | #define nIFSGEN 0x0 | ||
3904 | #define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */ | ||
3905 | #define POLS 0x6000 /* Frame Sync Polarity */ | ||
3906 | #define DLENGTH 0x38000 /* Data Length */ | ||
3907 | #define SKIP_EN 0x40000 /* Skip Enable */ | ||
3908 | #define nSKIP_EN 0x0 | ||
3909 | #define SKIP_EO 0x80000 /* Skip Even or Odd */ | ||
3910 | #define nSKIP_EO 0x0 | ||
3911 | #define PACKEN 0x100000 /* Packing/Unpacking Enable */ | ||
3912 | #define nPACKEN 0x0 | ||
3913 | #define SWAPEN 0x200000 /* Swap Enable */ | ||
3914 | #define nSWAPEN 0x0 | ||
3915 | #define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */ | ||
3916 | #define nSIGN_EXT 0x0 | ||
3917 | #define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */ | ||
3918 | #define nSPLT_EVEN_ODD 0x0 | ||
3919 | #define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */ | ||
3920 | #define nSUBSPLT_ODD 0x0 | ||
3921 | #define DMACFG 0x2000000 /* One or Two DMA Channels Mode */ | ||
3922 | #define nDMACFG 0x0 | ||
3923 | #define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */ | ||
3924 | #define nRGB_FMT_EN 0x0 | ||
3925 | #define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */ | ||
3926 | #define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */ | ||
3927 | |||
3928 | /* Bit masks for EPPIx_FS2W_LVB */ | ||
3929 | |||
3930 | #define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */ | ||
3931 | #define F1VB_AD 0xff00 /* Vertical Blanking after Field 1 Active Data */ | ||
3932 | #define F2VB_BD 0xff0000 /* Vertical Blanking before Field 2 Active Data */ | ||
3933 | #define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */ | ||
3934 | |||
3935 | /* Bit masks for EPPIx_FS2W_LAVF */ | ||
3936 | |||
3937 | #define F1_ACT 0xffff /* Number of Lines of Active Data in Field 1 */ | ||
3938 | #define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */ | ||
3939 | |||
3940 | /* Bit masks for EPPIx_CLIP */ | ||
3941 | |||
3942 | #define LOW_ODD 0xff /* Lower Limit for Odd Bytes (Chroma) */ | ||
3943 | #define HIGH_ODD 0xff00 /* Upper Limit for Odd Bytes (Chroma) */ | ||
3944 | #define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */ | ||
3945 | #define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */ | ||
3946 | |||
3947 | /* Bit masks for SPIx_BAUD */ | ||
3948 | |||
3949 | #define SPI_BAUD 0xffff /* Baud Rate */ | ||
3950 | |||
3951 | /* Bit masks for SPIx_CTL */ | ||
3952 | |||
3953 | #define SPE 0x4000 /* SPI Enable */ | ||
3954 | #define nSPE 0x0 | ||
3955 | #define WOM 0x2000 /* Write Open Drain Master */ | ||
3956 | #define nWOM 0x0 | ||
3957 | #define MSTR 0x1000 /* Master Mode */ | ||
3958 | #define nMSTR 0x0 | ||
3959 | #define CPOL 0x800 /* Clock Polarity */ | ||
3960 | #define nCPOL 0x0 | ||
3961 | #define CPHA 0x400 /* Clock Phase */ | ||
3962 | #define nCPHA 0x0 | ||
3963 | #define LSBF 0x200 /* LSB First */ | ||
3964 | #define nLSBF 0x0 | ||
3965 | #define SIZE 0x100 /* Size of Words */ | ||
3966 | #define nSIZE 0x0 | ||
3967 | #define EMISO 0x20 /* Enable MISO Output */ | ||
3968 | #define nEMISO 0x0 | ||
3969 | #define PSSE 0x10 /* Slave-Select Enable */ | ||
3970 | #define nPSSE 0x0 | ||
3971 | #define GM 0x8 /* Get More Data */ | ||
3972 | #define nGM 0x0 | ||
3973 | #define SZ 0x4 /* Send Zero */ | ||
3974 | #define nSZ 0x0 | ||
3975 | #define TIMOD 0x3 /* Transfer Initiation Mode */ | ||
3976 | |||
3977 | /* Bit masks for SPIx_FLG */ | ||
3978 | |||
3979 | #define FLS1 0x2 /* Slave Select Enable 1 */ | ||
3980 | #define nFLS1 0x0 | ||
3981 | #define FLS2 0x4 /* Slave Select Enable 2 */ | ||
3982 | #define nFLS2 0x0 | ||
3983 | #define FLS3 0x8 /* Slave Select Enable 3 */ | ||
3984 | #define nFLS3 0x0 | ||
3985 | #define FLG1 0x200 /* Slave Select Value 1 */ | ||
3986 | #define nFLG1 0x0 | ||
3987 | #define FLG2 0x400 /* Slave Select Value 2 */ | ||
3988 | #define nFLG2 0x0 | ||
3989 | #define FLG3 0x800 /* Slave Select Value 3 */ | ||
3990 | #define nFLG3 0x0 | ||
3991 | |||
3992 | /* Bit masks for SPIx_STAT */ | ||
3993 | |||
3994 | #define TXCOL 0x40 /* Transmit Collision Error */ | ||
3995 | #define nTXCOL 0x0 | ||
3996 | #define RXS 0x20 /* RDBR Data Buffer Status */ | ||
3997 | #define nRXS 0x0 | ||
3998 | #define RBSY 0x10 /* Receive Error */ | ||
3999 | #define nRBSY 0x0 | ||
4000 | #define TXS 0x8 /* TDBR Data Buffer Status */ | ||
4001 | #define nTXS 0x0 | ||
4002 | #define TXE 0x4 /* Transmission Error */ | ||
4003 | #define nTXE 0x0 | ||
4004 | #define MODF 0x2 /* Mode Fault Error */ | ||
4005 | #define nMODF 0x0 | ||
4006 | #define SPIF 0x1 /* SPI Finished */ | ||
4007 | #define nSPIF 0x0 | ||
4008 | |||
4009 | /* Bit masks for SPIx_TDBR */ | ||
4010 | |||
4011 | #define TDBR 0xffff /* Transmit Data Buffer */ | ||
4012 | |||
4013 | /* Bit masks for SPIx_RDBR */ | ||
4014 | |||
4015 | #define RDBR 0xffff /* Receive Data Buffer */ | ||
4016 | |||
4017 | /* Bit masks for SPIx_SHADOW */ | ||
4018 | |||
4019 | #define SHADOW 0xffff /* RDBR Shadow */ | ||
4020 | |||
4021 | /* ************************************************ */ | ||
4022 | /* The TWI bit masks fields are from the ADSP-BF538 */ | ||
4023 | /* and they have not been verified as the final */ | ||
4024 | /* ones for the Moab processors ... bz 1/19/2007 */ | ||
4025 | /* ************************************************ */ | ||
4026 | |||
4027 | /* Bit masks for TWIx_CONTROL */ | ||
4028 | |||
4029 | #define PRESCALE 0x7f /* Prescale Value */ | ||
4030 | #define TWI_ENA 0x80 /* TWI Enable */ | ||
4031 | #define nTWI_ENA 0x0 | ||
4032 | #define SCCB 0x200 /* Serial Camera Control Bus */ | ||
4033 | #define nSCCB 0x0 | ||
4034 | |||
4035 | /* Bit maskes for TWIx_CLKDIV */ | ||
4036 | |||
4037 | #define CLKLOW 0xff /* Clock Low */ | ||
4038 | #define CLKHI 0xff00 /* Clock High */ | ||
4039 | |||
4040 | /* Bit maskes for TWIx_SLAVE_CTL */ | ||
4041 | |||
4042 | #define SEN 0x1 /* Slave Enable */ | ||
4043 | #define nSEN 0x0 | ||
4044 | #define STDVAL 0x4 /* Slave Transmit Data Valid */ | ||
4045 | #define nSTDVAL 0x0 | ||
4046 | #define NAK 0x8 /* Not Acknowledge */ | ||
4047 | #define nNAK 0x0 | ||
4048 | #define GEN 0x10 /* General Call Enable */ | ||
4049 | #define nGEN 0x0 | ||
4050 | |||
4051 | /* Bit maskes for TWIx_SLAVE_ADDR */ | ||
4052 | |||
4053 | #define SADDR 0x7f /* Slave Mode Address */ | ||
4054 | |||
4055 | /* Bit maskes for TWIx_SLAVE_STAT */ | ||
4056 | |||
4057 | #define SDIR 0x1 /* Slave Transfer Direction */ | ||
4058 | #define nSDIR 0x0 | ||
4059 | #define GCALL 0x2 /* General Call */ | ||
4060 | #define nGCALL 0x0 | ||
4061 | |||
4062 | /* Bit maskes for TWIx_MASTER_CTL */ | ||
4063 | |||
4064 | #define MEN 0x1 /* Master Mode Enable */ | ||
4065 | #define nMEN 0x0 | ||
4066 | #define MDIR 0x4 /* Master Transfer Direction */ | ||
4067 | #define nMDIR 0x0 | ||
4068 | #define FAST 0x8 /* Fast Mode */ | ||
4069 | #define nFAST 0x0 | ||
4070 | #define STOP 0x10 /* Issue Stop Condition */ | ||
4071 | #define nSTOP 0x0 | ||
4072 | #define RSTART 0x20 /* Repeat Start */ | ||
4073 | #define nRSTART 0x0 | ||
4074 | #define DCNT 0x3fc0 /* Data Transfer Count */ | ||
4075 | #define SDAOVR 0x4000 /* Serial Data Override */ | ||
4076 | #define nSDAOVR 0x0 | ||
4077 | #define SCLOVR 0x8000 /* Serial Clock Override */ | ||
4078 | #define nSCLOVR 0x0 | ||
4079 | |||
4080 | /* Bit maskes for TWIx_MASTER_ADDR */ | ||
4081 | |||
4082 | #define MADDR 0x7f /* Master Mode Address */ | ||
4083 | |||
4084 | /* Bit maskes for TWIx_MASTER_STAT */ | ||
4085 | |||
4086 | #define MPROG 0x1 /* Master Transfer in Progress */ | ||
4087 | #define nMPROG 0x0 | ||
4088 | #define LOSTARB 0x2 /* Lost Arbitration */ | ||
4089 | #define nLOSTARB 0x0 | ||
4090 | #define ANAK 0x4 /* Address Not Acknowledged */ | ||
4091 | #define nANAK 0x0 | ||
4092 | #define DNAK 0x8 /* Data Not Acknowledged */ | ||
4093 | #define nDNAK 0x0 | ||
4094 | #define BUFRDERR 0x10 /* Buffer Read Error */ | ||
4095 | #define nBUFRDERR 0x0 | ||
4096 | #define BUFWRERR 0x20 /* Buffer Write Error */ | ||
4097 | #define nBUFWRERR 0x0 | ||
4098 | #define SDASEN 0x40 /* Serial Data Sense */ | ||
4099 | #define nSDASEN 0x0 | ||
4100 | #define SCLSEN 0x80 /* Serial Clock Sense */ | ||
4101 | #define nSCLSEN 0x0 | ||
4102 | #define BUSBUSY 0x100 /* Bus Busy */ | ||
4103 | #define nBUSBUSY 0x0 | ||
4104 | |||
4105 | /* Bit maskes for TWIx_FIFO_CTL */ | ||
4106 | |||
4107 | #define XMTFLUSH 0x1 /* Transmit Buffer Flush */ | ||
4108 | #define nXMTFLUSH 0x0 | ||
4109 | #define RCVFLUSH 0x2 /* Receive Buffer Flush */ | ||
4110 | #define nRCVFLUSH 0x0 | ||
4111 | #define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */ | ||
4112 | #define nXMTINTLEN 0x0 | ||
4113 | #define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */ | ||
4114 | #define nRCVINTLEN 0x0 | ||
4115 | |||
4116 | /* Bit maskes for TWIx_FIFO_STAT */ | ||
4117 | |||
4118 | #define XMTSTAT 0x3 /* Transmit FIFO Status */ | ||
4119 | #define RCVSTAT 0xc /* Receive FIFO Status */ | ||
4120 | |||
4121 | /* Bit maskes for TWIx_INT_MASK */ | ||
4122 | |||
4123 | #define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */ | ||
4124 | #define nSINITM 0x0 | ||
4125 | #define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */ | ||
4126 | #define nSCOMPM 0x0 | ||
4127 | #define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */ | ||
4128 | #define nSERRM 0x0 | ||
4129 | #define SOVFM 0x8 /* Slave Overflow Interrupt Mask */ | ||
4130 | #define nSOVFM 0x0 | ||
4131 | #define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */ | ||
4132 | #define nMCOMPM 0x0 | ||
4133 | #define MERRM 0x20 /* Master Transfer Error Interrupt Mask */ | ||
4134 | #define nMERRM 0x0 | ||
4135 | #define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */ | ||
4136 | #define nXMTSERVM 0x0 | ||
4137 | #define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */ | ||
4138 | #define nRCVSERVM 0x0 | ||
4139 | |||
4140 | /* Bit maskes for TWIx_INT_STAT */ | ||
4141 | |||
4142 | #define SINIT 0x1 /* Slave Transfer Initiated */ | ||
4143 | #define nSINIT 0x0 | ||
4144 | #define SCOMP 0x2 /* Slave Transfer Complete */ | ||
4145 | #define nSCOMP 0x0 | ||
4146 | #define SERR 0x4 /* Slave Transfer Error */ | ||
4147 | #define nSERR 0x0 | ||
4148 | #define SOVF 0x8 /* Slave Overflow */ | ||
4149 | #define nSOVF 0x0 | ||
4150 | #define MCOMP 0x10 /* Master Transfer Complete */ | ||
4151 | #define nMCOMP 0x0 | ||
4152 | #define MERR 0x20 /* Master Transfer Error */ | ||
4153 | #define nMERR 0x0 | ||
4154 | #define XMTSERV 0x40 /* Transmit FIFO Service */ | ||
4155 | #define nXMTSERV 0x0 | ||
4156 | #define RCVSERV 0x80 /* Receive FIFO Service */ | ||
4157 | #define nRCVSERV 0x0 | ||
4158 | |||
4159 | /* Bit maskes for TWIx_XMT_DATA8 */ | ||
4160 | |||
4161 | #define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */ | ||
4162 | |||
4163 | /* Bit maskes for TWIx_XMT_DATA16 */ | ||
4164 | |||
4165 | #define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */ | ||
4166 | |||
4167 | /* Bit maskes for TWIx_RCV_DATA8 */ | ||
4168 | |||
4169 | #define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */ | ||
4170 | |||
4171 | /* Bit maskes for TWIx_RCV_DATA16 */ | ||
4172 | |||
4173 | #define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */ | ||
4174 | |||
4175 | /* Bit masks for SPORTx_TCR1 */ | ||
4176 | |||
4177 | #define TCKFE 0x4000 /* Clock Falling Edge Select */ | ||
4178 | #define nTCKFE 0x0 | ||
4179 | #define LATFS 0x2000 /* Late Transmit Frame Sync */ | ||
4180 | #define nLATFS 0x0 | ||
4181 | #define LTFS 0x1000 /* Low Transmit Frame Sync Select */ | ||
4182 | #define nLTFS 0x0 | ||
4183 | #define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */ | ||
4184 | #define nDITFS 0x0 | ||
4185 | #define TFSR 0x400 /* Transmit Frame Sync Required Select */ | ||
4186 | #define nTFSR 0x0 | ||
4187 | #define ITFS 0x200 /* Internal Transmit Frame Sync Select */ | ||
4188 | #define nITFS 0x0 | ||
4189 | #define TLSBIT 0x10 /* Transmit Bit Order */ | ||
4190 | #define nTLSBIT 0x0 | ||
4191 | #define TDTYPE 0xc /* Data Formatting Type Select */ | ||
4192 | #define ITCLK 0x2 /* Internal Transmit Clock Select */ | ||
4193 | #define nITCLK 0x0 | ||
4194 | #define TSPEN 0x1 /* Transmit Enable */ | ||
4195 | #define nTSPEN 0x0 | ||
4196 | |||
4197 | /* Bit masks for SPORTx_TCR2 */ | ||
4198 | |||
4199 | #define TRFST 0x400 /* Left/Right Order */ | ||
4200 | #define nTRFST 0x0 | ||
4201 | #define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */ | ||
4202 | #define nTSFSE 0x0 | ||
4203 | #define TXSE 0x100 /* TxSEC Enable */ | ||
4204 | #define nTXSE 0x0 | ||
4205 | #define SLEN_T 0x1f /* SPORT Word Length */ | ||
4206 | |||
4207 | /* Bit masks for SPORTx_RCR1 */ | ||
4208 | |||
4209 | #define RCKFE 0x4000 /* Clock Falling Edge Select */ | ||
4210 | #define nRCKFE 0x0 | ||
4211 | #define LARFS 0x2000 /* Late Receive Frame Sync */ | ||
4212 | #define nLARFS 0x0 | ||
4213 | #define LRFS 0x1000 /* Low Receive Frame Sync Select */ | ||
4214 | #define nLRFS 0x0 | ||
4215 | #define RFSR 0x400 /* Receive Frame Sync Required Select */ | ||
4216 | #define nRFSR 0x0 | ||
4217 | #define IRFS 0x200 /* Internal Receive Frame Sync Select */ | ||
4218 | #define nIRFS 0x0 | ||
4219 | #define RLSBIT 0x10 /* Receive Bit Order */ | ||
4220 | #define nRLSBIT 0x0 | ||
4221 | #define RDTYPE 0xc /* Data Formatting Type Select */ | ||
4222 | #define IRCLK 0x2 /* Internal Receive Clock Select */ | ||
4223 | #define nIRCLK 0x0 | ||
4224 | #define RSPEN 0x1 /* Receive Enable */ | ||
4225 | #define nRSPEN 0x0 | ||
4226 | |||
4227 | /* Bit masks for SPORTx_RCR2 */ | ||
4228 | |||
4229 | #define RRFST 0x400 /* Left/Right Order */ | ||
4230 | #define nRRFST 0x0 | ||
4231 | #define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */ | ||
4232 | #define nRSFSE 0x0 | ||
4233 | #define RXSE 0x100 /* RxSEC Enable */ | ||
4234 | #define nRXSE 0x0 | ||
4235 | #define SLEN_R 0x1f /* SPORT Word Length */ | ||
4236 | |||
4237 | /* Bit masks for SPORTx_STAT */ | ||
4238 | |||
4239 | #define TXHRE 0x40 /* Transmit Hold Register Empty */ | ||
4240 | #define nTXHRE 0x0 | ||
4241 | #define TOVF 0x20 /* Sticky Transmit Overflow Status */ | ||
4242 | #define nTOVF 0x0 | ||
4243 | #define TUVF 0x10 /* Sticky Transmit Underflow Status */ | ||
4244 | #define nTUVF 0x0 | ||
4245 | #define TXF 0x8 /* Transmit FIFO Full Status */ | ||
4246 | #define nTXF 0x0 | ||
4247 | #define ROVF 0x4 /* Sticky Receive Overflow Status */ | ||
4248 | #define nROVF 0x0 | ||
4249 | #define RUVF 0x2 /* Sticky Receive Underflow Status */ | ||
4250 | #define nRUVF 0x0 | ||
4251 | #define RXNE 0x1 /* Receive FIFO Not Empty Status */ | ||
4252 | #define nRXNE 0x0 | ||
4253 | |||
4254 | /* Bit masks for SPORTx_MCMC1 */ | ||
4255 | |||
4256 | #define SP_WSIZE 0xf000 /* Window Size */ | ||
4257 | #define SP_WOFF 0x3ff /* Windows Offset */ | ||
4258 | |||
4259 | /* Bit masks for SPORTx_MCMC2 */ | ||
4260 | |||
4261 | #define MFD 0xf000 /* Multi channel Frame Delay */ | ||
4262 | #define FSDR 0x80 /* Frame Sync to Data Relationship */ | ||
4263 | #define nFSDR 0x0 | ||
4264 | #define MCMEM 0x10 /* Multi channel Frame Mode Enable */ | ||
4265 | #define nMCMEM 0x0 | ||
4266 | #define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */ | ||
4267 | #define nMCDRXPE 0x0 | ||
4268 | #define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */ | ||
4269 | #define nMCDTXPE 0x0 | ||
4270 | #define MCCRM 0x3 /* 2X Clock Recovery Mode */ | ||
4271 | |||
4272 | /* Bit masks for SPORTx_CHNL */ | ||
4273 | |||
4274 | #define CUR_CHNL 0x3ff /* Current Channel Indicator */ | ||
4275 | |||
4276 | /* Bit masks for UARTx_LCR */ | ||
4277 | |||
4278 | #if 0 | ||
4279 | /* conflicts with legacy one in last section */ | ||
4280 | #define WLS 0x3 /* Word Length Select */ | ||
4281 | #endif | ||
4282 | #define STB 0x4 /* Stop Bits */ | ||
4283 | #define nSTB 0x0 | ||
4284 | #define PEN 0x8 /* Parity Enable */ | ||
4285 | #define nPEN 0x0 | ||
4286 | #define EPS 0x10 /* Even Parity Select */ | ||
4287 | #define nEPS 0x0 | ||
4288 | #define STP 0x20 /* Sticky Parity */ | ||
4289 | #define nSTP 0x0 | ||
4290 | #define SB 0x40 /* Set Break */ | ||
4291 | #define nSB 0x0 | ||
4292 | |||
4293 | /* Bit masks for UARTx_MCR */ | ||
4294 | |||
4295 | #define XOFF 0x1 /* Transmitter Off */ | ||
4296 | #define nXOFF 0x0 | ||
4297 | #define MRTS 0x2 /* Manual Request To Send */ | ||
4298 | #define nMRTS 0x0 | ||
4299 | #define RFIT 0x4 /* Receive FIFO IRQ Threshold */ | ||
4300 | #define nRFIT 0x0 | ||
4301 | #define RFRT 0x8 /* Receive FIFO RTS Threshold */ | ||
4302 | #define nRFRT 0x0 | ||
4303 | #define LOOP_ENA 0x10 /* Loopback Mode Enable */ | ||
4304 | #define nLOOP_ENA 0x0 | ||
4305 | #define FCPOL 0x20 /* Flow Control Pin Polarity */ | ||
4306 | #define nFCPOL 0x0 | ||
4307 | #define ARTS 0x40 /* Automatic Request To Send */ | ||
4308 | #define nARTS 0x0 | ||
4309 | #define ACTS 0x80 /* Automatic Clear To Send */ | ||
4310 | #define nACTS 0x0 | ||
4311 | |||
4312 | /* Bit masks for UARTx_LSR */ | ||
4313 | |||
4314 | #define DR 0x1 /* Data Ready */ | ||
4315 | #define nDR 0x0 | ||
4316 | #define OE 0x2 /* Overrun Error */ | ||
4317 | #define nOE 0x0 | ||
4318 | #define PE 0x4 /* Parity Error */ | ||
4319 | #define nPE 0x0 | ||
4320 | #define FE 0x8 /* Framing Error */ | ||
4321 | #define nFE 0x0 | ||
4322 | #define BI 0x10 /* Break Interrupt */ | ||
4323 | #define nBI 0x0 | ||
4324 | #define THRE 0x20 /* THR Empty */ | ||
4325 | #define nTHRE 0x0 | ||
4326 | #define TEMT 0x40 /* Transmitter Empty */ | ||
4327 | #define nTEMT 0x0 | ||
4328 | #define TFI 0x80 /* Transmission Finished Indicator */ | ||
4329 | #define nTFI 0x0 | ||
4330 | |||
4331 | /* Bit masks for UARTx_MSR */ | ||
4332 | |||
4333 | #define SCTS 0x1 /* Sticky CTS */ | ||
4334 | #define nSCTS 0x0 | ||
4335 | #define CTS 0x10 /* Clear To Send */ | ||
4336 | #define nCTS 0x0 | ||
4337 | #define RFCS 0x20 /* Receive FIFO Count Status */ | ||
4338 | #define nRFCS 0x0 | ||
4339 | |||
4340 | /* Bit masks for UARTx_IER_SET */ | ||
4341 | |||
4342 | #define ERBFI_S 0x1 /* Enable Receive Buffer Full Interrupt */ | ||
4343 | #define nERBFI_S 0x0 | ||
4344 | #define ETBEI_S 0x2 /* Enable Transmit Buffer Empty Interrupt */ | ||
4345 | #define nETBEI_S 0x0 | ||
4346 | #define ELSI_S 0x4 /* Enable Receive Status Interrupt */ | ||
4347 | #define nELSI_S 0x0 | ||
4348 | #define EDSSI_S 0x8 /* Enable Modem Status Interrupt */ | ||
4349 | #define nEDSSI_S 0x0 | ||
4350 | #define EDTPTI_S 0x10 /* Enable DMA Transmit PIRQ Interrupt */ | ||
4351 | #define nEDTPTI_S 0x0 | ||
4352 | #define ETFI_S 0x20 /* Enable Transmission Finished Interrupt */ | ||
4353 | #define nETFI_S 0x0 | ||
4354 | #define ERFCI_S 0x40 /* Enable Receive FIFO Count Interrupt */ | ||
4355 | #define nERFCI_S 0x0 | ||
4356 | |||
4357 | /* Bit masks for UARTx_IER_CLEAR */ | ||
4358 | |||
4359 | #define ERBFI_C 0x1 /* Enable Receive Buffer Full Interrupt */ | ||
4360 | #define nERBFI_C 0x0 | ||
4361 | #define ETBEI_C 0x2 /* Enable Transmit Buffer Empty Interrupt */ | ||
4362 | #define nETBEI_C 0x0 | ||
4363 | #define ELSI_C 0x4 /* Enable Receive Status Interrupt */ | ||
4364 | #define nELSI_C 0x0 | ||
4365 | #define EDSSI_C 0x8 /* Enable Modem Status Interrupt */ | ||
4366 | #define nEDSSI_C 0x0 | ||
4367 | #define EDTPTI_C 0x10 /* Enable DMA Transmit PIRQ Interrupt */ | ||
4368 | #define nEDTPTI_C 0x0 | ||
4369 | #define ETFI_C 0x20 /* Enable Transmission Finished Interrupt */ | ||
4370 | #define nETFI_C 0x0 | ||
4371 | #define ERFCI_C 0x40 /* Enable Receive FIFO Count Interrupt */ | ||
4372 | #define nERFCI_C 0x0 | ||
4373 | |||
4374 | /* Bit masks for UARTx_GCTL */ | ||
4375 | |||
4376 | #define UCEN 0x1 /* UART Enable */ | ||
4377 | #define nUCEN 0x0 | ||
4378 | #define IREN 0x2 /* IrDA Mode Enable */ | ||
4379 | #define nIREN 0x0 | ||
4380 | #define TPOLC 0x4 /* IrDA TX Polarity Change */ | ||
4381 | #define nTPOLC 0x0 | ||
4382 | #define RPOLC 0x8 /* IrDA RX Polarity Change */ | ||
4383 | #define nRPOLC 0x0 | ||
4384 | #define FPE 0x10 /* Force Parity Error */ | ||
4385 | #define nFPE 0x0 | ||
4386 | #define FFE 0x20 /* Force Framing Error */ | ||
4387 | #define nFFE 0x0 | ||
4388 | #define EDBO 0x40 /* Enable Divide-by-One */ | ||
4389 | #define nEDBO 0x0 | ||
4390 | #define EGLSI 0x80 /* Enable Global LS Interrupt */ | ||
4391 | #define nEGLSI 0x0 | ||
4392 | |||
4393 | |||
4394 | /* ******************************************* */ | ||
4395 | /* MULTI BIT MACRO ENUMERATIONS */ | ||
4396 | /* ******************************************* */ | ||
4397 | |||
4398 | /* BCODE bit field options (SYSCFG register) */ | ||
4399 | |||
4400 | #define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */ | ||
4401 | #define BCODE_FULLBOOT 0x0010 /* always perform full boot */ | ||
4402 | #define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */ | ||
4403 | #define BCODE_NOBOOT 0x0030 /* always perform full boot */ | ||
4404 | |||
4405 | /* CNT_COMMAND bit field options */ | ||
4406 | |||
4407 | #define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */ | ||
4408 | #define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */ | ||
4409 | #define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */ | ||
4410 | |||
4411 | #define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */ | ||
4412 | #define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */ | ||
4413 | #define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */ | ||
4414 | |||
4415 | #define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */ | ||
4416 | #define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */ | ||
4417 | #define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */ | ||
4418 | |||
4419 | /* CNT_CONFIG bit field options */ | ||
4420 | |||
4421 | #define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */ | ||
4422 | #define CNTMODE_BINENC 0x0100 /* binary encoder mode */ | ||
4423 | #define CNTMODE_UDCNT 0x0200 /* up/down counter mode */ | ||
4424 | #define CNTMODE_DIRCNT 0x0400 /* direction counter mode */ | ||
4425 | #define CNTMODE_DIRTMR 0x0500 /* direction timer mode */ | ||
4426 | |||
4427 | #define BNDMODE_COMP 0x0000 /* boundary compare mode */ | ||
4428 | #define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */ | ||
4429 | #define BNDMODE_CAPT 0x2000 /* boundary capture mode */ | ||
4430 | #define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */ | ||
4431 | |||
4432 | /* TMODE in TIMERx_CONFIG bit field options */ | ||
4433 | |||
4434 | #define PWM_OUT 0x0001 | ||
4435 | #define WDTH_CAP 0x0002 | ||
4436 | #define EXT_CLK 0x0003 | ||
4437 | |||
4438 | /* UARTx_LCR bit field options */ | ||
4439 | |||
4440 | #define WLS_5 0x0000 /* 5 data bits */ | ||
4441 | #define WLS_6 0x0001 /* 6 data bits */ | ||
4442 | #define WLS_7 0x0002 /* 7 data bits */ | ||
4443 | #define WLS_8 0x0003 /* 8 data bits */ | ||
4444 | |||
4445 | /* PINTx Register Bit Definitions */ | ||
4446 | |||
4447 | #define PIQ0 0x00000001 | ||
4448 | #define PIQ1 0x00000002 | ||
4449 | #define PIQ2 0x00000004 | ||
4450 | #define PIQ3 0x00000008 | ||
4451 | |||
4452 | #define PIQ4 0x00000010 | ||
4453 | #define PIQ5 0x00000020 | ||
4454 | #define PIQ6 0x00000040 | ||
4455 | #define PIQ7 0x00000080 | ||
4456 | |||
4457 | #define PIQ8 0x00000100 | ||
4458 | #define PIQ9 0x00000200 | ||
4459 | #define PIQ10 0x00000400 | ||
4460 | #define PIQ11 0x00000800 | ||
4461 | |||
4462 | #define PIQ12 0x00001000 | ||
4463 | #define PIQ13 0x00002000 | ||
4464 | #define PIQ14 0x00004000 | ||
4465 | #define PIQ15 0x00008000 | ||
4466 | |||
4467 | #define PIQ16 0x00010000 | ||
4468 | #define PIQ17 0x00020000 | ||
4469 | #define PIQ18 0x00040000 | ||
4470 | #define PIQ19 0x00080000 | ||
4471 | |||
4472 | #define PIQ20 0x00100000 | ||
4473 | #define PIQ21 0x00200000 | ||
4474 | #define PIQ22 0x00400000 | ||
4475 | #define PIQ23 0x00800000 | ||
4476 | |||
4477 | #define PIQ24 0x01000000 | ||
4478 | #define PIQ25 0x02000000 | ||
4479 | #define PIQ26 0x04000000 | ||
4480 | #define PIQ27 0x08000000 | ||
4481 | |||
4482 | #define PIQ28 0x10000000 | ||
4483 | #define PIQ29 0x20000000 | ||
4484 | #define PIQ30 0x40000000 | ||
4485 | #define PIQ31 0x80000000 | ||
4486 | |||
4487 | /* PORT A Bit Definitions for the registers | ||
4488 | PORTA, PORTA_SET, PORTA_CLEAR, | ||
4489 | PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN, | ||
4490 | PORTA_FER registers | ||
4491 | */ | ||
4492 | |||
4493 | #define PA0 0x0001 | ||
4494 | #define PA1 0x0002 | ||
4495 | #define PA2 0x0004 | ||
4496 | #define PA3 0x0008 | ||
4497 | #define PA4 0x0010 | ||
4498 | #define PA5 0x0020 | ||
4499 | #define PA6 0x0040 | ||
4500 | #define PA7 0x0080 | ||
4501 | #define PA8 0x0100 | ||
4502 | #define PA9 0x0200 | ||
4503 | #define PA10 0x0400 | ||
4504 | #define PA11 0x0800 | ||
4505 | #define PA12 0x1000 | ||
4506 | #define PA13 0x2000 | ||
4507 | #define PA14 0x4000 | ||
4508 | #define PA15 0x8000 | ||
4509 | |||
4510 | /* PORT B Bit Definitions for the registers | ||
4511 | PORTB, PORTB_SET, PORTB_CLEAR, | ||
4512 | PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN, | ||
4513 | PORTB_FER registers | ||
4514 | */ | ||
4515 | |||
4516 | #define PB0 0x0001 | ||
4517 | #define PB1 0x0002 | ||
4518 | #define PB2 0x0004 | ||
4519 | #define PB3 0x0008 | ||
4520 | #define PB4 0x0010 | ||
4521 | #define PB5 0x0020 | ||
4522 | #define PB6 0x0040 | ||
4523 | #define PB7 0x0080 | ||
4524 | #define PB8 0x0100 | ||
4525 | #define PB9 0x0200 | ||
4526 | #define PB10 0x0400 | ||
4527 | #define PB11 0x0800 | ||
4528 | #define PB12 0x1000 | ||
4529 | #define PB13 0x2000 | ||
4530 | #define PB14 0x4000 | ||
4531 | |||
4532 | |||
4533 | /* PORT C Bit Definitions for the registers | ||
4534 | PORTC, PORTC_SET, PORTC_CLEAR, | ||
4535 | PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN, | ||
4536 | PORTC_FER registers | ||
4537 | */ | ||
4538 | |||
4539 | |||
4540 | #define PC0 0x0001 | ||
4541 | #define PC1 0x0002 | ||
4542 | #define PC2 0x0004 | ||
4543 | #define PC3 0x0008 | ||
4544 | #define PC4 0x0010 | ||
4545 | #define PC5 0x0020 | ||
4546 | #define PC6 0x0040 | ||
4547 | #define PC7 0x0080 | ||
4548 | #define PC8 0x0100 | ||
4549 | #define PC9 0x0200 | ||
4550 | #define PC10 0x0400 | ||
4551 | #define PC11 0x0800 | ||
4552 | #define PC12 0x1000 | ||
4553 | #define PC13 0x2000 | ||
4554 | |||
4555 | |||
4556 | /* PORT D Bit Definitions for the registers | ||
4557 | PORTD, PORTD_SET, PORTD_CLEAR, | ||
4558 | PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN, | ||
4559 | PORTD_FER registers | ||
4560 | */ | ||
4561 | |||
4562 | #define PD0 0x0001 | ||
4563 | #define PD1 0x0002 | ||
4564 | #define PD2 0x0004 | ||
4565 | #define PD3 0x0008 | ||
4566 | #define PD4 0x0010 | ||
4567 | #define PD5 0x0020 | ||
4568 | #define PD6 0x0040 | ||
4569 | #define PD7 0x0080 | ||
4570 | #define PD8 0x0100 | ||
4571 | #define PD9 0x0200 | ||
4572 | #define PD10 0x0400 | ||
4573 | #define PD11 0x0800 | ||
4574 | #define PD12 0x1000 | ||
4575 | #define PD13 0x2000 | ||
4576 | #define PD14 0x4000 | ||
4577 | #define PD15 0x8000 | ||
4578 | |||
4579 | /* PORT E Bit Definitions for the registers | ||
4580 | PORTE, PORTE_SET, PORTE_CLEAR, | ||
4581 | PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN, | ||
4582 | PORTE_FER registers | ||
4583 | */ | ||
4584 | |||
4585 | |||
4586 | #define PE0 0x0001 | ||
4587 | #define PE1 0x0002 | ||
4588 | #define PE2 0x0004 | ||
4589 | #define PE3 0x0008 | ||
4590 | #define PE4 0x0010 | ||
4591 | #define PE5 0x0020 | ||
4592 | #define PE6 0x0040 | ||
4593 | #define PE7 0x0080 | ||
4594 | #define PE8 0x0100 | ||
4595 | #define PE9 0x0200 | ||
4596 | #define PE10 0x0400 | ||
4597 | #define PE11 0x0800 | ||
4598 | #define PE12 0x1000 | ||
4599 | #define PE13 0x2000 | ||
4600 | #define PE14 0x4000 | ||
4601 | #define PE15 0x8000 | ||
4602 | |||
4603 | /* PORT F Bit Definitions for the registers | ||
4604 | PORTF, PORTF_SET, PORTF_CLEAR, | ||
4605 | PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN, | ||
4606 | PORTF_FER registers | ||
4607 | */ | ||
4608 | |||
4609 | |||
4610 | #define PF0 0x0001 | ||
4611 | #define PF1 0x0002 | ||
4612 | #define PF2 0x0004 | ||
4613 | #define PF3 0x0008 | ||
4614 | #define PF4 0x0010 | ||
4615 | #define PF5 0x0020 | ||
4616 | #define PF6 0x0040 | ||
4617 | #define PF7 0x0080 | ||
4618 | #define PF8 0x0100 | ||
4619 | #define PF9 0x0200 | ||
4620 | #define PF10 0x0400 | ||
4621 | #define PF11 0x0800 | ||
4622 | #define PF12 0x1000 | ||
4623 | #define PF13 0x2000 | ||
4624 | #define PF14 0x4000 | ||
4625 | #define PF15 0x8000 | ||
4626 | |||
4627 | /* PORT G Bit Definitions for the registers | ||
4628 | PORTG, PORTG_SET, PORTG_CLEAR, | ||
4629 | PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN, | ||
4630 | PORTG_FER registers | ||
4631 | */ | ||
4632 | |||
4633 | |||
4634 | #define PG0 0x0001 | ||
4635 | #define PG1 0x0002 | ||
4636 | #define PG2 0x0004 | ||
4637 | #define PG3 0x0008 | ||
4638 | #define PG4 0x0010 | ||
4639 | #define PG5 0x0020 | ||
4640 | #define PG6 0x0040 | ||
4641 | #define PG7 0x0080 | ||
4642 | #define PG8 0x0100 | ||
4643 | #define PG9 0x0200 | ||
4644 | #define PG10 0x0400 | ||
4645 | #define PG11 0x0800 | ||
4646 | #define PG12 0x1000 | ||
4647 | #define PG13 0x2000 | ||
4648 | #define PG14 0x4000 | ||
4649 | #define PG15 0x8000 | ||
4650 | |||
4651 | /* PORT H Bit Definitions for the registers | ||
4652 | PORTH, PORTH_SET, PORTH_CLEAR, | ||
4653 | PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN, | ||
4654 | PORTH_FER registers | ||
4655 | */ | ||
4656 | |||
4657 | |||
4658 | #define PH0 0x0001 | ||
4659 | #define PH1 0x0002 | ||
4660 | #define PH2 0x0004 | ||
4661 | #define PH3 0x0008 | ||
4662 | #define PH4 0x0010 | ||
4663 | #define PH5 0x0020 | ||
4664 | #define PH6 0x0040 | ||
4665 | #define PH7 0x0080 | ||
4666 | #define PH8 0x0100 | ||
4667 | #define PH9 0x0200 | ||
4668 | #define PH10 0x0400 | ||
4669 | #define PH11 0x0800 | ||
4670 | #define PH12 0x1000 | ||
4671 | #define PH13 0x2000 | ||
4672 | |||
4673 | |||
4674 | /* PORT I Bit Definitions for the registers | ||
4675 | PORTI, PORTI_SET, PORTI_CLEAR, | ||
4676 | PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN, | ||
4677 | PORTI_FER registers | ||
4678 | */ | ||
4679 | |||
4680 | |||
4681 | #define PI0 0x0001 | ||
4682 | #define PI1 0x0002 | ||
4683 | #define PI2 0x0004 | ||
4684 | #define PI3 0x0008 | ||
4685 | #define PI4 0x0010 | ||
4686 | #define PI5 0x0020 | ||
4687 | #define PI6 0x0040 | ||
4688 | #define PI7 0x0080 | ||
4689 | #define PI8 0x0100 | ||
4690 | #define PI9 0x0200 | ||
4691 | #define PI10 0x0400 | ||
4692 | #define PI11 0x0800 | ||
4693 | #define PI12 0x1000 | ||
4694 | #define PI13 0x2000 | ||
4695 | #define PI14 0x4000 | ||
4696 | #define PI15 0x8000 | ||
4697 | |||
4698 | /* PORT J Bit Definitions for the registers | ||
4699 | PORTJ, PORTJ_SET, PORTJ_CLEAR, | ||
4700 | PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN, | ||
4701 | PORTJ_FER registers | ||
4702 | */ | ||
4703 | |||
4704 | |||
4705 | #define PJ0 0x0001 | ||
4706 | #define PJ1 0x0002 | ||
4707 | #define PJ2 0x0004 | ||
4708 | #define PJ3 0x0008 | ||
4709 | #define PJ4 0x0010 | ||
4710 | #define PJ5 0x0020 | ||
4711 | #define PJ6 0x0040 | ||
4712 | #define PJ7 0x0080 | ||
4713 | #define PJ8 0x0100 | ||
4714 | #define PJ9 0x0200 | ||
4715 | #define PJ10 0x0400 | ||
4716 | #define PJ11 0x0800 | ||
4717 | #define PJ12 0x1000 | ||
4718 | #define PJ13 0x2000 | ||
4719 | |||
4720 | |||
4721 | /* Port Muxing Bit Fields for PORTx_MUX Registers */ | ||
4722 | |||
4723 | #define MUX0 0x00000003 | ||
4724 | #define MUX0_0 0x00000000 | ||
4725 | #define MUX0_1 0x00000001 | ||
4726 | #define MUX0_2 0x00000002 | ||
4727 | #define MUX0_3 0x00000003 | ||
4728 | |||
4729 | #define MUX1 0x0000000C | ||
4730 | #define MUX1_0 0x00000000 | ||
4731 | #define MUX1_1 0x00000004 | ||
4732 | #define MUX1_2 0x00000008 | ||
4733 | #define MUX1_3 0x0000000C | ||
4734 | |||
4735 | #define MUX2 0x00000030 | ||
4736 | #define MUX2_0 0x00000000 | ||
4737 | #define MUX2_1 0x00000010 | ||
4738 | #define MUX2_2 0x00000020 | ||
4739 | #define MUX2_3 0x00000030 | ||
4740 | |||
4741 | #define MUX3 0x000000C0 | ||
4742 | #define MUX3_0 0x00000000 | ||
4743 | #define MUX3_1 0x00000040 | ||
4744 | #define MUX3_2 0x00000080 | ||
4745 | #define MUX3_3 0x000000C0 | ||
4746 | |||
4747 | #define MUX4 0x00000300 | ||
4748 | #define MUX4_0 0x00000000 | ||
4749 | #define MUX4_1 0x00000100 | ||
4750 | #define MUX4_2 0x00000200 | ||
4751 | #define MUX4_3 0x00000300 | ||
4752 | |||
4753 | #define MUX5 0x00000C00 | ||
4754 | #define MUX5_0 0x00000000 | ||
4755 | #define MUX5_1 0x00000400 | ||
4756 | #define MUX5_2 0x00000800 | ||
4757 | #define MUX5_3 0x00000C00 | ||
4758 | |||
4759 | #define MUX6 0x00003000 | ||
4760 | #define MUX6_0 0x00000000 | ||
4761 | #define MUX6_1 0x00001000 | ||
4762 | #define MUX6_2 0x00002000 | ||
4763 | #define MUX6_3 0x00003000 | ||
4764 | |||
4765 | #define MUX7 0x0000C000 | ||
4766 | #define MUX7_0 0x00000000 | ||
4767 | #define MUX7_1 0x00004000 | ||
4768 | #define MUX7_2 0x00008000 | ||
4769 | #define MUX7_3 0x0000C000 | ||
4770 | |||
4771 | #define MUX8 0x00030000 | ||
4772 | #define MUX8_0 0x00000000 | ||
4773 | #define MUX8_1 0x00010000 | ||
4774 | #define MUX8_2 0x00020000 | ||
4775 | #define MUX8_3 0x00030000 | ||
4776 | |||
4777 | #define MUX9 0x000C0000 | ||
4778 | #define MUX9_0 0x00000000 | ||
4779 | #define MUX9_1 0x00040000 | ||
4780 | #define MUX9_2 0x00080000 | ||
4781 | #define MUX9_3 0x000C0000 | ||
4782 | |||
4783 | #define MUX10 0x00300000 | ||
4784 | #define MUX10_0 0x00000000 | ||
4785 | #define MUX10_1 0x00100000 | ||
4786 | #define MUX10_2 0x00200000 | ||
4787 | #define MUX10_3 0x00300000 | ||
4788 | |||
4789 | #define MUX11 0x00C00000 | ||
4790 | #define MUX11_0 0x00000000 | ||
4791 | #define MUX11_1 0x00400000 | ||
4792 | #define MUX11_2 0x00800000 | ||
4793 | #define MUX11_3 0x00C00000 | ||
4794 | |||
4795 | #define MUX12 0x03000000 | ||
4796 | #define MUX12_0 0x00000000 | ||
4797 | #define MUX12_1 0x01000000 | ||
4798 | #define MUX12_2 0x02000000 | ||
4799 | #define MUX12_3 0x03000000 | ||
4800 | |||
4801 | #define MUX13 0x0C000000 | ||
4802 | #define MUX13_0 0x00000000 | ||
4803 | #define MUX13_1 0x04000000 | ||
4804 | #define MUX13_2 0x08000000 | ||
4805 | #define MUX13_3 0x0C000000 | ||
4806 | |||
4807 | #define MUX14 0x30000000 | ||
4808 | #define MUX14_0 0x00000000 | ||
4809 | #define MUX14_1 0x10000000 | ||
4810 | #define MUX14_2 0x20000000 | ||
4811 | #define MUX14_3 0x30000000 | ||
4812 | |||
4813 | #define MUX15 0xC0000000 | ||
4814 | #define MUX15_0 0x00000000 | ||
4815 | #define MUX15_1 0x40000000 | ||
4816 | #define MUX15_2 0x80000000 | ||
4817 | #define MUX15_3 0xC0000000 | ||
4818 | |||
4819 | #define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \ | ||
4820 | ((((b15)&3) << 30) | \ | ||
4821 | (((b14)&3) << 28) | \ | ||
4822 | (((b13)&3) << 26) | \ | ||
4823 | (((b12)&3) << 24) | \ | ||
4824 | (((b11)&3) << 22) | \ | ||
4825 | (((b10)&3) << 20) | \ | ||
4826 | (((b9) &3) << 18) | \ | ||
4827 | (((b8) &3) << 16) | \ | ||
4828 | (((b7) &3) << 14) | \ | ||
4829 | (((b6) &3) << 12) | \ | ||
4830 | (((b5) &3) << 10) | \ | ||
4831 | (((b4) &3) << 8) | \ | ||
4832 | (((b3) &3) << 6) | \ | ||
4833 | (((b2) &3) << 4) | \ | ||
4834 | (((b1) &3) << 2) | \ | ||
4835 | (((b0) &3))) | ||
4836 | |||
4837 | /* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */ | ||
4838 | |||
4839 | #define B0MAP 0x000000FF /* Byte 0 Lower Half Port Mapping */ | ||
4840 | #define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */ | ||
4841 | #define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */ | ||
4842 | #define B1MAP 0x0000FF00 /* Byte 1 Upper Half Port Mapping */ | ||
4843 | #define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */ | ||
4844 | #define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */ | ||
4845 | #define B2MAP 0x00FF0000 /* Byte 2 Lower Half Port Mapping */ | ||
4846 | #define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */ | ||
4847 | #define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */ | ||
4848 | #define B3MAP 0xFF000000 /* Byte 3 Upper Half Port Mapping */ | ||
4849 | #define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */ | ||
4850 | #define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */ | ||
4851 | |||
4852 | /* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */ | ||
4853 | |||
4854 | #define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */ | ||
4855 | #define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */ | ||
4856 | #define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */ | ||
4857 | #define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */ | ||
4858 | #define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */ | ||
4859 | #define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */ | ||
4860 | #define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */ | ||
4861 | #define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */ | ||
4862 | |||
4863 | #define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */ | ||
4864 | #define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */ | ||
4865 | #define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */ | ||
4866 | #define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */ | ||
4867 | #define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */ | ||
4868 | #define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */ | ||
4869 | #define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */ | ||
4870 | #define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */ | ||
4871 | |||
4872 | #define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */ | ||
4873 | #define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */ | ||
4874 | #define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */ | ||
4875 | #define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */ | ||
4876 | #define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */ | ||
4877 | #define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */ | ||
4878 | #define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */ | ||
4879 | #define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */ | ||
4880 | |||
4881 | #define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */ | ||
4882 | #define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */ | ||
4883 | #define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */ | ||
4884 | #define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */ | ||
4885 | #define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */ | ||
4886 | #define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */ | ||
4887 | #define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ | ||
4888 | #define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ | ||
4889 | |||
4890 | |||
4891 | /* for legacy compatibility */ | ||
4892 | |||
4893 | #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ | ||
4894 | #define W1LMAX_MAX W1LMAX_MIN | ||
4895 | #define EBIU_AMCBCTL0 EBIU_AMBCTL0 | ||
4896 | #define EBIU_AMCBCTL1 EBIU_AMBCTL1 | ||
4897 | #define PINT0_IRQ PINT0_REQUEST | ||
4898 | #define PINT1_IRQ PINT1_REQUEST | ||
4899 | #define PINT2_IRQ PINT2_REQUEST | ||
4900 | #define PINT3_IRQ PINT3_REQUEST | ||
4901 | |||
4902 | #endif /* _DEF_BF54X_H */ | ||